Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	672	1			T11	11		T18	21		T25	4
all_values[1]	672	1			T11	11		T18	21		T25	4
all_values[2]	672	1			T11	11		T18	21		T25	4
all_values[3]	672	1			T11	11		T18	21		T25	4
all_values[4]	672	1			T11	11		T18	21		T25	4
all_values[5]	672	1			T11	11		T18	21		T25	4
all_values[6]	672	1			T11	11		T18	21		T25	4
all_values[7]	672	1			T11	11		T18	21		T25	4
all_values[8]	672	1			T11	11		T18	21		T25	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3296

1

T11

50

T18

92

T25

20

auto[1]

2752

1

T11

49

T18

97

T25

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1906

1

T11

29

T18

60

T25

11

auto[1]

4142

1

T11

70

T18

129

T25

25

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3553

1

T11

51

T18

108

T25

22

auto[1]

2495

1

T11

48

T18

81

T25

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	229	1			T18	3		T33	2		T34	2
all_values[0]	auto[0]	auto[1]	auto[1]	178	1			T11	5		T18	8		T25	2
all_values[0]	auto[1]	auto[0]	auto[1]	148	1			T11	4		T18	4		T25	1
all_values[0]	auto[1]	auto[1]	auto[1]	117	1			T11	2		T18	6		T25	1
all_values[1]	auto[0]	auto[0]	auto[0]	233	1			T11	2		T18	10		T25	2
all_values[1]	auto[0]	auto[1]	auto[0]	163	1			T11	3		T18	5		T25	1
all_values[1]	auto[1]	auto[0]	auto[1]	159	1			T11	1		T18	3		T25	1
all_values[1]	auto[1]	auto[1]	auto[1]	117	1			T11	5		T18	3		T33	2
all_values[2]	auto[0]	auto[0]	auto[0]	135	1			T11	1		T18	4		T33	1
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T11	3		T18	2		T35	1
all_values[2]	auto[0]	auto[1]	auto[0]	105	1			T18	3		T34	2		T93	3
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T11	2		T18	2		T25	2
all_values[2]	auto[1]	auto[0]	auto[1]	173	1			T11	2		T18	7		T25	2
all_values[2]	auto[1]	auto[1]	auto[1]	119	1			T11	3		T18	3		T33	1
all_values[3]	auto[0]	auto[0]	auto[0]	159	1			T11	4		T18	1		T25	2
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T11	1		T18	3		T33	1
all_values[3]	auto[0]	auto[1]	auto[0]	130	1			T11	2		T18	5		T25	2
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T18	2		T34	1		T35	3
all_values[3]	auto[1]	auto[0]	auto[1]	136	1			T11	4		T18	3		T33	1
all_values[3]	auto[1]	auto[1]	auto[1]	116	1			T18	7		T33	1		T34	1
all_values[4]	auto[0]	auto[0]	auto[0]	123	1			T11	2		T18	1		T25	1
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T11	1		T18	5		T25	1
all_values[4]	auto[0]	auto[1]	auto[0]	97	1			T11	3		T18	3		T25	1
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T11	1		T18	1		T34	2
all_values[4]	auto[1]	auto[0]	auto[1]	176	1			T11	2		T18	9		T25	1
all_values[4]	auto[1]	auto[1]	auto[1]	130	1			T11	2		T18	2		T34	5
all_values[5]	auto[0]	auto[0]	auto[0]	149	1			T11	5		T18	2		T35	4
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T34	2		T38	1		T105	1
all_values[5]	auto[0]	auto[1]	auto[0]	103	1			T11	2		T18	3		T33	3
all_values[5]	auto[0]	auto[1]	auto[1]	80	1			T18	5		T25	1		T34	1
all_values[5]	auto[1]	auto[0]	auto[1]	161	1			T11	1		T18	8		T25	2
all_values[5]	auto[1]	auto[1]	auto[1]	112	1			T11	3		T18	3		T25	1
all_values[6]	auto[0]	auto[0]	auto[0]	140	1			T11	2		T18	5		T25	1
all_values[6]	auto[0]	auto[0]	auto[1]	57	1			T35	1		T94	1		T106	1
all_values[6]	auto[0]	auto[1]	auto[0]	125	1			T11	3		T18	6		T33	1
all_values[6]	auto[0]	auto[1]	auto[1]	68	1			T18	3		T25	2		T35	2
all_values[6]	auto[1]	auto[0]	auto[1]	156	1			T11	5		T18	2		T25	1
all_values[6]	auto[1]	auto[1]	auto[1]	126	1			T11	1		T18	5		T33	3
all_values[7]	auto[0]	auto[0]	auto[0]	127	1			T18	4		T25	1		T34	2
all_values[7]	auto[0]	auto[0]	auto[1]	68	1			T11	1		T18	2		T25	1
all_values[7]	auto[0]	auto[1]	auto[0]	117	1			T18	8		T38	2		T94	1
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T11	3		T18	1		T33	3
all_values[7]	auto[1]	auto[0]	auto[1]	139	1			T11	2		T18	1		T25	2
all_values[7]	auto[1]	auto[1]	auto[1]	133	1			T11	5		T18	5		T33	1
all_values[8]	auto[0]	auto[0]	auto[1]	210	1			T11	3		T18	8		T34	1
all_values[8]	auto[0]	auto[1]	auto[1]	185	1			T11	2		T18	3		T25	2
all_values[8]	auto[1]	auto[0]	auto[1]	139	1			T11	4		T18	5		T25	1
all_values[8]	auto[1]	auto[1]	auto[1]	138	1			T11	2		T18	5		T25	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal