UART Lint Results
Thursday June 13 2024 19:02:12 UTC
Branch: os_regression
Tool: ASCENTLINT
| Build Mode |
Flow Infos |
Flow Warnings |
Flow Errors |
Lint Infos |
Lint Warnings |
Lint Errors |
| default |
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207 |
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Messages for Build Mode 'default'
Lint Infos
I FSM_DEFAULT_REQ: prim_diff_decode.sv:158 Next state register 'gen_async.state_d' has no assignment in the default branch of the case statement for this finite state machine New
I NESTED_SUBPROG: tlul_pkg.sv:143 Function 'prim_mubi_pkg::mubi4_test_invalid' is called from within a function New
I VAR_INDEX_WRITE: prim_fifo_sync.sv:124 Variable index expression 'gen_normal_fifo.storage[gen_normal_fifo.fifo_wptr]' encountered New
I CASE_INC: uart_core.sv:113 Case statement tag not specified for value 'h3 New
I CASE_INC: prim_alert_sender.sv:199 Case statement tag not specified for value 'b111 New
I CASE_INC: prim_diff_decode.sv:115 Case statement tag not specified for value 'b11 New
I CASE_INC: tlul_err.sv:62 Case statement tag not specified for value 'h3 New
I ONE_BIT_VEC: uart.sv:12 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'AlertAsyncOn' has a length of one, instance 'uart' of module 'uart' (NumAlerts=1) New
I ONE_BIT_VEC: uart.sv:22 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_rx_i' has a length of one, instance 'uart' of module 'uart' (NumAlerts=1) New
I ONE_BIT_VEC: uart.sv:23 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_tx_o' has a length of one, instance 'uart' of module 'uart' (NumAlerts=1) New
I ONE_BIT_VEC: uart.sv:42 Declaration range '[NumAlerts - 1:0]' ([0:0]) of 'alert_test' has a length of one, instance 'uart' of module 'uart' (NumAlerts=1) New
I ONE_BIT_VEC: uart_reg_top.sv:866 Declaration range '[0:0]' of 'alert_test_flds_we' has a length of one New
I ONE_BIT_VEC: uart_reg_top.sv:1239 Declaration range '[0:0]' of 'wdata_flds_we' has a length of one New
I ONE_BIT_VEC: prim_buf.sv:24 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'uart.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_buf.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'uart.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf' of module 'prim_buf' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:22 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'uart.u_reg.u_wdata0_qe' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:27 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'uart.u_reg.u_wdata0_qe' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop.sv:28 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'uart.u_reg.u_wdata0_qe' of module 'prim_flop' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:19 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'uart.uart_core.sync_rx' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:25 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'uart.uart_core.sync_rx' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_flop_2sync.sv:26 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'uart.uart_core.sync_rx' of module 'prim_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:44 Declaration range '[Width - 1:0]' ([0:0]) of 'event_intr_i' has a length of one, instance 'uart.uart_core.intr_hw_tx_watermark' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:47 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_enable_q_i' has a length of one, instance 'uart.uart_core.intr_hw_tx_watermark' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:48 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_test_q_i' has a length of one, instance 'uart.uart_core.intr_hw_tx_watermark' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:50 Declaration range '[Width - 1:0]' ([0:0]) of 'reg2hw_intr_state_q_i' has a length of one, instance 'uart.uart_core.intr_hw_tx_watermark' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:52 Declaration range '[Width - 1:0]' ([0:0]) of 'hw2reg_intr_state_d_o' has a length of one, instance 'uart.uart_core.intr_hw_tx_watermark' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:55 Declaration range '[Width - 1:0]' ([0:0]) of 'intr_o' has a length of one, instance 'uart.uart_core.intr_hw_tx_watermark' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:58 Declaration range '[Width - 1:0]' ([0:0]) of 'status' has a length of one, instance 'uart.uart_core.intr_hw_tx_watermark' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:61 Declaration range '[Width - 1:0]' ([0:0]) of 'g_intr_event.new_event' has a length of one, instance 'uart.uart_core.intr_hw_tx_done' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_intr_hw.sv:72 Declaration range '[Width - 1:0]' ([0:0]) of 'g_intr_status.test_q' has a length of one, instance 'uart.uart_core.intr_hw_tx_watermark' of module 'prim_intr_hw' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'uart.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'uart.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_buf.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'inv' has a length of one, instance 'uart.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req.u_secure_anchor_buf.gen_generic.u_impl_generic' of module 'prim_generic_buf' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'uart.u_reg.u_wdata0_qe.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:13 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'uart.u_reg.u_wdata0_qe.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'uart.u_reg.u_wdata0_qe.gen_generic.u_impl_generic' of module 'prim_generic_flop' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:9 Declaration range '[Width - 1:0]' ([0:0]) of 'ResetValue' has a length of one, instance 'uart.uart_core.sync_rx.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:14 Declaration range '[Width - 1:0]' ([0:0]) of 'd_i' has a length of one, instance 'uart.uart_core.sync_rx.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:15 Declaration range '[Width - 1:0]' ([0:0]) of 'q_o' has a length of one, instance 'uart.uart_core.sync_rx.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:18 Declaration range '[Width - 1:0]' ([0:0]) of 'd_o' has a length of one, instance 'uart.uart_core.sync_rx.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_generic_flop_2sync.sv:19 Declaration range '[Width - 1:0]' ([0:0]) of 'intq' has a length of one, instance 'uart.uart_core.sync_rx.gen_generic.u_impl_generic' of module 'prim_generic_flop_2sync' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:10 Declaration range '[Width - 1:0]' ([0:0]) of 'in_i' has a length of one, instance 'uart.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_sec_anchor_buf.sv:11 Declaration range '[Width - 1:0]' ([0:0]) of 'out_o' has a length of one, instance 'uart.gen_alert_tx[0].u_prim_alert_sender.u_prim_buf_in_req' of module 'prim_sec_anchor_buf' (Width=1) New
I ONE_BIT_VEC: prim_subreg.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'RESVAL' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:25 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:29 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:34 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:35 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg.sv:39 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark' of module 'prim_subreg' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:17 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:24 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:28 Declaration range '[DW - 1:0]' ([0:0]) of 'wr_data' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:36 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_w.unused_q' has a length of one, instance 'uart.u_reg.u_intr_enable_tx_watermark.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:47 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_wd' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_arb.sv:48 Declaration range '[DW - 1:0]' ([0:0]) of 'gen_ro.unused_q' has a length of one, instance 'uart.u_reg.u_intr_state_tx_watermark.wr_en_data_arb' of module 'prim_subreg_arb' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:12 Declaration range '[DW - 1:0]' ([0:0]) of 'wd' has a length of one, instance 'uart.u_reg.u_intr_test_tx_watermark' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:14 Declaration range '[DW - 1:0]' ([0:0]) of 'd' has a length of one, instance 'uart.u_reg.u_intr_test_tx_watermark' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:19 Declaration range '[DW - 1:0]' ([0:0]) of 'q' has a length of one, instance 'uart.u_reg.u_intr_test_tx_watermark' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:20 Declaration range '[DW - 1:0]' ([0:0]) of 'ds' has a length of one, instance 'uart.u_reg.u_intr_test_tx_watermark' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: prim_subreg_ext.sv:21 Declaration range '[DW - 1:0]' ([0:0]) of 'qs' has a length of one, instance 'uart.u_reg.u_intr_test_tx_watermark' of module 'prim_subreg_ext' (DW=1) New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'd_sink' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_d2h_t' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_i' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_o_pre' has a length of one New
I ONE_BIT_VEC: tlul_pkg.sv:111 Declaration range '[top_pkg::TL_DIW - 1:0]' ([0:0]) of 'tl_reg_d2h' has a length of one New
I EXPLICIT_BITLEN: uart_core.sv:315 Bit length not specified for constant '2' New
I EXPLICIT_BITLEN: uart_core.sv:341 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: uart_core.sv:343 Bit length not specified for constant '2' New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:51 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_fifo_sync_cnt.sv:52 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: prim_util_pkg.sv:85 Bit length not specified for constant '1' New
I EXPLICIT_BITLEN: tlul_err.sv:69 Bit length not specified for constant "'h1" New
I EXPLICIT_BITLEN: tlul_err.sv:77 Bit length not specified for constant "'h2" New
I MIN_NAME_LEN: uart_reg_pkg.sv:23 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:26 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:32 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:35 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:38 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:41 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:44 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:47 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:53 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:56 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:59 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:62 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:65 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:68 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:71 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:74 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:77 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:83 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:87 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:91 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:95 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:99 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:103 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:107 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:111 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:115 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:121 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:127 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:130 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:133 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:136 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:139 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:142 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:145 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:148 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:151 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:157 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:161 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:165 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:169 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:173 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:177 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:183 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:188 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:194 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:198 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:202 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:206 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:213 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:216 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:222 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:225 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:231 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:235 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:239 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:243 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:247 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:251 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:255 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:259 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:263 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:270 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:273 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:276 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:279 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:282 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:285 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:290 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:295 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:299 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:306 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:309 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: uart_reg_pkg.sv:314 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:80 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:85 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:106 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:111 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:124 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:131 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:212 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:217 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:238 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:243 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:256 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:263 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:344 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:349 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:370 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:375 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:388 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:395 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:476 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:481 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:502 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:507 Name 'k' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:520 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'a' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_mubi_pkg.sv:527 Name 'b' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:25 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg.sv:29 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:21 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_arb.sv:24 Name 'q' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:14 Name 'd' is shorter than minimum length 2 New
I MIN_NAME_LEN: prim_subreg_ext.sv:19 Name 'q' is shorter than minimum length 2 New
I CONST_OUTPUT: uart_core.sv:151 Output 'hw2reg.fifo_status.txlvl.d[7:6]' is driven by constant zeros New
I CONST_OUTPUT: uart_core.sv:152 Output 'hw2reg.fifo_status.rxlvl.d[7]' is driven by constant zero New
I CONST_OUTPUT: uart_core.sv:393 Output 'hw2reg.intr_state.tx_watermark.de' is driven by constant one by port 'intr_hw_tx_watermark.hw2reg_intr_state_de_o' New
I CONST_OUTPUT: uart_core.sv:406 Output 'hw2reg.intr_state.tx_empty.de' is driven by constant one by port 'intr_hw_tx_empty.hw2reg_intr_state_de_o' New
I CONST_OUTPUT: uart_core.sv:419 Output 'hw2reg.intr_state.rx_watermark.de' is driven by constant one by port 'intr_hw_rx_watermark.hw2reg_intr_state_de_o' New
I CONST_OUTPUT: prim_intr_hw.sv:80 Output 'hw2reg_intr_state_de_o' is driven by constant one in module 'prim_intr_hw' (IntrT="Status") New
I CONST_OUTPUT: prim_fifo_sync.sv:98 Output 'err_o' is driven by constant zero by port 'gen_normal_fifo.u_fifo_cnt.err_o' in module 'prim_fifo_sync' (Width=8,Pass=1'h0,Depth=32'h20) New
I CONST_OUTPUT: prim_fifo_sync_cnt.sv:136 Output 'err_o' is driven by constant zero in module 'prim_fifo_sync_cnt' (Depth=32'h20) New
I CONST_OUTPUT: tlul_adapter_reg.sv:91 Output 'addr_o[1:0]' is driven by constant zeros in module 'tlul_adapter_reg' (RegAw=6) New
I CONST_OUTPUT: tlul_adapter_reg.sv:195 Output 'intg_error_o' is driven by constant zero in module 'tlul_adapter_reg' (RegAw=6) New
Lint Warnings
W STAR_PORT_CONN_USE: prim_flop_2sync.sv:35 '.*' wild card port connection encountered on instance 'gen_generic.u_impl_generic' New
Lint Errors
E IFDEF_CODE: prim_generic_flop_2sync.sv:35 Assignment to 'unused_sig' contained within `else block at prim_generic_flop_2sync.sv:33 prim_generic_flop_2sync.sv:33 New
Past Results