USBDEV Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: 83db9403d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 9.510s 10.007ms 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.820s 47.180us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.090s 69.783us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 10.660s 1.518ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.680s 393.902us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 3.480s 129.832us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.090s 69.783us 20 20 100.00
usbdev_csr_aliasing 3.680s 393.902us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.400s 695.391us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.450s 169.564us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.700s 169.622us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.070s 298.585us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.070s 298.585us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.820s 47.180us 5 5 100.00
usbdev_csr_rw 1.090s 69.783us 20 20 100.00
usbdev_csr_aliasing 3.680s 393.902us 5 5 100.00
usbdev_same_csr_outstanding 1.570s 136.418us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.820s 47.180us 5 5 100.00
usbdev_csr_rw 1.090s 69.783us 20 20 100.00
usbdev_csr_aliasing 3.680s 393.902us 5 5 100.00
usbdev_same_csr_outstanding 1.570s 136.418us 20 20 100.00
V2 TOTAL 90 90 100.00
V2S tl_intg_err usbdev_sec_cm 10.050s 10.003ms 2 5 40.00
usbdev_tl_intg_err 10.820s 10.011ms 7 20 35.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.820s 10.011ms 7 20 35.00
V2S TOTAL 9 25 36.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.620s 2.120us 0 50 0.00
usbdev_stress_all 0.630s 0 50 0.00
TOTAL 164 330 49.70

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 3 100.00
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.45 90.29 74.29 95.23 0.00 86.85 92.01 96.47

Failure Buckets

Past Results