USBDEV Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: 26b0ee226

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 9.140s 10.009ms 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.840s 127.032us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.130s 71.635us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 18.440s 11.751ms 4 5 80.00
V1 csr_aliasing usbdev_csr_aliasing 3.450s 302.044us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.920s 91.262us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.130s 71.635us 20 20 100.00
usbdev_csr_aliasing 3.450s 302.044us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.560s 691.536us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.430s 181.934us 5 5 100.00
V1 TOTAL 64 115 55.65
V2 intr_test usbdev_intr_test 0.750s 40.941us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.520s 271.432us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.520s 271.432us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.840s 127.032us 5 5 100.00
usbdev_csr_rw 1.130s 71.635us 20 20 100.00
usbdev_csr_aliasing 3.450s 302.044us 5 5 100.00
usbdev_same_csr_outstanding 9.510s 10.114ms 19 20 95.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.840s 127.032us 5 5 100.00
usbdev_csr_rw 1.130s 71.635us 20 20 100.00
usbdev_csr_aliasing 3.450s 302.044us 5 5 100.00
usbdev_same_csr_outstanding 9.510s 10.114ms 19 20 95.00
V2 TOTAL 89 90 98.89
V2S tl_intg_err usbdev_sec_cm 9.720s 10.005ms 1 5 20.00
usbdev_tl_intg_err 10.790s 10.034ms 1 20 5.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.790s 10.034ms 1 20 5.00
V2S TOTAL 2 25 8.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.610s 1.287us 0 50 0.00
usbdev_stress_all 0.610s 0 50 0.00
TOTAL 155 330 46.97

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 6 75.00
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.20 90.13 74.03 95.23 0.00 86.85 92.01 95.17

Failure Buckets

Past Results