USBDEV Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.660s 3.318us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.800s 37.779us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.030s 70.409us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 10.020s 1.761ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.330s 358.444us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.580s 111.068us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.030s 70.409us 20 20 100.00
usbdev_csr_aliasing 3.330s 358.444us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.050s 605.382us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.160s 146.094us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.730s 12.903us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.010s 300.528us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.010s 300.528us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.800s 37.779us 5 5 100.00
usbdev_csr_rw 1.030s 70.409us 20 20 100.00
usbdev_csr_aliasing 3.330s 358.444us 5 5 100.00
usbdev_same_csr_outstanding 11.080s 10.058ms 19 20 95.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.800s 37.779us 5 5 100.00
usbdev_csr_rw 1.030s 70.409us 20 20 100.00
usbdev_csr_aliasing 3.330s 358.444us 5 5 100.00
usbdev_same_csr_outstanding 11.080s 10.058ms 19 20 95.00
V2 TOTAL 89 90 98.89
V2S tl_intg_err usbdev_sec_cm 9.030s 10.007ms 2 5 40.00
usbdev_tl_intg_err 11.120s 10.009ms 4 20 20.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 11.120s 10.009ms 4 20 20.00
V2S TOTAL 6 25 24.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.640s 3.712us 0 50 0.00
usbdev_stress_all 0.590s 0 50 0.00
TOTAL 160 330 48.48

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.34 90.13 74.44 95.01 0.00 86.90 92.01 95.91

Failure Buckets

Past Results