USBDEV Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: 213e792ea

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.630s 1.667us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.750s 39.399us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.020s 54.737us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 13.510s 10.907ms 4 5 80.00
V1 csr_aliasing usbdev_csr_aliasing 3.640s 386.840us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 4.060s 128.428us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.020s 54.737us 20 20 100.00
usbdev_csr_aliasing 3.640s 386.840us 5 5 100.00
V1 mem_walk usbdev_mem_walk 3.990s 488.177us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.330s 143.909us 5 5 100.00
V1 TOTAL 64 115 55.65
V2 intr_test usbdev_intr_test 0.710s 15.248us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 2.890s 308.059us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 2.890s 308.059us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.750s 39.399us 5 5 100.00
usbdev_csr_rw 1.020s 54.737us 20 20 100.00
usbdev_csr_aliasing 3.640s 386.840us 5 5 100.00
usbdev_same_csr_outstanding 9.940s 10.094ms 19 20 95.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.750s 39.399us 5 5 100.00
usbdev_csr_rw 1.020s 54.737us 20 20 100.00
usbdev_csr_aliasing 3.640s 386.840us 5 5 100.00
usbdev_same_csr_outstanding 9.940s 10.094ms 19 20 95.00
V2 TOTAL 89 90 98.89
V2S tl_intg_err usbdev_sec_cm 9.980s 10.005ms 0 5 0.00
usbdev_tl_intg_err 10.260s 10.011ms 1 20 5.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.260s 10.011ms 1 20 5.00
V2S TOTAL 1 25 4.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 9.170s 10.005ms 0 50 0.00
usbdev_stress_all 0.600s 0 50 0.00
TOTAL 154 330 46.67

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 6 75.00
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
69.62 69.25 63.91 87.42 0.00 74.05 97.77 94.98

Failure Buckets

Past Results