USBDEV Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 8.660s 10.011ms 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.890s 45.280us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.140s 97.647us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 10.160s 1.777ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 2.290s 195.362us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 8.830s 10.006ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.140s 97.647us 20 20 100.00
usbdev_csr_aliasing 2.290s 195.362us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.860s 690.942us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.670s 178.858us 5 5 100.00
V1 TOTAL 64 115 55.65
V2 intr_test usbdev_intr_test 0.780s 34.205us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.540s 89.863us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.540s 89.863us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.890s 45.280us 5 5 100.00
usbdev_csr_rw 1.140s 97.647us 20 20 100.00
usbdev_csr_aliasing 2.290s 195.362us 5 5 100.00
usbdev_same_csr_outstanding 8.640s 10.008ms 19 20 95.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.890s 45.280us 5 5 100.00
usbdev_csr_rw 1.140s 97.647us 20 20 100.00
usbdev_csr_aliasing 2.290s 195.362us 5 5 100.00
usbdev_same_csr_outstanding 8.640s 10.008ms 19 20 95.00
V2 TOTAL 89 90 98.89
V2S tl_intg_err usbdev_sec_cm 9.690s 10.007ms 0 5 0.00
usbdev_tl_intg_err 11.080s 10.014ms 2 20 10.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 11.080s 10.014ms 2 20 10.00
V2S TOTAL 2 25 8.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 9.110s 10.007ms 0 50 0.00
usbdev_stress_all 0.590s 0 50 0.00
TOTAL 155 330 46.97

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 6 75.00
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
69.73 69.25 63.93 87.20 0.00 74.05 97.77 95.91

Failure Buckets

Past Results