USBDEV Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.620s 2.224us 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.820s 29.334us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.090s 67.926us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.740s 371.300us 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.560s 360.974us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.660s 81.575us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.090s 67.926us 20 20 100.00
usbdev_csr_aliasing 3.560s 360.974us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.450s 696.344us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.420s 165.599us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 intr_test usbdev_intr_test 0.710s 50.257us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.290s 247.170us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.290s 247.170us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.820s 29.334us 5 5 100.00
usbdev_csr_rw 1.090s 67.926us 20 20 100.00
usbdev_csr_aliasing 3.560s 360.974us 5 5 100.00
usbdev_same_csr_outstanding 10.100s 10.040ms 18 20 90.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.820s 29.334us 5 5 100.00
usbdev_csr_rw 1.090s 67.926us 20 20 100.00
usbdev_csr_aliasing 3.560s 360.974us 5 5 100.00
usbdev_same_csr_outstanding 10.100s 10.040ms 18 20 90.00
V2 TOTAL 88 90 97.78
V2S tl_intg_err usbdev_sec_cm 9.820s 10.004ms 2 5 40.00
usbdev_tl_intg_err 10.600s 10.036ms 3 20 15.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.600s 10.036ms 3 20 15.00
V2S TOTAL 5 25 20.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.610s 2.680us 0 50 0.00
usbdev_stress_all 0.590s 0 50 0.00
TOTAL 158 330 47.88

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 3 3 2 66.67
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.40 90.48 74.16 95.23 0.00 86.85 92.01 96.10

Failure Buckets

Past Results