Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	549	1		T1	2		T2	2		T3	2
all_values[1]	549	1		T1	2		T2	2		T3	2
all_values[2]	549	1		T1	2		T2	2		T3	2
all_values[3]	549	1		T1	2		T2	2		T3	2
all_values[4]	549	1		T1	2		T2	2		T3	2
all_values[5]	549	1		T1	2		T2	2		T3	2
all_values[6]	549	1		T1	2		T2	2		T3	2
all_values[7]	549	1		T1	2		T2	2		T3	2
all_values[8]	549	1		T1	2		T2	2		T3	2
all_values[9]	549	1		T1	2		T2	2		T3	2
all_values[10]	549	1		T1	2		T2	2		T3	2
all_values[11]	549	1		T1	2		T2	2		T3	2
all_values[12]	549	1		T1	2		T2	2		T3	2
all_values[13]	549	1		T1	2		T2	2		T3	2
all_values[14]	549	1		T1	2		T2	2		T3	2
all_values[15]	549	1		T1	2		T2	2		T3	2
all_values[16]	549	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	7267	1		T1	34		T2	34		T3	34
auto[1]	2066	1		T4	2		T5	2		T6	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6202	1		T1	34		T2	34		T3	34
auto[1]	3131	1		T25	122		T26	121		T27	130

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	159	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	84	1		T25	2		T26	4		T27	3
all_values[0]	auto[1]	auto[0]	224	1		T4	2		T5	2		T6	2
all_values[0]	auto[1]	auto[1]	82	1		T25	4		T26	4		T27	5
all_values[1]	auto[0]	auto[0]	348	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	103	1		T25	6		T26	3		T27	4
all_values[1]	auto[1]	auto[0]	11	1		T25	1		T26	1		T65	3
all_values[1]	auto[1]	auto[1]	87	1		T25	1		T26	4		T27	4
all_values[2]	auto[0]	auto[0]	342	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	84	1		T25	2		T26	6		T27	1
all_values[2]	auto[1]	auto[0]	24	1		T26	1		T59	1		T60	1
all_values[2]	auto[1]	auto[1]	99	1		T25	6		T26	1		T27	7
all_values[3]	auto[0]	auto[0]	347	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	111	1		T25	5		T26	3		T27	3
all_values[3]	auto[1]	auto[0]	11	1		T26	2		T51	1		T62	1
all_values[3]	auto[1]	auto[1]	80	1		T25	3		T26	2		T27	5
all_values[4]	auto[0]	auto[0]	341	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	84	1		T25	4		T26	6		T27	3
all_values[4]	auto[1]	auto[0]	13	1		T26	1		T28	1		T59	2
all_values[4]	auto[1]	auto[1]	111	1		T25	4		T27	5		T28	6
all_values[5]	auto[0]	auto[0]	341	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	113	1		T25	7		T26	2		T27	3
all_values[5]	auto[1]	auto[0]	13	1		T60	1		T51	1		T65	1
all_values[5]	auto[1]	auto[1]	82	1		T25	1		T26	6		T27	5
all_values[6]	auto[0]	auto[0]	340	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	101	1		T25	1		T26	1		T27	5
all_values[6]	auto[1]	auto[0]	16	1		T59	1		T60	2		T51	1
all_values[6]	auto[1]	auto[1]	92	1		T25	7		T26	7		T27	2
all_values[7]	auto[0]	auto[0]	347	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	95	1		T25	2		T27	5		T28	6
all_values[7]	auto[1]	auto[0]	14	1		T25	1		T26	2		T27	1
all_values[7]	auto[1]	auto[1]	93	1		T25	5		T26	4		T27	1
all_values[8]	auto[0]	auto[0]	343	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	103	1		T25	2		T26	4		T27	5
all_values[8]	auto[1]	auto[0]	16	1		T28	3		T59	1		T60	1
all_values[8]	auto[1]	auto[1]	87	1		T25	6		T26	4		T27	3
all_values[9]	auto[0]	auto[0]	351	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	82	1		T25	3		T26	5		T27	1
all_values[9]	auto[1]	auto[0]	20	1		T27	1		T60	2		T102	1
all_values[9]	auto[1]	auto[1]	96	1		T25	5		T26	3		T27	5
all_values[10]	auto[0]	auto[0]	355	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	80	1		T25	5		T26	2		T27	1
all_values[10]	auto[1]	auto[0]	12	1		T25	1		T59	1		T60	1
all_values[10]	auto[1]	auto[1]	102	1		T25	2		T26	6		T27	6
all_values[11]	auto[0]	auto[0]	356	1		T1	2		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	61	1		T25	3		T26	1		T27	2
all_values[11]	auto[1]	auto[0]	27	1		T28	1		T59	1		T60	1
all_values[11]	auto[1]	auto[1]	105	1		T25	5		T26	7		T27	6
all_values[12]	auto[0]	auto[0]	348	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	68	1		T25	3		T26	6		T27	4
all_values[12]	auto[1]	auto[0]	29	1		T25	1		T59	1		T103	3
all_values[12]	auto[1]	auto[1]	104	1		T25	4		T26	2		T27	4
all_values[13]	auto[0]	auto[0]	347	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	96	1		T25	1		T26	5		T27	6
all_values[13]	auto[1]	auto[0]	16	1		T25	1		T60	1		T51	1
all_values[13]	auto[1]	auto[1]	90	1		T25	6		T26	2		T27	2
all_values[14]	auto[0]	auto[0]	347	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	97	1		T25	7		T26	4		T27	5
all_values[14]	auto[1]	auto[0]	19	1		T28	1		T103	2		T104	1
all_values[14]	auto[1]	auto[1]	86	1		T25	1		T26	1		T27	3
all_values[15]	auto[0]	auto[0]	340	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	114	1		T25	3		T26	3		T27	7
all_values[15]	auto[1]	auto[0]	14	1		T25	2		T51	2		T103	1
all_values[15]	auto[1]	auto[1]	81	1		T26	5		T27	1		T28	2
all_values[16]	auto[0]	auto[0]	352	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	87	1		T25	4		T26	1		T27	5
all_values[16]	auto[1]	auto[0]	19	1		T25	2		T28	2		T59	1
all_values[16]	auto[1]	auto[1]	91	1		T25	2		T26	7		T27	3