Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	549	1		T1	2		T2	2		T3	2
all_pins[1]	549	1		T1	2		T2	2		T3	2
all_pins[2]	549	1		T1	2		T2	2		T3	2
all_pins[3]	549	1		T1	2		T2	2		T3	2
all_pins[4]	549	1		T1	2		T2	2		T3	2
all_pins[5]	549	1		T1	2		T2	2		T3	2
all_pins[6]	549	1		T1	2		T2	2		T3	2
all_pins[7]	549	1		T1	2		T2	2		T3	2
all_pins[8]	549	1		T1	2		T2	2		T3	2
all_pins[9]	549	1		T1	2		T2	2		T3	2
all_pins[10]	549	1		T1	2		T2	2		T3	2
all_pins[11]	549	1		T1	2		T2	2		T3	2
all_pins[12]	549	1		T1	2		T2	2		T3	2
all_pins[13]	549	1		T1	2		T2	2		T3	2
all_pins[14]	549	1		T1	2		T2	2		T3	2
all_pins[15]	549	1		T1	2		T2	2		T3	2
all_pins[16]	549	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8444	1		T1	34		T2	34		T3	34
values[0x1]	889	1		T4	1		T5	1		T6	1
transitions[0x0=>0x1]	672	1		T4	1		T5	1		T6	1
transitions[0x1=>0x0]	678	1		T4	1		T5	1		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	381	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	168	1		T4	1		T5	1		T6	1
all_pins[0]	transitions[0x0=>0x1]	152	1		T4	1		T5	1		T6	1
all_pins[0]	transitions[0x1=>0x0]	34	1		T26	2		T28	2		T59	1
all_pins[1]	values[0x0]	499	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	50	1		T26	2		T27	2		T28	2
all_pins[1]	transitions[0x0=>0x1]	36	1		T26	2		T28	2		T59	1
all_pins[1]	transitions[0x1=>0x0]	44	1		T25	3		T26	2		T27	1
all_pins[2]	values[0x0]	491	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	58	1		T25	3		T26	2		T27	3
all_pins[2]	transitions[0x0=>0x1]	36	1		T25	3		T26	1		T27	1
all_pins[2]	transitions[0x1=>0x0]	28	1		T25	2		T26	1		T27	2
all_pins[3]	values[0x0]	499	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	50	1		T25	2		T26	2		T27	4
all_pins[3]	transitions[0x0=>0x1]	37	1		T25	2		T26	2		T27	2
all_pins[3]	transitions[0x1=>0x0]	29	1		T59	2		T62	2		T63	3
all_pins[4]	values[0x0]	507	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	42	1		T27	2		T28	2		T59	2
all_pins[4]	transitions[0x0=>0x1]	29	1		T27	2		T28	1		T59	2
all_pins[4]	transitions[0x1=>0x0]	27	1		T25	1		T26	5		T27	1
all_pins[5]	values[0x0]	509	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	40	1		T25	1		T26	5		T27	1
all_pins[5]	transitions[0x0=>0x1]	34	1		T25	1		T26	3		T27	1
all_pins[5]	transitions[0x1=>0x0]	45	1		T25	3		T26	1		T28	1
all_pins[6]	values[0x0]	498	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	51	1		T25	3		T26	3		T28	1
all_pins[6]	transitions[0x0=>0x1]	39	1		T25	1		T26	2		T28	1
all_pins[6]	transitions[0x1=>0x0]	40	1		T25	2		T26	2		T27	1
all_pins[7]	values[0x0]	497	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	52	1		T25	4		T26	3		T27	1
all_pins[7]	transitions[0x0=>0x1]	41	1		T25	2		T26	3		T27	1
all_pins[7]	transitions[0x1=>0x0]	29	1		T25	2		T27	1		T28	1
all_pins[8]	values[0x0]	509	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	40	1		T25	4		T27	1		T28	1
all_pins[8]	transitions[0x0=>0x1]	25	1		T25	3		T28	1		T59	1
all_pins[8]	transitions[0x1=>0x0]	29	1		T26	2		T28	2		T60	1
all_pins[9]	values[0x0]	505	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	44	1		T25	1		T26	2		T27	1
all_pins[9]	transitions[0x0=>0x1]	35	1		T25	1		T26	2		T27	1
all_pins[9]	transitions[0x1=>0x0]	31	1		T25	1		T26	3		T27	2
all_pins[10]	values[0x0]	509	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	40	1		T25	1		T26	3		T27	2
all_pins[10]	transitions[0x0=>0x1]	26	1		T26	2		T28	2		T60	3
all_pins[10]	transitions[0x1=>0x0]	38	1		T25	1		T26	3		T28	2
all_pins[11]	values[0x0]	497	1		T1	2		T2	2		T3	2
all_pins[11]	values[0x1]	52	1		T25	2		T26	4		T27	2
all_pins[11]	transitions[0x0=>0x1]	36	1		T25	2		T26	4		T27	2
all_pins[11]	transitions[0x1=>0x0]	29	1		T25	3		T27	1		T28	3
all_pins[12]	values[0x0]	504	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	45	1		T25	3		T27	1		T28	4
all_pins[12]	transitions[0x0=>0x1]	32	1		T25	1		T28	3		T59	2
all_pins[12]	transitions[0x1=>0x0]	31	1		T27	1		T28	1		T60	1
all_pins[13]	values[0x0]	505	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	44	1		T25	2		T27	2		T28	2
all_pins[13]	transitions[0x0=>0x1]	35	1		T25	2		T27	1		T28	1
all_pins[13]	transitions[0x1=>0x0]	31	1		T28	3		T59	3		T60	1
all_pins[14]	values[0x0]	509	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	40	1		T27	1		T28	4		T59	3
all_pins[14]	transitions[0x0=>0x1]	33	1		T27	1		T28	3		T59	3
all_pins[14]	transitions[0x1=>0x0]	25	1		T26	1		T63	2		T103	4
all_pins[15]	values[0x0]	517	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	32	1		T26	1		T28	1		T63	3
all_pins[15]	transitions[0x0=>0x1]	23	1		T26	1		T63	2		T103	4
all_pins[15]	transitions[0x1=>0x0]	32	1		T26	4		T27	1		T59	2
all_pins[16]	values[0x0]	508	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	41	1		T26	4		T27	1		T28	1
all_pins[16]	transitions[0x0=>0x1]	23	1		T26	2		T27	1		T28	1
all_pins[16]	transitions[0x1=>0x0]	156	1		T4	1		T5	1		T6	1