Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	186	1		T25	7		T26	7		T27	7
all_values[1]	186	1		T25	7		T26	7		T27	7
all_values[2]	186	1		T25	7		T26	7		T27	7
all_values[3]	186	1		T25	7		T26	7		T27	7
all_values[4]	186	1		T25	7		T26	7		T27	7
all_values[5]	186	1		T25	7		T26	7		T27	7
all_values[6]	186	1		T25	7		T26	7		T27	7
all_values[7]	186	1		T25	7		T26	7		T27	7
all_values[8]	186	1		T25	7		T26	7		T27	7
all_values[9]	186	1		T25	7		T26	7		T27	7
all_values[10]	186	1		T25	7		T26	7		T27	7
all_values[11]	186	1		T25	7		T26	7		T27	7
all_values[12]	186	1		T25	7		T26	7		T27	7
all_values[13]	186	1		T25	7		T26	7		T27	7
all_values[14]	186	1		T25	7		T26	7		T27	7
all_values[15]	186	1		T25	7		T26	7		T27	7
all_values[16]	186	1		T25	7		T26	7		T27	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1752	1		T25	67		T26	68		T27	66
auto[1]	1410	1		T25	52		T26	51		T27	53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	555	1		T25	14		T26	15		T27	6
auto[1]	2607	1		T25	105		T26	104		T27	113

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1891	1		T25	70		T26	72		T27	64
auto[1]	1271	1		T25	49		T26	47		T27	55

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	36	1		T25	1		T59	1		T60	2
all_values[0]	auto[0]	auto[0]	auto[1]	37	1		T25	1		T26	1		T27	1
all_values[0]	auto[0]	auto[1]	auto[0]	13	1		T25	1		T28	1		T60	1
all_values[0]	auto[0]	auto[1]	auto[1]	35	1		T25	2		T26	3		T27	1
all_values[0]	auto[1]	auto[0]	auto[1]	39	1		T25	2		T26	3		T27	2
all_values[0]	auto[1]	auto[1]	auto[1]	26	1		T27	3		T28	1		T59	1
all_values[1]	auto[0]	auto[0]	auto[0]	22	1		T25	1		T26	1		T59	1
all_values[1]	auto[0]	auto[0]	auto[1]	43	1		T25	3		T26	3		T27	1
all_values[1]	auto[0]	auto[1]	auto[0]	6	1		T65	2		T100	1		T105	1
all_values[1]	auto[0]	auto[1]	auto[1]	31	1		T26	1		T27	2		T28	3
all_values[1]	auto[1]	auto[0]	auto[1]	46	1		T25	1		T27	3		T28	1
all_values[1]	auto[1]	auto[1]	auto[1]	38	1		T25	2		T26	2		T27	1
all_values[2]	auto[0]	auto[0]	auto[0]	18	1		T26	1		T59	2		T60	2
all_values[2]	auto[0]	auto[0]	auto[1]	36	1		T25	2		T26	3		T27	2
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T60	1		T65	1		T106	1
all_values[2]	auto[0]	auto[1]	auto[1]	41	1		T25	2		T27	3		T28	1
all_values[2]	auto[1]	auto[0]	auto[1]	39	1		T25	1		T26	2		T27	1
all_values[2]	auto[1]	auto[1]	auto[1]	36	1		T25	2		T26	1		T27	1
all_values[3]	auto[0]	auto[0]	auto[0]	21	1		T26	2		T28	2		T60	1
all_values[3]	auto[0]	auto[0]	auto[1]	44	1		T25	4		T26	2		T28	2
all_values[3]	auto[0]	auto[1]	auto[0]	6	1		T26	1		T51	1		T62	1
all_values[3]	auto[0]	auto[1]	auto[1]	37	1		T26	1		T27	4		T28	2
all_values[3]	auto[1]	auto[0]	auto[1]	44	1		T25	1		T27	2		T59	3
all_values[3]	auto[1]	auto[1]	auto[1]	34	1		T25	2		T26	1		T27	1
all_values[4]	auto[0]	auto[0]	auto[0]	15	1		T26	1		T59	1		T102	1
all_values[4]	auto[0]	auto[0]	auto[1]	45	1		T25	3		T26	3		T27	3
all_values[4]	auto[0]	auto[1]	auto[0]	9	1		T26	1		T28	2		T59	1
all_values[4]	auto[0]	auto[1]	auto[1]	44	1		T25	2		T27	1		T28	3
all_values[4]	auto[1]	auto[0]	auto[1]	41	1		T25	2		T26	2		T27	1
all_values[4]	auto[1]	auto[1]	auto[1]	32	1		T27	2		T28	2		T59	1
all_values[5]	auto[0]	auto[0]	auto[0]	12	1		T65	2		T107	2		T102	1
all_values[5]	auto[0]	auto[0]	auto[1]	46	1		T25	2		T27	1		T28	2
all_values[5]	auto[0]	auto[1]	auto[0]	11	1		T60	2		T51	1		T107	2
all_values[5]	auto[0]	auto[1]	auto[1]	37	1		T25	1		T26	3		T27	3
all_values[5]	auto[1]	auto[0]	auto[1]	49	1		T25	4		T26	1		T27	3
all_values[5]	auto[1]	auto[1]	auto[1]	31	1		T26	3		T28	3		T51	1
all_values[6]	auto[0]	auto[0]	auto[0]	11	1		T27	1		T59	1		T65	1
all_values[6]	auto[0]	auto[0]	auto[1]	43	1		T27	2		T28	4		T60	1
all_values[6]	auto[0]	auto[1]	auto[0]	13	1		T60	3		T51	1		T65	3
all_values[6]	auto[0]	auto[1]	auto[1]	36	1		T25	2		T26	4		T28	1
all_values[6]	auto[1]	auto[0]	auto[1]	46	1		T25	2		T26	1		T27	4
all_values[6]	auto[1]	auto[1]	auto[1]	37	1		T25	3		T26	2		T28	2
all_values[7]	auto[0]	auto[0]	auto[0]	24	1		T25	1		T26	2		T27	2
all_values[7]	auto[0]	auto[0]	auto[1]	34	1		T27	1		T28	2		T59	1
all_values[7]	auto[0]	auto[1]	auto[0]	7	1		T26	2		T60	2		T51	1
all_values[7]	auto[0]	auto[1]	auto[1]	37	1		T25	1		T26	2		T28	1
all_values[7]	auto[1]	auto[0]	auto[1]	49	1		T25	2		T27	3		T28	3
all_values[7]	auto[1]	auto[1]	auto[1]	35	1		T25	3		T26	1		T27	1
all_values[8]	auto[0]	auto[0]	auto[0]	19	1		T28	2		T59	1		T51	1
all_values[8]	auto[0]	auto[0]	auto[1]	48	1		T25	2		T27	2		T28	2
all_values[8]	auto[0]	auto[1]	auto[0]	9	1		T28	2		T60	1		T102	1
all_values[8]	auto[0]	auto[1]	auto[1]	41	1		T25	3		T26	2		T27	1
all_values[8]	auto[1]	auto[0]	auto[1]	38	1		T25	1		T26	5		T27	4
all_values[8]	auto[1]	auto[1]	auto[1]	31	1		T25	1		T28	1		T59	1
all_values[9]	auto[0]	auto[0]	auto[0]	24	1		T27	1		T59	1		T51	1
all_values[9]	auto[0]	auto[0]	auto[1]	36	1		T25	2		T26	4		T28	1
all_values[9]	auto[0]	auto[1]	auto[0]	14	1		T27	1		T60	2		T102	1
all_values[9]	auto[0]	auto[1]	auto[1]	43	1		T25	2		T27	4		T28	2
all_values[9]	auto[1]	auto[0]	auto[1]	37	1		T25	1		T26	2		T27	1
all_values[9]	auto[1]	auto[1]	auto[1]	32	1		T25	2		T26	1		T28	1
all_values[10]	auto[0]	auto[0]	auto[0]	27	1		T25	1		T27	1		T28	1
all_values[10]	auto[0]	auto[0]	auto[1]	41	1		T25	4		T26	2		T28	2
all_values[10]	auto[0]	auto[1]	auto[0]	8	1		T51	1		T102	1		T99	1
all_values[10]	auto[0]	auto[1]	auto[1]	40	1		T26	1		T27	2		T28	2
all_values[10]	auto[1]	auto[0]	auto[1]	41	1		T26	2		T27	1		T28	1
all_values[10]	auto[1]	auto[1]	auto[1]	29	1		T25	2		T26	2		T27	3
all_values[11]	auto[0]	auto[0]	auto[0]	26	1		T28	1		T59	1		T107	1
all_values[11]	auto[0]	auto[0]	auto[1]	27	1		T25	1		T28	1		T60	2
all_values[11]	auto[0]	auto[1]	auto[0]	22	1		T28	2		T59	1		T60	1
all_values[11]	auto[0]	auto[1]	auto[1]	45	1		T25	3		T26	3		T27	3
all_values[11]	auto[1]	auto[0]	auto[1]	31	1		T25	2		T26	1		T27	2
all_values[11]	auto[1]	auto[1]	auto[1]	35	1		T25	1		T26	3		T27	2
all_values[12]	auto[0]	auto[0]	auto[0]	23	1		T25	1		T59	1		T103	1
all_values[12]	auto[0]	auto[0]	auto[1]	31	1		T25	1		T26	4		T27	2
all_values[12]	auto[0]	auto[1]	auto[0]	19	1		T59	1		T103	2		T108	1
all_values[12]	auto[0]	auto[1]	auto[1]	47	1		T25	2		T26	1		T27	3
all_values[12]	auto[1]	auto[0]	auto[1]	33	1		T25	1		T26	2		T27	2
all_values[12]	auto[1]	auto[1]	auto[1]	33	1		T25	2		T28	3		T59	1
all_values[13]	auto[0]	auto[0]	auto[0]	24	1		T25	1		T26	1		T28	3
all_values[13]	auto[0]	auto[0]	auto[1]	37	1		T26	3		T27	2		T28	1
all_values[13]	auto[0]	auto[1]	auto[0]	8	1		T60	1		T62	1		T103	1
all_values[13]	auto[0]	auto[1]	auto[1]	38	1		T25	3		T26	1		T27	1
all_values[13]	auto[1]	auto[0]	auto[1]	46	1		T25	1		T26	2		T27	3
all_values[13]	auto[1]	auto[1]	auto[1]	33	1		T25	2		T27	1		T28	2
all_values[14]	auto[0]	auto[0]	auto[0]	19	1		T26	3		T62	1		T65	1
all_values[14]	auto[0]	auto[0]	auto[1]	39	1		T25	4		T26	1		T27	2
all_values[14]	auto[0]	auto[1]	auto[0]	15	1		T28	1		T103	2		T109	1
all_values[14]	auto[0]	auto[1]	auto[1]	37	1		T25	1		T27	2		T28	2
all_values[14]	auto[1]	auto[0]	auto[1]	48	1		T25	2		T26	3		T27	1
all_values[14]	auto[1]	auto[1]	auto[1]	28	1		T27	2		T28	2		T59	1
all_values[15]	auto[0]	auto[0]	auto[0]	12	1		T25	3		T60	1		T51	1
all_values[15]	auto[0]	auto[0]	auto[1]	51	1		T25	1		T26	1		T27	3
all_values[15]	auto[0]	auto[1]	auto[0]	10	1		T25	2		T51	3		T106	2
all_values[15]	auto[0]	auto[1]	auto[1]	33	1		T26	4		T27	2		T62	1
all_values[15]	auto[1]	auto[0]	auto[1]	50	1		T25	1		T26	2		T27	2
all_values[15]	auto[1]	auto[1]	auto[1]	30	1		T28	1		T62	1		T63	3
all_values[16]	auto[0]	auto[0]	auto[0]	20	1		T25	1		T59	1		T51	2
all_values[16]	auto[0]	auto[0]	auto[1]	39	1		T25	2		T27	2		T28	2
all_values[16]	auto[0]	auto[1]	auto[0]	16	1		T25	1		T28	2		T59	1
all_values[16]	auto[0]	auto[1]	auto[1]	37	1		T26	4		T27	2		T59	1
all_values[16]	auto[1]	auto[0]	auto[1]	45	1		T25	1		T26	2		T27	2
all_values[16]	auto[1]	auto[1]	auto[1]	29	1		T25	2		T26	1		T27	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal