Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.92	94.83	84.31	97.14	31.25	93.34	96.91	96.65

Total test records in report: 269

tests.html | tests1.html | tests2.html | tests3.html | tests4.html

T251	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3098612149			Feb 07 12:47:35 PM PST 24	Feb 07 12:47:37 PM PST 24	71674497 ps
T252	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3909331868			Feb 07 12:47:34 PM PST 24	Feb 07 12:47:36 PM PST 24	148941227 ps
T253	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2339963021			Feb 07 12:47:32 PM PST 24	Feb 07 12:47:35 PM PST 24	130657352 ps
T254	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.599983084			Feb 07 12:47:30 PM PST 24	Feb 07 12:47:32 PM PST 24	30855433 ps
T255	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1736514905			Feb 07 12:47:19 PM PST 24	Feb 07 12:47:22 PM PST 24	50995664 ps
T256	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.744508726			Feb 07 12:47:15 PM PST 24	Feb 07 12:47:19 PM PST 24	117942662 ps
T257	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2820220255			Feb 07 12:47:33 PM PST 24	Feb 07 12:47:35 PM PST 24	100754573 ps
T258	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2466096183			Feb 07 12:47:40 PM PST 24	Feb 07 12:47:42 PM PST 24	27792465 ps
T259	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.21697830			Feb 07 12:47:24 PM PST 24	Feb 07 12:47:25 PM PST 24	26582551 ps
T260	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.35825641			Feb 07 12:47:38 PM PST 24	Feb 07 12:47:40 PM PST 24	26198627 ps
T261	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3476854086			Feb 07 12:47:33 PM PST 24	Feb 07 12:47:36 PM PST 24	55488473 ps
T262	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4288922639			Feb 07 12:47:38 PM PST 24	Feb 07 12:47:40 PM PST 24	67059966 ps
T263	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1772488629			Feb 07 12:47:31 PM PST 24	Feb 07 12:47:33 PM PST 24	47857856 ps
T264	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1007156312			Feb 07 12:47:24 PM PST 24	Feb 07 12:47:25 PM PST 24	26682084 ps
T265	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3338145046			Feb 07 12:47:29 PM PST 24	Feb 07 12:47:34 PM PST 24	366534574 ps
T266	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3731978841			Feb 07 12:47:16 PM PST 24	Feb 07 12:47:18 PM PST 24	40486424 ps
T267	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2933146580			Feb 07 12:47:18 PM PST 24	Feb 07 12:47:21 PM PST 24	39077757 ps
T268	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.195340797			Feb 07 12:47:35 PM PST 24	Feb 07 12:47:38 PM PST 24	91525413 ps
T269	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3059119753			Feb 07 12:47:16 PM PST 24	Feb 07 12:47:19 PM PST 24	150020834 ps

Test location	/workspace/coverage/default/20.usbdev_smoke.394936550
Short name	T4
Test name
Test status
Simulation time	8371862238 ps
CPU time	7.33 seconds
Started	Feb 07 12:54:25 PM PST 24
Finished	Feb 07 12:54:45 PM PST 24
Peak memory	201904 kb
Host	smart-6ebbd446-3c9d-47ce-9aa5-883210989959
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39493 6550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.394936550
Directory	/workspace/20.usbdev_smoke/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3509966373
Short name	T15
Test name
Test status
Simulation time	238541561 ps
CPU time	4.31 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:38 PM PST 24
Peak memory	202400 kb
Host	smart-b67e5863-3e98-4ffa-8550-d537113947ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3509966373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3509966373
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.3817872810
Short name	T28
Test name
Test status
Simulation time	28851708 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:33 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	201520 kb
Host	smart-3a88d691-40d6-4518-806e-789b6f482bec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3817872810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3817872810
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/default/44.usbdev_av_buffer.333460239
Short name	T9
Test name
Test status
Simulation time	8372604430 ps
CPU time	7.52 seconds
Started	Feb 07 12:54:30 PM PST 24
Finished	Feb 07 12:54:46 PM PST 24
Peak memory	201924 kb
Host	smart-11c39961-61d2-49e5-a9ea-13665b463e6e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33346 0239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.333460239
Directory	/workspace/44.usbdev_av_buffer/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2246654002
Short name	T16
Test name
Test status
Simulation time	203029515 ps
CPU time	2.6 seconds
Started	Feb 07 12:47:24 PM PST 24
Finished	Feb 07 12:47:28 PM PST 24
Peak memory	202456 kb
Host	smart-475903b5-4587-4b18-a092-fccb992014dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2246654002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2246654002
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.2294663887
Short name	T19
Test name
Test status
Simulation time	215687069 ps
CPU time	1.08 seconds
Started	Feb 07 12:54:01 PM PST 24
Finished	Feb 07 12:54:04 PM PST 24
Peak memory	221732 kb
Host	smart-d2920bc7-87ef-4686-bb5d-6f9e53c8a3ef
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2294663887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2294663887
Directory	/workspace/0.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.36958420
Short name	T103
Test name
Test status
Simulation time	27072807 ps
CPU time	0.65 seconds
Started	Feb 07 12:47:30 PM PST 24
Finished	Feb 07 12:47:31 PM PST 24
Peak memory	201516 kb
Host	smart-3d599589-594a-4aae-8d44-9f0082c26dc3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=36958420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.36958420
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3899558945
Short name	T48
Test name
Test status
Simulation time	79750954 ps
CPU time	1.06 seconds
Started	Feb 07 12:47:29 PM PST 24
Finished	Feb 07 12:47:31 PM PST 24
Peak memory	202276 kb
Host	smart-aaa53f71-5140-49c9-858d-dd4205abb48d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899558945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.3899558945
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1075959326
Short name	T60
Test name
Test status
Simulation time	30338687 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:45 PM PST 24
Finished	Feb 07 12:47:46 PM PST 24
Peak memory	201468 kb
Host	smart-1a21a48f-31dc-4fef-9b61-a794e86e0b28
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1075959326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1075959326
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.4274556661
Short name	T61
Test name
Test status
Simulation time	69779463 ps
CPU time	2.11 seconds
Started	Feb 07 12:47:19 PM PST 24
Finished	Feb 07 12:47:22 PM PST 24
Peak memory	202388 kb
Host	smart-d1dd8757-76b8-472d-8531-c10c3eaa1b38
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4274556661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.4274556661
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1444129742
Short name	T250
Test name
Test status
Simulation time	24029492 ps
CPU time	0.64 seconds
Started	Feb 07 12:47:27 PM PST 24
Finished	Feb 07 12:47:29 PM PST 24
Peak memory	201456 kb
Host	smart-833a40da-86fc-4c19-bece-a12579ab5e56
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1444129742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1444129742
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3520285181
Short name	T111
Test name
Test status
Simulation time	293856613 ps
CPU time	4.16 seconds
Started	Feb 07 12:47:34 PM PST 24
Finished	Feb 07 12:47:40 PM PST 24
Peak memory	202456 kb
Host	smart-fcd7a751-cae5-428e-90c0-e028e8a2e02c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3520285181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3520285181
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2907126628
Short name	T20
Test name
Test status
Simulation time	30960671 ps
CPU time	0.74 seconds
Started	Feb 07 12:47:08 PM PST 24
Finished	Feb 07 12:47:10 PM PST 24
Peak memory	202112 kb
Host	smart-abf231e7-33a8-45e1-a060-bd0be71becf2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907126628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2907126628
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.541285314
Short name	T51
Test name
Test status
Simulation time	18345018 ps
CPU time	0.63 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:37 PM PST 24
Peak memory	201528 kb
Host	smart-63fc43fb-04a9-4c64-9553-5f5ffd947265
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=541285314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.541285314
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/default/22.usbdev_av_buffer.447961781
Short name	T39
Test name
Test status
Simulation time	8370590926 ps
CPU time	7.45 seconds
Started	Feb 07 12:54:15 PM PST 24
Finished	Feb 07 12:54:23 PM PST 24
Peak memory	201888 kb
Host	smart-4810ff1d-09b5-4011-8212-a41f487bb845
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44796 1781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.447961781
Directory	/workspace/22.usbdev_av_buffer/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.170528302
Short name	T115
Test name
Test status
Simulation time	47286500 ps
CPU time	1.19 seconds
Started	Feb 07 12:47:23 PM PST 24
Finished	Feb 07 12:47:25 PM PST 24
Peak memory	211588 kb
Host	smart-32f32a7c-df4e-4cb4-941f-48fec558d27e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170528302 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.170528302
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1134128560
Short name	T113
Test name
Test status
Simulation time	345370140 ps
CPU time	3.03 seconds
Started	Feb 07 12:47:42 PM PST 24
Finished	Feb 07 12:47:46 PM PST 24
Peak memory	202404 kb
Host	smart-3bf59d57-bfef-4ebe-8943-d29548f7d03f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1134128560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1134128560
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2720592035
Short name	T102
Test name
Test status
Simulation time	37271903 ps
CPU time	0.65 seconds
Started	Feb 07 12:47:37 PM PST 24
Finished	Feb 07 12:47:39 PM PST 24
Peak memory	201484 kb
Host	smart-e7bfabed-c030-4be8-895d-1da27c7b10ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2720592035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2720592035
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.571794663
Short name	T214
Test name
Test status
Simulation time	86971090 ps
CPU time	2.51 seconds
Started	Feb 07 12:47:42 PM PST 24
Finished	Feb 07 12:47:45 PM PST 24
Peak memory	202460 kb
Host	smart-cfacaf8c-4571-482e-bf31-e2a086c7b6c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=571794663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.571794663
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/23.usbdev_pkt_received.560190564
Short name	T13
Test name
Test status
Simulation time	8412667401 ps
CPU time	8.19 seconds
Started	Feb 07 12:53:57 PM PST 24
Finished	Feb 07 12:54:06 PM PST 24
Peak memory	201860 kb
Host	smart-23bda91d-7f8d-4681-a59e-66ecc98d8b5d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56019 0564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.560190564
Directory	/workspace/23.usbdev_pkt_received/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4173323384
Short name	T69
Test name
Test status
Simulation time	365395699 ps
CPU time	8.39 seconds
Started	Feb 07 12:47:17 PM PST 24
Finished	Feb 07 12:47:26 PM PST 24
Peak memory	202332 kb
Host	smart-ce4ef457-0c6f-41d4-a1d7-582e87142621
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173323384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.4173323384
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/default/12.usbdev_pkt_received.3665065741
Short name	T194
Test name
Test status
Simulation time	8396983446 ps
CPU time	6.83 seconds
Started	Feb 07 12:54:08 PM PST 24
Finished	Feb 07 12:54:16 PM PST 24
Peak memory	201864 kb
Host	smart-5022da17-98cf-4565-87b1-f9787d6bc09b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36650 65741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3665065741
Directory	/workspace/12.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/14.usbdev_av_buffer.3514776218
Short name	T87
Test name
Test status
Simulation time	8367959661 ps
CPU time	8.05 seconds
Started	Feb 07 12:54:14 PM PST 24
Finished	Feb 07 12:54:23 PM PST 24
Peak memory	201896 kb
Host	smart-242b85f2-7afb-42e6-9f90-e6db11b2e10f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35147 76218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3514776218
Directory	/workspace/14.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/21.usbdev_av_buffer.169004785
Short name	T11
Test name
Test status
Simulation time	8369905032 ps
CPU time	7.59 seconds
Started	Feb 07 12:54:17 PM PST 24
Finished	Feb 07 12:54:25 PM PST 24
Peak memory	201936 kb
Host	smart-6dda7f3c-38dc-40e9-affd-e8616223c01a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900 4785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.169004785
Directory	/workspace/21.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/48.usbdev_av_buffer.2715987522
Short name	T34
Test name
Test status
Simulation time	8369013072 ps
CPU time	7.63 seconds
Started	Feb 07 12:54:35 PM PST 24
Finished	Feb 07 12:54:51 PM PST 24
Peak memory	201896 kb
Host	smart-7de817bb-f00b-45a7-a8ec-2c1d499593c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159 87522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2715987522
Directory	/workspace/48.usbdev_av_buffer/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.579450745
Short name	T232
Test name
Test status
Simulation time	116130006 ps
CPU time	3.22 seconds
Started	Feb 07 12:47:18 PM PST 24
Finished	Feb 07 12:47:22 PM PST 24
Peak memory	202364 kb
Host	smart-358a806a-7186-4cad-abb2-4f9c511c1431
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579450745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.579450745
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3298707550
Short name	T74
Test name
Test status
Simulation time	42754232 ps
CPU time	0.98 seconds
Started	Feb 07 12:47:07 PM PST 24
Finished	Feb 07 12:47:10 PM PST 24
Peak memory	202300 kb
Host	smart-949a34f9-918f-467b-bfa3-39ad18d74acd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298707550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3298707550
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.2421049157
Short name	T109
Test name
Test status
Simulation time	25569276 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:08 PM PST 24
Finished	Feb 07 12:47:10 PM PST 24
Peak memory	201544 kb
Host	smart-b22927ea-3579-45bb-a12c-03a6385c57e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2421049157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2421049157
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1481017811
Short name	T68
Test name
Test status
Simulation time	171247116 ps
CPU time	2.34 seconds
Started	Feb 07 12:47:21 PM PST 24
Finished	Feb 07 12:47:25 PM PST 24
Peak memory	202092 kb
Host	smart-b5a1a35a-e8d6-4df6-a5b0-3b8d41e39881
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1481017811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1481017811
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1901148915
Short name	T229
Test name
Test status
Simulation time	147471621 ps
CPU time	3.72 seconds
Started	Feb 07 12:47:07 PM PST 24
Finished	Feb 07 12:47:13 PM PST 24
Peak memory	202376 kb
Host	smart-55883f65-fdbd-4833-8a35-55adabecd0d6
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1901148915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1901148915
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3739060532
Short name	T46
Test name
Test status
Simulation time	65439698 ps
CPU time	1 seconds
Started	Feb 07 12:47:18 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202388 kb
Host	smart-3fa1980a-5ce1-4127-b4db-64e994832686
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739060532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.3739060532
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.968904746
Short name	T56
Test name
Test status
Simulation time	332112008 ps
CPU time	3.58 seconds
Started	Feb 07 12:47:21 PM PST 24
Finished	Feb 07 12:47:26 PM PST 24
Peak memory	202216 kb
Host	smart-735b0095-f616-4a72-a197-0d8eabf56e78
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=968904746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.968904746
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1543352682
Short name	T112
Test name
Test status
Simulation time	269301518 ps
CPU time	4.32 seconds
Started	Feb 07 12:47:11 PM PST 24
Finished	Feb 07 12:47:16 PM PST 24
Peak memory	202296 kb
Host	smart-dfaadcc1-2ae7-4d62-b86a-65cb3e62dec6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1543352682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1543352682
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1487712129
Short name	T24
Test name
Test status
Simulation time	117819784 ps
CPU time	2.98 seconds
Started	Feb 07 12:47:16 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202312 kb
Host	smart-4ade3f60-9832-469d-9948-fee2e3b92d1f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487712129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1487712129
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2457426199
Short name	T23
Test name
Test status
Simulation time	45212361 ps
CPU time	0.83 seconds
Started	Feb 07 12:47:25 PM PST 24
Finished	Feb 07 12:47:27 PM PST 24
Peak memory	201668 kb
Host	smart-be2c7798-bfe9-4255-80b1-6c6aa35b3a4e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457426199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2457426199
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2933146580
Short name	T267
Test name
Test status
Simulation time	39077757 ps
CPU time	1.42 seconds
Started	Feb 07 12:47:18 PM PST 24
Finished	Feb 07 12:47:21 PM PST 24
Peak memory	210640 kb
Host	smart-256cb583-ba84-4b1b-930b-4aef567d62e1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933146580 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.2933146580
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.945385120
Short name	T27
Test name
Test status
Simulation time	26466793 ps
CPU time	0.67 seconds
Started	Feb 07 12:47:15 PM PST 24
Finished	Feb 07 12:47:17 PM PST 24
Peak memory	201508 kb
Host	smart-dd585cde-9a04-4c1a-907e-74e107b6f05a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=945385120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.945385120
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2651312450
Short name	T222
Test name
Test status
Simulation time	154494337 ps
CPU time	3.72 seconds
Started	Feb 07 12:47:27 PM PST 24
Finished	Feb 07 12:47:32 PM PST 24
Peak memory	202228 kb
Host	smart-1d4c4c2b-9dce-43ce-bba1-38365de1857e
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2651312450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2651312450
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1461716998
Short name	T218
Test name
Test status
Simulation time	119423411 ps
CPU time	1.49 seconds
Started	Feb 07 12:47:21 PM PST 24
Finished	Feb 07 12:47:24 PM PST 24
Peak memory	202260 kb
Host	smart-6c05321f-970b-4e93-8b31-6252673b90c7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461716998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.1461716998
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1736514905
Short name	T255
Test name
Test status
Simulation time	50995664 ps
CPU time	1.53 seconds
Started	Feb 07 12:47:19 PM PST 24
Finished	Feb 07 12:47:22 PM PST 24
Peak memory	202500 kb
Host	smart-5043b452-19bb-4ed8-a9df-cbb4af4f842f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1736514905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1736514905
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2936811628
Short name	T241
Test name
Test status
Simulation time	39329892 ps
CPU time	1.08 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:38 PM PST 24
Peak memory	201848 kb
Host	smart-2120a08f-b9e0-4e0a-8a41-0005dae6a41a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936811628 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2936811628
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.546065311
Short name	T50
Test name
Test status
Simulation time	24168019 ps
CPU time	0.73 seconds
Started	Feb 07 12:47:29 PM PST 24
Finished	Feb 07 12:47:31 PM PST 24
Peak memory	201988 kb
Host	smart-78452235-607f-44d9-b729-478dd702cfad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546065311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.546065311
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1929820503
Short name	T21
Test name
Test status
Simulation time	123333280 ps
CPU time	1.44 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202212 kb
Host	smart-d17af6a5-5fd9-4df2-b38d-ba1f6ff10b25
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929820503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.1929820503
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1867570276
Short name	T221
Test name
Test status
Simulation time	106801281 ps
CPU time	1.73 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:33 PM PST 24
Peak memory	202220 kb
Host	smart-2992f974-d9c4-47d6-95ef-ac954775cb9c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1867570276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1867570276
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2331936260
Short name	T240
Test name
Test status
Simulation time	284238041 ps
CPU time	2.81 seconds
Started	Feb 07 12:47:23 PM PST 24
Finished	Feb 07 12:47:26 PM PST 24
Peak memory	202320 kb
Host	smart-6a7d7f85-53bc-424c-8206-74ce71daac69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2331936260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2331936260
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2835180153
Short name	T220
Test name
Test status
Simulation time	45440613 ps
CPU time	1.5 seconds
Started	Feb 07 12:47:39 PM PST 24
Finished	Feb 07 12:47:43 PM PST 24
Peak memory	210560 kb
Host	smart-93432ad2-9dc5-49fe-a456-99d7626a8987
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835180153 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2835180153
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2698792185
Short name	T70
Test name
Test status
Simulation time	36029200 ps
CPU time	0.81 seconds
Started	Feb 07 12:47:39 PM PST 24
Finished	Feb 07 12:47:41 PM PST 24
Peak memory	202184 kb
Host	smart-92083949-665e-4b49-b5c7-2a19dd30ff3c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698792185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2698792185
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1007156312
Short name	T264
Test name
Test status
Simulation time	26682084 ps
CPU time	0.61 seconds
Started	Feb 07 12:47:24 PM PST 24
Finished	Feb 07 12:47:25 PM PST 24
Peak memory	201532 kb
Host	smart-97d1c8a1-2508-42dd-b90b-89e779f862b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1007156312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1007156312
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2499548675
Short name	T55
Test name
Test status
Simulation time	84029422 ps
CPU time	2.53 seconds
Started	Feb 07 12:47:29 PM PST 24
Finished	Feb 07 12:47:32 PM PST 24
Peak memory	202412 kb
Host	smart-afdf4c41-c132-4f9e-97fa-36217aa9e38f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2499548675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2499548675
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.570416238
Short name	T207
Test name
Test status
Simulation time	61115787 ps
CPU time	0.99 seconds
Started	Feb 07 12:47:29 PM PST 24
Finished	Feb 07 12:47:31 PM PST 24
Peak memory	202188 kb
Host	smart-38c43e68-a6b8-4e28-8825-0cab76847e8a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570416238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.570416238
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.201009332
Short name	T91
Test name
Test status
Simulation time	161468121 ps
CPU time	1.52 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:34 PM PST 24
Peak memory	202224 kb
Host	smart-92d2c75e-980c-4c03-a7d8-42220d4cd029
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201009332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c sr_outstanding.201009332
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3271084583
Short name	T116
Test name
Test status
Simulation time	24108540 ps
CPU time	0.94 seconds
Started	Feb 07 12:47:27 PM PST 24
Finished	Feb 07 12:47:29 PM PST 24
Peak memory	202476 kb
Host	smart-22145002-2fcc-451e-a94c-3b91c0de7f1b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271084583 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.3271084583
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1094889973
Short name	T67
Test name
Test status
Simulation time	55789407 ps
CPU time	0.94 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202392 kb
Host	smart-ed255e80-0bf5-4195-a54a-c56570170146
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094889973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1094889973
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.4210916046
Short name	T105
Test name
Test status
Simulation time	19296612 ps
CPU time	0.63 seconds
Started	Feb 07 12:47:38 PM PST 24
Finished	Feb 07 12:47:41 PM PST 24
Peak memory	201532 kb
Host	smart-691964c2-40e7-4fd6-9a85-86a6c7d1521a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4210916046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.4210916046
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3481970652
Short name	T226
Test name
Test status
Simulation time	41173015 ps
CPU time	1.04 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202376 kb
Host	smart-b5377cf4-bfc8-447b-8911-f2adee104ec0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481970652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.3481970652
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.128559247
Short name	T213
Test name
Test status
Simulation time	104556161 ps
CPU time	1.45 seconds
Started	Feb 07 12:47:19 PM PST 24
Finished	Feb 07 12:47:22 PM PST 24
Peak memory	202392 kb
Host	smart-7561d641-d669-48b9-9a9b-f1dc06c96002
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=128559247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.128559247
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.599983084
Short name	T254
Test name
Test status
Simulation time	30855433 ps
CPU time	1.18 seconds
Started	Feb 07 12:47:30 PM PST 24
Finished	Feb 07 12:47:32 PM PST 24
Peak memory	202408 kb
Host	smart-75988e27-6c09-410c-a20f-4e9d63d81704
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599983084 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.599983084
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4246048974
Short name	T242
Test name
Test status
Simulation time	51317723 ps
CPU time	0.87 seconds
Started	Feb 07 12:47:22 PM PST 24
Finished	Feb 07 12:47:24 PM PST 24
Peak memory	202184 kb
Host	smart-affc1cdf-1f9a-4432-9199-f104cc3facf5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246048974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4246048974
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3512605136
Short name	T45
Test name
Test status
Simulation time	39436193 ps
CPU time	1 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202224 kb
Host	smart-0c59d2a3-a18d-4710-98e9-9b47c5d5cd8c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512605136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.3512605136
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3808061976
Short name	T93
Test name
Test status
Simulation time	165441719 ps
CPU time	2.04 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202284 kb
Host	smart-10f2c1bc-1e0b-41da-8b61-cff39d6a88f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3808061976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3808061976
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2192809005
Short name	T238
Test name
Test status
Simulation time	33365851 ps
CPU time	1.05 seconds
Started	Feb 07 12:47:29 PM PST 24
Finished	Feb 07 12:47:31 PM PST 24
Peak memory	202416 kb
Host	smart-d67d719d-b041-4853-a8e3-1aa4231c1227
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192809005 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.2192809005
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1772488629
Short name	T263
Test name
Test status
Simulation time	47857856 ps
CPU time	0.82 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:33 PM PST 24
Peak memory	202160 kb
Host	smart-62b11fe2-13cc-4d3b-926e-d1a6a282732a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772488629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1772488629
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3328888169
Short name	T249
Test name
Test status
Simulation time	90357987 ps
CPU time	1.2 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:33 PM PST 24
Peak memory	202376 kb
Host	smart-e3e00392-f241-4a0a-b67e-81000ec8ac4f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328888169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.3328888169
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.100412338
Short name	T239
Test name
Test status
Simulation time	199554507 ps
CPU time	2.47 seconds
Started	Feb 07 12:47:39 PM PST 24
Finished	Feb 07 12:47:43 PM PST 24
Peak memory	202468 kb
Host	smart-3ed8d108-26f2-465c-b770-6a858140e9fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=100412338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.100412338
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3338145046
Short name	T265
Test name
Test status
Simulation time	366534574 ps
CPU time	4.45 seconds
Started	Feb 07 12:47:29 PM PST 24
Finished	Feb 07 12:47:34 PM PST 24
Peak memory	202396 kb
Host	smart-c1b2f29e-4457-4236-a7fd-d70986705927
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3338145046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3338145046
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3794879133
Short name	T228
Test name
Test status
Simulation time	62280759 ps
CPU time	1.47 seconds
Started	Feb 07 12:47:34 PM PST 24
Finished	Feb 07 12:47:36 PM PST 24
Peak memory	218856 kb
Host	smart-bce61202-c4cb-47f6-9c1d-39b95e0b3faf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794879133 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.3794879133
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2966575680
Short name	T47
Test name
Test status
Simulation time	59805267 ps
CPU time	0.87 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:32 PM PST 24
Peak memory	202084 kb
Host	smart-c1b68ea9-7fd2-4276-8d0d-e6e8edb0ce28
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966575680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2966575680
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.2970635185
Short name	T65
Test name
Test status
Simulation time	20717709 ps
CPU time	0.62 seconds
Started	Feb 07 12:47:33 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	201460 kb
Host	smart-f761f600-dcd7-432a-a50f-775c92866696
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2970635185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2970635185
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3098612149
Short name	T251
Test name
Test status
Simulation time	71674497 ps
CPU time	0.97 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:37 PM PST 24
Peak memory	202360 kb
Host	smart-ca78363b-233e-4a37-b09e-e307893514c4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098612149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.3098612149
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2820220255
Short name	T257
Test name
Test status
Simulation time	100754573 ps
CPU time	1.45 seconds
Started	Feb 07 12:47:33 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202400 kb
Host	smart-b61a64f6-1a89-4638-9009-5027afd19c93
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2820220255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2820220255
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3476854086
Short name	T261
Test name
Test status
Simulation time	55488473 ps
CPU time	1.29 seconds
Started	Feb 07 12:47:33 PM PST 24
Finished	Feb 07 12:47:36 PM PST 24
Peak memory	210692 kb
Host	smart-a657f737-5b3e-4339-83fc-02874427089b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476854086 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.3476854086
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.230249861
Short name	T101
Test name
Test status
Simulation time	75158172 ps
CPU time	1.08 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:32 PM PST 24
Peak memory	202360 kb
Host	smart-6f825d06-e00b-49af-8dc4-26a1c43528cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230249861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.230249861
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3909331868
Short name	T252
Test name
Test status
Simulation time	148941227 ps
CPU time	1.5 seconds
Started	Feb 07 12:47:34 PM PST 24
Finished	Feb 07 12:47:36 PM PST 24
Peak memory	202372 kb
Host	smart-208f2852-fac0-4561-8fe3-5da8d2a48b0b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909331868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.3909331868
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2231484216
Short name	T52
Test name
Test status
Simulation time	54999250 ps
CPU time	1.39 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202416 kb
Host	smart-74153f9e-79dd-4cf4-bf50-c8c2f1b2f12b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2231484216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2231484216
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.195340797
Short name	T268
Test name
Test status
Simulation time	91525413 ps
CPU time	1.67 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:38 PM PST 24
Peak memory	210468 kb
Host	smart-96fd65a9-44b8-4de9-b80e-f06072466165
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195340797 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.195340797
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.448794
Short name	T72
Test name
Test status
Simulation time	41806883 ps
CPU time	0.96 seconds
Started	Feb 07 12:47:33 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202320 kb
Host	smart-66409099-3cbd-4c6c-bbbb-f7ef9d159a69
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.448794
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1857863353
Short name	T206
Test name
Test status
Simulation time	68873488 ps
CPU time	1.04 seconds
Started	Feb 07 12:47:33 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202384 kb
Host	smart-a52ff77e-76b4-46eb-9f56-16db63d792b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857863353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.1857863353
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2100635482
Short name	T223
Test name
Test status
Simulation time	54345501 ps
CPU time	1.77 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:33 PM PST 24
Peak memory	202432 kb
Host	smart-78da03d9-770f-42ac-b2de-fe5598b4246a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2100635482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2100635482
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.505245184
Short name	T97
Test name
Test status
Simulation time	451041583 ps
CPU time	3.05 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:40 PM PST 24
Peak memory	202216 kb
Host	smart-d755d1e1-7c47-4b78-9cbe-0dcc38be1e99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=505245184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.505245184
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1161563430
Short name	T96
Test name
Test status
Simulation time	44096186 ps
CPU time	0.92 seconds
Started	Feb 07 12:47:34 PM PST 24
Finished	Feb 07 12:47:36 PM PST 24
Peak memory	202456 kb
Host	smart-f3c761af-688e-4f09-a153-603ee23faa66
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161563430 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.1161563430
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2160640451
Short name	T219
Test name
Test status
Simulation time	46153394 ps
CPU time	0.8 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:32 PM PST 24
Peak memory	202052 kb
Host	smart-20d20f0f-6f8a-4860-84d2-2963468ba8cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160640451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2160640451
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.1958103101
Short name	T108
Test name
Test status
Simulation time	20094724 ps
CPU time	0.64 seconds
Started	Feb 07 12:47:31 PM PST 24
Finished	Feb 07 12:47:33 PM PST 24
Peak memory	201448 kb
Host	smart-1593c976-3210-4d5f-ba7a-777be3ea5814
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1958103101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1958103101
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2910550339
Short name	T215
Test name
Test status
Simulation time	65488835 ps
CPU time	1.07 seconds
Started	Feb 07 12:47:30 PM PST 24
Finished	Feb 07 12:47:32 PM PST 24
Peak memory	202320 kb
Host	smart-64961ee2-e834-4296-89fc-51ae55c2ce15
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910550339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.2910550339
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1074140157
Short name	T243
Test name
Test status
Simulation time	202266447 ps
CPU time	2.02 seconds
Started	Feb 07 12:47:17 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202308 kb
Host	smart-801e76f8-6fb7-495e-8ade-c5be1e85ad3d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074140157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1074140157
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2702857222
Short name	T216
Test name
Test status
Simulation time	30221037 ps
CPU time	0.9 seconds
Started	Feb 07 12:47:22 PM PST 24
Finished	Feb 07 12:47:24 PM PST 24
Peak memory	210644 kb
Host	smart-fbf28bcc-8b25-423f-81f8-ab31dbbfe45c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702857222 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.2702857222
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.953857875
Short name	T208
Test name
Test status
Simulation time	30822399 ps
CPU time	0.74 seconds
Started	Feb 07 12:47:14 PM PST 24
Finished	Feb 07 12:47:16 PM PST 24
Peak memory	202064 kb
Host	smart-09f20a52-aaae-4075-b984-29d5166c64e4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953857875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.953857875
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3367394047
Short name	T76
Test name
Test status
Simulation time	64383472 ps
CPU time	2.09 seconds
Started	Feb 07 12:47:16 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202428 kb
Host	smart-b5dea10d-41d5-4432-99bd-50b395189cfb
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3367394047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3367394047
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3318710685
Short name	T209
Test name
Test status
Simulation time	132556403 ps
CPU time	2.23 seconds
Started	Feb 07 12:47:17 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202376 kb
Host	smart-388cd90b-2db7-4ef3-8556-b795792d0bab
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3318710685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3318710685
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2958053346
Short name	T205
Test name
Test status
Simulation time	97319785 ps
CPU time	1.04 seconds
Started	Feb 07 12:47:18 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202388 kb
Host	smart-e9ab378b-5c4f-47bd-b4df-f55246131879
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958053346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.2958053346
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3556463642
Short name	T57
Test name
Test status
Simulation time	62671506 ps
CPU time	1.65 seconds
Started	Feb 07 12:47:17 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202500 kb
Host	smart-a1bfffec-65b9-43f7-b018-f0e91755f587
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3556463642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3556463642
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2654938217
Short name	T77
Test name
Test status
Simulation time	149886939 ps
CPU time	2.45 seconds
Started	Feb 07 12:47:23 PM PST 24
Finished	Feb 07 12:47:26 PM PST 24
Peak memory	202328 kb
Host	smart-abb1e602-d691-4167-9e1e-75cdf6f688a8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2654938217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2654938217
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.1926487050
Short name	T100
Test name
Test status
Simulation time	24281384 ps
CPU time	0.64 seconds
Started	Feb 07 12:47:40 PM PST 24
Finished	Feb 07 12:47:42 PM PST 24
Peak memory	201448 kb
Host	smart-d8b2a804-c8da-4b9d-9470-a61e7e402618
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1926487050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1926487050
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.705791
Short name	T246
Test name
Test status
Simulation time	25961801 ps
CPU time	0.68 seconds
Started	Feb 07 12:47:38 PM PST 24
Finished	Feb 07 12:47:40 PM PST 24
Peak memory	201496 kb
Host	smart-19142eb4-3b52-484e-85c8-340a0ea96759
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=705791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.705791
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.3144174324
Short name	T62
Test name
Test status
Simulation time	37985693 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:37 PM PST 24
Finished	Feb 07 12:47:39 PM PST 24
Peak memory	201452 kb
Host	smart-b86f3e7a-a2fb-4cc1-a726-9072f6bb40d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3144174324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3144174324
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2795256588
Short name	T234
Test name
Test status
Simulation time	19125443 ps
CPU time	0.6 seconds
Started	Feb 07 12:47:40 PM PST 24
Finished	Feb 07 12:47:42 PM PST 24
Peak memory	201540 kb
Host	smart-6d314d70-bc3b-4bab-855d-3da5d4d361ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2795256588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2795256588
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.4216807132
Short name	T26
Test name
Test status
Simulation time	27786757 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:36 PM PST 24
Finished	Feb 07 12:47:38 PM PST 24
Peak memory	201468 kb
Host	smart-e8055c35-5d2b-474f-907e-59dd16f2f57d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4216807132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.4216807132
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.744508726
Short name	T256
Test name
Test status
Simulation time	117942662 ps
CPU time	2.97 seconds
Started	Feb 07 12:47:15 PM PST 24
Finished	Feb 07 12:47:19 PM PST 24
Peak memory	202312 kb
Host	smart-bd145038-aeac-40ea-a6ca-4735e715391c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744508726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.744508726
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1435475913
Short name	T22
Test name
Test status
Simulation time	54614894 ps
CPU time	0.84 seconds
Started	Feb 07 12:47:19 PM PST 24
Finished	Feb 07 12:47:22 PM PST 24
Peak memory	202152 kb
Host	smart-64c212a1-cb85-4a98-9cf6-e611a62dd08f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435475913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1435475913
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1106700165
Short name	T224
Test name
Test status
Simulation time	51318793 ps
CPU time	1.41 seconds
Started	Feb 07 12:47:17 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	210676 kb
Host	smart-eefe37d9-0d8b-42d8-ac51-a3920a2a1f72
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106700165 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.1106700165
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3731978841
Short name	T266
Test name
Test status
Simulation time	40486424 ps
CPU time	1.02 seconds
Started	Feb 07 12:47:16 PM PST 24
Finished	Feb 07 12:47:18 PM PST 24
Peak memory	202180 kb
Host	smart-232c3a5b-65ca-4a70-9ad9-85e9b185e146
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731978841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3731978841
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3374892159
Short name	T99
Test name
Test status
Simulation time	36147956 ps
CPU time	0.65 seconds
Started	Feb 07 12:47:17 PM PST 24
Finished	Feb 07 12:47:19 PM PST 24
Peak memory	201536 kb
Host	smart-40fac97a-e6dc-4ed4-997f-f8e3b8dff4c0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3374892159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3374892159
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3059119753
Short name	T269
Test name
Test status
Simulation time	150020834 ps
CPU time	2.2 seconds
Started	Feb 07 12:47:16 PM PST 24
Finished	Feb 07 12:47:19 PM PST 24
Peak memory	202420 kb
Host	smart-83e9e31c-f42f-406f-bc31-967fa8ecdf25
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3059119753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3059119753
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.394466019
Short name	T89
Test name
Test status
Simulation time	42484302 ps
CPU time	1.22 seconds
Started	Feb 07 12:47:27 PM PST 24
Finished	Feb 07 12:47:29 PM PST 24
Peak memory	202508 kb
Host	smart-3d9931dc-554e-47a8-b236-007a870a4a4f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=394466019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.394466019
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1993838054
Short name	T64
Test name
Test status
Simulation time	251587499 ps
CPU time	2.77 seconds
Started	Feb 07 12:47:16 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202392 kb
Host	smart-7cb46ff9-42ed-4bd8-9a04-b8b72c0bc8a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1993838054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1993838054
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.2985282723
Short name	T107
Test name
Test status
Simulation time	130990944 ps
CPU time	0.75 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:37 PM PST 24
Peak memory	201608 kb
Host	smart-e6d155ef-ef71-4f5d-b267-df91f0f694b5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2985282723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2985282723
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3977719339
Short name	T244
Test name
Test status
Simulation time	32244212 ps
CPU time	0.64 seconds
Started	Feb 07 12:47:38 PM PST 24
Finished	Feb 07 12:47:40 PM PST 24
Peak memory	201520 kb
Host	smart-8b261042-4148-42ef-b140-b4cc4ead7e1d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3977719339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3977719339
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2974000654
Short name	T235
Test name
Test status
Simulation time	36771250 ps
CPU time	0.64 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:37 PM PST 24
Peak memory	201524 kb
Host	smart-a55865b5-f336-4db3-9f38-106379a69625
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2974000654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2974000654
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.5693836
Short name	T106
Test name
Test status
Simulation time	27314434 ps
CPU time	0.63 seconds
Started	Feb 07 12:47:37 PM PST 24
Finished	Feb 07 12:47:39 PM PST 24
Peak memory	201556 kb
Host	smart-a112f52f-a2cc-4bdb-98d4-fddc69100b6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=5693836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.5693836
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.1037560308
Short name	T63
Test name
Test status
Simulation time	24720117 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:36 PM PST 24
Finished	Feb 07 12:47:38 PM PST 24
Peak memory	201528 kb
Host	smart-fb17ab51-572f-4e91-bd09-4ecc18c92924
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1037560308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1037560308
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3647221873
Short name	T59
Test name
Test status
Simulation time	27258809 ps
CPU time	0.64 seconds
Started	Feb 07 12:47:55 PM PST 24
Finished	Feb 07 12:47:56 PM PST 24
Peak memory	201508 kb
Host	smart-e953820a-fc77-4d9d-a3ef-6e3143134897
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3647221873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3647221873
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.556374346
Short name	T237
Test name
Test status
Simulation time	164631213 ps
CPU time	2.08 seconds
Started	Feb 07 12:47:25 PM PST 24
Finished	Feb 07 12:47:28 PM PST 24
Peak memory	202340 kb
Host	smart-7797b42c-a5ed-43d2-894c-958420ac2858
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556374346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.556374346
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.622673619
Short name	T114
Test name
Test status
Simulation time	39357017 ps
CPU time	1.4 seconds
Started	Feb 07 12:47:24 PM PST 24
Finished	Feb 07 12:47:26 PM PST 24
Peak memory	210588 kb
Host	smart-828c8578-a6d3-493f-b6a2-8ee3774bb64f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622673619 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.622673619
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3549509091
Short name	T49
Test name
Test status
Simulation time	31256460 ps
CPU time	0.8 seconds
Started	Feb 07 12:47:19 PM PST 24
Finished	Feb 07 12:47:21 PM PST 24
Peak memory	202140 kb
Host	smart-21f7ae61-ee32-4c77-bc39-94e7426b7c8b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549509091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3549509091
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1416999768
Short name	T71
Test name
Test status
Simulation time	68080006 ps
CPU time	2.08 seconds
Started	Feb 07 12:47:21 PM PST 24
Finished	Feb 07 12:47:25 PM PST 24
Peak memory	202364 kb
Host	smart-df87d06c-d76d-4206-9706-2995192a5e12
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1416999768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1416999768
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4238172631
Short name	T236
Test name
Test status
Simulation time	122287788 ps
CPU time	1.52 seconds
Started	Feb 07 12:47:21 PM PST 24
Finished	Feb 07 12:47:24 PM PST 24
Peak memory	202404 kb
Host	smart-4cb48049-6e34-4f5f-862b-eadac4d82aeb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238172631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c sr_outstanding.4238172631
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1746829581
Short name	T212
Test name
Test status
Simulation time	208151620 ps
CPU time	2.89 seconds
Started	Feb 07 12:47:19 PM PST 24
Finished	Feb 07 12:47:23 PM PST 24
Peak memory	202452 kb
Host	smart-d6f66060-a655-4ded-ab14-83a1e8203d35
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1746829581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1746829581
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1197403462
Short name	T227
Test name
Test status
Simulation time	346650757 ps
CPU time	2.8 seconds
Started	Feb 07 12:47:16 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202352 kb
Host	smart-49a78359-42b9-4260-8eb5-7156b84393a5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1197403462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1197403462
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.1482568429
Short name	T25
Test name
Test status
Simulation time	22886445 ps
CPU time	0.65 seconds
Started	Feb 07 12:47:38 PM PST 24
Finished	Feb 07 12:47:40 PM PST 24
Peak memory	201552 kb
Host	smart-a6b377cc-1a18-457c-a79a-6d7d86dfb11c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1482568429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1482568429
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.35825641
Short name	T260
Test name
Test status
Simulation time	26198627 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:38 PM PST 24
Finished	Feb 07 12:47:40 PM PST 24
Peak memory	201552 kb
Host	smart-deb6e35b-ede5-47b3-a870-78ddf4517f48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=35825641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.35825641
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.1821945465
Short name	T225
Test name
Test status
Simulation time	21932040 ps
CPU time	0.6 seconds
Started	Feb 07 12:47:43 PM PST 24
Finished	Feb 07 12:47:45 PM PST 24
Peak memory	201508 kb
Host	smart-76e5cdf7-7d85-4738-a43c-029ca4568f07
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1821945465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1821945465
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2466096183
Short name	T258
Test name
Test status
Simulation time	27792465 ps
CPU time	0.63 seconds
Started	Feb 07 12:47:40 PM PST 24
Finished	Feb 07 12:47:42 PM PST 24
Peak memory	201300 kb
Host	smart-7f5fb971-dfaf-4122-a2ea-603796ec0d4c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2466096183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2466096183
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.751220365
Short name	T248
Test name
Test status
Simulation time	33119504 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:55 PM PST 24
Finished	Feb 07 12:47:57 PM PST 24
Peak memory	201456 kb
Host	smart-e1df7a49-bcf6-48a3-ad8c-e85832b970a1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=751220365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.751220365
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2424434163
Short name	T211
Test name
Test status
Simulation time	23224610 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:37 PM PST 24
Finished	Feb 07 12:47:39 PM PST 24
Peak memory	201412 kb
Host	smart-5a43e0b0-3bed-41b1-9115-e08761a6a4e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2424434163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2424434163
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.707719412
Short name	T94
Test name
Test status
Simulation time	61319074 ps
CPU time	1.4 seconds
Started	Feb 07 12:47:27 PM PST 24
Finished	Feb 07 12:47:29 PM PST 24
Peak memory	210724 kb
Host	smart-742ba7a3-e5cd-47d8-94d4-3d44ab469f8b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707719412 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.707719412
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3024270614
Short name	T66
Test name
Test status
Simulation time	113647408 ps
CPU time	0.86 seconds
Started	Feb 07 12:47:25 PM PST 24
Finished	Feb 07 12:47:27 PM PST 24
Peak memory	201652 kb
Host	smart-7d38f587-afb3-4c6f-b77d-a8ad677ca8f1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024270614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3024270614
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3406775686
Short name	T231
Test name
Test status
Simulation time	82505543 ps
CPU time	1.09 seconds
Started	Feb 07 12:47:18 PM PST 24
Finished	Feb 07 12:47:20 PM PST 24
Peak memory	202380 kb
Host	smart-78d75606-7355-4cd0-820e-5c88dc1fa07d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406775686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.3406775686
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2661191943
Short name	T54
Test name
Test status
Simulation time	355685412 ps
CPU time	2.72 seconds
Started	Feb 07 12:47:17 PM PST 24
Finished	Feb 07 12:47:21 PM PST 24
Peak memory	202452 kb
Host	smart-57b8fce4-d3f6-4ee3-84f3-d16a36d1c576
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2661191943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2661191943
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3072860349
Short name	T92
Test name
Test status
Simulation time	283470821 ps
CPU time	2.86 seconds
Started	Feb 07 12:47:20 PM PST 24
Finished	Feb 07 12:47:24 PM PST 24
Peak memory	202292 kb
Host	smart-bf8322d3-602a-461d-a2e2-fd7d719c1b0e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3072860349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3072860349
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.264990451
Short name	T73
Test name
Test status
Simulation time	50119003 ps
CPU time	1.96 seconds
Started	Feb 07 12:47:24 PM PST 24
Finished	Feb 07 12:47:27 PM PST 24
Peak memory	202524 kb
Host	smart-8d568f2e-6a0f-4c8e-9736-13f1ae7ba96e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264990451 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.264990451
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2128978407
Short name	T95
Test name
Test status
Simulation time	67152243 ps
CPU time	1.03 seconds
Started	Feb 07 12:47:24 PM PST 24
Finished	Feb 07 12:47:26 PM PST 24
Peak memory	202320 kb
Host	smart-cebe1b95-fc6b-45fa-85f0-b7524018d5f1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128978407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2128978407
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.21697830
Short name	T259
Test name
Test status
Simulation time	26582551 ps
CPU time	0.65 seconds
Started	Feb 07 12:47:24 PM PST 24
Finished	Feb 07 12:47:25 PM PST 24
Peak memory	201512 kb
Host	smart-e91abffd-9d9f-4633-85e6-9fda17a4b54d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=21697830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.21697830
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2706586127
Short name	T14
Test name
Test status
Simulation time	89022937 ps
CPU time	1.42 seconds
Started	Feb 07 12:47:17 PM PST 24
Finished	Feb 07 12:47:19 PM PST 24
Peak memory	202444 kb
Host	smart-d9fa81b5-2d71-4bc1-812b-9f0b1b449502
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2706586127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2706586127
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3703479285
Short name	T210
Test name
Test status
Simulation time	67325399 ps
CPU time	1.5 seconds
Started	Feb 07 12:47:39 PM PST 24
Finished	Feb 07 12:47:43 PM PST 24
Peak memory	202360 kb
Host	smart-f27eaec7-5685-42ce-80dc-3cf9ec0f820f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703479285 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.3703479285
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.709875883
Short name	T75
Test name
Test status
Simulation time	80812493 ps
CPU time	1.09 seconds
Started	Feb 07 12:47:39 PM PST 24
Finished	Feb 07 12:47:42 PM PST 24
Peak memory	202204 kb
Host	smart-1d5ea9b4-f56f-4e64-a518-5cbfc1946e0d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709875883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.709875883
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.4196706644
Short name	T247
Test name
Test status
Simulation time	36062601 ps
CPU time	0.66 seconds
Started	Feb 07 12:47:27 PM PST 24
Finished	Feb 07 12:47:28 PM PST 24
Peak memory	201448 kb
Host	smart-805a02b7-20f7-42c0-a234-523393acc970
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4196706644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4196706644
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4288922639
Short name	T262
Test name
Test status
Simulation time	67059966 ps
CPU time	1.01 seconds
Started	Feb 07 12:47:38 PM PST 24
Finished	Feb 07 12:47:40 PM PST 24
Peak memory	202484 kb
Host	smart-9a488f25-2cba-42a3-99bd-3dfe39820073
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288922639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.4288922639
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3921486585
Short name	T53
Test name
Test status
Simulation time	192979053 ps
CPU time	2.4 seconds
Started	Feb 07 12:47:24 PM PST 24
Finished	Feb 07 12:47:27 PM PST 24
Peak memory	202436 kb
Host	smart-8bbafe37-e966-4d2d-a98e-9b2e7404fe71
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3921486585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3921486585
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2169704582
Short name	T233
Test name
Test status
Simulation time	63781239 ps
CPU time	1.16 seconds
Started	Feb 07 12:47:29 PM PST 24
Finished	Feb 07 12:47:31 PM PST 24
Peak memory	210520 kb
Host	smart-0c4cd72a-0180-4a55-a7bf-9c2e56974103
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169704582 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.2169704582
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2991872976
Short name	T204
Test name
Test status
Simulation time	28978078 ps
CPU time	0.77 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:37 PM PST 24
Peak memory	202188 kb
Host	smart-3c2fe7bd-35e5-423b-89e7-5252957e533d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991872976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2991872976
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.948639536
Short name	T104
Test name
Test status
Simulation time	32808681 ps
CPU time	0.63 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:34 PM PST 24
Peak memory	201336 kb
Host	smart-6072364f-f681-44de-a36e-a15ad8ba8e37
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=948639536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.948639536
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1520187281
Short name	T245
Test name
Test status
Simulation time	114208629 ps
CPU time	1.35 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:38 PM PST 24
Peak memory	202412 kb
Host	smart-1b4ca6fd-5086-41ff-a434-e97f16c4f800
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520187281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.1520187281
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2339963021
Short name	T253
Test name
Test status
Simulation time	130657352 ps
CPU time	1.87 seconds
Started	Feb 07 12:47:32 PM PST 24
Finished	Feb 07 12:47:35 PM PST 24
Peak memory	202464 kb
Host	smart-a3660739-6611-4e6f-bb15-bc5dd6860829
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2339963021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2339963021
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3434313386
Short name	T217
Test name
Test status
Simulation time	35242850 ps
CPU time	0.99 seconds
Started	Feb 07 12:47:24 PM PST 24
Finished	Feb 07 12:47:26 PM PST 24
Peak memory	202524 kb
Host	smart-6dd44c13-bf53-46dd-a14d-7d388972b275
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434313386 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.3434313386
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2945045031
Short name	T98
Test name
Test status
Simulation time	47646473 ps
CPU time	0.79 seconds
Started	Feb 07 12:47:35 PM PST 24
Finished	Feb 07 12:47:38 PM PST 24
Peak memory	202188 kb
Host	smart-0374e6e1-c689-4dab-ab12-049fa4add013
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945045031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2945045031
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3428353543
Short name	T230
Test name
Test status
Simulation time	48779119 ps
CPU time	1.3 seconds
Started	Feb 07 12:47:38 PM PST 24
Finished	Feb 07 12:47:41 PM PST 24
Peak memory	202416 kb
Host	smart-3208641b-26ff-452e-81b0-1a359923c13d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428353543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.3428353543
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2141389747
Short name	T58
Test name
Test status
Simulation time	174989450 ps
CPU time	1.99 seconds
Started	Feb 07 12:47:25 PM PST 24
Finished	Feb 07 12:47:28 PM PST 24
Peak memory	202476 kb
Host	smart-d9e291a5-1af7-4159-844b-ddc51789729e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2141389747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2141389747
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1861213365
Short name	T110
Test name
Test status
Simulation time	137323885 ps
CPU time	2.44 seconds
Started	Feb 07 12:47:39 PM PST 24
Finished	Feb 07 12:47:44 PM PST 24
Peak memory	202324 kb
Host	smart-3e66a686-770b-45d3-ac94-4aa1b316aa6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1861213365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1861213365
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/0.usbdev_av_buffer.3698271283
Short name	T132
Test name
Test status
Simulation time	8373057432 ps
CPU time	7.44 seconds
Started	Feb 07 12:54:04 PM PST 24
Finished	Feb 07 12:54:12 PM PST 24
Peak memory	201896 kb
Host	smart-6936c390-6e01-4ad7-9ed0-43e52810fbea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36982 71283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3698271283
Directory	/workspace/0.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/0.usbdev_pkt_received.3514037335
Short name	T166
Test name
Test status
Simulation time	8394934295 ps
CPU time	7.71 seconds
Started	Feb 07 12:53:59 PM PST 24
Finished	Feb 07 12:54:07 PM PST 24
Peak memory	201888 kb
Host	smart-542dad57-df55-46c9-ac4c-6346f36fb3f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35140 37335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3514037335
Directory	/workspace/0.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/0.usbdev_smoke.725127995
Short name	T88
Test name
Test status
Simulation time	8383189634 ps
CPU time	8.87 seconds
Started	Feb 07 12:53:52 PM PST 24
Finished	Feb 07 12:54:02 PM PST 24
Peak memory	201896 kb
Host	smart-8a0cf6f8-ae9f-4190-84df-928cce7b6f14
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72512 7995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.725127995
Directory	/workspace/0.usbdev_smoke/latest

Test location	/workspace/coverage/default/1.usbdev_av_buffer.1442137990
Short name	T141
Test name
Test status
Simulation time	8422309029 ps
CPU time	7.55 seconds
Started	Feb 07 12:54:07 PM PST 24
Finished	Feb 07 12:54:15 PM PST 24
Peak memory	202008 kb
Host	smart-d2387fe2-67ad-419a-8650-a4d23bac9a41
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14421 37990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1442137990
Directory	/workspace/1.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/1.usbdev_pkt_received.3575253623
Short name	T143
Test name
Test status
Simulation time	8374793162 ps
CPU time	7.37 seconds
Started	Feb 07 12:53:57 PM PST 24
Finished	Feb 07 12:54:05 PM PST 24
Peak memory	201904 kb
Host	smart-510b93eb-9098-4e60-bef0-77617f2e7564
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35752 53623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3575253623
Directory	/workspace/1.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.2984812307
Short name	T18
Test name
Test status
Simulation time	184893248 ps
CPU time	1.01 seconds
Started	Feb 07 12:53:57 PM PST 24
Finished	Feb 07 12:53:59 PM PST 24
Peak memory	221704 kb
Host	smart-6c80536f-54ab-48b9-85fe-fb094da3bc07
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2984812307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2984812307
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/1.usbdev_smoke.3875006164
Short name	T175
Test name
Test status
Simulation time	8368826689 ps
CPU time	7.84 seconds
Started	Feb 07 12:54:10 PM PST 24
Finished	Feb 07 12:54:18 PM PST 24
Peak memory	201984 kb
Host	smart-45d20d5c-b3dc-475a-84ae-ed1386614834
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38750 06164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3875006164
Directory	/workspace/1.usbdev_smoke/latest

Test location	/workspace/coverage/default/10.usbdev_pkt_received.2589686389
Short name	T165
Test name
Test status
Simulation time	8372391921 ps
CPU time	7.31 seconds
Started	Feb 07 12:54:06 PM PST 24
Finished	Feb 07 12:54:14 PM PST 24
Peak memory	201880 kb
Host	smart-b16b473e-bbdb-4a10-8ec1-fae626858fc1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25896 86389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2589686389
Directory	/workspace/10.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/10.usbdev_smoke.2168440765
Short name	T135
Test name
Test status
Simulation time	8385281975 ps
CPU time	8.38 seconds
Started	Feb 07 12:54:02 PM PST 24
Finished	Feb 07 12:54:11 PM PST 24
Peak memory	201884 kb
Host	smart-9e121434-966b-4b4b-8fe6-ba162a94d8a9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21684 40765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2168440765
Directory	/workspace/10.usbdev_smoke/latest

Test location	/workspace/coverage/default/11.usbdev_av_buffer.265669870
Short name	T153
Test name
Test status
Simulation time	8368238413 ps
CPU time	7.41 seconds
Started	Feb 07 12:53:57 PM PST 24
Finished	Feb 07 12:54:06 PM PST 24
Peak memory	201768 kb
Host	smart-8cbee5b0-8919-4794-9cf1-d3c3a9e77cc4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26566 9870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.265669870
Directory	/workspace/11.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/11.usbdev_pkt_received.3310837804
Short name	T134
Test name
Test status
Simulation time	8389984905 ps
CPU time	9.4 seconds
Started	Feb 07 12:54:06 PM PST 24
Finished	Feb 07 12:54:16 PM PST 24
Peak memory	201960 kb
Host	smart-da38f9c5-6b64-4aeb-9d6e-b419ce25a824
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33108 37804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3310837804
Directory	/workspace/11.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/11.usbdev_smoke.508578891
Short name	T201
Test name
Test status
Simulation time	8372232045 ps
CPU time	8.25 seconds
Started	Feb 07 12:54:00 PM PST 24
Finished	Feb 07 12:54:10 PM PST 24
Peak memory	201952 kb
Host	smart-a1e1a88e-56c7-4397-ac62-ef959649823f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50857 8891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.508578891
Directory	/workspace/11.usbdev_smoke/latest

Test location	/workspace/coverage/default/12.usbdev_smoke.3267399672
Short name	T6
Test name
Test status
Simulation time	8372642857 ps
CPU time	7.95 seconds
Started	Feb 07 12:54:18 PM PST 24
Finished	Feb 07 12:54:27 PM PST 24
Peak memory	201860 kb
Host	smart-08afdcff-1816-4b52-89cd-cd9e8e5beed6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32673 99672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3267399672
Directory	/workspace/12.usbdev_smoke/latest

Test location	/workspace/coverage/default/13.usbdev_av_buffer.2293247105
Short name	T160
Test name
Test status
Simulation time	8373562875 ps
CPU time	7.08 seconds
Started	Feb 07 12:53:57 PM PST 24
Finished	Feb 07 12:54:05 PM PST 24
Peak memory	201652 kb
Host	smart-56b0e38a-32b1-4262-a1f2-8473f89a0a6b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22932 47105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2293247105
Directory	/workspace/13.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/13.usbdev_pkt_received.1433442060
Short name	T199
Test name
Test status
Simulation time	8391145717 ps
CPU time	7.51 seconds
Started	Feb 07 12:54:12 PM PST 24
Finished	Feb 07 12:54:20 PM PST 24
Peak memory	201928 kb
Host	smart-67d2ef60-929d-4e65-8940-1c24f1c78ffc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14334 42060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1433442060
Directory	/workspace/13.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/13.usbdev_smoke.1402000300
Short name	T84
Test name
Test status
Simulation time	8367332740 ps
CPU time	9.81 seconds
Started	Feb 07 12:54:01 PM PST 24
Finished	Feb 07 12:54:12 PM PST 24
Peak memory	201920 kb
Host	smart-4a2e17a0-7a5c-4618-bec3-bf81c93ad14d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14020 00300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1402000300
Directory	/workspace/13.usbdev_smoke/latest

Test location	/workspace/coverage/default/14.usbdev_pkt_received.4288590248
Short name	T117
Test name
Test status
Simulation time	8388199092 ps
CPU time	9.55 seconds
Started	Feb 07 12:54:34 PM PST 24
Finished	Feb 07 12:54:53 PM PST 24
Peak memory	201920 kb
Host	smart-7ab2237e-0a9e-4514-a5bf-c0ffa02664e8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42885 90248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4288590248
Directory	/workspace/14.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/14.usbdev_smoke.571887303
Short name	T151
Test name
Test status
Simulation time	8373608707 ps
CPU time	8.03 seconds
Started	Feb 07 12:54:23 PM PST 24
Finished	Feb 07 12:54:33 PM PST 24
Peak memory	201892 kb
Host	smart-406d52cf-fbed-49e2-8399-1be1bcc9f33b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57188 7303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.571887303
Directory	/workspace/14.usbdev_smoke/latest

Test location	/workspace/coverage/default/15.usbdev_pkt_received.746256237
Short name	T83
Test name
Test status
Simulation time	8372814956 ps
CPU time	7.03 seconds
Started	Feb 07 12:53:59 PM PST 24
Finished	Feb 07 12:54:06 PM PST 24
Peak memory	201920 kb
Host	smart-b379b787-b740-4f17-be08-449aea20a998
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74625 6237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.746256237
Directory	/workspace/15.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/15.usbdev_smoke.231364106
Short name	T155
Test name
Test status
Simulation time	8372242264 ps
CPU time	8.93 seconds
Started	Feb 07 12:54:09 PM PST 24
Finished	Feb 07 12:54:18 PM PST 24
Peak memory	201816 kb
Host	smart-42a8b461-6cd9-4855-90b9-dc3a3116fc9f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136 4106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.231364106
Directory	/workspace/15.usbdev_smoke/latest

Test location	/workspace/coverage/default/16.usbdev_av_buffer.646263814
Short name	T187
Test name
Test status
Simulation time	8368012948 ps
CPU time	7.37 seconds
Started	Feb 07 12:54:12 PM PST 24
Finished	Feb 07 12:54:20 PM PST 24
Peak memory	201888 kb
Host	smart-e337ef60-a880-4b65-9e31-1077d710164b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64626 3814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.646263814
Directory	/workspace/16.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/16.usbdev_smoke.3171912521
Short name	T133
Test name
Test status
Simulation time	8439656303 ps
CPU time	7.62 seconds
Started	Feb 07 12:54:00 PM PST 24
Finished	Feb 07 12:54:09 PM PST 24
Peak memory	201952 kb
Host	smart-637df0c7-ada6-4a79-bf93-40fc975ebe16
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31719 12521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3171912521
Directory	/workspace/16.usbdev_smoke/latest

Test location	/workspace/coverage/default/17.usbdev_av_buffer.2568788931
Short name	T121
Test name
Test status
Simulation time	8370554865 ps
CPU time	7.05 seconds
Started	Feb 07 12:54:00 PM PST 24
Finished	Feb 07 12:54:09 PM PST 24
Peak memory	201792 kb
Host	smart-cc412617-2aba-410d-a7e9-a43118345e8e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25687 88931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2568788931
Directory	/workspace/17.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/17.usbdev_pkt_received.2326425191
Short name	T144
Test name
Test status
Simulation time	8385985908 ps
CPU time	7.24 seconds
Started	Feb 07 12:54:06 PM PST 24
Finished	Feb 07 12:54:14 PM PST 24
Peak memory	201880 kb
Host	smart-28518326-8549-4f2d-a0e4-2547cb8d7eed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23264 25191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2326425191
Directory	/workspace/17.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/17.usbdev_smoke.2390536318
Short name	T127
Test name
Test status
Simulation time	8378733330 ps
CPU time	7.34 seconds
Started	Feb 07 12:54:01 PM PST 24
Finished	Feb 07 12:54:10 PM PST 24
Peak memory	201872 kb
Host	smart-08597910-53d6-4587-8257-3aa2123c152b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23905 36318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2390536318
Directory	/workspace/17.usbdev_smoke/latest

Test location	/workspace/coverage/default/18.usbdev_av_buffer.2596789358
Short name	T81
Test name
Test status
Simulation time	8371657805 ps
CPU time	7.27 seconds
Started	Feb 07 12:54:02 PM PST 24
Finished	Feb 07 12:54:11 PM PST 24
Peak memory	201880 kb
Host	smart-9f88ce50-6421-46b8-9899-d027245f3ff0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25967 89358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2596789358
Directory	/workspace/18.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/18.usbdev_pkt_received.1162710506
Short name	T122
Test name
Test status
Simulation time	8405094525 ps
CPU time	7.94 seconds
Started	Feb 07 12:54:01 PM PST 24
Finished	Feb 07 12:54:10 PM PST 24
Peak memory	201876 kb
Host	smart-0f1ed03e-3b8e-43c3-bfb3-6c9ba7d075ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11627 10506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1162710506
Directory	/workspace/18.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/18.usbdev_smoke.3097694051
Short name	T78
Test name
Test status
Simulation time	8368415043 ps
CPU time	8.09 seconds
Started	Feb 07 12:54:09 PM PST 24
Finished	Feb 07 12:54:18 PM PST 24
Peak memory	201900 kb
Host	smart-320203da-5239-432c-86da-9c88cb34c3b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30976 94051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3097694051
Directory	/workspace/18.usbdev_smoke/latest

Test location	/workspace/coverage/default/19.usbdev_av_buffer.4119964585
Short name	T40
Test name
Test status
Simulation time	8383511635 ps
CPU time	7.14 seconds
Started	Feb 07 12:54:07 PM PST 24
Finished	Feb 07 12:54:15 PM PST 24
Peak memory	201792 kb
Host	smart-e09c6859-2e4e-41e0-8510-9ef692fb7ced
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41199 64585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.4119964585
Directory	/workspace/19.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/19.usbdev_smoke.2002762822
Short name	T125
Test name
Test status
Simulation time	8372526579 ps
CPU time	8.41 seconds
Started	Feb 07 12:54:07 PM PST 24
Finished	Feb 07 12:54:16 PM PST 24
Peak memory	201904 kb
Host	smart-0fb57796-5967-45bf-8243-638f321827db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027 62822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2002762822
Directory	/workspace/19.usbdev_smoke/latest

Test location	/workspace/coverage/default/2.usbdev_av_buffer.826697107
Short name	T7
Test name
Test status
Simulation time	8370613786 ps
CPU time	7.03 seconds
Started	Feb 07 12:54:22 PM PST 24
Finished	Feb 07 12:54:31 PM PST 24
Peak memory	201836 kb
Host	smart-02bfa605-22b2-4850-8088-f5c65e6e6c92
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82669 7107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.826697107
Directory	/workspace/2.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.2940161799
Short name	T30
Test name
Test status
Simulation time	152742350 ps
CPU time	0.97 seconds
Started	Feb 07 12:54:19 PM PST 24
Finished	Feb 07 12:54:21 PM PST 24
Peak memory	221588 kb
Host	smart-d03610a4-1499-4411-b5d3-02584b7349ae
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2940161799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2940161799
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/2.usbdev_smoke.1231952892
Short name	T202
Test name
Test status
Simulation time	8366330640 ps
CPU time	7.08 seconds
Started	Feb 07 12:54:05 PM PST 24
Finished	Feb 07 12:54:13 PM PST 24
Peak memory	201944 kb
Host	smart-7232646f-d4fd-4329-9584-5852a7991ca4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12319 52892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1231952892
Directory	/workspace/2.usbdev_smoke/latest

Test location	/workspace/coverage/default/20.usbdev_av_buffer.193632570
Short name	T86
Test name
Test status
Simulation time	8370864415 ps
CPU time	7.31 seconds
Started	Feb 07 12:54:17 PM PST 24
Finished	Feb 07 12:54:25 PM PST 24
Peak memory	201932 kb
Host	smart-8f5bcd75-cdbc-4dfd-bfe1-12c7f462635f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363 2570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.193632570
Directory	/workspace/20.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/20.usbdev_pkt_received.3640481155
Short name	T158
Test name
Test status
Simulation time	8411013049 ps
CPU time	7.52 seconds
Started	Feb 07 12:54:17 PM PST 24
Finished	Feb 07 12:54:26 PM PST 24
Peak memory	201820 kb
Host	smart-db70e837-c4a0-40f3-a4bf-fab30b63d52a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36404 81155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3640481155
Directory	/workspace/20.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/21.usbdev_smoke.3940813902
Short name	T126
Test name
Test status
Simulation time	8367533979 ps
CPU time	7.03 seconds
Started	Feb 07 12:54:15 PM PST 24
Finished	Feb 07 12:54:22 PM PST 24
Peak memory	201888 kb
Host	smart-9cdeda2d-6a90-4d60-8e16-8bf7196dd47f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39408 13902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3940813902
Directory	/workspace/21.usbdev_smoke/latest

Test location	/workspace/coverage/default/22.usbdev_pkt_received.624993961
Short name	T35
Test name
Test status
Simulation time	8411386705 ps
CPU time	8.8 seconds
Started	Feb 07 12:54:17 PM PST 24
Finished	Feb 07 12:54:27 PM PST 24
Peak memory	201888 kb
Host	smart-5e9a61c7-8aa0-4069-a711-60cd8eaf336b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62499 3961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.624993961
Directory	/workspace/22.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/22.usbdev_smoke.3638873992
Short name	T162
Test name
Test status
Simulation time	8376596936 ps
CPU time	7.63 seconds
Started	Feb 07 12:54:08 PM PST 24
Finished	Feb 07 12:54:16 PM PST 24
Peak memory	201940 kb
Host	smart-eef25007-45fb-49b4-8590-08aac95dc642
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388 73992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3638873992
Directory	/workspace/22.usbdev_smoke/latest

Test location	/workspace/coverage/default/23.usbdev_av_buffer.1333663591
Short name	T189
Test name
Test status
Simulation time	8410835243 ps
CPU time	7.21 seconds
Started	Feb 07 12:54:17 PM PST 24
Finished	Feb 07 12:54:25 PM PST 24
Peak memory	201944 kb
Host	smart-a7ec2bf2-b2fe-4da8-8367-752bf8b69192
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13336 63591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1333663591
Directory	/workspace/23.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/23.usbdev_smoke.496271997
Short name	T36
Test name
Test status
Simulation time	8383763915 ps
CPU time	9.26 seconds
Started	Feb 07 12:54:11 PM PST 24
Finished	Feb 07 12:54:21 PM PST 24
Peak memory	201868 kb
Host	smart-04e2db09-61d9-489d-b3f7-079d75d99ea2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49627 1997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.496271997
Directory	/workspace/23.usbdev_smoke/latest

Test location	/workspace/coverage/default/24.usbdev_av_buffer.557366381
Short name	T82
Test name
Test status
Simulation time	8369521390 ps
CPU time	7.04 seconds
Started	Feb 07 12:54:06 PM PST 24
Finished	Feb 07 12:54:13 PM PST 24
Peak memory	201876 kb
Host	smart-386c42b8-586e-4057-83a9-05782664f843
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55736 6381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.557366381
Directory	/workspace/24.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/24.usbdev_pkt_received.1895671654
Short name	T44
Test name
Test status
Simulation time	8393639043 ps
CPU time	7.3 seconds
Started	Feb 07 12:53:59 PM PST 24
Finished	Feb 07 12:54:07 PM PST 24
Peak memory	201892 kb
Host	smart-1ab4793e-5ce5-4568-a8c7-cce38a7c5481
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18956 71654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1895671654
Directory	/workspace/24.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/24.usbdev_smoke.2476531269
Short name	T156
Test name
Test status
Simulation time	8377532658 ps
CPU time	7.31 seconds
Started	Feb 07 12:54:10 PM PST 24
Finished	Feb 07 12:54:18 PM PST 24
Peak memory	201980 kb
Host	smart-15f775d0-a651-4d77-80fc-f4aabc483246
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24765 31269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2476531269
Directory	/workspace/24.usbdev_smoke/latest

Test location	/workspace/coverage/default/25.usbdev_av_buffer.1522228938
Short name	T137
Test name
Test status
Simulation time	8367299053 ps
CPU time	8.43 seconds
Started	Feb 07 12:54:23 PM PST 24
Finished	Feb 07 12:54:33 PM PST 24
Peak memory	201900 kb
Host	smart-4559572f-7470-42b0-b0c8-7b5d529307dd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15222 28938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1522228938
Directory	/workspace/25.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/25.usbdev_pkt_received.2620426699
Short name	T136
Test name
Test status
Simulation time	8386790034 ps
CPU time	8.1 seconds
Started	Feb 07 12:54:25 PM PST 24
Finished	Feb 07 12:54:45 PM PST 24
Peak memory	201916 kb
Host	smart-1ebbfc50-e971-4397-8b96-e4f24d14f3d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26204 26699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2620426699
Directory	/workspace/25.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/25.usbdev_smoke.4029949608
Short name	T5
Test name
Test status
Simulation time	8371159097 ps
CPU time	8.84 seconds
Started	Feb 07 12:54:20 PM PST 24
Finished	Feb 07 12:54:29 PM PST 24
Peak memory	201888 kb
Host	smart-26d4d9ca-63f5-4477-ac4d-0d7e8ab93342
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40299 49608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.4029949608
Directory	/workspace/25.usbdev_smoke/latest

Test location	/workspace/coverage/default/26.usbdev_av_buffer.2012183938
Short name	T118
Test name
Test status
Simulation time	8433381359 ps
CPU time	7.45 seconds
Started	Feb 07 12:54:24 PM PST 24
Finished	Feb 07 12:54:41 PM PST 24
Peak memory	201924 kb
Host	smart-9998e068-8f3a-4edd-a8d0-ff27edfcf977
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121 83938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2012183938
Directory	/workspace/26.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/26.usbdev_smoke.498415353
Short name	T138
Test name
Test status
Simulation time	8367524516 ps
CPU time	7.6 seconds
Started	Feb 07 12:54:23 PM PST 24
Finished	Feb 07 12:54:32 PM PST 24
Peak memory	201904 kb
Host	smart-c10d877d-21c5-499c-9102-37c1d71173cd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49841 5353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.498415353
Directory	/workspace/26.usbdev_smoke/latest

Test location	/workspace/coverage/default/27.usbdev_av_buffer.2003228595
Short name	T188
Test name
Test status
Simulation time	8369909737 ps
CPU time	7.03 seconds
Started	Feb 07 12:54:24 PM PST 24
Finished	Feb 07 12:54:43 PM PST 24
Peak memory	201924 kb
Host	smart-7732f129-2589-4bdd-a782-9cfa4870e8f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20032 28595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2003228595
Directory	/workspace/27.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/28.usbdev_pkt_received.3743076095
Short name	T37
Test name
Test status
Simulation time	8381623563 ps
CPU time	9.54 seconds
Started	Feb 07 12:54:25 PM PST 24
Finished	Feb 07 12:54:48 PM PST 24
Peak memory	201920 kb
Host	smart-df5aadf5-0156-41ed-a752-59ba1e179d01
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37430 76095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3743076095
Directory	/workspace/28.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/28.usbdev_smoke.2543601046
Short name	T149
Test name
Test status
Simulation time	8373219937 ps
CPU time	6.87 seconds
Started	Feb 07 12:54:18 PM PST 24
Finished	Feb 07 12:54:26 PM PST 24
Peak memory	201952 kb
Host	smart-f136ce77-e9ec-4a3a-9351-c2fb8ffce30c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25436 01046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2543601046
Directory	/workspace/28.usbdev_smoke/latest

Test location	/workspace/coverage/default/29.usbdev_av_buffer.3102635047
Short name	T3
Test name
Test status
Simulation time	8371374260 ps
CPU time	7.43 seconds
Started	Feb 07 12:54:31 PM PST 24
Finished	Feb 07 12:54:50 PM PST 24
Peak memory	201876 kb
Host	smart-6dc63d1f-36a7-4cbf-bc65-b2434fd5138c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31026 35047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3102635047
Directory	/workspace/29.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/29.usbdev_smoke.2088266691
Short name	T185
Test name
Test status
Simulation time	8382131178 ps
CPU time	7.35 seconds
Started	Feb 07 12:54:24 PM PST 24
Finished	Feb 07 12:54:38 PM PST 24
Peak memory	201920 kb
Host	smart-8863cfe0-0200-4cdf-af13-b1a72af7ae61
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20882 66691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2088266691
Directory	/workspace/29.usbdev_smoke/latest

Test location	/workspace/coverage/default/3.usbdev_av_buffer.312307981
Short name	T186
Test name
Test status
Simulation time	8401163539 ps
CPU time	9.18 seconds
Started	Feb 07 12:54:15 PM PST 24
Finished	Feb 07 12:54:25 PM PST 24
Peak memory	201936 kb
Host	smart-54b107c2-4cb5-47c3-8cb2-67f3204b336c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31230 7981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.312307981
Directory	/workspace/3.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/3.usbdev_pkt_received.2439561515
Short name	T191
Test name
Test status
Simulation time	8388565687 ps
CPU time	7.64 seconds
Started	Feb 07 12:53:55 PM PST 24
Finished	Feb 07 12:54:04 PM PST 24
Peak memory	201920 kb
Host	smart-289705a7-d997-4bd1-857f-1b256f7aba59
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24395 61515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2439561515
Directory	/workspace/3.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.1448924441
Short name	T17
Test name
Test status
Simulation time	88103211 ps
CPU time	0.85 seconds
Started	Feb 07 12:54:06 PM PST 24
Finished	Feb 07 12:54:13 PM PST 24
Peak memory	220576 kb
Host	smart-16ef1f2e-e710-4d8e-a7a5-74d209f4152b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1448924441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1448924441
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/30.usbdev_av_buffer.2435310112
Short name	T196
Test name
Test status
Simulation time	8385549042 ps
CPU time	8.72 seconds
Started	Feb 07 12:54:29 PM PST 24
Finished	Feb 07 12:54:47 PM PST 24
Peak memory	201928 kb
Host	smart-76921030-d314-4188-9af1-e47d9b828aaf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24353 10112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2435310112
Directory	/workspace/30.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/30.usbdev_smoke.2404966731
Short name	T183
Test name
Test status
Simulation time	8391691269 ps
CPU time	7.43 seconds
Started	Feb 07 12:54:21 PM PST 24
Finished	Feb 07 12:54:31 PM PST 24
Peak memory	201972 kb
Host	smart-19312265-bad8-46ec-b269-79aa6cfdb70a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24049 66731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2404966731
Directory	/workspace/30.usbdev_smoke/latest

Test location	/workspace/coverage/default/31.usbdev_av_buffer.4008998604
Short name	T10
Test name
Test status
Simulation time	8368752189 ps
CPU time	7.16 seconds
Started	Feb 07 12:54:23 PM PST 24
Finished	Feb 07 12:54:32 PM PST 24
Peak memory	201888 kb
Host	smart-23d07b9e-6d64-4e13-9aca-7d01da78d7b2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40089 98604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4008998604
Directory	/workspace/31.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/31.usbdev_pkt_received.193664922
Short name	T80
Test name
Test status
Simulation time	8364752708 ps
CPU time	9.08 seconds
Started	Feb 07 12:54:20 PM PST 24
Finished	Feb 07 12:54:31 PM PST 24
Peak memory	201964 kb
Host	smart-cf05135e-fbb0-457a-88f5-a383689122d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19366 4922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.193664922
Directory	/workspace/31.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/31.usbdev_smoke.202836465
Short name	T120
Test name
Test status
Simulation time	8370512404 ps
CPU time	7.69 seconds
Started	Feb 07 12:54:26 PM PST 24
Finished	Feb 07 12:54:46 PM PST 24
Peak memory	201856 kb
Host	smart-7edd1019-6e29-4734-b1f8-9a835c40d1b8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20283 6465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.202836465
Directory	/workspace/31.usbdev_smoke/latest

Test location	/workspace/coverage/default/32.usbdev_av_buffer.1240055597
Short name	T8
Test name
Test status
Simulation time	8370390823 ps
CPU time	6.96 seconds
Started	Feb 07 12:54:21 PM PST 24
Finished	Feb 07 12:54:30 PM PST 24
Peak memory	201932 kb
Host	smart-99250e5c-1819-4a1f-8665-6baa4a55d88f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12400 55597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1240055597
Directory	/workspace/32.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/32.usbdev_pkt_received.2175449477
Short name	T33
Test name
Test status
Simulation time	8373209121 ps
CPU time	8.11 seconds
Started	Feb 07 12:54:25 PM PST 24
Finished	Feb 07 12:54:45 PM PST 24
Peak memory	201928 kb
Host	smart-77f0aecf-0939-4777-bcf5-dd48689f6891
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21754 49477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2175449477
Directory	/workspace/32.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/32.usbdev_smoke.2262318228
Short name	T173
Test name
Test status
Simulation time	8368016883 ps
CPU time	6.93 seconds
Started	Feb 07 12:54:14 PM PST 24
Finished	Feb 07 12:54:21 PM PST 24
Peak memory	201924 kb
Host	smart-5e9b6d30-9fda-4708-9d76-459868462e69
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22623 18228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2262318228
Directory	/workspace/32.usbdev_smoke/latest

Test location	/workspace/coverage/default/33.usbdev_av_buffer.3277907780
Short name	T1
Test name
Test status
Simulation time	8370999248 ps
CPU time	7.47 seconds
Started	Feb 07 12:54:41 PM PST 24
Finished	Feb 07 12:54:55 PM PST 24
Peak memory	201944 kb
Host	smart-14edc4be-158e-48a5-9f02-120091c1f373
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32779 07780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3277907780
Directory	/workspace/33.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/33.usbdev_pkt_received.2502275255
Short name	T12
Test name
Test status
Simulation time	8405398772 ps
CPU time	7.75 seconds
Started	Feb 07 12:54:18 PM PST 24
Finished	Feb 07 12:54:27 PM PST 24
Peak memory	201864 kb
Host	smart-3c705c46-69d7-4f9c-a405-fb81f082581f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25022 75255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2502275255
Directory	/workspace/33.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/33.usbdev_smoke.1086257421
Short name	T170
Test name
Test status
Simulation time	8372909913 ps
CPU time	9.11 seconds
Started	Feb 07 12:54:23 PM PST 24
Finished	Feb 07 12:54:38 PM PST 24
Peak memory	201936 kb
Host	smart-577164f0-74bf-4f7d-a44d-fedec6fe3764
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10862 57421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1086257421
Directory	/workspace/33.usbdev_smoke/latest

Test location	/workspace/coverage/default/34.usbdev_av_buffer.861665221
Short name	T163
Test name
Test status
Simulation time	8377988133 ps
CPU time	7.58 seconds
Started	Feb 07 12:54:26 PM PST 24
Finished	Feb 07 12:54:46 PM PST 24
Peak memory	201972 kb
Host	smart-2074870e-6999-4fe5-8a6e-f655d735a5a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86166 5221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.861665221
Directory	/workspace/34.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/34.usbdev_smoke.3196481623
Short name	T139
Test name
Test status
Simulation time	8371102398 ps
CPU time	7.45 seconds
Started	Feb 07 12:54:26 PM PST 24
Finished	Feb 07 12:54:45 PM PST 24
Peak memory	201916 kb
Host	smart-7b95c0db-80ca-43b0-9b2f-053efde800c4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31964 81623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3196481623
Directory	/workspace/34.usbdev_smoke/latest

Test location	/workspace/coverage/default/35.usbdev_av_buffer.1432749964
Short name	T179
Test name
Test status
Simulation time	8372876552 ps
CPU time	7.73 seconds
Started	Feb 07 12:54:38 PM PST 24
Finished	Feb 07 12:54:54 PM PST 24
Peak memory	201924 kb
Host	smart-7d30f9d7-3596-4007-9a6a-babc9bdc665c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14327 49964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1432749964
Directory	/workspace/35.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/35.usbdev_pkt_received.3377163931
Short name	T42
Test name
Test status
Simulation time	8414366520 ps
CPU time	7.4 seconds
Started	Feb 07 12:54:27 PM PST 24
Finished	Feb 07 12:54:45 PM PST 24
Peak memory	201892 kb
Host	smart-00e38611-f6d1-482e-9e83-2829bbbb8181
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33771 63931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3377163931
Directory	/workspace/35.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/35.usbdev_smoke.4033045525
Short name	T200
Test name
Test status
Simulation time	8374301194 ps
CPU time	7.3 seconds
Started	Feb 07 12:54:33 PM PST 24
Finished	Feb 07 12:54:50 PM PST 24
Peak memory	201868 kb
Host	smart-252851a9-1680-42d6-b987-7eb5a84231bf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40330 45525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.4033045525
Directory	/workspace/35.usbdev_smoke/latest

Test location	/workspace/coverage/default/36.usbdev_av_buffer.178364591
Short name	T195
Test name
Test status
Simulation time	8418138798 ps
CPU time	7.22 seconds
Started	Feb 07 12:54:44 PM PST 24
Finished	Feb 07 12:54:56 PM PST 24
Peak memory	201948 kb
Host	smart-56c5338d-cae0-442b-b904-9d9b0bc4f6ca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17836 4591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.178364591
Directory	/workspace/36.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/36.usbdev_pkt_received.2192783633
Short name	T79
Test name
Test status
Simulation time	8382939607 ps
CPU time	7.25 seconds
Started	Feb 07 12:54:31 PM PST 24
Finished	Feb 07 12:54:49 PM PST 24
Peak memory	201960 kb
Host	smart-0cc3dad8-4804-4876-8ea7-3de106e1f6df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21927 83633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2192783633
Directory	/workspace/36.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/36.usbdev_smoke.2477516758
Short name	T154
Test name
Test status
Simulation time	8372391260 ps
CPU time	9.08 seconds
Started	Feb 07 12:54:42 PM PST 24
Finished	Feb 07 12:54:56 PM PST 24
Peak memory	201912 kb
Host	smart-409161a7-b351-4256-9300-8ca36087e011
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24775 16758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2477516758
Directory	/workspace/36.usbdev_smoke/latest

Test location	/workspace/coverage/default/37.usbdev_av_buffer.3862604526
Short name	T41
Test name
Test status
Simulation time	8373156923 ps
CPU time	9.67 seconds
Started	Feb 07 12:54:28 PM PST 24
Finished	Feb 07 12:54:48 PM PST 24
Peak memory	201916 kb
Host	smart-7ca220ab-3803-43cd-a462-390753558a3d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626 04526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3862604526
Directory	/workspace/37.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/37.usbdev_pkt_received.2024450471
Short name	T193
Test name
Test status
Simulation time	8374251507 ps
CPU time	7.15 seconds
Started	Feb 07 12:54:33 PM PST 24
Finished	Feb 07 12:54:49 PM PST 24
Peak memory	201908 kb
Host	smart-9abd3801-b40d-4f2d-ab00-d44028352eab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20244 50471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2024450471
Directory	/workspace/37.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/38.usbdev_av_buffer.1240807213
Short name	T2
Test name
Test status
Simulation time	8372076239 ps
CPU time	7.91 seconds
Started	Feb 07 12:54:34 PM PST 24
Finished	Feb 07 12:54:51 PM PST 24
Peak memory	201916 kb
Host	smart-fe709e80-10be-4374-981e-f4bd378dcd1b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12408 07213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1240807213
Directory	/workspace/38.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/38.usbdev_pkt_received.308513374
Short name	T159
Test name
Test status
Simulation time	8365924546 ps
CPU time	7.51 seconds
Started	Feb 07 12:54:39 PM PST 24
Finished	Feb 07 12:54:54 PM PST 24
Peak memory	201924 kb
Host	smart-64460421-ec2e-4468-8557-fbfa06f69326
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30851 3374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.308513374
Directory	/workspace/38.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/38.usbdev_smoke.4067569744
Short name	T169
Test name
Test status
Simulation time	8373645103 ps
CPU time	8.63 seconds
Started	Feb 07 12:54:24 PM PST 24
Finished	Feb 07 12:54:43 PM PST 24
Peak memory	201912 kb
Host	smart-597f49ee-eeee-4e79-9fd4-5aaaa7ad89a3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40675 69744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.4067569744
Directory	/workspace/38.usbdev_smoke/latest

Test location	/workspace/coverage/default/39.usbdev_pkt_received.2946610436
Short name	T148
Test name
Test status
Simulation time	8380722874 ps
CPU time	8.1 seconds
Started	Feb 07 12:54:39 PM PST 24
Finished	Feb 07 12:54:54 PM PST 24
Peak memory	201984 kb
Host	smart-bb62def6-b0dc-475e-b849-2ea3cd3d18de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29466 10436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2946610436
Directory	/workspace/39.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/39.usbdev_smoke.783103055
Short name	T177
Test name
Test status
Simulation time	8368544130 ps
CPU time	7.89 seconds
Started	Feb 07 12:54:42 PM PST 24
Finished	Feb 07 12:54:55 PM PST 24
Peak memory	201836 kb
Host	smart-61a6b1a8-488f-4986-a8b5-f40da5554b25
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78310 3055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.783103055
Directory	/workspace/39.usbdev_smoke/latest

Test location	/workspace/coverage/default/4.usbdev_av_buffer.720336455
Short name	T157
Test name
Test status
Simulation time	8370193627 ps
CPU time	7.53 seconds
Started	Feb 07 12:54:00 PM PST 24
Finished	Feb 07 12:54:09 PM PST 24
Peak memory	201964 kb
Host	smart-849ecacc-1f1c-41c1-b94e-ccadf3a102b5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72033 6455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.720336455
Directory	/workspace/4.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/4.usbdev_pkt_received.2937748029
Short name	T161
Test name
Test status
Simulation time	8411564537 ps
CPU time	8.47 seconds
Started	Feb 07 12:54:07 PM PST 24
Finished	Feb 07 12:54:17 PM PST 24
Peak memory	201888 kb
Host	smart-e3f75657-6d92-4fa1-807b-87d5cc2fd888
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29377 48029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2937748029
Directory	/workspace/4.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/4.usbdev_sec_cm.693952952
Short name	T29
Test name
Test status
Simulation time	145168252 ps
CPU time	1.03 seconds
Started	Feb 07 12:54:15 PM PST 24
Finished	Feb 07 12:54:17 PM PST 24
Peak memory	220692 kb
Host	smart-858a0bce-96af-485d-8f02-45e9cf80a41f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=693952952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.693952952
Directory	/workspace/4.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/4.usbdev_smoke.665359984
Short name	T130
Test name
Test status
Simulation time	8369766989 ps
CPU time	7.61 seconds
Started	Feb 07 12:54:11 PM PST 24
Finished	Feb 07 12:54:19 PM PST 24
Peak memory	201936 kb
Host	smart-424adb45-3679-442f-81b3-37b1ce9a02e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66535 9984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.665359984
Directory	/workspace/4.usbdev_smoke/latest

Test location	/workspace/coverage/default/40.usbdev_av_buffer.170601692
Short name	T85
Test name
Test status
Simulation time	8366247906 ps
CPU time	9.95 seconds
Started	Feb 07 12:54:36 PM PST 24
Finished	Feb 07 12:54:55 PM PST 24
Peak memory	201900 kb
Host	smart-a8459ff4-2a03-4ccd-b515-b0bd728a3438
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17060 1692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.170601692
Directory	/workspace/40.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/40.usbdev_pkt_received.3426335771
Short name	T140
Test name
Test status
Simulation time	8395090551 ps
CPU time	7.23 seconds
Started	Feb 07 12:54:34 PM PST 24
Finished	Feb 07 12:54:50 PM PST 24
Peak memory	201884 kb
Host	smart-214232d4-d1b2-47ce-8a1b-2c604e3d3f16
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34263 35771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3426335771
Directory	/workspace/40.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/40.usbdev_smoke.2374740596
Short name	T145
Test name
Test status
Simulation time	8367358011 ps
CPU time	8.44 seconds
Started	Feb 07 12:54:26 PM PST 24
Finished	Feb 07 12:54:46 PM PST 24
Peak memory	201924 kb
Host	smart-7bf3c8b0-f1bb-482b-a309-0763b2cf925e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23747 40596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2374740596
Directory	/workspace/40.usbdev_smoke/latest

Test location	/workspace/coverage/default/41.usbdev_pkt_received.739549265
Short name	T174
Test name
Test status
Simulation time	8393631080 ps
CPU time	7.02 seconds
Started	Feb 07 12:54:35 PM PST 24
Finished	Feb 07 12:54:51 PM PST 24
Peak memory	201948 kb
Host	smart-7821120e-87bf-44db-b0f9-80ab3e4e018d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73954 9265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.739549265
Directory	/workspace/41.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/41.usbdev_smoke.3089496757
Short name	T198
Test name
Test status
Simulation time	8369800525 ps
CPU time	7.4 seconds
Started	Feb 07 12:54:33 PM PST 24
Finished	Feb 07 12:54:50 PM PST 24
Peak memory	201924 kb
Host	smart-4149848a-2e87-47fb-9866-aece8a9b130d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30894 96757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3089496757
Directory	/workspace/41.usbdev_smoke/latest

Test location	/workspace/coverage/default/42.usbdev_av_buffer.1627330055
Short name	T190
Test name
Test status
Simulation time	8375531682 ps
CPU time	7.18 seconds
Started	Feb 07 12:54:33 PM PST 24
Finished	Feb 07 12:54:49 PM PST 24
Peak memory	201928 kb
Host	smart-2af76788-3be4-4e9f-bc80-63e97935136d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16273 30055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1627330055
Directory	/workspace/42.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/42.usbdev_pkt_received.137038137
Short name	T129
Test name
Test status
Simulation time	8392933394 ps
CPU time	9.59 seconds
Started	Feb 07 12:54:41 PM PST 24
Finished	Feb 07 12:54:57 PM PST 24
Peak memory	201948 kb
Host	smart-d9777050-e0fd-4fcb-99ad-1565d707785b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13703 8137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.137038137
Directory	/workspace/42.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/42.usbdev_smoke.3489907497
Short name	T128
Test name
Test status
Simulation time	8367664664 ps
CPU time	7.49 seconds
Started	Feb 07 12:54:44 PM PST 24
Finished	Feb 07 12:54:57 PM PST 24
Peak memory	201888 kb
Host	smart-8b72a32e-4a6d-4ae1-b338-eafe408cad83
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34899 07497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3489907497
Directory	/workspace/42.usbdev_smoke/latest

Test location	/workspace/coverage/default/43.usbdev_av_buffer.151604012
Short name	T123
Test name
Test status
Simulation time	8382864681 ps
CPU time	7.34 seconds
Started	Feb 07 12:54:35 PM PST 24
Finished	Feb 07 12:54:51 PM PST 24
Peak memory	202008 kb
Host	smart-80cd106a-1409-4514-84ff-00c3b76d8e89
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15160 4012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.151604012
Directory	/workspace/43.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/43.usbdev_smoke.2471153754
Short name	T192
Test name
Test status
Simulation time	8373349451 ps
CPU time	7.44 seconds
Started	Feb 07 12:54:27 PM PST 24
Finished	Feb 07 12:54:46 PM PST 24
Peak memory	201876 kb
Host	smart-8910dc78-bc27-4fac-afc0-f671492f3193
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24711 53754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2471153754
Directory	/workspace/43.usbdev_smoke/latest

Test location	/workspace/coverage/default/44.usbdev_pkt_received.3937572094
Short name	T150
Test name
Test status
Simulation time	8377367853 ps
CPU time	8.45 seconds
Started	Feb 07 12:54:32 PM PST 24
Finished	Feb 07 12:54:51 PM PST 24
Peak memory	201984 kb
Host	smart-c397ba04-d759-4338-9f20-6c1921a79573
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39375 72094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3937572094
Directory	/workspace/44.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/44.usbdev_smoke.3584394802
Short name	T164
Test name
Test status
Simulation time	8377542230 ps
CPU time	7.3 seconds
Started	Feb 07 12:54:38 PM PST 24
Finished	Feb 07 12:54:53 PM PST 24
Peak memory	201872 kb
Host	smart-79ce73df-48ed-4886-8a1f-e99d559050ed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35843 94802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3584394802
Directory	/workspace/44.usbdev_smoke/latest

Test location	/workspace/coverage/default/45.usbdev_av_buffer.3258663991
Short name	T197
Test name
Test status
Simulation time	8369626924 ps
CPU time	9.2 seconds
Started	Feb 07 12:54:21 PM PST 24
Finished	Feb 07 12:54:33 PM PST 24
Peak memory	201900 kb
Host	smart-51fbb8ff-a8f5-4be1-a879-1ad97319fcf1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32586 63991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3258663991
Directory	/workspace/45.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/45.usbdev_pkt_received.2239077698
Short name	T43
Test name
Test status
Simulation time	8401480366 ps
CPU time	6.98 seconds
Started	Feb 07 12:54:27 PM PST 24
Finished	Feb 07 12:54:45 PM PST 24
Peak memory	201932 kb
Host	smart-7ce10834-9980-4fe4-a309-df39fba76e22
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22390 77698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2239077698
Directory	/workspace/45.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/45.usbdev_smoke.1569970077
Short name	T152
Test name
Test status
Simulation time	8369109004 ps
CPU time	9.19 seconds
Started	Feb 07 12:54:45 PM PST 24
Finished	Feb 07 12:55:00 PM PST 24
Peak memory	201888 kb
Host	smart-09ba8d92-f18e-4d27-8041-2c8b3a5021dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15699 70077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1569970077
Directory	/workspace/45.usbdev_smoke/latest

Test location	/workspace/coverage/default/46.usbdev_av_buffer.1245334197
Short name	T119
Test name
Test status
Simulation time	8370694489 ps
CPU time	7.54 seconds
Started	Feb 07 12:54:33 PM PST 24
Finished	Feb 07 12:54:50 PM PST 24
Peak memory	201808 kb
Host	smart-9a8af0d9-1f61-4575-a6fd-d64bac9c8afb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453 34197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1245334197
Directory	/workspace/46.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/46.usbdev_pkt_received.77848560
Short name	T180
Test name
Test status
Simulation time	8370905366 ps
CPU time	8.61 seconds
Started	Feb 07 12:54:42 PM PST 24
Finished	Feb 07 12:54:56 PM PST 24
Peak memory	201916 kb
Host	smart-299a45f5-a857-4518-8b22-561d413d72ba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77848 560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.77848560
Directory	/workspace/46.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/46.usbdev_smoke.2259795412
Short name	T31
Test name
Test status
Simulation time	8369779585 ps
CPU time	7.52 seconds
Started	Feb 07 12:54:43 PM PST 24
Finished	Feb 07 12:54:55 PM PST 24
Peak memory	201932 kb
Host	smart-85e78562-3246-41bb-99f6-48d38d9c26d1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22597 95412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2259795412
Directory	/workspace/46.usbdev_smoke/latest

Test location	/workspace/coverage/default/47.usbdev_av_buffer.3161334731
Short name	T171
Test name
Test status
Simulation time	8367102354 ps
CPU time	7.36 seconds
Started	Feb 07 12:54:33 PM PST 24
Finished	Feb 07 12:54:50 PM PST 24
Peak memory	201796 kb
Host	smart-1e2cc09d-80c6-4074-bca4-cdb0b650d90e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31613 34731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3161334731
Directory	/workspace/47.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/47.usbdev_pkt_received.3776313599
Short name	T38
Test name
Test status
Simulation time	8371273140 ps
CPU time	7.44 seconds
Started	Feb 07 12:54:28 PM PST 24
Finished	Feb 07 12:54:46 PM PST 24
Peak memory	201928 kb
Host	smart-629170d6-18b4-44f0-99d9-ab90809ea146
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37763 13599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3776313599
Directory	/workspace/47.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/48.usbdev_pkt_received.3626626426
Short name	T147
Test name
Test status
Simulation time	8387424990 ps
CPU time	7.15 seconds
Started	Feb 07 12:54:44 PM PST 24
Finished	Feb 07 12:54:56 PM PST 24
Peak memory	201920 kb
Host	smart-d8bf8bd9-efea-4cd8-934a-04f1502f4668
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36266 26426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3626626426
Directory	/workspace/48.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/48.usbdev_smoke.1040823343
Short name	T131
Test name
Test status
Simulation time	8374011796 ps
CPU time	7.04 seconds
Started	Feb 07 12:54:33 PM PST 24
Finished	Feb 07 12:54:49 PM PST 24
Peak memory	201872 kb
Host	smart-af67ff38-eafd-42a0-a183-6cce5d743dc0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10408 23343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1040823343
Directory	/workspace/48.usbdev_smoke/latest

Test location	/workspace/coverage/default/49.usbdev_smoke.3673106857
Short name	T142
Test name
Test status
Simulation time	8370692943 ps
CPU time	7.64 seconds
Started	Feb 07 12:54:29 PM PST 24
Finished	Feb 07 12:54:46 PM PST 24
Peak memory	201912 kb
Host	smart-52a32acc-76f6-4cd1-8683-c9e734a2e26a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36731 06857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3673106857
Directory	/workspace/49.usbdev_smoke/latest

Test location	/workspace/coverage/default/5.usbdev_av_buffer.1098278184
Short name	T178
Test name
Test status
Simulation time	8371688405 ps
CPU time	7.37 seconds
Started	Feb 07 12:54:06 PM PST 24
Finished	Feb 07 12:54:14 PM PST 24
Peak memory	201892 kb
Host	smart-f861e956-98c2-4177-babc-223309871d0a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10982 78184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1098278184
Directory	/workspace/5.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/5.usbdev_pkt_received.2441300817
Short name	T167
Test name
Test status
Simulation time	8385323303 ps
CPU time	7.13 seconds
Started	Feb 07 12:54:09 PM PST 24
Finished	Feb 07 12:54:17 PM PST 24
Peak memory	201924 kb
Host	smart-2d6a1b05-f729-4f5c-9ccf-009efb5b7a50
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24413 00817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2441300817
Directory	/workspace/5.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/5.usbdev_smoke.553090793
Short name	T176
Test name
Test status
Simulation time	8376351839 ps
CPU time	8.76 seconds
Started	Feb 07 12:54:01 PM PST 24
Finished	Feb 07 12:54:12 PM PST 24
Peak memory	201784 kb
Host	smart-a8c7c840-f387-4cad-ac45-f45bb75b5ce1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55309 0793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.553090793
Directory	/workspace/5.usbdev_smoke/latest

Test location	/workspace/coverage/default/6.usbdev_av_buffer.596493317
Short name	T168
Test name
Test status
Simulation time	8386022802 ps
CPU time	7.16 seconds
Started	Feb 07 12:54:34 PM PST 24
Finished	Feb 07 12:54:49 PM PST 24
Peak memory	201816 kb
Host	smart-57cd26d1-9165-48f5-b5f7-df60af02c20a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59649 3317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.596493317
Directory	/workspace/6.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/6.usbdev_pkt_received.1280397254
Short name	T172
Test name
Test status
Simulation time	8384691706 ps
CPU time	7.63 seconds
Started	Feb 07 12:54:11 PM PST 24
Finished	Feb 07 12:54:19 PM PST 24
Peak memory	201916 kb
Host	smart-c694a0ee-f1dd-4dff-8359-82336914b8d0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12803 97254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1280397254
Directory	/workspace/6.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/6.usbdev_smoke.2093110150
Short name	T146
Test name
Test status
Simulation time	8373300113 ps
CPU time	7.56 seconds
Started	Feb 07 12:54:22 PM PST 24
Finished	Feb 07 12:54:32 PM PST 24
Peak memory	201904 kb
Host	smart-4d007ada-5ac6-4d61-a8d0-ba0dc1311e6f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20931 10150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2093110150
Directory	/workspace/6.usbdev_smoke/latest

Test location	/workspace/coverage/default/7.usbdev_av_buffer.2888420421
Short name	T182
Test name
Test status
Simulation time	8368099757 ps
CPU time	7.59 seconds
Started	Feb 07 12:54:21 PM PST 24
Finished	Feb 07 12:54:29 PM PST 24
Peak memory	201936 kb
Host	smart-52f68ac5-cfbb-45a2-a961-0adca2c9abb5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28884 20421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2888420421
Directory	/workspace/7.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/7.usbdev_pkt_received.445901060
Short name	T32
Test name
Test status
Simulation time	8414299053 ps
CPU time	9.67 seconds
Started	Feb 07 12:54:19 PM PST 24
Finished	Feb 07 12:54:30 PM PST 24
Peak memory	201968 kb
Host	smart-2d71c954-f7e6-40c0-84d1-212298ec1e99
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44590 1060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.445901060
Directory	/workspace/7.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/7.usbdev_smoke.2115194219
Short name	T181
Test name
Test status
Simulation time	8367564901 ps
CPU time	7.42 seconds
Started	Feb 07 12:54:27 PM PST 24
Finished	Feb 07 12:54:45 PM PST 24
Peak memory	201888 kb
Host	smart-2a6858bb-db82-4049-ac49-b9df83e36682
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21151 94219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2115194219
Directory	/workspace/7.usbdev_smoke/latest

Test location	/workspace/coverage/default/8.usbdev_smoke.3921625270
Short name	T184
Test name
Test status
Simulation time	8367546372 ps
CPU time	7.99 seconds
Started	Feb 07 12:54:00 PM PST 24
Finished	Feb 07 12:54:10 PM PST 24
Peak memory	201968 kb
Host	smart-d7f62636-b08f-4fcd-bfba-7ae61283cde8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216 25270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3921625270
Directory	/workspace/8.usbdev_smoke/latest

Test location	/workspace/coverage/default/9.usbdev_av_buffer.2282385344
Short name	T124
Test name
Test status
Simulation time	8375172314 ps
CPU time	7.1 seconds
Started	Feb 07 12:53:58 PM PST 24
Finished	Feb 07 12:54:06 PM PST 24
Peak memory	201924 kb
Host	smart-f154e746-7ede-4e67-a3ae-4ca136fb9df5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22823 85344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2282385344
Directory	/workspace/9.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/9.usbdev_pkt_received.134109025
Short name	T90
Test name
Test status
Simulation time	8394169654 ps
CPU time	8.57 seconds
Started	Feb 07 12:54:15 PM PST 24
Finished	Feb 07 12:54:30 PM PST 24
Peak memory	201880 kb
Host	smart-67f26970-5e24-4638-8253-8ea843132dcc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13410 9025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.134109025
Directory	/workspace/9.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/9.usbdev_smoke.71463617
Short name	T203
Test name
Test status
Simulation time	8414026942 ps
CPU time	6.87 seconds
Started	Feb 07 12:53:53 PM PST 24
Finished	Feb 07 12:54:01 PM PST 24
Peak memory	201924 kb
Host	smart-122968c3-4f38-4e8a-920a-c00560e9ea17
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71463 617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.71463617
Directory	/workspace/9.usbdev_smoke/latest

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