SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
45.74 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
Crosses | 72 | 51 | 21 | 29.17 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_intr_pin | 18 | 0 | 18 | 100.00 | 100 | 1 | 1 | 0 | |
cp_intr_pin_value | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
cp_intr_pins_all_values | 72 | 51 | 21 | 29.17 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 18 | 0 | 18 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
all_pins[0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[1] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[2] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[3] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[4] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[5] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[6] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[7] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[8] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[9] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[10] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[11] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[12] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[13] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[14] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[15] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[16] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[17] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0x0] | 11317 | 1 | T1 | 36 | T2 | 36 | T3 | 36 | |||
values[0x1] | 95 | 1 | T4 | 1 | T5 | 1 | T6 | 1 | |||
transitions[0x0=>0x1] | 95 | 1 | T4 | 1 | T5 | 1 | T6 | 1 | |||
transitions[0x1=>0x0] | 95 | 1 | T4 | 1 | T5 | 1 | T6 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 72 | 51 | 21 | 29.17 | 51 |
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | NUMBER |
[all_pins[0]] | [values[0x1] , transitions[0x0=>0x1]] | -- | -- | 2 |
[all_pins[1]] | [transitions[0x1=>0x0]] | 0 | 1 | 1 |
[all_pins[2] , all_pins[3] , all_pins[4] , all_pins[5] , all_pins[6] , all_pins[7] , all_pins[8] , all_pins[9] , all_pins[10] , all_pins[11] , all_pins[12] , all_pins[13] , all_pins[14] , all_pins[15] , all_pins[16] , all_pins[17]] | [values[0x1] , transitions[0x0=>0x1] , transitions[0x1=>0x0]] | -- | -- | 48 |
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
all_pins[0] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[0] | transitions[0x1=>0x0] | 95 | 1 | T4 | 1 | T5 | 1 | T6 | 1 | |||
all_pins[1] | values[0x0] | 539 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[1] | values[0x1] | 95 | 1 | T4 | 1 | T5 | 1 | T6 | 1 | |||
all_pins[1] | transitions[0x0=>0x1] | 95 | 1 | T4 | 1 | T5 | 1 | T6 | 1 | |||
all_pins[2] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[3] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[4] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[5] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[6] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[7] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[8] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[9] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[10] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[11] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[12] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[13] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[14] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[15] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[16] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | |||
all_pins[17] | values[0x0] | 634 | 1 | T1 | 2 | T2 | 2 | T3 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |