Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
81.26	95.98	85.41	96.94	45.31	93.76	97.36	54.05

Total test records in report: 392

T181	/workspace/coverage/default/31.usbdev_pkt_sent.1278381143	Feb 18 12:55:09 PM PST 24	Feb 18 12:55:25 PM PST 24	8404281798 ps
T313	/workspace/coverage/default/33.usbdev_av_buffer.2670512807	Feb 18 12:55:09 PM PST 24	Feb 18 12:55:28 PM PST 24	8372705044 ps
T314	/workspace/coverage/default/23.setup_trans_ignored.3502453672	Feb 18 12:54:42 PM PST 24	Feb 18 12:54:54 PM PST 24	8360262676 ps
T315	/workspace/coverage/default/32.usbdev_smoke.3795601959	Feb 18 12:55:10 PM PST 24	Feb 18 12:55:28 PM PST 24	8369001555 ps
T316	/workspace/coverage/default/18.usbdev_av_buffer.286924490	Feb 18 12:54:39 PM PST 24	Feb 18 12:54:50 PM PST 24	8365443189 ps
T317	/workspace/coverage/default/44.usbdev_av_buffer.4030713846	Feb 18 12:55:25 PM PST 24	Feb 18 12:55:44 PM PST 24	8368607105 ps
T318	/workspace/coverage/default/12.usbdev_pkt_sent.1599472165	Feb 18 12:54:24 PM PST 24	Feb 18 12:54:41 PM PST 24	8437268061 ps
T319	/workspace/coverage/default/18.usbdev_smoke.2626120941	Feb 18 12:54:32 PM PST 24	Feb 18 12:54:44 PM PST 24	8369460142 ps
T320	/workspace/coverage/default/31.usbdev_smoke.2007184261	Feb 18 12:54:57 PM PST 24	Feb 18 12:55:14 PM PST 24	8374854448 ps
T321	/workspace/coverage/default/14.in_trans.2897920202	Feb 18 12:54:29 PM PST 24	Feb 18 12:54:42 PM PST 24	8437360609 ps
T245	/workspace/coverage/default/6.usbdev_pkt_sent.1834011298	Feb 18 12:54:15 PM PST 24	Feb 18 12:54:29 PM PST 24	8436538812 ps
T322	/workspace/coverage/default/29.usbdev_av_buffer.2844256101	Feb 18 12:54:58 PM PST 24	Feb 18 12:55:15 PM PST 24	8372074223 ps
T323	/workspace/coverage/default/4.setup_trans_ignored.2637979394	Feb 18 12:53:52 PM PST 24	Feb 18 12:54:08 PM PST 24	8357236896 ps
T324	/workspace/coverage/default/25.usbdev_av_buffer.4112902184	Feb 18 12:54:41 PM PST 24	Feb 18 12:54:53 PM PST 24	8380730756 ps
T325	/workspace/coverage/default/22.setup_trans_ignored.808574251	Feb 18 12:54:32 PM PST 24	Feb 18 12:54:44 PM PST 24	8357712267 ps
T326	/workspace/coverage/default/42.usbdev_pkt_sent.2377991543	Feb 18 12:55:29 PM PST 24	Feb 18 12:55:47 PM PST 24	8414313824 ps
T160	/workspace/coverage/default/30.setup_trans_ignored.964835882	Feb 18 12:55:06 PM PST 24	Feb 18 12:55:23 PM PST 24	8368196065 ps
T327	/workspace/coverage/default/27.usbdev_smoke.1192431553	Feb 18 12:55:00 PM PST 24	Feb 18 12:55:18 PM PST 24	8368027347 ps
T328	/workspace/coverage/default/19.usbdev_smoke.4260952546	Feb 18 12:54:19 PM PST 24	Feb 18 12:54:32 PM PST 24	8370347417 ps
T329	/workspace/coverage/default/21.setup_trans_ignored.95314551	Feb 18 12:54:24 PM PST 24	Feb 18 12:54:39 PM PST 24	8359225151 ps
T330	/workspace/coverage/default/12.usbdev_smoke.818426949	Feb 18 12:54:23 PM PST 24	Feb 18 12:54:37 PM PST 24	8370010240 ps
T331	/workspace/coverage/default/0.in_trans.2784873508	Feb 18 12:53:43 PM PST 24	Feb 18 12:53:55 PM PST 24	8425725773 ps
T332	/workspace/coverage/default/15.usbdev_nak_trans.1952610033	Feb 18 12:54:24 PM PST 24	Feb 18 12:54:38 PM PST 24	8404260194 ps
T333	/workspace/coverage/default/40.setup_trans_ignored.3712503450	Feb 18 12:55:20 PM PST 24	Feb 18 12:55:36 PM PST 24	8359733557 ps
T201	/workspace/coverage/default/26.in_trans.3444933322	Feb 18 12:54:48 PM PST 24	Feb 18 12:54:57 PM PST 24	8481066786 ps
T84	/workspace/coverage/default/23.usbdev_nak_trans.1070192041	Feb 18 12:54:38 PM PST 24	Feb 18 12:54:48 PM PST 24	8382892282 ps
T334	/workspace/coverage/default/42.in_trans.2841318304	Feb 18 12:55:33 PM PST 24	Feb 18 12:55:49 PM PST 24	8433618730 ps
T71	/workspace/coverage/default/16.usbdev_nak_trans.4086609470	Feb 18 12:54:23 PM PST 24	Feb 18 12:54:37 PM PST 24	8399013737 ps
T207	/workspace/coverage/default/13.usbdev_smoke.3746412466	Feb 18 12:54:20 PM PST 24	Feb 18 12:54:36 PM PST 24	8365267377 ps
T335	/workspace/coverage/default/27.usbdev_nak_trans.862163828	Feb 18 12:54:59 PM PST 24	Feb 18 12:55:19 PM PST 24	8447792909 ps
T145	/workspace/coverage/default/39.usbdev_smoke.287373492	Feb 18 12:55:17 PM PST 24	Feb 18 12:55:32 PM PST 24	8365946077 ps
T232	/workspace/coverage/default/10.usbdev_pkt_sent.2839088463	Feb 18 12:54:08 PM PST 24	Feb 18 12:54:21 PM PST 24	8419633459 ps
T219	/workspace/coverage/default/37.in_trans.637893334	Feb 18 12:55:19 PM PST 24	Feb 18 12:55:37 PM PST 24	8396051946 ps
T336	/workspace/coverage/default/24.setup_trans_ignored.3259639687	Feb 18 12:54:48 PM PST 24	Feb 18 12:54:57 PM PST 24	8361531660 ps
T337	/workspace/coverage/default/7.usbdev_av_buffer.3979291016	Feb 18 12:53:55 PM PST 24	Feb 18 12:54:13 PM PST 24	8373503805 ps
T338	/workspace/coverage/default/34.usbdev_av_buffer.390317607	Feb 18 12:55:19 PM PST 24	Feb 18 12:55:35 PM PST 24	8369049024 ps
T146	/workspace/coverage/default/16.in_trans.4215828099	Feb 18 12:54:20 PM PST 24	Feb 18 12:54:34 PM PST 24	8432816267 ps
T339	/workspace/coverage/default/33.usbdev_nak_trans.2846849526	Feb 18 12:55:13 PM PST 24	Feb 18 12:55:29 PM PST 24	8421888866 ps
T340	/workspace/coverage/default/45.usbdev_smoke.1537530879	Feb 18 12:55:24 PM PST 24	Feb 18 12:55:43 PM PST 24	8397050698 ps
T46	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1122442228	Feb 18 12:28:21 PM PST 24	Feb 18 12:28:29 PM PST 24	204735217 ps
T38	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1613715302	Feb 18 12:27:57 PM PST 24	Feb 18 12:28:10 PM PST 24	193379281 ps
T128	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.594241978	Feb 18 12:27:45 PM PST 24	Feb 18 12:27:47 PM PST 24	87262833 ps
T50	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1353572684	Feb 18 12:27:47 PM PST 24	Feb 18 12:27:51 PM PST 24	121889111 ps
T47	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1642109255	Feb 18 12:28:07 PM PST 24	Feb 18 12:28:15 PM PST 24	133717363 ps
T39	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3981593889	Feb 18 12:27:54 PM PST 24	Feb 18 12:28:02 PM PST 24	203927906 ps
T52	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1624066504	Feb 18 12:28:03 PM PST 24	Feb 18 12:28:08 PM PST 24	46362235 ps
T116	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.442903487	Feb 18 12:27:55 PM PST 24	Feb 18 12:28:03 PM PST 24	203725098 ps
T40	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.737555785	Feb 18 12:28:02 PM PST 24	Feb 18 12:28:10 PM PST 24	205530534 ps
T51	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1256938527	Feb 18 12:28:04 PM PST 24	Feb 18 12:28:09 PM PST 24	37753714 ps
T117	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.551918674	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:11 PM PST 24	106238580 ps
T118	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.892868533	Feb 18 12:27:55 PM PST 24	Feb 18 12:28:04 PM PST 24	308352959 ps
T341	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3591939738	Feb 18 12:28:08 PM PST 24	Feb 18 12:28:21 PM PST 24	320800615 ps
T129	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3317237643	Feb 18 12:27:58 PM PST 24	Feb 18 12:28:06 PM PST 24	73931514 ps
T119	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2117154098	Feb 18 12:28:03 PM PST 24	Feb 18 12:28:10 PM PST 24	82893321 ps
T120	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.242175108	Feb 18 12:27:45 PM PST 24	Feb 18 12:27:52 PM PST 24	161907539 ps
T121	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3656958260	Feb 18 12:28:04 PM PST 24	Feb 18 12:28:13 PM PST 24	494648215 ps
T122	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1313630554	Feb 18 12:28:10 PM PST 24	Feb 18 12:28:20 PM PST 24	231594628 ps
T130	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2540514491	Feb 18 12:27:55 PM PST 24	Feb 18 12:28:03 PM PST 24	76900296 ps
T141	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3805234254	Feb 18 12:28:21 PM PST 24	Feb 18 12:28:30 PM PST 24	154318972 ps
T143	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.422870275	Feb 18 12:28:18 PM PST 24	Feb 18 12:28:27 PM PST 24	297338394 ps
T123	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1548968123	Feb 18 12:27:58 PM PST 24	Feb 18 12:28:09 PM PST 24	151139477 ps
T131	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3437455848	Feb 18 12:28:02 PM PST 24	Feb 18 12:28:09 PM PST 24	241911312 ps
T132	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.675095520	Feb 18 12:27:58 PM PST 24	Feb 18 12:28:06 PM PST 24	60003241 ps
T342	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.75541214	Feb 18 12:28:03 PM PST 24	Feb 18 12:28:12 PM PST 24	464822894 ps
T124	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3615532358	Feb 18 12:28:01 PM PST 24	Feb 18 12:28:10 PM PST 24	278284765 ps
T133	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.741244042	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:11 PM PST 24	102678852 ps
T125	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2076709621	Feb 18 12:28:14 PM PST 24	Feb 18 12:28:25 PM PST 24	479896418 ps
T134	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.711217978	Feb 18 12:28:04 PM PST 24	Feb 18 12:28:10 PM PST 24	55465299 ps
T162	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3018056831	Feb 18 12:28:03 PM PST 24	Feb 18 12:28:09 PM PST 24	141686789 ps
T126	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2485891177	Feb 18 12:27:55 PM PST 24	Feb 18 12:28:05 PM PST 24	383735804 ps
T135	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1402427122	Feb 18 12:27:56 PM PST 24	Feb 18 12:28:05 PM PST 24	199329488 ps
T127	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4032491504	Feb 18 12:27:53 PM PST 24	Feb 18 12:28:01 PM PST 24	61607769 ps
T343	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1678994943	Feb 18 12:27:58 PM PST 24	Feb 18 12:28:09 PM PST 24	187398681 ps
T344	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2273551496	Feb 18 12:28:11 PM PST 24	Feb 18 12:28:18 PM PST 24	62641169 ps
T169	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4129090151	Feb 18 12:28:18 PM PST 24	Feb 18 12:28:28 PM PST 24	308787874 ps
T345	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.614108427	Feb 18 12:28:01 PM PST 24	Feb 18 12:28:13 PM PST 24	30161602 ps
T346	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2225170582	Feb 18 12:28:14 PM PST 24	Feb 18 12:28:22 PM PST 24	142379300 ps
T347	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1547380787	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:13 PM PST 24	120669200 ps
T348	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3632125319	Feb 18 12:28:19 PM PST 24	Feb 18 12:28:25 PM PST 24	47297443 ps
T53	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1278978259	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:10 PM PST 24	29786731 ps
T163	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.93743491	Feb 18 12:27:49 PM PST 24	Feb 18 12:28:03 PM PST 24	338240057 ps
T172	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2450272516	Feb 18 12:28:06 PM PST 24	Feb 18 12:28:17 PM PST 24	494783577 ps
T136	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1214738252	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:10 PM PST 24	53905078 ps
T137	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3942558853	Feb 18 12:28:16 PM PST 24	Feb 18 12:28:23 PM PST 24	32185091 ps
T349	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2282645898	Feb 18 12:28:01 PM PST 24	Feb 18 12:28:09 PM PST 24	246934358 ps
T350	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1483330590	Feb 18 12:28:17 PM PST 24	Feb 18 12:28:24 PM PST 24	96117978 ps
T351	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.580905756	Feb 18 12:28:16 PM PST 24	Feb 18 12:28:22 PM PST 24	47084911 ps
T352	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2436800602	Feb 18 12:28:06 PM PST 24	Feb 18 12:28:15 PM PST 24	86029532 ps
T48	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2049696590	Feb 18 12:27:59 PM PST 24	Feb 18 12:28:06 PM PST 24	34079033 ps
T353	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.427501015	Feb 18 12:28:06 PM PST 24	Feb 18 12:28:14 PM PST 24	57550414 ps
T354	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2662824378	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:16 PM PST 24	173229753 ps
T355	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1072061719	Feb 18 12:27:59 PM PST 24	Feb 18 12:28:10 PM PST 24	152441235 ps
T49	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.61587738	Feb 18 12:28:07 PM PST 24	Feb 18 12:28:15 PM PST 24	36853037 ps
T356	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3550739661	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:11 PM PST 24	116709715 ps
T170	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.167315089	Feb 18 12:28:16 PM PST 24	Feb 18 12:28:26 PM PST 24	491681255 ps
T357	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.804504052	Feb 18 12:27:50 PM PST 24	Feb 18 12:27:59 PM PST 24	75695158 ps
T358	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3770864731	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:12 PM PST 24	74077602 ps
T359	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1399021974	Feb 18 12:27:56 PM PST 24	Feb 18 12:28:03 PM PST 24	57069540 ps
T139	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.267031749	Feb 18 12:27:54 PM PST 24	Feb 18 12:28:01 PM PST 24	98053430 ps
T360	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2868934877	Feb 18 12:28:04 PM PST 24	Feb 18 12:28:10 PM PST 24	35637965 ps
T361	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4063089303	Feb 18 12:28:06 PM PST 24	Feb 18 12:28:12 PM PST 24	35076901 ps
T362	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4103194521	Feb 18 12:27:46 PM PST 24	Feb 18 12:27:51 PM PST 24	238660600 ps
T167	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2008838449	Feb 18 12:28:18 PM PST 24	Feb 18 12:28:26 PM PST 24	274851124 ps
T363	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.827796044	Feb 18 12:27:53 PM PST 24	Feb 18 12:28:00 PM PST 24	147274952 ps
T166	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3371913116	Feb 18 12:28:00 PM PST 24	Feb 18 12:28:09 PM PST 24	302662551 ps
T164	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2732433754	Feb 18 12:28:08 PM PST 24	Feb 18 12:28:16 PM PST 24	51540691 ps
T364	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3651693412	Feb 18 12:28:03 PM PST 24	Feb 18 12:28:09 PM PST 24	30219399 ps
T44	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.628066517	Feb 18 12:27:45 PM PST 24	Feb 18 12:27:47 PM PST 24	49118895 ps
T365	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4168346327	Feb 18 12:28:22 PM PST 24	Feb 18 12:28:30 PM PST 24	123076681 ps
T366	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.39245277	Feb 18 12:27:52 PM PST 24	Feb 18 12:28:02 PM PST 24	107995638 ps
T45	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3076660430	Feb 18 12:28:01 PM PST 24	Feb 18 12:28:08 PM PST 24	29406950 ps
T367	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1003533402	Feb 18 12:28:15 PM PST 24	Feb 18 12:28:21 PM PST 24	30668589 ps
T368	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.920725160	Feb 18 12:28:17 PM PST 24	Feb 18 12:28:28 PM PST 24	176226355 ps
T165	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.406546601	Feb 18 12:28:11 PM PST 24	Feb 18 12:28:20 PM PST 24	305575391 ps
T369	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2656855099	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:10 PM PST 24	74553259 ps
T370	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3867488646	Feb 18 12:27:55 PM PST 24	Feb 18 12:28:02 PM PST 24	43825836 ps
T371	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2661844758	Feb 18 12:28:02 PM PST 24	Feb 18 12:28:10 PM PST 24	204191463 ps
T372	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1897300286	Feb 18 12:28:22 PM PST 24	Feb 18 12:28:29 PM PST 24	33312329 ps
T373	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2321754173	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:11 PM PST 24	277429891 ps
T374	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.31558250	Feb 18 12:28:03 PM PST 24	Feb 18 12:28:10 PM PST 24	77484458 ps
T140	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.283460426	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:11 PM PST 24	65714720 ps
T375	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.817939314	Feb 18 12:27:46 PM PST 24	Feb 18 12:27:50 PM PST 24	82326452 ps
T376	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1693206778	Feb 18 12:28:22 PM PST 24	Feb 18 12:28:31 PM PST 24	84089866 ps
T171	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1747928280	Feb 18 12:27:58 PM PST 24	Feb 18 12:28:08 PM PST 24	170655063 ps
T377	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3359929558	Feb 18 12:28:09 PM PST 24	Feb 18 12:28:17 PM PST 24	80256842 ps
T138	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3602569379	Feb 18 12:28:19 PM PST 24	Feb 18 12:28:25 PM PST 24	26499314 ps
T378	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2885019540	Feb 18 12:28:16 PM PST 24	Feb 18 12:28:23 PM PST 24	121141455 ps
T379	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.66805565	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:11 PM PST 24	49152978 ps
T380	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.967411224	Feb 18 12:27:54 PM PST 24	Feb 18 12:28:02 PM PST 24	151141458 ps
T381	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3554854876	Feb 18 12:28:06 PM PST 24	Feb 18 12:28:14 PM PST 24	129234413 ps
T382	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3003007283	Feb 18 12:28:17 PM PST 24	Feb 18 12:28:24 PM PST 24	36796293 ps
T383	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4248725388	Feb 18 12:28:23 PM PST 24	Feb 18 12:28:30 PM PST 24	44945295 ps
T384	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.355447376	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:11 PM PST 24	34486709 ps
T385	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4288487503	Feb 18 12:28:01 PM PST 24	Feb 18 12:28:09 PM PST 24	84072797 ps
T386	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2406980415	Feb 18 12:27:45 PM PST 24	Feb 18 12:27:49 PM PST 24	130101263 ps
T387	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.169363881	Feb 18 12:28:02 PM PST 24	Feb 18 12:28:08 PM PST 24	58146231 ps
T388	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2479639147	Feb 18 12:28:08 PM PST 24	Feb 18 12:28:16 PM PST 24	79343061 ps
T389	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.225277134	Feb 18 12:28:13 PM PST 24	Feb 18 12:28:21 PM PST 24	88759085 ps
T168	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.130505331	Feb 18 12:28:05 PM PST 24	Feb 18 12:28:14 PM PST 24	233046624 ps
T390	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3931675079	Feb 18 12:27:48 PM PST 24	Feb 18 12:27:55 PM PST 24	169392686 ps
T391	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1234205438	Feb 18 12:28:21 PM PST 24	Feb 18 12:28:29 PM PST 24	77039354 ps
T392	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.323844788	Feb 18 12:28:04 PM PST 24	Feb 18 12:28:10 PM PST 24	76930350 ps

Test location	/workspace/coverage/default/6.in_trans.1681362138
Short name	T5
Test name
Test status
Simulation time	8388320582 ps
CPU time	9.52 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:28 PM PST 24
Peak memory	202020 kb
Host	smart-f200ce62-8e48-4beb-8051-79f6c4709045
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16813 62138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.in_trans.1681362138
Directory	/workspace/6.in_trans/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1613715302
Short name	T38
Test name
Test status
Simulation time	193379281 ps
CPU time	6.53 seconds
Started	Feb 18 12:27:57 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	211108 kb
Host	smart-44222947-426e-44de-b6e4-f6c6455921fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613715302 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.1613715302
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/0.usbdev_smoke.2773900367
Short name	T9
Test name
Test status
Simulation time	8369558391 ps
CPU time	7.4 seconds
Started	Feb 18 12:53:43 PM PST 24
Finished	Feb 18 12:53:54 PM PST 24
Peak memory	202020 kb
Host	smart-679302be-7222-4e6f-bbf5-bfa33e943e8c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27739 00367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2773900367
Directory	/workspace/0.usbdev_smoke/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.3678403153
Short name	T43
Test name
Test status
Simulation time	171767516 ps
CPU time	1.05 seconds
Started	Feb 18 12:54:09 PM PST 24
Finished	Feb 18 12:54:14 PM PST 24
Peak memory	217916 kb
Host	smart-834779c9-c031-404c-9756-21a849e23184
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3678403153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3678403153
Directory	/workspace/0.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1122442228
Short name	T46
Test name
Test status
Simulation time	204735217 ps
CPU time	1.65 seconds
Started	Feb 18 12:28:21 PM PST 24
Finished	Feb 18 12:28:29 PM PST 24
Peak memory	203012 kb
Host	smart-2ed81a05-2729-4705-b845-7d917213f314
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122442228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.1122442228
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/default/4.usbdev_av_buffer.2467694356
Short name	T30
Test name
Test status
Simulation time	8373740764 ps
CPU time	7.74 seconds
Started	Feb 18 12:53:59 PM PST 24
Finished	Feb 18 12:54:14 PM PST 24
Peak memory	202008 kb
Host	smart-74e36285-79e0-4210-9f35-a5fff55cce38
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676 94356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2467694356
Directory	/workspace/4.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/21.usbdev_nak_trans.1612436390
Short name	T87
Test name
Test status
Simulation time	8415184790 ps
CPU time	7.6 seconds
Started	Feb 18 12:54:42 PM PST 24
Finished	Feb 18 12:54:53 PM PST 24
Peak memory	202016 kb
Host	smart-0dd20179-4b10-4fab-a0ce-44348e1f3b46
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16124 36390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1612436390
Directory	/workspace/21.usbdev_nak_trans/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.892868533
Short name	T118
Test name
Test status
Simulation time	308352959 ps
CPU time	2.99 seconds
Started	Feb 18 12:27:55 PM PST 24
Finished	Feb 18 12:28:04 PM PST 24
Peak memory	202844 kb
Host	smart-e355cdc4-7a2d-47b2-ae60-275328e4b915
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=892868533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.892868533
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2049696590
Short name	T48
Test name
Test status
Simulation time	34079033 ps
CPU time	0.79 seconds
Started	Feb 18 12:27:59 PM PST 24
Finished	Feb 18 12:28:06 PM PST 24
Peak memory	202680 kb
Host	smart-5546a683-76ea-4ba1-87f5-d6fe4c446157
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049696590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2049696590
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.628066517
Short name	T44
Test name
Test status
Simulation time	49118895 ps
CPU time	0.8 seconds
Started	Feb 18 12:27:45 PM PST 24
Finished	Feb 18 12:27:47 PM PST 24
Peak memory	202336 kb
Host	smart-cf055222-8000-4326-b7c3-cf9e449f890f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628066517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.628066517
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/default/12.in_trans.247629419
Short name	T22
Test name
Test status
Simulation time	8457766337 ps
CPU time	7.31 seconds
Started	Feb 18 12:54:20 PM PST 24
Finished	Feb 18 12:54:34 PM PST 24
Peak memory	202004 kb
Host	smart-fa7f3b83-ca56-488d-826f-a826de944aa4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24762 9419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.in_trans.247629419
Directory	/workspace/12.in_trans/latest

Test location	/workspace/coverage/default/21.in_trans.1941058652
Short name	T106
Test name
Test status
Simulation time	8434745095 ps
CPU time	7.23 seconds
Started	Feb 18 12:54:28 PM PST 24
Finished	Feb 18 12:54:41 PM PST 24
Peak memory	201960 kb
Host	smart-f1395b1a-741f-4510-82ce-3fb3357780a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19410 58652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.in_trans.1941058652
Directory	/workspace/21.in_trans/latest

Test location	/workspace/coverage/default/13.in_trans.2065876900
Short name	T60
Test name
Test status
Simulation time	8463369492 ps
CPU time	7.71 seconds
Started	Feb 18 12:54:20 PM PST 24
Finished	Feb 18 12:54:34 PM PST 24
Peak memory	202020 kb
Host	smart-78823a4d-d217-4555-a65c-603a0fb3e2fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20658 76900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.in_trans.2065876900
Directory	/workspace/13.in_trans/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.167315089
Short name	T170
Test name
Test status
Simulation time	491681255 ps
CPU time	4.03 seconds
Started	Feb 18 12:28:16 PM PST 24
Finished	Feb 18 12:28:26 PM PST 24
Peak memory	202836 kb
Host	smart-436d520f-8cd1-4bd0-b07e-ced521be27c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=167315089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.167315089
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/38.in_trans.2812792029
Short name	T226
Test name
Test status
Simulation time	8438540692 ps
CPU time	8.4 seconds
Started	Feb 18 12:55:21 PM PST 24
Finished	Feb 18 12:55:38 PM PST 24
Peak memory	201420 kb
Host	smart-b625cd6e-4f06-426e-85aa-278a2f88f0d9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28127 92029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.in_trans.2812792029
Directory	/workspace/38.in_trans/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.442903487
Short name	T116
Test name
Test status
Simulation time	203725098 ps
CPU time	2.1 seconds
Started	Feb 18 12:27:55 PM PST 24
Finished	Feb 18 12:28:03 PM PST 24
Peak memory	201900 kb
Host	smart-0527bf17-44bc-418d-ac17-b135c83d2bb3
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442903487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.442903487
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3615532358
Short name	T124
Test name
Test status
Simulation time	278284765 ps
CPU time	3.56 seconds
Started	Feb 18 12:28:01 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202896 kb
Host	smart-fb8ec09b-995f-4a25-94da-5e1108f28007
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3615532358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3615532358
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.130505331
Short name	T168
Test name
Test status
Simulation time	233046624 ps
CPU time	4.29 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:14 PM PST 24
Peak memory	203028 kb
Host	smart-510e6712-7600-4dfb-855f-f6638007a0ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=130505331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.130505331
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2450272516
Short name	T172
Test name
Test status
Simulation time	494783577 ps
CPU time	4.61 seconds
Started	Feb 18 12:28:06 PM PST 24
Finished	Feb 18 12:28:17 PM PST 24
Peak memory	202864 kb
Host	smart-dd62eb91-c2d1-4a94-9f78-cc5abd04cdad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2450272516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2450272516
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/33.usbdev_pkt_sent.3317689272
Short name	T24
Test name
Test status
Simulation time	8414706591 ps
CPU time	7.07 seconds
Started	Feb 18 12:55:09 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	201972 kb
Host	smart-921dccd6-45ef-4317-8708-94269c2fb008
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33176 89272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3317689272
Directory	/workspace/33.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/46.usbdev_pkt_sent.3189496192
Short name	T212
Test name
Test status
Simulation time	8371161343 ps
CPU time	8.92 seconds
Started	Feb 18 12:55:39 PM PST 24
Finished	Feb 18 12:55:54 PM PST 24
Peak memory	202024 kb
Host	smart-0f3a5eb8-9224-40d0-ba96-17e8460d5a6a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31894 96192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3189496192
Directory	/workspace/46.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/35.in_trans.4064877636
Short name	T108
Test name
Test status
Simulation time	8414085720 ps
CPU time	7.17 seconds
Started	Feb 18 12:55:15 PM PST 24
Finished	Feb 18 12:55:31 PM PST 24
Peak memory	202008 kb
Host	smart-5293e77b-060c-48e9-a004-eab76030e929
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40648 77636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.in_trans.4064877636
Directory	/workspace/35.in_trans/latest

Test location	/workspace/coverage/default/10.in_trans.3714445245
Short name	T253
Test name
Test status
Simulation time	8444393726 ps
CPU time	7.15 seconds
Started	Feb 18 12:54:17 PM PST 24
Finished	Feb 18 12:54:30 PM PST 24
Peak memory	201940 kb
Host	smart-ecdb2086-4c3f-49ff-909a-d05502b8fc30
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37144 45245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.in_trans.3714445245
Directory	/workspace/10.in_trans/latest

Test location	/workspace/coverage/default/20.usbdev_pkt_sent.959785964
Short name	T218
Test name
Test status
Simulation time	8408109396 ps
CPU time	7.31 seconds
Started	Feb 18 12:54:26 PM PST 24
Finished	Feb 18 12:54:40 PM PST 24
Peak memory	201988 kb
Host	smart-229281b8-55a5-43a4-b642-fcc07db94e65
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95978 5964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.959785964
Directory	/workspace/20.usbdev_pkt_sent/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.61587738
Short name	T49
Test name
Test status
Simulation time	36853037 ps
CPU time	0.73 seconds
Started	Feb 18 12:28:07 PM PST 24
Finished	Feb 18 12:28:15 PM PST 24
Peak memory	202660 kb
Host	smart-435c7931-1b31-482a-afd5-cd37a44da6c8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61587738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.61587738
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/default/0.in_trans.2784873508
Short name	T331
Test name
Test status
Simulation time	8425725773 ps
CPU time	7.75 seconds
Started	Feb 18 12:53:43 PM PST 24
Finished	Feb 18 12:53:55 PM PST 24
Peak memory	202020 kb
Host	smart-ac089e58-55c7-408e-8f4e-c54ab3432a34
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27848 73508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.in_trans.2784873508
Directory	/workspace/0.in_trans/latest

Test location	/workspace/coverage/default/1.in_trans.2965214098
Short name	T68
Test name
Test status
Simulation time	8435434861 ps
CPU time	7.73 seconds
Started	Feb 18 12:54:01 PM PST 24
Finished	Feb 18 12:54:15 PM PST 24
Peak memory	202028 kb
Host	smart-62dd30a3-3bc4-40cd-a2b1-7e9469b4f19c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29652 14098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.in_trans.2965214098
Directory	/workspace/1.in_trans/latest

Test location	/workspace/coverage/default/17.usbdev_pkt_sent.1762397215
Short name	T295
Test name
Test status
Simulation time	8445098641 ps
CPU time	9.22 seconds
Started	Feb 18 12:54:27 PM PST 24
Finished	Feb 18 12:54:43 PM PST 24
Peak memory	201956 kb
Host	smart-7564f6d0-eb05-40c7-b53f-159248021330
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17623 97215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1762397215
Directory	/workspace/17.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/30.usbdev_nak_trans.360622290
Short name	T78
Test name
Test status
Simulation time	8402975799 ps
CPU time	7.56 seconds
Started	Feb 18 12:55:08 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	201964 kb
Host	smart-17f6067c-34a1-476d-aae5-b09ea4ed4d17
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36062 2290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.360622290
Directory	/workspace/30.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/0.usbdev_av_buffer.2265040858
Short name	T149
Test name
Test status
Simulation time	8372477503 ps
CPU time	7.09 seconds
Started	Feb 18 12:53:42 PM PST 24
Finished	Feb 18 12:53:53 PM PST 24
Peak memory	201936 kb
Host	smart-62ea60d6-a917-4261-bcbb-6825a92978fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22650 40858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2265040858
Directory	/workspace/0.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/1.usbdev_nak_trans.3592434169
Short name	T10
Test name
Test status
Simulation time	8410937913 ps
CPU time	7.06 seconds
Started	Feb 18 12:54:09 PM PST 24
Finished	Feb 18 12:54:21 PM PST 24
Peak memory	202012 kb
Host	smart-965d0999-61b5-4248-b1f1-babf06b4aa0f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924 34169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3592434169
Directory	/workspace/1.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/10.setup_trans_ignored.137453121
Short name	T18
Test name
Test status
Simulation time	8401498825 ps
CPU time	7.4 seconds
Started	Feb 18 12:54:02 PM PST 24
Finished	Feb 18 12:54:15 PM PST 24
Peak memory	202024 kb
Host	smart-60971aef-7fb0-4e41-8246-5e4d4f24f42d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13745 3121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.setup_trans_ignored.137453121
Directory	/workspace/10.setup_trans_ignored/latest

Test location	/workspace/coverage/default/10.usbdev_nak_trans.3709730654
Short name	T79
Test name
Test status
Simulation time	8421546856 ps
CPU time	7.28 seconds
Started	Feb 18 12:54:18 PM PST 24
Finished	Feb 18 12:54:31 PM PST 24
Peak memory	202036 kb
Host	smart-21d02f2c-7e07-447e-9794-0398b7f00a5d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37097 30654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3709730654
Directory	/workspace/10.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/11.usbdev_nak_trans.824043239
Short name	T73
Test name
Test status
Simulation time	8420927539 ps
CPU time	8.46 seconds
Started	Feb 18 12:54:01 PM PST 24
Finished	Feb 18 12:54:16 PM PST 24
Peak memory	202008 kb
Host	smart-9d81bb02-2a5b-48a8-851c-929d3ed751b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82404 3239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.824043239
Directory	/workspace/11.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/13.usbdev_nak_trans.1993465289
Short name	T15
Test name
Test status
Simulation time	8403819132 ps
CPU time	8.64 seconds
Started	Feb 18 12:54:22 PM PST 24
Finished	Feb 18 12:54:38 PM PST 24
Peak memory	202016 kb
Host	smart-a51c064a-0aa4-43d8-8aad-37b86ad13eb1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19934 65289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1993465289
Directory	/workspace/13.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/14.usbdev_nak_trans.1981236642
Short name	T302
Test name
Test status
Simulation time	8409146743 ps
CPU time	8.86 seconds
Started	Feb 18 12:54:17 PM PST 24
Finished	Feb 18 12:54:32 PM PST 24
Peak memory	201896 kb
Host	smart-f3540d2b-2f7d-415b-83d8-5399545b3cea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19812 36642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1981236642
Directory	/workspace/14.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/15.usbdev_nak_trans.1952610033
Short name	T332
Test name
Test status
Simulation time	8404260194 ps
CPU time	7.14 seconds
Started	Feb 18 12:54:24 PM PST 24
Finished	Feb 18 12:54:38 PM PST 24
Peak memory	202016 kb
Host	smart-e3265768-afc7-4ac8-9464-e8a182a97d54
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19526 10033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1952610033
Directory	/workspace/15.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/16.usbdev_nak_trans.4086609470
Short name	T71
Test name
Test status
Simulation time	8399013737 ps
CPU time	7.16 seconds
Started	Feb 18 12:54:23 PM PST 24
Finished	Feb 18 12:54:37 PM PST 24
Peak memory	201876 kb
Host	smart-bb3dea89-64f5-49f2-bc13-ef8b9ca6ad89
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40866 09470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.4086609470
Directory	/workspace/16.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/17.usbdev_nak_trans.723598958
Short name	T83
Test name
Test status
Simulation time	8417196952 ps
CPU time	7.49 seconds
Started	Feb 18 12:54:29 PM PST 24
Finished	Feb 18 12:54:42 PM PST 24
Peak memory	201856 kb
Host	smart-eebe6f37-cb28-45bd-a601-fa0025ccd3b0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72359 8958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.723598958
Directory	/workspace/17.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/18.usbdev_nak_trans.4286035940
Short name	T74
Test name
Test status
Simulation time	8391348783 ps
CPU time	8.17 seconds
Started	Feb 18 12:54:18 PM PST 24
Finished	Feb 18 12:54:32 PM PST 24
Peak memory	202000 kb
Host	smart-49dcda5c-fb63-41d5-846a-ba052d674375
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42860 35940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4286035940
Directory	/workspace/18.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/27.usbdev_nak_trans.862163828
Short name	T335
Test name
Test status
Simulation time	8447792909 ps
CPU time	9.68 seconds
Started	Feb 18 12:54:59 PM PST 24
Finished	Feb 18 12:55:19 PM PST 24
Peak memory	201964 kb
Host	smart-4f235e36-c4c0-4342-9234-e4f771ee4fda
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86216 3828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.862163828
Directory	/workspace/27.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/29.usbdev_nak_trans.4257826419
Short name	T69
Test name
Test status
Simulation time	8415850431 ps
CPU time	7.65 seconds
Started	Feb 18 12:54:55 PM PST 24
Finished	Feb 18 12:55:13 PM PST 24
Peak memory	201944 kb
Host	smart-0c5de9f0-2136-4499-90b0-2d3969ebca2f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578 26419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.4257826419
Directory	/workspace/29.usbdev_nak_trans/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.242175108
Short name	T120
Test name
Test status
Simulation time	161907539 ps
CPU time	5.11 seconds
Started	Feb 18 12:27:45 PM PST 24
Finished	Feb 18 12:27:52 PM PST 24
Peak memory	210952 kb
Host	smart-77d3af50-f5e8-487d-a73d-7058ccfad5cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242175108 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.242175108
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1399021974
Short name	T359
Test name
Test status
Simulation time	57069540 ps
CPU time	0.8 seconds
Started	Feb 18 12:27:56 PM PST 24
Finished	Feb 18 12:28:03 PM PST 24
Peak memory	202568 kb
Host	smart-3cd8d3f0-2a7c-4c79-a997-2edc6d6d0ca4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399021974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1399021974
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.967411224
Short name	T380
Test name
Test status
Simulation time	151141458 ps
CPU time	2.26 seconds
Started	Feb 18 12:27:54 PM PST 24
Finished	Feb 18 12:28:02 PM PST 24
Peak memory	201768 kb
Host	smart-3076ea9e-5233-46e7-8e48-d5778bb7e494
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=967411224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.967411224
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1072061719
Short name	T355
Test name
Test status
Simulation time	152441235 ps
CPU time	3.7 seconds
Started	Feb 18 12:27:59 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	201836 kb
Host	smart-2e94ae25-195b-4cd3-b840-074eb9d894bd
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1072061719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1072061719
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2656855099
Short name	T369
Test name
Test status
Simulation time	74553259 ps
CPU time	1.05 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202896 kb
Host	smart-e77efa22-3f0f-4f72-a1ec-6d83d0918ba1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656855099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.2656855099
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3371913116
Short name	T166
Test name
Test status
Simulation time	302662551 ps
CPU time	3.17 seconds
Started	Feb 18 12:28:00 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	202824 kb
Host	smart-55a2e197-28b7-4a62-a974-fcea8c493736
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3371913116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3371913116
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1353572684
Short name	T50
Test name
Test status
Simulation time	121889111 ps
CPU time	3.23 seconds
Started	Feb 18 12:27:47 PM PST 24
Finished	Feb 18 12:27:51 PM PST 24
Peak memory	201924 kb
Host	smart-ca88b83b-2fc0-482f-9900-ec784ebd81a1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353572684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1353572684
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4103194521
Short name	T362
Test name
Test status
Simulation time	238660600 ps
CPU time	3.48 seconds
Started	Feb 18 12:27:46 PM PST 24
Finished	Feb 18 12:27:51 PM PST 24
Peak memory	210024 kb
Host	smart-f4dc58e2-e436-481d-999f-1e1422c8fa57
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103194521 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.4103194521
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2732433754
Short name	T164
Test name
Test status
Simulation time	51540691 ps
CPU time	0.79 seconds
Started	Feb 18 12:28:08 PM PST 24
Finished	Feb 18 12:28:16 PM PST 24
Peak memory	202592 kb
Host	smart-59426caa-fefb-481a-bec1-1374dfd2c085
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732433754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2732433754
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.267031749
Short name	T139
Test name
Test status
Simulation time	98053430 ps
CPU time	1.39 seconds
Started	Feb 18 12:27:54 PM PST 24
Finished	Feb 18 12:28:01 PM PST 24
Peak memory	201776 kb
Host	smart-2f50baa5-5b91-4bcb-9797-23d2797c300a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=267031749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.267031749
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.827796044
Short name	T363
Test name
Test status
Simulation time	147274952 ps
CPU time	1.15 seconds
Started	Feb 18 12:27:53 PM PST 24
Finished	Feb 18 12:28:00 PM PST 24
Peak memory	202536 kb
Host	smart-0c88c710-1608-4578-ac60-4b1ac56e4310
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827796044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_cs r_outstanding.827796044
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.4288487503
Short name	T385
Test name
Test status
Simulation time	84072797 ps
CPU time	2.62 seconds
Started	Feb 18 12:28:01 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	202604 kb
Host	smart-1094e30d-70ad-45d5-827c-e3ec33b256e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4288487503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.4288487503
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2661844758
Short name	T371
Test name
Test status
Simulation time	204191463 ps
CPU time	2.83 seconds
Started	Feb 18 12:28:02 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	211152 kb
Host	smart-2f5f9f38-f212-4469-adb5-b1aea4814215
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661844758 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2661844758
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3602569379
Short name	T138
Test name
Test status
Simulation time	26499314 ps
CPU time	0.8 seconds
Started	Feb 18 12:28:19 PM PST 24
Finished	Feb 18 12:28:25 PM PST 24
Peak memory	202668 kb
Host	smart-2aa2d50f-3ddf-45bc-8e23-9f57da235bd9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602569379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3602569379
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.551918674
Short name	T117
Test name
Test status
Simulation time	106238580 ps
CPU time	1.4 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:11 PM PST 24
Peak memory	202916 kb
Host	smart-d0356a25-66c7-4948-89d3-e0266cb5a665
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551918674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_c sr_outstanding.551918674
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1693206778
Short name	T376
Test name
Test status
Simulation time	84089866 ps
CPU time	2.61 seconds
Started	Feb 18 12:28:22 PM PST 24
Finished	Feb 18 12:28:31 PM PST 24
Peak memory	202796 kb
Host	smart-862781f3-b5bf-4fc9-afcb-7aa82e404b11
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1693206778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1693206778
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2662824378
Short name	T354
Test name
Test status
Simulation time	173229753 ps
CPU time	5.63 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:16 PM PST 24
Peak memory	211300 kb
Host	smart-25a07739-bedd-4729-8fa5-c1497803ac8d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662824378 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2662824378
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3651693412
Short name	T364
Test name
Test status
Simulation time	30219399 ps
CPU time	0.84 seconds
Started	Feb 18 12:28:03 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	201812 kb
Host	smart-100b4584-d3bc-45d4-9c37-476cb7f5b1a4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651693412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3651693412
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3805234254
Short name	T141
Test name
Test status
Simulation time	154318972 ps
CPU time	1.62 seconds
Started	Feb 18 12:28:21 PM PST 24
Finished	Feb 18 12:28:30 PM PST 24
Peak memory	202876 kb
Host	smart-7d3775e2-7a6e-49c6-b600-077cf2063318
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805234254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.3805234254
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2117154098
Short name	T119
Test name
Test status
Simulation time	82893321 ps
CPU time	2.37 seconds
Started	Feb 18 12:28:03 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202784 kb
Host	smart-9f53bb84-5893-4bca-81c2-69bf0ac2bb4e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2117154098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2117154098
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4129090151
Short name	T169
Test name
Test status
Simulation time	308787874 ps
CPU time	4.11 seconds
Started	Feb 18 12:28:18 PM PST 24
Finished	Feb 18 12:28:28 PM PST 24
Peak memory	202884 kb
Host	smart-275c592b-3839-4f8e-be93-a5440fad422b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4129090151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4129090151
Directory	/workspace/11.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2273551496
Short name	T344
Test name
Test status
Simulation time	62641169 ps
CPU time	0.83 seconds
Started	Feb 18 12:28:11 PM PST 24
Finished	Feb 18 12:28:18 PM PST 24
Peak memory	202624 kb
Host	smart-a6fc1a35-64e8-4287-b2d1-15c98498d8d9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273551496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2273551496
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1234205438
Short name	T391
Test name
Test status
Simulation time	77039354 ps
CPU time	1.03 seconds
Started	Feb 18 12:28:21 PM PST 24
Finished	Feb 18 12:28:29 PM PST 24
Peak memory	202860 kb
Host	smart-6a1e0f8e-f85b-4f5d-bfdc-2f8390cb9e02
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234205438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_ csr_outstanding.1234205438
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.66805565
Short name	T379
Test name
Test status
Simulation time	49152978 ps
CPU time	1.6 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:11 PM PST 24
Peak memory	202844 kb
Host	smart-caa7b31a-3b66-4eca-b6c3-0ce77bca685f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=66805565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.66805565
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.737555785
Short name	T40
Test name
Test status
Simulation time	205530534 ps
CPU time	2.78 seconds
Started	Feb 18 12:28:02 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	211108 kb
Host	smart-f697a023-2102-4022-a5e5-5439bbfcab59
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737555785 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.737555785
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.283460426
Short name	T140
Test name
Test status
Simulation time	65714720 ps
CPU time	1.06 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:11 PM PST 24
Peak memory	202956 kb
Host	smart-1dcb2a91-32bf-44e8-9c96-babb6885d4ad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283460426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.283460426
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3550739661
Short name	T356
Test name
Test status
Simulation time	116709715 ps
CPU time	1.43 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:11 PM PST 24
Peak memory	202872 kb
Host	smart-2f01aae8-d63c-46b0-9e46-d5ee2ba5aae7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3550739661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3550739661
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2485891177
Short name	T126
Test name
Test status
Simulation time	383735804 ps
CPU time	3.98 seconds
Started	Feb 18 12:27:55 PM PST 24
Finished	Feb 18 12:28:05 PM PST 24
Peak memory	202524 kb
Host	smart-c82a7270-1edd-4596-9d27-aebda3d993d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2485891177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2485891177
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.711217978
Short name	T134
Test name
Test status
Simulation time	55465299 ps
CPU time	0.98 seconds
Started	Feb 18 12:28:04 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202856 kb
Host	smart-e3813562-40fa-4ec8-b5fa-c7f2bbf57b7b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711217978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.711217978
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.323844788
Short name	T392
Test name
Test status
Simulation time	76930350 ps
CPU time	1.01 seconds
Started	Feb 18 12:28:04 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202896 kb
Host	smart-2590469c-fdfd-46e7-8d46-b68633ba4765
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323844788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_c sr_outstanding.323844788
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.4032491504
Short name	T127
Test name
Test status
Simulation time	61607769 ps
CPU time	2.07 seconds
Started	Feb 18 12:27:53 PM PST 24
Finished	Feb 18 12:28:01 PM PST 24
Peak memory	202724 kb
Host	smart-1098a5e2-7290-4885-a003-b61f06d5e87e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4032491504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.4032491504
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.355447376
Short name	T384
Test name
Test status
Simulation time	34486709 ps
CPU time	0.87 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:11 PM PST 24
Peak memory	202808 kb
Host	smart-cbdbf324-0a05-420c-96d4-0a8d3b3e333f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355447376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.355447376
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3359929558
Short name	T377
Test name
Test status
Simulation time	80256842 ps
CPU time	1.04 seconds
Started	Feb 18 12:28:09 PM PST 24
Finished	Feb 18 12:28:17 PM PST 24
Peak memory	202868 kb
Host	smart-a23135a9-a28e-41d0-a0d1-da6a3e396755
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359929558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.3359929558
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1483330590
Short name	T350
Test name
Test status
Simulation time	96117978 ps
CPU time	1.44 seconds
Started	Feb 18 12:28:17 PM PST 24
Finished	Feb 18 12:28:24 PM PST 24
Peak memory	202784 kb
Host	smart-7afa299e-cb82-4dfb-9ca2-09c80d4a3548
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1483330590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1483330590
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2225170582
Short name	T346
Test name
Test status
Simulation time	142379300 ps
CPU time	2.35 seconds
Started	Feb 18 12:28:14 PM PST 24
Finished	Feb 18 12:28:22 PM PST 24
Peak memory	202864 kb
Host	smart-1490d877-0835-441a-a654-9224ad406abb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2225170582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2225170582
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.920725160
Short name	T368
Test name
Test status
Simulation time	176226355 ps
CPU time	5.7 seconds
Started	Feb 18 12:28:17 PM PST 24
Finished	Feb 18 12:28:28 PM PST 24
Peak memory	211144 kb
Host	smart-d7608e17-f697-41c3-bcff-b183befc00a8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920725160 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.920725160
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1897300286
Short name	T372
Test name
Test status
Simulation time	33312329 ps
CPU time	0.93 seconds
Started	Feb 18 12:28:22 PM PST 24
Finished	Feb 18 12:28:29 PM PST 24
Peak memory	202872 kb
Host	smart-f7b6933f-e6f4-4eaa-8680-def7877347a0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897300286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1897300286
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3554854876
Short name	T381
Test name
Test status
Simulation time	129234413 ps
CPU time	1.43 seconds
Started	Feb 18 12:28:06 PM PST 24
Finished	Feb 18 12:28:14 PM PST 24
Peak memory	202832 kb
Host	smart-65ef4c63-844b-4a8b-b5e1-548647815d80
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554854876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.3554854876
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.31558250
Short name	T374
Test name
Test status
Simulation time	77484458 ps
CPU time	2.29 seconds
Started	Feb 18 12:28:03 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202780 kb
Host	smart-9719aaee-4425-4fae-b2ec-ad423edb705b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=31558250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.31558250
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4248725388
Short name	T383
Test name
Test status
Simulation time	44945295 ps
CPU time	0.79 seconds
Started	Feb 18 12:28:23 PM PST 24
Finished	Feb 18 12:28:30 PM PST 24
Peak memory	202596 kb
Host	smart-7f2dd261-47ac-4d14-a7e2-8de48bfb7fe8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248725388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4248725388
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1642109255
Short name	T47
Test name
Test status
Simulation time	133717363 ps
CPU time	1.6 seconds
Started	Feb 18 12:28:07 PM PST 24
Finished	Feb 18 12:28:15 PM PST 24
Peak memory	202692 kb
Host	smart-565342b3-23f8-4c4b-9d7f-390970665d15
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642109255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.1642109255
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3981593889
Short name	T39
Test name
Test status
Simulation time	203927906 ps
CPU time	2.33 seconds
Started	Feb 18 12:27:54 PM PST 24
Finished	Feb 18 12:28:02 PM PST 24
Peak memory	201996 kb
Host	smart-1b95377e-ddc6-4b56-8c69-09c5fdeaa989
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3981593889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3981593889
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.225277134
Short name	T389
Test name
Test status
Simulation time	88759085 ps
CPU time	2.59 seconds
Started	Feb 18 12:28:13 PM PST 24
Finished	Feb 18 12:28:21 PM PST 24
Peak memory	211056 kb
Host	smart-09693f99-ebde-45d6-bc9d-4101b0bdf155
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225277134 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.225277134
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2868934877
Short name	T360
Test name
Test status
Simulation time	35637965 ps
CPU time	0.78 seconds
Started	Feb 18 12:28:04 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202372 kb
Host	smart-7209889a-935d-4024-83fe-3d16094c1430
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868934877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2868934877
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2479639147
Short name	T388
Test name
Test status
Simulation time	79343061 ps
CPU time	1.03 seconds
Started	Feb 18 12:28:08 PM PST 24
Finished	Feb 18 12:28:16 PM PST 24
Peak memory	202924 kb
Host	smart-52f96171-930d-4a3a-a116-3960f2f6a1b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479639147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.2479639147
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1547380787
Short name	T347
Test name
Test status
Simulation time	120669200 ps
CPU time	1.61 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:13 PM PST 24
Peak memory	203008 kb
Host	smart-3eb7f892-affb-45e3-b654-eff403b0e5c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1547380787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1547380787
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.406546601
Short name	T165
Test name
Test status
Simulation time	305575391 ps
CPU time	2.85 seconds
Started	Feb 18 12:28:11 PM PST 24
Finished	Feb 18 12:28:20 PM PST 24
Peak memory	202820 kb
Host	smart-f7de443b-13a7-4f65-80d5-36e56397c09a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=406546601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.406546601
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1003533402
Short name	T367
Test name
Test status
Simulation time	30668589 ps
CPU time	0.79 seconds
Started	Feb 18 12:28:15 PM PST 24
Finished	Feb 18 12:28:21 PM PST 24
Peak memory	201820 kb
Host	smart-52fcbb0a-054a-4931-8b68-f859512bec61
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003533402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1003533402
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3003007283
Short name	T382
Test name
Test status
Simulation time	36796293 ps
CPU time	0.97 seconds
Started	Feb 18 12:28:17 PM PST 24
Finished	Feb 18 12:28:24 PM PST 24
Peak memory	202892 kb
Host	smart-20b9a289-2697-4573-b55a-3874c49dd25b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003007283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.3003007283
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1313630554
Short name	T122
Test name
Test status
Simulation time	231594628 ps
CPU time	2.96 seconds
Started	Feb 18 12:28:10 PM PST 24
Finished	Feb 18 12:28:20 PM PST 24
Peak memory	202824 kb
Host	smart-aed2228a-bf95-44fa-88b9-9f3a7fa5a5f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1313630554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1313630554
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1747928280
Short name	T171
Test name
Test status
Simulation time	170655063 ps
CPU time	2.27 seconds
Started	Feb 18 12:27:58 PM PST 24
Finished	Feb 18 12:28:08 PM PST 24
Peak memory	202732 kb
Host	smart-657e9628-053f-44ed-ae1a-1618314f804e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1747928280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1747928280
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.169363881
Short name	T387
Test name
Test status
Simulation time	58146231 ps
CPU time	1.03 seconds
Started	Feb 18 12:28:02 PM PST 24
Finished	Feb 18 12:28:08 PM PST 24
Peak memory	202904 kb
Host	smart-1f5ade74-7001-4640-a8f8-5c65f156deee
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169363881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.169363881
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2540514491
Short name	T130
Test name
Test status
Simulation time	76900296 ps
CPU time	2.11 seconds
Started	Feb 18 12:27:55 PM PST 24
Finished	Feb 18 12:28:03 PM PST 24
Peak memory	201372 kb
Host	smart-4a7c12c8-08b2-4f77-a49d-7092fc9eddce
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2540514491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2540514491
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3591939738
Short name	T341
Test name
Test status
Simulation time	320800615 ps
CPU time	2.36 seconds
Started	Feb 18 12:28:08 PM PST 24
Finished	Feb 18 12:28:21 PM PST 24
Peak memory	202600 kb
Host	smart-f5490522-b2aa-40c3-9c7d-035bb6e47746
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3591939738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3591939738
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2321754173
Short name	T373
Test name
Test status
Simulation time	277429891 ps
CPU time	1.71 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:11 PM PST 24
Peak memory	202872 kb
Host	smart-c80c5c1a-5161-4fe0-8217-ccb175a301d9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321754173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.2321754173
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2008838449
Short name	T167
Test name
Test status
Simulation time	274851124 ps
CPU time	2.25 seconds
Started	Feb 18 12:28:18 PM PST 24
Finished	Feb 18 12:28:26 PM PST 24
Peak memory	202820 kb
Host	smart-23520ded-adf5-4c7c-872b-d4e9c7c3924f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2008838449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2008838449
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1402427122
Short name	T135
Test name
Test status
Simulation time	199329488 ps
CPU time	2.21 seconds
Started	Feb 18 12:27:56 PM PST 24
Finished	Feb 18 12:28:05 PM PST 24
Peak memory	202660 kb
Host	smart-cbd9d841-140a-466d-86c2-f5fbb486f01c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402427122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1402427122
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1678994943
Short name	T343
Test name
Test status
Simulation time	187398681 ps
CPU time	4.71 seconds
Started	Feb 18 12:27:58 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	202916 kb
Host	smart-eca04b5f-549f-4228-8f32-b5baf54df62b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678994943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1678994943
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1278978259
Short name	T53
Test name
Test status
Simulation time	29786731 ps
CPU time	0.72 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202572 kb
Host	smart-1c1143ba-7f38-481a-a6a0-783911a62f34
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278978259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1278978259
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1548968123
Short name	T123
Test name
Test status
Simulation time	151139477 ps
CPU time	5.04 seconds
Started	Feb 18 12:27:58 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	211132 kb
Host	smart-f91313cf-1917-4b25-8595-7ff833cc9370
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548968123 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.1548968123
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1214738252
Short name	T136
Test name
Test status
Simulation time	53905078 ps
CPU time	0.83 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:10 PM PST 24
Peak memory	202564 kb
Host	smart-ca826f08-6efc-4127-80a6-cc5be0bb0a28
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214738252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1214738252
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.594241978
Short name	T128
Test name
Test status
Simulation time	87262833 ps
CPU time	1.34 seconds
Started	Feb 18 12:27:45 PM PST 24
Finished	Feb 18 12:27:47 PM PST 24
Peak memory	202156 kb
Host	smart-571dd162-a1ea-4243-9d03-ec67bc86bdff
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=594241978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.594241978
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2282645898
Short name	T349
Test name
Test status
Simulation time	246934358 ps
CPU time	2.39 seconds
Started	Feb 18 12:28:01 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	202700 kb
Host	smart-f144dc62-268c-488f-b8ba-91900eae23d7
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2282645898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2282645898
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3018056831
Short name	T162
Test name
Test status
Simulation time	141686789 ps
CPU time	1.55 seconds
Started	Feb 18 12:28:03 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	202884 kb
Host	smart-fc316680-fd54-4a0b-bb09-6c90e2b55882
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018056831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.3018056831
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3770864731
Short name	T358
Test name
Test status
Simulation time	74077602 ps
CPU time	2.23 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:12 PM PST 24
Peak memory	202836 kb
Host	smart-76137a2d-3889-4d0f-9c7d-63cbca6aec30
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3770864731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3770864731
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2406980415
Short name	T386
Test name
Test status
Simulation time	130101263 ps
CPU time	2.36 seconds
Started	Feb 18 12:27:45 PM PST 24
Finished	Feb 18 12:27:49 PM PST 24
Peak memory	202660 kb
Host	smart-6df87c5c-711f-449a-8501-dfc56546b364
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2406980415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2406980415
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.39245277
Short name	T366
Test name
Test status
Simulation time	107995638 ps
CPU time	3.04 seconds
Started	Feb 18 12:27:52 PM PST 24
Finished	Feb 18 12:28:02 PM PST 24
Peak memory	201916 kb
Host	smart-05deb528-4265-49a3-a8a1-fc2249cc6fdd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39245277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.39245277
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3076660430
Short name	T45
Test name
Test status
Simulation time	29406950 ps
CPU time	0.73 seconds
Started	Feb 18 12:28:01 PM PST 24
Finished	Feb 18 12:28:08 PM PST 24
Peak memory	202408 kb
Host	smart-202f0f38-84ce-42cf-86d5-b3e7dfa06105
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076660430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3076660430
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.580905756
Short name	T351
Test name
Test status
Simulation time	47084911 ps
CPU time	0.8 seconds
Started	Feb 18 12:28:16 PM PST 24
Finished	Feb 18 12:28:22 PM PST 24
Peak memory	202620 kb
Host	smart-ac70667c-15a1-4503-9154-34584ac6ef36
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580905756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.580905756
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.741244042
Short name	T133
Test name
Test status
Simulation time	102678852 ps
CPU time	1.4 seconds
Started	Feb 18 12:28:05 PM PST 24
Finished	Feb 18 12:28:11 PM PST 24
Peak memory	202784 kb
Host	smart-b3dda03d-1fb8-46d0-a750-f6d7207f7cf8
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=741244042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.741244042
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.75541214
Short name	T342
Test name
Test status
Simulation time	464822894 ps
CPU time	4.15 seconds
Started	Feb 18 12:28:03 PM PST 24
Finished	Feb 18 12:28:12 PM PST 24
Peak memory	202584 kb
Host	smart-f8f3a4c0-c3db-429e-83b7-453729f46a45
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=75541214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.75541214
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.675095520
Short name	T132
Test name
Test status
Simulation time	60003241 ps
CPU time	1.27 seconds
Started	Feb 18 12:27:58 PM PST 24
Finished	Feb 18 12:28:06 PM PST 24
Peak memory	202916 kb
Host	smart-b455a6d9-8fda-441d-9d1d-9855dfaa1509
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675095520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_cs r_outstanding.675095520
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.817939314
Short name	T375
Test name
Test status
Simulation time	82326452 ps
CPU time	2.36 seconds
Started	Feb 18 12:27:46 PM PST 24
Finished	Feb 18 12:27:50 PM PST 24
Peak memory	202712 kb
Host	smart-076356ab-e59c-4d90-a37b-8474a39f2544
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=817939314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.817939314
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.93743491
Short name	T163
Test name
Test status
Simulation time	338240057 ps
CPU time	2.74 seconds
Started	Feb 18 12:27:49 PM PST 24
Finished	Feb 18 12:28:03 PM PST 24
Peak memory	201964 kb
Host	smart-1293dcf3-8214-4f31-a255-33b636ceeb0f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=93743491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.93743491
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3942558853
Short name	T137
Test name
Test status
Simulation time	32185091 ps
CPU time	0.77 seconds
Started	Feb 18 12:28:16 PM PST 24
Finished	Feb 18 12:28:23 PM PST 24
Peak memory	202528 kb
Host	smart-137d1aa4-d3ae-4cea-b01b-13fdb985cce2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942558853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3942558853
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3437455848
Short name	T131
Test name
Test status
Simulation time	241911312 ps
CPU time	1.63 seconds
Started	Feb 18 12:28:02 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	202744 kb
Host	smart-a91e7548-ab99-489a-a601-bc81a468b413
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437455848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.3437455848
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3632125319
Short name	T348
Test name
Test status
Simulation time	47297443 ps
CPU time	1.28 seconds
Started	Feb 18 12:28:19 PM PST 24
Finished	Feb 18 12:28:25 PM PST 24
Peak memory	202828 kb
Host	smart-e5b52e0b-dc42-4aa1-902f-b5e817f6c42b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3632125319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3632125319
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2076709621
Short name	T125
Test name
Test status
Simulation time	479896418 ps
CPU time	4.27 seconds
Started	Feb 18 12:28:14 PM PST 24
Finished	Feb 18 12:28:25 PM PST 24
Peak memory	202648 kb
Host	smart-365ee5fb-1f0c-40c0-9457-c5b15b41ae50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2076709621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2076709621
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3931675079
Short name	T390
Test name
Test status
Simulation time	169392686 ps
CPU time	5.16 seconds
Started	Feb 18 12:27:48 PM PST 24
Finished	Feb 18 12:27:55 PM PST 24
Peak memory	210452 kb
Host	smart-e48c425c-9749-42ee-9fd0-8a63c717a0a0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931675079 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3931675079
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3867488646
Short name	T370
Test name
Test status
Simulation time	43825836 ps
CPU time	0.81 seconds
Started	Feb 18 12:27:55 PM PST 24
Finished	Feb 18 12:28:02 PM PST 24
Peak memory	202696 kb
Host	smart-42813658-7c5d-47dd-bdb2-c9a8f66b08b6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867488646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3867488646
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3317237643
Short name	T129
Test name
Test status
Simulation time	73931514 ps
CPU time	1.17 seconds
Started	Feb 18 12:27:58 PM PST 24
Finished	Feb 18 12:28:06 PM PST 24
Peak memory	201764 kb
Host	smart-866c5c5a-dd11-45be-ac37-de78d6717d17
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317237643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.3317237643
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3656958260
Short name	T121
Test name
Test status
Simulation time	494648215 ps
CPU time	4.96 seconds
Started	Feb 18 12:28:04 PM PST 24
Finished	Feb 18 12:28:13 PM PST 24
Peak memory	202624 kb
Host	smart-8c9079be-ca92-4063-b4d8-ac95c7f0802f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3656958260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3656958260
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.614108427
Short name	T345
Test name
Test status
Simulation time	30161602 ps
CPU time	0.88 seconds
Started	Feb 18 12:28:01 PM PST 24
Finished	Feb 18 12:28:13 PM PST 24
Peak memory	202388 kb
Host	smart-5b828488-f352-458e-b0f7-a6467b4b8cfe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614108427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.614108427
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1256938527
Short name	T51
Test name
Test status
Simulation time	37753714 ps
CPU time	0.97 seconds
Started	Feb 18 12:28:04 PM PST 24
Finished	Feb 18 12:28:09 PM PST 24
Peak memory	202652 kb
Host	smart-04c20484-0daf-4125-bf10-3d7883eb7064
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256938527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.1256938527
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.804504052
Short name	T357
Test name
Test status
Simulation time	75695158 ps
CPU time	2.09 seconds
Started	Feb 18 12:27:50 PM PST 24
Finished	Feb 18 12:27:59 PM PST 24
Peak memory	201936 kb
Host	smart-022adf9e-be94-4090-af9c-4a1b04847850
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=804504052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.804504052
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4063089303
Short name	T361
Test name
Test status
Simulation time	35076901 ps
CPU time	0.78 seconds
Started	Feb 18 12:28:06 PM PST 24
Finished	Feb 18 12:28:12 PM PST 24
Peak memory	202676 kb
Host	smart-d3c53788-c437-4d1f-9f92-c26b1f73824b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063089303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.4063089303
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2885019540
Short name	T378
Test name
Test status
Simulation time	121141455 ps
CPU time	1.59 seconds
Started	Feb 18 12:28:16 PM PST 24
Finished	Feb 18 12:28:23 PM PST 24
Peak memory	202884 kb
Host	smart-2bfb7eb0-0bdd-46ca-afef-f4f4560b8e16
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885019540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.2885019540
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4168346327
Short name	T365
Test name
Test status
Simulation time	123076681 ps
CPU time	1.43 seconds
Started	Feb 18 12:28:22 PM PST 24
Finished	Feb 18 12:28:30 PM PST 24
Peak memory	202860 kb
Host	smart-07a77814-d0ec-4cac-91e2-a1bf3fa38a30
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4168346327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4168346327
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1624066504
Short name	T52
Test name
Test status
Simulation time	46362235 ps
CPU time	0.77 seconds
Started	Feb 18 12:28:03 PM PST 24
Finished	Feb 18 12:28:08 PM PST 24
Peak memory	202476 kb
Host	smart-ede8a990-a37f-440d-a688-f491494eb2ed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624066504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1624066504
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.427501015
Short name	T353
Test name
Test status
Simulation time	57550414 ps
CPU time	1.33 seconds
Started	Feb 18 12:28:06 PM PST 24
Finished	Feb 18 12:28:14 PM PST 24
Peak memory	202952 kb
Host	smart-c9b8bb92-ff53-4d1a-b3f3-734ebe53575d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427501015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_cs r_outstanding.427501015
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2436800602
Short name	T352
Test name
Test status
Simulation time	86029532 ps
CPU time	2.42 seconds
Started	Feb 18 12:28:06 PM PST 24
Finished	Feb 18 12:28:15 PM PST 24
Peak memory	202820 kb
Host	smart-85ee6fee-c620-4fec-b50d-4492aa0afdaf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2436800602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2436800602
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.422870275
Short name	T143
Test name
Test status
Simulation time	297338394 ps
CPU time	3.02 seconds
Started	Feb 18 12:28:18 PM PST 24
Finished	Feb 18 12:28:27 PM PST 24
Peak memory	202868 kb
Host	smart-39ce4b32-eca3-46ae-b651-6b00594ac2d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=422870275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.422870275
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/0.setup_trans_ignored.2933762907
Short name	T210
Test name
Test status
Simulation time	8361042186 ps
CPU time	7.8 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:25 PM PST 24
Peak memory	202012 kb
Host	smart-ac81ad6f-ef17-44e2-b37c-33f3e38812d1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29337 62907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.setup_trans_ignored.2933762907
Directory	/workspace/0.setup_trans_ignored/latest

Test location	/workspace/coverage/default/0.usbdev_pkt_sent.3048032664
Short name	T113
Test name
Test status
Simulation time	8429533885 ps
CPU time	8.17 seconds
Started	Feb 18 12:53:50 PM PST 24
Finished	Feb 18 12:54:05 PM PST 24
Peak memory	202036 kb
Host	smart-a7dc1b44-7298-4f2f-8f0b-bff5fcd01a4d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30480 32664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3048032664
Directory	/workspace/0.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/1.setup_trans_ignored.797497105
Short name	T261
Test name
Test status
Simulation time	8360227559 ps
CPU time	7.71 seconds
Started	Feb 18 12:53:49 PM PST 24
Finished	Feb 18 12:54:04 PM PST 24
Peak memory	201940 kb
Host	smart-faa321e9-3c4b-4683-bf27-c9d64702c72f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79749 7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.setup_trans_ignored.797497105
Directory	/workspace/1.setup_trans_ignored/latest

Test location	/workspace/coverage/default/1.usbdev_av_buffer.1194658546
Short name	T304
Test name
Test status
Simulation time	8373248379 ps
CPU time	8.62 seconds
Started	Feb 18 12:53:47 PM PST 24
Finished	Feb 18 12:54:03 PM PST 24
Peak memory	202024 kb
Host	smart-ed6f793f-0e61-4779-8f62-d58b46ecbe92
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11946 58546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1194658546
Directory	/workspace/1.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/1.usbdev_pkt_sent.610743377
Short name	T109
Test name
Test status
Simulation time	8371154809 ps
CPU time	7.41 seconds
Started	Feb 18 12:53:45 PM PST 24
Finished	Feb 18 12:53:56 PM PST 24
Peak memory	201916 kb
Host	smart-1924f13c-567c-41a4-a680-fdc355bf9e54
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61074 3377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.610743377
Directory	/workspace/1.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.318074220
Short name	T41
Test name
Test status
Simulation time	276362265 ps
CPU time	1.16 seconds
Started	Feb 18 12:54:04 PM PST 24
Finished	Feb 18 12:54:10 PM PST 24
Peak memory	217904 kb
Host	smart-5ad31d59-d7ed-4bd9-8f25-b322ff4a0e0d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=318074220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.318074220
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/1.usbdev_smoke.358955915
Short name	T251
Test name
Test status
Simulation time	8371783472 ps
CPU time	7.8 seconds
Started	Feb 18 12:53:46 PM PST 24
Finished	Feb 18 12:54:00 PM PST 24
Peak memory	202012 kb
Host	smart-9c172596-d3a4-420e-bff9-9fb7d307d702
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35895 5915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.358955915
Directory	/workspace/1.usbdev_smoke/latest

Test location	/workspace/coverage/default/10.usbdev_av_buffer.3911414464
Short name	T300
Test name
Test status
Simulation time	8373252065 ps
CPU time	8.25 seconds
Started	Feb 18 12:54:16 PM PST 24
Finished	Feb 18 12:54:30 PM PST 24
Peak memory	201940 kb
Host	smart-c35deb78-7d98-475d-9ccf-27002df38a77
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114 14464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3911414464
Directory	/workspace/10.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/10.usbdev_pkt_sent.2839088463
Short name	T232
Test name
Test status
Simulation time	8419633459 ps
CPU time	8.79 seconds
Started	Feb 18 12:54:08 PM PST 24
Finished	Feb 18 12:54:21 PM PST 24
Peak memory	202004 kb
Host	smart-6b42bea3-21f3-4e47-983b-fd8c4e25d9fc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390 88463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2839088463
Directory	/workspace/10.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/10.usbdev_smoke.4025831277
Short name	T66
Test name
Test status
Simulation time	8375266278 ps
CPU time	7.14 seconds
Started	Feb 18 12:54:14 PM PST 24
Finished	Feb 18 12:54:27 PM PST 24
Peak memory	202024 kb
Host	smart-4964c859-a2f0-4091-9996-6672aeb72119
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40258 31277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.4025831277
Directory	/workspace/10.usbdev_smoke/latest

Test location	/workspace/coverage/default/11.in_trans.1858330735
Short name	T14
Test name
Test status
Simulation time	8385325590 ps
CPU time	9.24 seconds
Started	Feb 18 12:54:08 PM PST 24
Finished	Feb 18 12:54:22 PM PST 24
Peak memory	202004 kb
Host	smart-d2833f76-8020-4f6b-8c92-2bc8ed4ebbd4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18583 30735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.in_trans.1858330735
Directory	/workspace/11.in_trans/latest

Test location	/workspace/coverage/default/11.setup_trans_ignored.3141725012
Short name	T17
Test name
Test status
Simulation time	8357955701 ps
CPU time	8.16 seconds
Started	Feb 18 12:54:14 PM PST 24
Finished	Feb 18 12:54:28 PM PST 24
Peak memory	202008 kb
Host	smart-1d0d1839-abf8-409e-b901-172c3012a286
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31417 25012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.setup_trans_ignored.3141725012
Directory	/workspace/11.setup_trans_ignored/latest

Test location	/workspace/coverage/default/11.usbdev_av_buffer.1218501906
Short name	T37
Test name
Test status
Simulation time	8375934964 ps
CPU time	7 seconds
Started	Feb 18 12:54:10 PM PST 24
Finished	Feb 18 12:54:22 PM PST 24
Peak memory	202024 kb
Host	smart-d89e88a4-2260-4f6d-85ef-81920f74ad49
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12185 01906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1218501906
Directory	/workspace/11.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/11.usbdev_pkt_sent.3727969044
Short name	T107
Test name
Test status
Simulation time	8425592253 ps
CPU time	7.4 seconds
Started	Feb 18 12:54:15 PM PST 24
Finished	Feb 18 12:54:28 PM PST 24
Peak memory	202012 kb
Host	smart-897e7304-2b11-48ea-b84a-4582cd7d1cc6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37279 69044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3727969044
Directory	/workspace/11.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/11.usbdev_smoke.3295898212
Short name	T263
Test name
Test status
Simulation time	8373536236 ps
CPU time	7.07 seconds
Started	Feb 18 12:54:14 PM PST 24
Finished	Feb 18 12:54:27 PM PST 24
Peak memory	201972 kb
Host	smart-41ba7e14-c96d-4bfa-b7fc-87fb088b0913
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958 98212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3295898212
Directory	/workspace/11.usbdev_smoke/latest

Test location	/workspace/coverage/default/12.setup_trans_ignored.2324764624
Short name	T189
Test name
Test status
Simulation time	8366363200 ps
CPU time	6.91 seconds
Started	Feb 18 12:54:16 PM PST 24
Finished	Feb 18 12:54:29 PM PST 24
Peak memory	202048 kb
Host	smart-d50438b0-605c-4689-b136-d7ea861d005c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23247 64624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.setup_trans_ignored.2324764624
Directory	/workspace/12.setup_trans_ignored/latest

Test location	/workspace/coverage/default/12.usbdev_av_buffer.3642988490
Short name	T272
Test name
Test status
Simulation time	8366903639 ps
CPU time	8.27 seconds
Started	Feb 18 12:54:11 PM PST 24
Finished	Feb 18 12:54:25 PM PST 24
Peak memory	202020 kb
Host	smart-5a76ce60-e97b-417a-929e-0c33bc9a9e4a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36429 88490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3642988490
Directory	/workspace/12.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/12.usbdev_pkt_sent.1599472165
Short name	T318
Test name
Test status
Simulation time	8437268061 ps
CPU time	9.91 seconds
Started	Feb 18 12:54:24 PM PST 24
Finished	Feb 18 12:54:41 PM PST 24
Peak memory	201992 kb
Host	smart-a620681b-fdd7-4fbd-b067-a081ee1500b3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15994 72165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1599472165
Directory	/workspace/12.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/12.usbdev_smoke.818426949
Short name	T330
Test name
Test status
Simulation time	8370010240 ps
CPU time	7.26 seconds
Started	Feb 18 12:54:23 PM PST 24
Finished	Feb 18 12:54:37 PM PST 24
Peak memory	201984 kb
Host	smart-6a19e40c-0146-4903-af13-b3b5999cc2f7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81842 6949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.818426949
Directory	/workspace/12.usbdev_smoke/latest

Test location	/workspace/coverage/default/13.setup_trans_ignored.2774161032
Short name	T233
Test name
Test status
Simulation time	8360401768 ps
CPU time	7.38 seconds
Started	Feb 18 12:54:22 PM PST 24
Finished	Feb 18 12:54:37 PM PST 24
Peak memory	201984 kb
Host	smart-08a1d533-fbd6-4c53-91ff-2de9ceed694c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741 61032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.setup_trans_ignored.2774161032
Directory	/workspace/13.setup_trans_ignored/latest

Test location	/workspace/coverage/default/13.usbdev_av_buffer.2500169697
Short name	T269
Test name
Test status
Simulation time	8387322423 ps
CPU time	9.52 seconds
Started	Feb 18 12:54:16 PM PST 24
Finished	Feb 18 12:54:32 PM PST 24
Peak memory	202000 kb
Host	smart-56f603b1-20d6-480b-9c20-5ec9dbb5418b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25001 69697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2500169697
Directory	/workspace/13.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/13.usbdev_pkt_sent.1617219126
Short name	T184
Test name
Test status
Simulation time	8484912799 ps
CPU time	7.97 seconds
Started	Feb 18 12:54:22 PM PST 24
Finished	Feb 18 12:54:37 PM PST 24
Peak memory	202024 kb
Host	smart-af1e0880-3e4e-414e-8c51-0f7abab344f5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16172 19126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1617219126
Directory	/workspace/13.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/13.usbdev_smoke.3746412466
Short name	T207
Test name
Test status
Simulation time	8365267377 ps
CPU time	8.87 seconds
Started	Feb 18 12:54:20 PM PST 24
Finished	Feb 18 12:54:36 PM PST 24
Peak memory	201976 kb
Host	smart-9c8a7cae-c88c-4c3b-a11a-7e24ae5b8fd3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37464 12466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3746412466
Directory	/workspace/13.usbdev_smoke/latest

Test location	/workspace/coverage/default/14.in_trans.2897920202
Short name	T321
Test name
Test status
Simulation time	8437360609 ps
CPU time	7.46 seconds
Started	Feb 18 12:54:29 PM PST 24
Finished	Feb 18 12:54:42 PM PST 24
Peak memory	202008 kb
Host	smart-07955752-7293-4caf-a9e2-22ca7d3739ea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28979 20202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.in_trans.2897920202
Directory	/workspace/14.in_trans/latest

Test location	/workspace/coverage/default/14.setup_trans_ignored.2838788852
Short name	T3
Test name
Test status
Simulation time	8366766786 ps
CPU time	7.54 seconds
Started	Feb 18 12:54:18 PM PST 24
Finished	Feb 18 12:54:31 PM PST 24
Peak memory	201992 kb
Host	smart-4880cc98-b826-4612-ac90-e80a30aa639b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28387 88852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.setup_trans_ignored.2838788852
Directory	/workspace/14.setup_trans_ignored/latest

Test location	/workspace/coverage/default/14.usbdev_av_buffer.4132808612
Short name	T28
Test name
Test status
Simulation time	8366382442 ps
CPU time	8.46 seconds
Started	Feb 18 12:54:26 PM PST 24
Finished	Feb 18 12:54:41 PM PST 24
Peak memory	202008 kb
Host	smart-7ff25198-3d46-41ec-836f-7b44d232b88b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41328 08612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.4132808612
Directory	/workspace/14.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/14.usbdev_pkt_sent.542840999
Short name	T114
Test name
Test status
Simulation time	8383483339 ps
CPU time	8.2 seconds
Started	Feb 18 12:54:32 PM PST 24
Finished	Feb 18 12:54:44 PM PST 24
Peak memory	201932 kb
Host	smart-5ca9305e-5e4e-496f-b597-716d2578cce8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54284 0999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.542840999
Directory	/workspace/14.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/14.usbdev_smoke.1008927936
Short name	T67
Test name
Test status
Simulation time	8367839687 ps
CPU time	7.03 seconds
Started	Feb 18 12:54:30 PM PST 24
Finished	Feb 18 12:54:42 PM PST 24
Peak memory	202024 kb
Host	smart-de5f117b-e5d5-4595-8715-1b3f8ac4b631
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10089 27936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1008927936
Directory	/workspace/14.usbdev_smoke/latest

Test location	/workspace/coverage/default/15.setup_trans_ignored.4044461381
Short name	T287
Test name
Test status
Simulation time	8362327612 ps
CPU time	7.48 seconds
Started	Feb 18 12:54:17 PM PST 24
Finished	Feb 18 12:54:31 PM PST 24
Peak memory	202024 kb
Host	smart-873a1f82-9f89-464f-90f9-5e4d720d3141
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40444 61381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.setup_trans_ignored.4044461381
Directory	/workspace/15.setup_trans_ignored/latest

Test location	/workspace/coverage/default/15.usbdev_av_buffer.1057416905
Short name	T242
Test name
Test status
Simulation time	8370063477 ps
CPU time	8.7 seconds
Started	Feb 18 12:54:18 PM PST 24
Finished	Feb 18 12:54:33 PM PST 24
Peak memory	201992 kb
Host	smart-9195384b-b84b-474f-b9c2-24f3d65029ad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10574 16905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1057416905
Directory	/workspace/15.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/15.usbdev_pkt_sent.2710333191
Short name	T103
Test name
Test status
Simulation time	8414445015 ps
CPU time	8.03 seconds
Started	Feb 18 12:54:17 PM PST 24
Finished	Feb 18 12:54:31 PM PST 24
Peak memory	202020 kb
Host	smart-0dd8cb7c-a883-4574-8bea-33c4abfb32cd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27103 33191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2710333191
Directory	/workspace/15.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/15.usbdev_smoke.4185652584
Short name	T63
Test name
Test status
Simulation time	8372062488 ps
CPU time	7.62 seconds
Started	Feb 18 12:54:23 PM PST 24
Finished	Feb 18 12:54:38 PM PST 24
Peak memory	202020 kb
Host	smart-a764a1eb-871a-4934-9b15-aa3eca528e60
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41856 52584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.4185652584
Directory	/workspace/15.usbdev_smoke/latest

Test location	/workspace/coverage/default/16.in_trans.4215828099
Short name	T146
Test name
Test status
Simulation time	8432816267 ps
CPU time	7.63 seconds
Started	Feb 18 12:54:20 PM PST 24
Finished	Feb 18 12:54:34 PM PST 24
Peak memory	202020 kb
Host	smart-37b25445-4362-4b66-9baf-1e968cb28599
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42158 28099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.in_trans.4215828099
Directory	/workspace/16.in_trans/latest

Test location	/workspace/coverage/default/16.setup_trans_ignored.3377757779
Short name	T252
Test name
Test status
Simulation time	8357369831 ps
CPU time	7.35 seconds
Started	Feb 18 12:54:26 PM PST 24
Finished	Feb 18 12:54:40 PM PST 24
Peak memory	202008 kb
Host	smart-66113f57-a634-4554-87d7-595b057be0c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33777 57779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.setup_trans_ignored.3377757779
Directory	/workspace/16.setup_trans_ignored/latest

Test location	/workspace/coverage/default/16.usbdev_av_buffer.512131187
Short name	T202
Test name
Test status
Simulation time	8368305011 ps
CPU time	9.34 seconds
Started	Feb 18 12:54:24 PM PST 24
Finished	Feb 18 12:54:41 PM PST 24
Peak memory	202016 kb
Host	smart-3443e280-d079-4ef2-90ab-2224455574cd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51213 1187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.512131187
Directory	/workspace/16.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/16.usbdev_pkt_sent.786529749
Short name	T186
Test name
Test status
Simulation time	8375482429 ps
CPU time	7.24 seconds
Started	Feb 18 12:54:29 PM PST 24
Finished	Feb 18 12:54:42 PM PST 24
Peak memory	202000 kb
Host	smart-2eca404b-97e5-4c61-9ff4-07405905e59a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78652 9749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.786529749
Directory	/workspace/16.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/16.usbdev_smoke.1053074921
Short name	T64
Test name
Test status
Simulation time	8374971220 ps
CPU time	7.51 seconds
Started	Feb 18 12:54:24 PM PST 24
Finished	Feb 18 12:54:38 PM PST 24
Peak memory	202004 kb
Host	smart-6685bdef-a88c-4045-ba2c-c4d21f8e29c1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10530 74921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1053074921
Directory	/workspace/16.usbdev_smoke/latest

Test location	/workspace/coverage/default/17.in_trans.277454750
Short name	T211
Test name
Test status
Simulation time	8452066730 ps
CPU time	7.93 seconds
Started	Feb 18 12:54:56 PM PST 24
Finished	Feb 18 12:55:14 PM PST 24
Peak memory	202012 kb
Host	smart-4b585fe0-b4fb-4763-b315-2265f1b872d0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27745 4750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.in_trans.277454750
Directory	/workspace/17.in_trans/latest

Test location	/workspace/coverage/default/17.setup_trans_ignored.1804218849
Short name	T227
Test name
Test status
Simulation time	8358107028 ps
CPU time	7.68 seconds
Started	Feb 18 12:54:24 PM PST 24
Finished	Feb 18 12:54:39 PM PST 24
Peak memory	202008 kb
Host	smart-22162b54-fc05-469e-a87b-6b2ccba473c5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18042 18849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.setup_trans_ignored.1804218849
Directory	/workspace/17.setup_trans_ignored/latest

Test location	/workspace/coverage/default/17.usbdev_av_buffer.2741945786
Short name	T36
Test name
Test status
Simulation time	8372662032 ps
CPU time	6.96 seconds
Started	Feb 18 12:54:25 PM PST 24
Finished	Feb 18 12:54:39 PM PST 24
Peak memory	201960 kb
Host	smart-ed15d88b-cf81-45db-954c-178cf1de5cc5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27419 45786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2741945786
Directory	/workspace/17.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/17.usbdev_smoke.2397963783
Short name	T187
Test name
Test status
Simulation time	8375232141 ps
CPU time	7.09 seconds
Started	Feb 18 12:54:25 PM PST 24
Finished	Feb 18 12:54:39 PM PST 24
Peak memory	202004 kb
Host	smart-03764779-a02c-49ed-98c9-856438b6c311
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979 63783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2397963783
Directory	/workspace/17.usbdev_smoke/latest

Test location	/workspace/coverage/default/18.in_trans.1526290749
Short name	T104
Test name
Test status
Simulation time	8434304644 ps
CPU time	9.09 seconds
Started	Feb 18 12:54:24 PM PST 24
Finished	Feb 18 12:54:40 PM PST 24
Peak memory	202020 kb
Host	smart-1a8046fa-b048-48ef-a0d7-ff53bed52bc4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15262 90749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.in_trans.1526290749
Directory	/workspace/18.in_trans/latest

Test location	/workspace/coverage/default/18.setup_trans_ignored.1559797310
Short name	T265
Test name
Test status
Simulation time	8359597682 ps
CPU time	7.11 seconds
Started	Feb 18 12:54:26 PM PST 24
Finished	Feb 18 12:54:40 PM PST 24
Peak memory	202036 kb
Host	smart-48ea0b7a-6459-4f57-9bc1-09a706b2efeb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15597 97310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.setup_trans_ignored.1559797310
Directory	/workspace/18.setup_trans_ignored/latest

Test location	/workspace/coverage/default/18.usbdev_av_buffer.286924490
Short name	T316
Test name
Test status
Simulation time	8365443189 ps
CPU time	8.35 seconds
Started	Feb 18 12:54:39 PM PST 24
Finished	Feb 18 12:54:50 PM PST 24
Peak memory	201936 kb
Host	smart-e9bbbc2f-d969-4b0c-9537-2ded4bbc9b02
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28692 4490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.286924490
Directory	/workspace/18.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/18.usbdev_pkt_sent.3786119589
Short name	T214
Test name
Test status
Simulation time	8389571052 ps
CPU time	7.54 seconds
Started	Feb 18 12:54:32 PM PST 24
Finished	Feb 18 12:54:43 PM PST 24
Peak memory	201956 kb
Host	smart-acaf969b-4e62-43c9-a3a6-05e47d3c0a60
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861 19589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3786119589
Directory	/workspace/18.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/18.usbdev_smoke.2626120941
Short name	T319
Test name
Test status
Simulation time	8369460142 ps
CPU time	7.31 seconds
Started	Feb 18 12:54:32 PM PST 24
Finished	Feb 18 12:54:44 PM PST 24
Peak memory	201948 kb
Host	smart-5e60f4f7-26b5-447b-9db3-e994d857aa07
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26261 20941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2626120941
Directory	/workspace/18.usbdev_smoke/latest

Test location	/workspace/coverage/default/19.in_trans.1233227314
Short name	T278
Test name
Test status
Simulation time	8456602280 ps
CPU time	9.44 seconds
Started	Feb 18 12:54:29 PM PST 24
Finished	Feb 18 12:54:44 PM PST 24
Peak memory	201820 kb
Host	smart-8d26bd38-0f7a-499f-991e-316cc70c6c54
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12332 27314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.in_trans.1233227314
Directory	/workspace/19.in_trans/latest

Test location	/workspace/coverage/default/19.setup_trans_ignored.461059824
Short name	T175
Test name
Test status
Simulation time	8357782226 ps
CPU time	8.95 seconds
Started	Feb 18 12:54:51 PM PST 24
Finished	Feb 18 12:55:10 PM PST 24
Peak memory	202016 kb
Host	smart-de06ff7c-f366-449d-ad0c-f1419e2adbba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46105 9824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.setup_trans_ignored.461059824
Directory	/workspace/19.setup_trans_ignored/latest

Test location	/workspace/coverage/default/19.usbdev_av_buffer.3568982037
Short name	T188
Test name
Test status
Simulation time	8377787259 ps
CPU time	7.64 seconds
Started	Feb 18 12:54:22 PM PST 24
Finished	Feb 18 12:54:36 PM PST 24
Peak memory	202012 kb
Host	smart-3d9056b5-d863-4614-bd77-dc6dca2829f7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35689 82037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3568982037
Directory	/workspace/19.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/19.usbdev_nak_trans.3248070126
Short name	T82
Test name
Test status
Simulation time	8418384801 ps
CPU time	7.35 seconds
Started	Feb 18 12:54:41 PM PST 24
Finished	Feb 18 12:54:52 PM PST 24
Peak memory	201940 kb
Host	smart-76c44449-0b50-4724-9427-388da7791e16
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32480 70126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3248070126
Directory	/workspace/19.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/19.usbdev_pkt_sent.2817342093
Short name	T6
Test name
Test status
Simulation time	8448803753 ps
CPU time	7.22 seconds
Started	Feb 18 12:54:29 PM PST 24
Finished	Feb 18 12:54:42 PM PST 24
Peak memory	201980 kb
Host	smart-d4dbf0b5-50b1-43a5-bb52-1a5d02deebc4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28173 42093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2817342093
Directory	/workspace/19.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/19.usbdev_smoke.4260952546
Short name	T328
Test name
Test status
Simulation time	8370347417 ps
CPU time	7.34 seconds
Started	Feb 18 12:54:19 PM PST 24
Finished	Feb 18 12:54:32 PM PST 24
Peak memory	202020 kb
Host	smart-897bc247-36ba-4771-ac13-5f9fd1ab15cc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42609 52546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4260952546
Directory	/workspace/19.usbdev_smoke/latest

Test location	/workspace/coverage/default/2.in_trans.1594993085
Short name	T61
Test name
Test status
Simulation time	8452404262 ps
CPU time	7.75 seconds
Started	Feb 18 12:54:08 PM PST 24
Finished	Feb 18 12:54:20 PM PST 24
Peak memory	202004 kb
Host	smart-7b104b06-7669-4c1f-a4c7-04da62515006
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15949 93085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.in_trans.1594993085
Directory	/workspace/2.in_trans/latest

Test location	/workspace/coverage/default/2.setup_trans_ignored.726986785
Short name	T224
Test name
Test status
Simulation time	8362548709 ps
CPU time	7.71 seconds
Started	Feb 18 12:53:48 PM PST 24
Finished	Feb 18 12:54:03 PM PST 24
Peak memory	202024 kb
Host	smart-d128697a-c050-40b8-9082-49b02a0c9a6e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72698 6785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.setup_trans_ignored.726986785
Directory	/workspace/2.setup_trans_ignored/latest

Test location	/workspace/coverage/default/2.usbdev_av_buffer.423785945
Short name	T238
Test name
Test status
Simulation time	8373089951 ps
CPU time	8.7 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:27 PM PST 24
Peak memory	201920 kb
Host	smart-ba656075-7421-469a-a9fe-8eed45526ffc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378 5945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.423785945
Directory	/workspace/2.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/2.usbdev_nak_trans.1343188446
Short name	T222
Test name
Test status
Simulation time	8391589517 ps
CPU time	7.97 seconds
Started	Feb 18 12:53:51 PM PST 24
Finished	Feb 18 12:54:05 PM PST 24
Peak memory	201972 kb
Host	smart-d8c98ab0-96c1-4f7f-880a-9422ad992fca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13431 88446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1343188446
Directory	/workspace/2.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/2.usbdev_pkt_sent.2662432315
Short name	T150
Test name
Test status
Simulation time	8452415871 ps
CPU time	7.37 seconds
Started	Feb 18 12:54:07 PM PST 24
Finished	Feb 18 12:54:18 PM PST 24
Peak memory	202012 kb
Host	smart-7fc4a5ca-ddea-4c1b-9031-c1977085fc12
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624 32315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2662432315
Directory	/workspace/2.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.2308910947
Short name	T42
Test name
Test status
Simulation time	177024390 ps
CPU time	1.07 seconds
Started	Feb 18 12:54:01 PM PST 24
Finished	Feb 18 12:54:09 PM PST 24
Peak memory	217972 kb
Host	smart-70f89151-1be3-41bb-83e9-f9e4a3f2268d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2308910947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2308910947
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/2.usbdev_smoke.1780429606
Short name	T208
Test name
Test status
Simulation time	8367681784 ps
CPU time	7.08 seconds
Started	Feb 18 12:53:51 PM PST 24
Finished	Feb 18 12:54:05 PM PST 24
Peak memory	201964 kb
Host	smart-2c9eadf5-effb-4e2a-878e-43488f2f4bf6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17804 29606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1780429606
Directory	/workspace/2.usbdev_smoke/latest

Test location	/workspace/coverage/default/20.in_trans.3174405254
Short name	T303
Test name
Test status
Simulation time	8406924274 ps
CPU time	7.4 seconds
Started	Feb 18 12:54:46 PM PST 24
Finished	Feb 18 12:54:56 PM PST 24
Peak memory	202008 kb
Host	smart-f6ada64a-9220-4d93-8369-f833e631d5b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31744 05254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.in_trans.3174405254
Directory	/workspace/20.in_trans/latest

Test location	/workspace/coverage/default/20.setup_trans_ignored.710808745
Short name	T241
Test name
Test status
Simulation time	8391776845 ps
CPU time	8.23 seconds
Started	Feb 18 12:54:40 PM PST 24
Finished	Feb 18 12:54:52 PM PST 24
Peak memory	202036 kb
Host	smart-8e46f0cc-3749-40ab-8f9f-45f4b7ab7185
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71080 8745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.setup_trans_ignored.710808745
Directory	/workspace/20.setup_trans_ignored/latest

Test location	/workspace/coverage/default/20.usbdev_av_buffer.2497662821
Short name	T34
Test name
Test status
Simulation time	8369607605 ps
CPU time	7.47 seconds
Started	Feb 18 12:54:42 PM PST 24
Finished	Feb 18 12:54:53 PM PST 24
Peak memory	202016 kb
Host	smart-74ba63e9-2642-4da2-88d4-7e281ee733e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976 62821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2497662821
Directory	/workspace/20.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/20.usbdev_nak_trans.1769964254
Short name	T12
Test name
Test status
Simulation time	8418142616 ps
CPU time	9.23 seconds
Started	Feb 18 12:54:38 PM PST 24
Finished	Feb 18 12:54:51 PM PST 24
Peak memory	202000 kb
Host	smart-7095df9a-d62b-4065-8c3b-2fd5e7f69c91
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17699 64254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1769964254
Directory	/workspace/20.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/20.usbdev_smoke.1173568957
Short name	T240
Test name
Test status
Simulation time	8368273148 ps
CPU time	7.1 seconds
Started	Feb 18 12:54:30 PM PST 24
Finished	Feb 18 12:54:42 PM PST 24
Peak memory	202020 kb
Host	smart-29f5813d-18fa-4cd6-8c4b-e690eb82d664
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11735 68957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1173568957
Directory	/workspace/20.usbdev_smoke/latest

Test location	/workspace/coverage/default/21.setup_trans_ignored.95314551
Short name	T329
Test name
Test status
Simulation time	8359225151 ps
CPU time	7.73 seconds
Started	Feb 18 12:54:24 PM PST 24
Finished	Feb 18 12:54:39 PM PST 24
Peak memory	202024 kb
Host	smart-6310cbae-56a6-4d54-8d2c-dab817c41ce5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95314 551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.setup_trans_ignored.95314551
Directory	/workspace/21.setup_trans_ignored/latest

Test location	/workspace/coverage/default/21.usbdev_av_buffer.1837133216
Short name	T32
Test name
Test status
Simulation time	8371287343 ps
CPU time	7.27 seconds
Started	Feb 18 12:54:37 PM PST 24
Finished	Feb 18 12:54:47 PM PST 24
Peak memory	202020 kb
Host	smart-0c7ad1c6-53b7-4349-b48d-2187942a7550
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18371 33216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1837133216
Directory	/workspace/21.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/21.usbdev_pkt_sent.3519744317
Short name	T21
Test name
Test status
Simulation time	8522476590 ps
CPU time	8.67 seconds
Started	Feb 18 12:54:46 PM PST 24
Finished	Feb 18 12:54:57 PM PST 24
Peak memory	202008 kb
Host	smart-fdec5883-c509-4245-84ab-24fd32ab8447
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35197 44317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3519744317
Directory	/workspace/21.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/21.usbdev_smoke.640171600
Short name	T176
Test name
Test status
Simulation time	8366439965 ps
CPU time	9.3 seconds
Started	Feb 18 12:54:27 PM PST 24
Finished	Feb 18 12:54:43 PM PST 24
Peak memory	202020 kb
Host	smart-18449889-5e1d-40ff-b97e-783e8d483f8b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64017 1600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.640171600
Directory	/workspace/21.usbdev_smoke/latest

Test location	/workspace/coverage/default/22.in_trans.3410900969
Short name	T183
Test name
Test status
Simulation time	8410747990 ps
CPU time	7.41 seconds
Started	Feb 18 12:54:34 PM PST 24
Finished	Feb 18 12:54:45 PM PST 24
Peak memory	202032 kb
Host	smart-4a38f90b-9f7a-4249-9501-8fcd87fffce4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34109 00969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.in_trans.3410900969
Directory	/workspace/22.in_trans/latest

Test location	/workspace/coverage/default/22.setup_trans_ignored.808574251
Short name	T325
Test name
Test status
Simulation time	8357712267 ps
CPU time	7.63 seconds
Started	Feb 18 12:54:32 PM PST 24
Finished	Feb 18 12:54:44 PM PST 24
Peak memory	202036 kb
Host	smart-81614ec9-130d-4b71-a54f-c4a5f214e2de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80857 4251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.setup_trans_ignored.808574251
Directory	/workspace/22.setup_trans_ignored/latest

Test location	/workspace/coverage/default/22.usbdev_av_buffer.2318360762
Short name	T182
Test name
Test status
Simulation time	8369713388 ps
CPU time	7.58 seconds
Started	Feb 18 12:54:34 PM PST 24
Finished	Feb 18 12:54:45 PM PST 24
Peak memory	202020 kb
Host	smart-3a88cb7a-df30-49d2-93d5-79969e41bd45
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23183 60762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2318360762
Directory	/workspace/22.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/22.usbdev_nak_trans.2147120492
Short name	T70
Test name
Test status
Simulation time	8430045664 ps
CPU time	7.39 seconds
Started	Feb 18 12:54:32 PM PST 24
Finished	Feb 18 12:54:44 PM PST 24
Peak memory	202024 kb
Host	smart-b798b94f-c8c0-4caa-8cab-5116308000c7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21471 20492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2147120492
Directory	/workspace/22.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/22.usbdev_pkt_sent.1068866507
Short name	T154
Test name
Test status
Simulation time	8387924632 ps
CPU time	7.78 seconds
Started	Feb 18 12:54:36 PM PST 24
Finished	Feb 18 12:54:47 PM PST 24
Peak memory	202028 kb
Host	smart-00bea97d-a42b-47cf-b324-2cdce409f648
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688 66507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1068866507
Directory	/workspace/22.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/22.usbdev_smoke.2785883552
Short name	T65
Test name
Test status
Simulation time	8368362767 ps
CPU time	7.45 seconds
Started	Feb 18 12:54:27 PM PST 24
Finished	Feb 18 12:54:41 PM PST 24
Peak memory	202020 kb
Host	smart-9a7e5702-b74b-4c21-aef2-3d5adadca83f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27858 83552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2785883552
Directory	/workspace/22.usbdev_smoke/latest

Test location	/workspace/coverage/default/23.in_trans.2138927300
Short name	T225
Test name
Test status
Simulation time	8429276820 ps
CPU time	7.25 seconds
Started	Feb 18 12:54:58 PM PST 24
Finished	Feb 18 12:55:15 PM PST 24
Peak memory	202020 kb
Host	smart-fa5fb20b-465c-4d86-9d82-ca409faddca5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21389 27300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.in_trans.2138927300
Directory	/workspace/23.in_trans/latest

Test location	/workspace/coverage/default/23.setup_trans_ignored.3502453672
Short name	T314
Test name
Test status
Simulation time	8360262676 ps
CPU time	8.11 seconds
Started	Feb 18 12:54:42 PM PST 24
Finished	Feb 18 12:54:54 PM PST 24
Peak memory	202036 kb
Host	smart-56c53a1f-bbb8-41f5-a0d6-59268ae9e832
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35024 53672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.setup_trans_ignored.3502453672
Directory	/workspace/23.setup_trans_ignored/latest

Test location	/workspace/coverage/default/23.usbdev_av_buffer.471189832
Short name	T254
Test name
Test status
Simulation time	8376803804 ps
CPU time	7.62 seconds
Started	Feb 18 12:54:49 PM PST 24
Finished	Feb 18 12:55:00 PM PST 24
Peak memory	202012 kb
Host	smart-7b828ec6-036b-4011-a2d0-3cfb27866751
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47118 9832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.471189832
Directory	/workspace/23.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/23.usbdev_nak_trans.1070192041
Short name	T84
Test name
Test status
Simulation time	8382892282 ps
CPU time	7.17 seconds
Started	Feb 18 12:54:38 PM PST 24
Finished	Feb 18 12:54:48 PM PST 24
Peak memory	202036 kb
Host	smart-fd0a55c9-5d5f-4b19-bb90-9c2ca6c20c0e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701 92041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1070192041
Directory	/workspace/23.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/23.usbdev_pkt_sent.3154528609
Short name	T111
Test name
Test status
Simulation time	8388327635 ps
CPU time	7.26 seconds
Started	Feb 18 12:54:53 PM PST 24
Finished	Feb 18 12:55:10 PM PST 24
Peak memory	202012 kb
Host	smart-107d4574-be7b-4e76-bb52-476c81618cd8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31545 28609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3154528609
Directory	/workspace/23.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/23.usbdev_smoke.3634293431
Short name	T180
Test name
Test status
Simulation time	8370589427 ps
CPU time	8.55 seconds
Started	Feb 18 12:54:39 PM PST 24
Finished	Feb 18 12:54:51 PM PST 24
Peak memory	201936 kb
Host	smart-9f990a99-2027-4829-8023-9ce3b080a90c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36342 93431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3634293431
Directory	/workspace/23.usbdev_smoke/latest

Test location	/workspace/coverage/default/24.in_trans.1370291548
Short name	T110
Test name
Test status
Simulation time	8474037738 ps
CPU time	7.82 seconds
Started	Feb 18 12:54:40 PM PST 24
Finished	Feb 18 12:54:51 PM PST 24
Peak memory	202020 kb
Host	smart-780b561d-47d2-4297-8920-6afd8b24561f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13702 91548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.in_trans.1370291548
Directory	/workspace/24.in_trans/latest

Test location	/workspace/coverage/default/24.setup_trans_ignored.3259639687
Short name	T336
Test name
Test status
Simulation time	8361531660 ps
CPU time	7.24 seconds
Started	Feb 18 12:54:48 PM PST 24
Finished	Feb 18 12:54:57 PM PST 24
Peak memory	202016 kb
Host	smart-886da677-88b5-43e4-8522-1af91cc6a0c5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32596 39687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.setup_trans_ignored.3259639687
Directory	/workspace/24.setup_trans_ignored/latest

Test location	/workspace/coverage/default/24.usbdev_av_buffer.437711317
Short name	T152
Test name
Test status
Simulation time	8368004602 ps
CPU time	9.07 seconds
Started	Feb 18 12:54:50 PM PST 24
Finished	Feb 18 12:55:09 PM PST 24
Peak memory	202004 kb
Host	smart-e3f6b96f-9d80-4828-ab90-9d9421cc83a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43771 1317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.437711317
Directory	/workspace/24.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/24.usbdev_nak_trans.1757840581
Short name	T89
Test name
Test status
Simulation time	8425078823 ps
CPU time	7.72 seconds
Started	Feb 18 12:54:38 PM PST 24
Finished	Feb 18 12:54:48 PM PST 24
Peak memory	201992 kb
Host	smart-1803974f-680b-4957-8cb2-71eb8d9f854d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17578 40581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1757840581
Directory	/workspace/24.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/24.usbdev_pkt_sent.2419276562
Short name	T92
Test name
Test status
Simulation time	8442522960 ps
CPU time	7.62 seconds
Started	Feb 18 12:54:54 PM PST 24
Finished	Feb 18 12:55:12 PM PST 24
Peak memory	202012 kb
Host	smart-c1a50221-53be-40ae-b5e0-1b8130fc7380
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24192 76562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2419276562
Directory	/workspace/24.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/24.usbdev_smoke.2305052678
Short name	T144
Test name
Test status
Simulation time	8372986181 ps
CPU time	9.27 seconds
Started	Feb 18 12:54:57 PM PST 24
Finished	Feb 18 12:55:17 PM PST 24
Peak memory	202020 kb
Host	smart-94aac364-6248-467d-8cec-a9f6dd7b0ca9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23050 52678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2305052678
Directory	/workspace/24.usbdev_smoke/latest

Test location	/workspace/coverage/default/25.in_trans.938515831
Short name	T256
Test name
Test status
Simulation time	8436085523 ps
CPU time	8.3 seconds
Started	Feb 18 12:54:47 PM PST 24
Finished	Feb 18 12:54:58 PM PST 24
Peak memory	202020 kb
Host	smart-0198d800-ba57-4b5d-bb8b-ea208067a861
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93851 5831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.in_trans.938515831
Directory	/workspace/25.in_trans/latest

Test location	/workspace/coverage/default/25.setup_trans_ignored.3336719119
Short name	T177
Test name
Test status
Simulation time	8358748144 ps
CPU time	7.17 seconds
Started	Feb 18 12:54:46 PM PST 24
Finished	Feb 18 12:54:56 PM PST 24
Peak memory	202028 kb
Host	smart-9e6f6ed8-018d-4a85-80c5-2c09278c2c48
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33367 19119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.setup_trans_ignored.3336719119
Directory	/workspace/25.setup_trans_ignored/latest

Test location	/workspace/coverage/default/25.usbdev_av_buffer.4112902184
Short name	T324
Test name
Test status
Simulation time	8380730756 ps
CPU time	8.2 seconds
Started	Feb 18 12:54:41 PM PST 24
Finished	Feb 18 12:54:53 PM PST 24
Peak memory	202028 kb
Host	smart-2008768a-08cb-41ed-9038-6c3140a8bfd2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41129 02184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.4112902184
Directory	/workspace/25.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/25.usbdev_smoke.881430666
Short name	T204
Test name
Test status
Simulation time	8387864431 ps
CPU time	7.21 seconds
Started	Feb 18 12:54:45 PM PST 24
Finished	Feb 18 12:54:54 PM PST 24
Peak memory	202020 kb
Host	smart-a7995cca-73d8-452c-95e6-f3a1b2456c28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88143 0666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.881430666
Directory	/workspace/25.usbdev_smoke/latest

Test location	/workspace/coverage/default/26.in_trans.3444933322
Short name	T201
Test name
Test status
Simulation time	8481066786 ps
CPU time	7.34 seconds
Started	Feb 18 12:54:48 PM PST 24
Finished	Feb 18 12:54:57 PM PST 24
Peak memory	202024 kb
Host	smart-92564d4c-dc9c-4c10-b402-9f4851536035
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34449 33322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.in_trans.3444933322
Directory	/workspace/26.in_trans/latest

Test location	/workspace/coverage/default/26.setup_trans_ignored.1051522483
Short name	T158
Test name
Test status
Simulation time	8363676743 ps
CPU time	7.88 seconds
Started	Feb 18 12:54:46 PM PST 24
Finished	Feb 18 12:54:56 PM PST 24
Peak memory	202028 kb
Host	smart-8dfe3faf-cb55-403c-9226-33ab348bc7ed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10515 22483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.setup_trans_ignored.1051522483
Directory	/workspace/26.setup_trans_ignored/latest

Test location	/workspace/coverage/default/26.usbdev_av_buffer.3115059604
Short name	T194
Test name
Test status
Simulation time	8370161302 ps
CPU time	8.27 seconds
Started	Feb 18 12:54:48 PM PST 24
Finished	Feb 18 12:54:58 PM PST 24
Peak memory	202020 kb
Host	smart-c0dc1833-420f-4002-be11-695661b5ae94
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31150 59604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3115059604
Directory	/workspace/26.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/26.usbdev_nak_trans.3793250852
Short name	T81
Test name
Test status
Simulation time	8422565465 ps
CPU time	7.22 seconds
Started	Feb 18 12:54:43 PM PST 24
Finished	Feb 18 12:54:54 PM PST 24
Peak memory	202036 kb
Host	smart-537945c2-eb4c-45e4-a9b9-131aa6aede73
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932 50852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3793250852
Directory	/workspace/26.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/26.usbdev_pkt_sent.1071520467
Short name	T112
Test name
Test status
Simulation time	8456351147 ps
CPU time	7.6 seconds
Started	Feb 18 12:54:38 PM PST 24
Finished	Feb 18 12:54:48 PM PST 24
Peak memory	202032 kb
Host	smart-18628ddd-5806-4ef7-871c-34fa9e40474a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10715 20467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1071520467
Directory	/workspace/26.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/26.usbdev_smoke.4293887088
Short name	T312
Test name
Test status
Simulation time	8403441371 ps
CPU time	7.58 seconds
Started	Feb 18 12:54:52 PM PST 24
Finished	Feb 18 12:55:09 PM PST 24
Peak memory	201948 kb
Host	smart-228d6025-38ae-450a-a980-0370472802cc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938 87088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4293887088
Directory	/workspace/26.usbdev_smoke/latest

Test location	/workspace/coverage/default/27.in_trans.1935459940
Short name	T262
Test name
Test status
Simulation time	8394128180 ps
CPU time	9.12 seconds
Started	Feb 18 12:55:04 PM PST 24
Finished	Feb 18 12:55:23 PM PST 24
Peak memory	202004 kb
Host	smart-7290d93d-4d74-4b77-9fcc-16a41f683103
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19354 59940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.in_trans.1935459940
Directory	/workspace/27.in_trans/latest

Test location	/workspace/coverage/default/27.setup_trans_ignored.3423254251
Short name	T235
Test name
Test status
Simulation time	8365480690 ps
CPU time	7.31 seconds
Started	Feb 18 12:55:04 PM PST 24
Finished	Feb 18 12:55:21 PM PST 24
Peak memory	202040 kb
Host	smart-54631cce-6f13-439c-b636-d9c7e75ee6d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34232 54251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.setup_trans_ignored.3423254251
Directory	/workspace/27.setup_trans_ignored/latest

Test location	/workspace/coverage/default/27.usbdev_av_buffer.965792888
Short name	T268
Test name
Test status
Simulation time	8376820507 ps
CPU time	7.43 seconds
Started	Feb 18 12:54:56 PM PST 24
Finished	Feb 18 12:55:13 PM PST 24
Peak memory	202012 kb
Host	smart-b5f94e4f-bfe7-4e8f-8505-df236365e77e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96579 2888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.965792888
Directory	/workspace/27.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/27.usbdev_pkt_sent.1456123629
Short name	T199
Test name
Test status
Simulation time	8442997568 ps
CPU time	9.46 seconds
Started	Feb 18 12:55:05 PM PST 24
Finished	Feb 18 12:55:24 PM PST 24
Peak memory	202012 kb
Host	smart-f6a85c47-2e99-4a49-87c2-e77e50381326
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14561 23629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1456123629
Directory	/workspace/27.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/27.usbdev_smoke.1192431553
Short name	T327
Test name
Test status
Simulation time	8368027347 ps
CPU time	7.8 seconds
Started	Feb 18 12:55:00 PM PST 24
Finished	Feb 18 12:55:18 PM PST 24
Peak memory	202004 kb
Host	smart-6608d2e7-e35b-430a-ad52-5129926d8c28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924 31553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1192431553
Directory	/workspace/27.usbdev_smoke/latest

Test location	/workspace/coverage/default/28.in_trans.1674815096
Short name	T293
Test name
Test status
Simulation time	8428767922 ps
CPU time	7.54 seconds
Started	Feb 18 12:55:01 PM PST 24
Finished	Feb 18 12:55:19 PM PST 24
Peak memory	202020 kb
Host	smart-96d90d56-4536-46c4-9fbc-b91733b5f0dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16748 15096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.in_trans.1674815096
Directory	/workspace/28.in_trans/latest

Test location	/workspace/coverage/default/28.setup_trans_ignored.3939213309
Short name	T246
Test name
Test status
Simulation time	8392676522 ps
CPU time	7.33 seconds
Started	Feb 18 12:55:01 PM PST 24
Finished	Feb 18 12:55:19 PM PST 24
Peak memory	202016 kb
Host	smart-046f3477-ddce-47a5-8c37-7ff84837e88a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39392 13309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.setup_trans_ignored.3939213309
Directory	/workspace/28.setup_trans_ignored/latest

Test location	/workspace/coverage/default/28.usbdev_nak_trans.3332898442
Short name	T19
Test name
Test status
Simulation time	8421090238 ps
CPU time	7.86 seconds
Started	Feb 18 12:54:57 PM PST 24
Finished	Feb 18 12:55:15 PM PST 24
Peak memory	202024 kb
Host	smart-ff47c544-cd3f-46df-af64-a720309264e1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33328 98442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3332898442
Directory	/workspace/28.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/28.usbdev_pkt_sent.482548003
Short name	T285
Test name
Test status
Simulation time	8418359398 ps
CPU time	6.91 seconds
Started	Feb 18 12:54:53 PM PST 24
Finished	Feb 18 12:55:10 PM PST 24
Peak memory	202008 kb
Host	smart-9b16942d-b216-4037-81de-91ab51f940b3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48254 8003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.482548003
Directory	/workspace/28.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/28.usbdev_smoke.1315431757
Short name	T157
Test name
Test status
Simulation time	8372550155 ps
CPU time	8.92 seconds
Started	Feb 18 12:54:58 PM PST 24
Finished	Feb 18 12:55:17 PM PST 24
Peak memory	202004 kb
Host	smart-4a85c4d7-15a1-4a5d-874b-d498a58dd2b5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13154 31757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1315431757
Directory	/workspace/28.usbdev_smoke/latest

Test location	/workspace/coverage/default/29.in_trans.2133160462
Short name	T57
Test name
Test status
Simulation time	8438456237 ps
CPU time	8.39 seconds
Started	Feb 18 12:54:57 PM PST 24
Finished	Feb 18 12:55:15 PM PST 24
Peak memory	201992 kb
Host	smart-bd42230a-eb20-4ca3-8267-6a4c8cbe2eb1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21331 60462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.in_trans.2133160462
Directory	/workspace/29.in_trans/latest

Test location	/workspace/coverage/default/29.setup_trans_ignored.2804583444
Short name	T217
Test name
Test status
Simulation time	8362422912 ps
CPU time	7 seconds
Started	Feb 18 12:55:02 PM PST 24
Finished	Feb 18 12:55:19 PM PST 24
Peak memory	202012 kb
Host	smart-e744ca3d-9de9-42a3-9153-07c5f9e984b3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28045 83444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.setup_trans_ignored.2804583444
Directory	/workspace/29.setup_trans_ignored/latest

Test location	/workspace/coverage/default/29.usbdev_av_buffer.2844256101
Short name	T322
Test name
Test status
Simulation time	8372074223 ps
CPU time	7.3 seconds
Started	Feb 18 12:54:58 PM PST 24
Finished	Feb 18 12:55:15 PM PST 24
Peak memory	202020 kb
Host	smart-8859a63e-2bfc-48ce-a2e1-74d8a6b4f514
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28442 56101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2844256101
Directory	/workspace/29.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/29.usbdev_pkt_sent.410724512
Short name	T292
Test name
Test status
Simulation time	8392276350 ps
CPU time	7.09 seconds
Started	Feb 18 12:55:08 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	202008 kb
Host	smart-4eee72ec-d0c8-4c86-9587-71964f4417da
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41072 4512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.410724512
Directory	/workspace/29.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/29.usbdev_smoke.254549244
Short name	T270
Test name
Test status
Simulation time	8367431102 ps
CPU time	8.28 seconds
Started	Feb 18 12:55:11 PM PST 24
Finished	Feb 18 12:55:28 PM PST 24
Peak memory	202008 kb
Host	smart-778e4d7d-6548-472d-9725-e34e4b627086
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454 9244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.254549244
Directory	/workspace/29.usbdev_smoke/latest

Test location	/workspace/coverage/default/3.in_trans.3114397949
Short name	T99
Test name
Test status
Simulation time	8414999792 ps
CPU time	8.33 seconds
Started	Feb 18 12:53:52 PM PST 24
Finished	Feb 18 12:54:07 PM PST 24
Peak memory	202016 kb
Host	smart-8c519237-a98f-48eb-b4f3-1e0553ae9a40
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31143 97949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.in_trans.3114397949
Directory	/workspace/3.in_trans/latest

Test location	/workspace/coverage/default/3.setup_trans_ignored.3894424763
Short name	T213
Test name
Test status
Simulation time	8362407443 ps
CPU time	7.44 seconds
Started	Feb 18 12:54:09 PM PST 24
Finished	Feb 18 12:54:21 PM PST 24
Peak memory	202008 kb
Host	smart-3bf833f6-48f7-4088-b34f-2871e95f61bd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38944 24763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.setup_trans_ignored.3894424763
Directory	/workspace/3.setup_trans_ignored/latest

Test location	/workspace/coverage/default/3.usbdev_av_buffer.1554853557
Short name	T290
Test name
Test status
Simulation time	8369115940 ps
CPU time	7.46 seconds
Started	Feb 18 12:54:03 PM PST 24
Finished	Feb 18 12:54:16 PM PST 24
Peak memory	202016 kb
Host	smart-bdd9b8b7-afff-4645-a991-72e5c97e85d6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15548 53557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1554853557
Directory	/workspace/3.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/3.usbdev_pkt_sent.3833231155
Short name	T26
Test name
Test status
Simulation time	8430438890 ps
CPU time	7.32 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:25 PM PST 24
Peak memory	201912 kb
Host	smart-2c02d32f-0157-4634-a71f-f8541446a712
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38332 31155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3833231155
Directory	/workspace/3.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.2364049718
Short name	T54
Test name
Test status
Simulation time	95956793 ps
CPU time	0.92 seconds
Started	Feb 18 12:53:52 PM PST 24
Finished	Feb 18 12:54:00 PM PST 24
Peak memory	216912 kb
Host	smart-119e07a8-9cc2-4eba-9fb4-6b9463b7e559
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2364049718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2364049718
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/3.usbdev_smoke.1661725253
Short name	T298
Test name
Test status
Simulation time	8390369593 ps
CPU time	9.62 seconds
Started	Feb 18 12:54:05 PM PST 24
Finished	Feb 18 12:54:19 PM PST 24
Peak memory	202004 kb
Host	smart-664c4ede-3e11-443b-991c-6774fcda2a25
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16617 25253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1661725253
Directory	/workspace/3.usbdev_smoke/latest

Test location	/workspace/coverage/default/30.in_trans.3201692047
Short name	T101
Test name
Test status
Simulation time	8448911272 ps
CPU time	7.97 seconds
Started	Feb 18 12:55:06 PM PST 24
Finished	Feb 18 12:55:23 PM PST 24
Peak memory	202012 kb
Host	smart-a3d97501-9238-499f-a312-9e4ced264513
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32016 92047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.in_trans.3201692047
Directory	/workspace/30.in_trans/latest

Test location	/workspace/coverage/default/30.setup_trans_ignored.964835882
Short name	T160
Test name
Test status
Simulation time	8368196065 ps
CPU time	7.68 seconds
Started	Feb 18 12:55:06 PM PST 24
Finished	Feb 18 12:55:23 PM PST 24
Peak memory	201960 kb
Host	smart-a2a5f779-e2bd-49a4-bf10-9fa128b82137
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96483 5882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.setup_trans_ignored.964835882
Directory	/workspace/30.setup_trans_ignored/latest

Test location	/workspace/coverage/default/30.usbdev_av_buffer.3074119172
Short name	T35
Test name
Test status
Simulation time	8368860584 ps
CPU time	8.44 seconds
Started	Feb 18 12:55:04 PM PST 24
Finished	Feb 18 12:55:23 PM PST 24
Peak memory	202020 kb
Host	smart-75b6b577-42db-4abf-8caa-5b7624a8a8e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30741 19172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3074119172
Directory	/workspace/30.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/30.usbdev_pkt_sent.2813193518
Short name	T306
Test name
Test status
Simulation time	8391741577 ps
CPU time	8.14 seconds
Started	Feb 18 12:54:57 PM PST 24
Finished	Feb 18 12:55:16 PM PST 24
Peak memory	202016 kb
Host	smart-8ad33981-df33-42fc-a2c2-52a6fe42396f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28131 93518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2813193518
Directory	/workspace/30.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/30.usbdev_smoke.3884215326
Short name	T151
Test name
Test status
Simulation time	8370161035 ps
CPU time	7.87 seconds
Started	Feb 18 12:55:06 PM PST 24
Finished	Feb 18 12:55:23 PM PST 24
Peak memory	202016 kb
Host	smart-51d2b2b3-107c-495a-80da-aad9d6d5d7d3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842 15326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3884215326
Directory	/workspace/30.usbdev_smoke/latest

Test location	/workspace/coverage/default/31.in_trans.4251938345
Short name	T105
Test name
Test status
Simulation time	8455664964 ps
CPU time	7.45 seconds
Started	Feb 18 12:55:06 PM PST 24
Finished	Feb 18 12:55:23 PM PST 24
Peak memory	202012 kb
Host	smart-001d58cf-9960-42cd-bc81-10b397b16be0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42519 38345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.in_trans.4251938345
Directory	/workspace/31.in_trans/latest

Test location	/workspace/coverage/default/31.setup_trans_ignored.2203714880
Short name	T142
Test name
Test status
Simulation time	8362859962 ps
CPU time	9.74 seconds
Started	Feb 18 12:54:58 PM PST 24
Finished	Feb 18 12:55:19 PM PST 24
Peak memory	202028 kb
Host	smart-efedafe6-40d4-41d7-a3e7-a58c524b0b6e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22037 14880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.setup_trans_ignored.2203714880
Directory	/workspace/31.setup_trans_ignored/latest

Test location	/workspace/coverage/default/31.usbdev_av_buffer.2529855327
Short name	T230
Test name
Test status
Simulation time	8376382393 ps
CPU time	7.68 seconds
Started	Feb 18 12:55:07 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	201376 kb
Host	smart-3edd3aaa-cd25-4a44-8e66-ee925641110a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25298 55327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2529855327
Directory	/workspace/31.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/31.usbdev_nak_trans.1474960060
Short name	T13
Test name
Test status
Simulation time	8405771897 ps
CPU time	7.28 seconds
Started	Feb 18 12:55:02 PM PST 24
Finished	Feb 18 12:55:19 PM PST 24
Peak memory	202012 kb
Host	smart-5e018181-f524-4cb6-b3e9-62d50ff3d77a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14749 60060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1474960060
Directory	/workspace/31.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/31.usbdev_pkt_sent.1278381143
Short name	T181
Test name
Test status
Simulation time	8404281798 ps
CPU time	7.3 seconds
Started	Feb 18 12:55:09 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	202008 kb
Host	smart-193b0dd3-e075-43e3-9b20-0c01516718bc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12783 81143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1278381143
Directory	/workspace/31.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/31.usbdev_smoke.2007184261
Short name	T320
Test name
Test status
Simulation time	8374854448 ps
CPU time	7.34 seconds
Started	Feb 18 12:54:57 PM PST 24
Finished	Feb 18 12:55:14 PM PST 24
Peak memory	201992 kb
Host	smart-c9b8c949-4044-4a66-8788-7c4edea28b93
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20071 84261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2007184261
Directory	/workspace/31.usbdev_smoke/latest

Test location	/workspace/coverage/default/32.in_trans.1012249216
Short name	T159
Test name
Test status
Simulation time	8404947839 ps
CPU time	6.98 seconds
Started	Feb 18 12:55:13 PM PST 24
Finished	Feb 18 12:55:29 PM PST 24
Peak memory	202028 kb
Host	smart-6aea992d-6c47-4ef6-8e8d-67638a11a8ab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10122 49216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.in_trans.1012249216
Directory	/workspace/32.in_trans/latest

Test location	/workspace/coverage/default/32.setup_trans_ignored.3076042499
Short name	T234
Test name
Test status
Simulation time	8357241611 ps
CPU time	6.79 seconds
Started	Feb 18 12:55:15 PM PST 24
Finished	Feb 18 12:55:31 PM PST 24
Peak memory	202012 kb
Host	smart-e9065023-5c04-415b-8281-8417e3892939
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760 42499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.setup_trans_ignored.3076042499
Directory	/workspace/32.setup_trans_ignored/latest

Test location	/workspace/coverage/default/32.usbdev_av_buffer.3511435204
Short name	T308
Test name
Test status
Simulation time	8367328855 ps
CPU time	7.13 seconds
Started	Feb 18 12:55:06 PM PST 24
Finished	Feb 18 12:55:22 PM PST 24
Peak memory	202024 kb
Host	smart-780912b5-154b-44b5-aa35-37c336a330b0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35114 35204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3511435204
Directory	/workspace/32.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/32.usbdev_nak_trans.3703928026
Short name	T77
Test name
Test status
Simulation time	8446937974 ps
CPU time	7.5 seconds
Started	Feb 18 12:55:07 PM PST 24
Finished	Feb 18 12:55:24 PM PST 24
Peak memory	201832 kb
Host	smart-e5f88914-df0e-4a64-9f3d-f9e3c8ad8c08
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37039 28026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3703928026
Directory	/workspace/32.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/32.usbdev_pkt_sent.3304039547
Short name	T244
Test name
Test status
Simulation time	8415147689 ps
CPU time	7.09 seconds
Started	Feb 18 12:55:15 PM PST 24
Finished	Feb 18 12:55:31 PM PST 24
Peak memory	202000 kb
Host	smart-d86e0182-5126-4597-81e1-b7f24b4c6b00
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040 39547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3304039547
Directory	/workspace/32.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/32.usbdev_smoke.3795601959
Short name	T315
Test name
Test status
Simulation time	8369001555 ps
CPU time	9.32 seconds
Started	Feb 18 12:55:10 PM PST 24
Finished	Feb 18 12:55:28 PM PST 24
Peak memory	201920 kb
Host	smart-f01828be-40cd-4987-b8c2-e146724111ca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37956 01959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3795601959
Directory	/workspace/32.usbdev_smoke/latest

Test location	/workspace/coverage/default/33.in_trans.2139494663
Short name	T93
Test name
Test status
Simulation time	8388316247 ps
CPU time	8.39 seconds
Started	Feb 18 12:55:09 PM PST 24
Finished	Feb 18 12:55:27 PM PST 24
Peak memory	201988 kb
Host	smart-f83088c3-743f-4b98-b902-ffe94d4f5fe1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21394 94663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.in_trans.2139494663
Directory	/workspace/33.in_trans/latest

Test location	/workspace/coverage/default/33.usbdev_av_buffer.2670512807
Short name	T313
Test name
Test status
Simulation time	8372705044 ps
CPU time	9.55 seconds
Started	Feb 18 12:55:09 PM PST 24
Finished	Feb 18 12:55:28 PM PST 24
Peak memory	202008 kb
Host	smart-2553d8fd-51e7-48eb-b395-c51667231279
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26705 12807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2670512807
Directory	/workspace/33.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/33.usbdev_nak_trans.2846849526
Short name	T339
Test name
Test status
Simulation time	8421888866 ps
CPU time	7.16 seconds
Started	Feb 18 12:55:13 PM PST 24
Finished	Feb 18 12:55:29 PM PST 24
Peak memory	202024 kb
Host	smart-2b15df8e-63fd-4c18-a1ea-1557387b71f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28468 49526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2846849526
Directory	/workspace/33.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/33.usbdev_smoke.3856517703
Short name	T271
Test name
Test status
Simulation time	8375684394 ps
CPU time	7.76 seconds
Started	Feb 18 12:55:08 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	202008 kb
Host	smart-0836116b-4b7c-4b59-9095-43356b69980c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38565 17703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3856517703
Directory	/workspace/33.usbdev_smoke/latest

Test location	/workspace/coverage/default/34.in_trans.1008711982
Short name	T228
Test name
Test status
Simulation time	8388668155 ps
CPU time	9.91 seconds
Started	Feb 18 12:55:10 PM PST 24
Finished	Feb 18 12:55:29 PM PST 24
Peak memory	201948 kb
Host	smart-b5a9552d-9ef8-49f4-b18c-94fab5f33de2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087 11982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.in_trans.1008711982
Directory	/workspace/34.in_trans/latest

Test location	/workspace/coverage/default/34.setup_trans_ignored.111306844
Short name	T237
Test name
Test status
Simulation time	8360771179 ps
CPU time	8.18 seconds
Started	Feb 18 12:55:19 PM PST 24
Finished	Feb 18 12:55:36 PM PST 24
Peak memory	202008 kb
Host	smart-b3a3ae7a-ecbe-4fa2-af87-6118c7ddb5f7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11130 6844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.setup_trans_ignored.111306844
Directory	/workspace/34.setup_trans_ignored/latest

Test location	/workspace/coverage/default/34.usbdev_av_buffer.390317607
Short name	T338
Test name
Test status
Simulation time	8369049024 ps
CPU time	7.28 seconds
Started	Feb 18 12:55:19 PM PST 24
Finished	Feb 18 12:55:35 PM PST 24
Peak memory	202012 kb
Host	smart-fd5a62b2-ac6f-4de5-af5b-90e1a60f2906
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39031 7607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.390317607
Directory	/workspace/34.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/34.usbdev_nak_trans.3811302048
Short name	T86
Test name
Test status
Simulation time	8400921230 ps
CPU time	8.65 seconds
Started	Feb 18 12:55:16 PM PST 24
Finished	Feb 18 12:55:34 PM PST 24
Peak memory	202012 kb
Host	smart-875d944f-81ab-43d1-b3cb-98b240022382
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38113 02048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3811302048
Directory	/workspace/34.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/34.usbdev_pkt_sent.3712444025
Short name	T301
Test name
Test status
Simulation time	8449123835 ps
CPU time	7.45 seconds
Started	Feb 18 12:55:10 PM PST 24
Finished	Feb 18 12:55:26 PM PST 24
Peak memory	201940 kb
Host	smart-79af95f4-c473-4f21-a120-af89b11588bb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37124 44025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3712444025
Directory	/workspace/34.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/34.usbdev_smoke.3158230087
Short name	T309
Test name
Test status
Simulation time	8371875887 ps
CPU time	9.7 seconds
Started	Feb 18 12:55:15 PM PST 24
Finished	Feb 18 12:55:33 PM PST 24
Peak memory	201948 kb
Host	smart-05f6b3bf-61ca-42d9-b2e4-30f1733cfd5f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31582 30087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3158230087
Directory	/workspace/34.usbdev_smoke/latest

Test location	/workspace/coverage/default/35.setup_trans_ignored.435292795
Short name	T161
Test name
Test status
Simulation time	8363562240 ps
CPU time	7.38 seconds
Started	Feb 18 12:55:19 PM PST 24
Finished	Feb 18 12:55:35 PM PST 24
Peak memory	202008 kb
Host	smart-2f024690-6f3f-43ea-a1a4-35056c1050bd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43529 2795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.setup_trans_ignored.435292795
Directory	/workspace/35.setup_trans_ignored/latest

Test location	/workspace/coverage/default/35.usbdev_av_buffer.2349913038
Short name	T29
Test name
Test status
Simulation time	8370459815 ps
CPU time	8.03 seconds
Started	Feb 18 12:55:09 PM PST 24
Finished	Feb 18 12:55:26 PM PST 24
Peak memory	202028 kb
Host	smart-f621d493-2263-487f-922a-479b364a97e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23499 13038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2349913038
Directory	/workspace/35.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/35.usbdev_nak_trans.1408303153
Short name	T91
Test name
Test status
Simulation time	8439693071 ps
CPU time	7.39 seconds
Started	Feb 18 12:55:16 PM PST 24
Finished	Feb 18 12:55:32 PM PST 24
Peak memory	201888 kb
Host	smart-95811140-9e76-4a59-82c5-50c8a9f2c40e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14083 03153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1408303153
Directory	/workspace/35.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/35.usbdev_pkt_sent.3376531884
Short name	T148
Test name
Test status
Simulation time	8423486936 ps
CPU time	7.67 seconds
Started	Feb 18 12:55:10 PM PST 24
Finished	Feb 18 12:55:27 PM PST 24
Peak memory	201944 kb
Host	smart-d8b9cd3d-2893-452b-9ead-7ff512e24983
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33765 31884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3376531884
Directory	/workspace/35.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/35.usbdev_smoke.3068835354
Short name	T236
Test name
Test status
Simulation time	8367398793 ps
CPU time	7.16 seconds
Started	Feb 18 12:55:10 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	202012 kb
Host	smart-fbbb40c0-a5f6-4967-be8f-9bed7c532a04
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688 35354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3068835354
Directory	/workspace/35.usbdev_smoke/latest

Test location	/workspace/coverage/default/36.in_trans.3459478564
Short name	T25
Test name
Test status
Simulation time	8447149094 ps
CPU time	7.62 seconds
Started	Feb 18 12:55:14 PM PST 24
Finished	Feb 18 12:55:30 PM PST 24
Peak memory	202020 kb
Host	smart-16122aa3-f8fc-4be2-8456-2f4ce7ec8860
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34594 78564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.in_trans.3459478564
Directory	/workspace/36.in_trans/latest

Test location	/workspace/coverage/default/36.setup_trans_ignored.127739253
Short name	T193
Test name
Test status
Simulation time	8360892089 ps
CPU time	7.44 seconds
Started	Feb 18 12:55:19 PM PST 24
Finished	Feb 18 12:55:34 PM PST 24
Peak memory	201944 kb
Host	smart-bf430125-eb70-41f9-b321-b3d6c4b991fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12773 9253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.setup_trans_ignored.127739253
Directory	/workspace/36.setup_trans_ignored/latest

Test location	/workspace/coverage/default/36.usbdev_av_buffer.1803355527
Short name	T220
Test name
Test status
Simulation time	8422277285 ps
CPU time	7.4 seconds
Started	Feb 18 12:55:19 PM PST 24
Finished	Feb 18 12:55:35 PM PST 24
Peak memory	201928 kb
Host	smart-ba03d24c-de10-4e3a-82f9-0bd62c570eab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18033 55527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1803355527
Directory	/workspace/36.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/36.usbdev_nak_trans.4108817054
Short name	T1
Test name
Test status
Simulation time	8389617230 ps
CPU time	9.41 seconds
Started	Feb 18 12:55:12 PM PST 24
Finished	Feb 18 12:55:30 PM PST 24
Peak memory	201492 kb
Host	smart-ab86571b-932b-4b83-a735-8e33bc293737
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41088 17054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.4108817054
Directory	/workspace/36.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/36.usbdev_pkt_sent.2461815927
Short name	T156
Test name
Test status
Simulation time	8405940185 ps
CPU time	8.03 seconds
Started	Feb 18 12:55:07 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	202012 kb
Host	smart-c7b71b94-37bd-4eaa-b69e-8fc8d8bc8ef1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24618 15927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2461815927
Directory	/workspace/36.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/36.usbdev_smoke.15621846
Short name	T280
Test name
Test status
Simulation time	8470474383 ps
CPU time	7.72 seconds
Started	Feb 18 12:55:19 PM PST 24
Finished	Feb 18 12:55:35 PM PST 24
Peak memory	201892 kb
Host	smart-d36ef6ba-b12d-47fb-8b95-b192bf174842
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15621 846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.15621846
Directory	/workspace/36.usbdev_smoke/latest

Test location	/workspace/coverage/default/37.in_trans.637893334
Short name	T219
Test name
Test status
Simulation time	8396051946 ps
CPU time	8.98 seconds
Started	Feb 18 12:55:19 PM PST 24
Finished	Feb 18 12:55:37 PM PST 24
Peak memory	201916 kb
Host	smart-f736ed0e-5da0-4390-baa3-ce867dd39fc7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63789 3334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.in_trans.637893334
Directory	/workspace/37.in_trans/latest

Test location	/workspace/coverage/default/37.setup_trans_ignored.1762240400
Short name	T288
Test name
Test status
Simulation time	8360640416 ps
CPU time	8.23 seconds
Started	Feb 18 12:55:12 PM PST 24
Finished	Feb 18 12:55:29 PM PST 24
Peak memory	201644 kb
Host	smart-1e96136d-4b09-42bf-a4e7-9eb2245b47b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17622 40400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.setup_trans_ignored.1762240400
Directory	/workspace/37.setup_trans_ignored/latest

Test location	/workspace/coverage/default/37.usbdev_av_buffer.3300460127
Short name	T33
Test name
Test status
Simulation time	8371421842 ps
CPU time	7.21 seconds
Started	Feb 18 12:55:17 PM PST 24
Finished	Feb 18 12:55:33 PM PST 24
Peak memory	202064 kb
Host	smart-7248d722-7d7c-4c8c-a42a-bb326a613a68
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33004 60127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3300460127
Directory	/workspace/37.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/37.usbdev_pkt_sent.1503970878
Short name	T249
Test name
Test status
Simulation time	8408395952 ps
CPU time	7.06 seconds
Started	Feb 18 12:55:09 PM PST 24
Finished	Feb 18 12:55:25 PM PST 24
Peak memory	202032 kb
Host	smart-98cc0657-97d0-4687-a160-a661b2d8c189
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15039 70878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1503970878
Directory	/workspace/37.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/37.usbdev_smoke.3214912704
Short name	T248
Test name
Test status
Simulation time	8366864262 ps
CPU time	7.13 seconds
Started	Feb 18 12:55:17 PM PST 24
Finished	Feb 18 12:55:32 PM PST 24
Peak memory	201872 kb
Host	smart-653006e1-7fa7-4069-9d42-7b23582740c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32149 12704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3214912704
Directory	/workspace/37.usbdev_smoke/latest

Test location	/workspace/coverage/default/38.setup_trans_ignored.3436360638
Short name	T282
Test name
Test status
Simulation time	8357096841 ps
CPU time	7.4 seconds
Started	Feb 18 12:55:21 PM PST 24
Finished	Feb 18 12:55:37 PM PST 24
Peak memory	202024 kb
Host	smart-59994b7b-411d-4310-af1a-2d2795950005
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34363 60638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.setup_trans_ignored.3436360638
Directory	/workspace/38.setup_trans_ignored/latest

Test location	/workspace/coverage/default/38.usbdev_av_buffer.3106362010
Short name	T8
Test name
Test status
Simulation time	8378652458 ps
CPU time	9.43 seconds
Started	Feb 18 12:55:18 PM PST 24
Finished	Feb 18 12:55:36 PM PST 24
Peak memory	202000 kb
Host	smart-baab4520-5995-462d-99ac-4c9feb3e98a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31063 62010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3106362010
Directory	/workspace/38.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/38.usbdev_nak_trans.985166051
Short name	T72
Test name
Test status
Simulation time	8426794708 ps
CPU time	7.11 seconds
Started	Feb 18 12:55:20 PM PST 24
Finished	Feb 18 12:55:35 PM PST 24
Peak memory	201860 kb
Host	smart-d1560d18-2179-46a7-88cc-e60552442131
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98516 6051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.985166051
Directory	/workspace/38.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/38.usbdev_pkt_sent.3294711150
Short name	T196
Test name
Test status
Simulation time	8423732552 ps
CPU time	8.91 seconds
Started	Feb 18 12:55:15 PM PST 24
Finished	Feb 18 12:55:33 PM PST 24
Peak memory	202024 kb
Host	smart-6f6dd7da-0746-42b5-8bf5-27b20251e524
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947 11150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3294711150
Directory	/workspace/38.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/38.usbdev_smoke.4053019850
Short name	T243
Test name
Test status
Simulation time	8366560827 ps
CPU time	8.14 seconds
Started	Feb 18 12:55:12 PM PST 24
Finished	Feb 18 12:55:29 PM PST 24
Peak memory	202016 kb
Host	smart-86fe1b27-a91e-44a2-94d3-185e2dd6365c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40530 19850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.4053019850
Directory	/workspace/38.usbdev_smoke/latest

Test location	/workspace/coverage/default/39.in_trans.849485291
Short name	T97
Test name
Test status
Simulation time	8382170718 ps
CPU time	7.57 seconds
Started	Feb 18 12:55:16 PM PST 24
Finished	Feb 18 12:55:32 PM PST 24
Peak memory	201856 kb
Host	smart-14563fa1-cd81-4223-9abb-61452a80bae0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84948 5291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.in_trans.849485291
Directory	/workspace/39.in_trans/latest

Test location	/workspace/coverage/default/39.setup_trans_ignored.2561109538
Short name	T229
Test name
Test status
Simulation time	8365395411 ps
CPU time	8.08 seconds
Started	Feb 18 12:55:21 PM PST 24
Finished	Feb 18 12:55:38 PM PST 24
Peak memory	202012 kb
Host	smart-15774d8f-6c23-49bb-a0e6-c02d3682b8b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25611 09538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.setup_trans_ignored.2561109538
Directory	/workspace/39.setup_trans_ignored/latest

Test location	/workspace/coverage/default/39.usbdev_av_buffer.780467923
Short name	T195
Test name
Test status
Simulation time	8417588987 ps
CPU time	7.66 seconds
Started	Feb 18 12:55:15 PM PST 24
Finished	Feb 18 12:55:32 PM PST 24
Peak memory	202020 kb
Host	smart-b4a81f69-090d-468d-9f55-823e3fd33f29
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78046 7923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.780467923
Directory	/workspace/39.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/39.usbdev_nak_trans.3235350759
Short name	T279
Test name
Test status
Simulation time	8383335456 ps
CPU time	7.7 seconds
Started	Feb 18 12:55:11 PM PST 24
Finished	Feb 18 12:55:28 PM PST 24
Peak memory	202004 kb
Host	smart-9dcacaf0-0c6b-47a4-84f3-816263093d66
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32353 50759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3235350759
Directory	/workspace/39.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/39.usbdev_pkt_sent.2915224545
Short name	T267
Test name
Test status
Simulation time	8382513066 ps
CPU time	7.9 seconds
Started	Feb 18 12:55:21 PM PST 24
Finished	Feb 18 12:55:37 PM PST 24
Peak memory	201960 kb
Host	smart-c7ddfb8e-047c-4480-b2da-61341c0f8ecc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29152 24545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2915224545
Directory	/workspace/39.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/39.usbdev_smoke.287373492
Short name	T145
Test name
Test status
Simulation time	8365946077 ps
CPU time	7.09 seconds
Started	Feb 18 12:55:17 PM PST 24
Finished	Feb 18 12:55:32 PM PST 24
Peak memory	202012 kb
Host	smart-a8f8d005-ab4b-475e-9b47-6f6d61f51638
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28737 3492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.287373492
Directory	/workspace/39.usbdev_smoke/latest

Test location	/workspace/coverage/default/4.setup_trans_ignored.2637979394
Short name	T323
Test name
Test status
Simulation time	8357236896 ps
CPU time	8.79 seconds
Started	Feb 18 12:53:52 PM PST 24
Finished	Feb 18 12:54:08 PM PST 24
Peak memory	202032 kb
Host	smart-0e671c34-af17-486e-a240-e05194c3ff1c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26379 79394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.setup_trans_ignored.2637979394
Directory	/workspace/4.setup_trans_ignored/latest

Test location	/workspace/coverage/default/4.usbdev_nak_trans.4058869644
Short name	T76
Test name
Test status
Simulation time	8454830098 ps
CPU time	8.38 seconds
Started	Feb 18 12:54:09 PM PST 24
Finished	Feb 18 12:54:22 PM PST 24
Peak memory	202004 kb
Host	smart-e3e92f10-bfa8-4071-a84f-c6008abc4298
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40588 69644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.4058869644
Directory	/workspace/4.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/4.usbdev_pkt_sent.1308206599
Short name	T284
Test name
Test status
Simulation time	8450187098 ps
CPU time	8.38 seconds
Started	Feb 18 12:54:03 PM PST 24
Finished	Feb 18 12:54:17 PM PST 24
Peak memory	202004 kb
Host	smart-41c439c6-d053-43aa-8480-0e606ddbc4d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13082 06599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1308206599
Directory	/workspace/4.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/4.usbdev_sec_cm.2983508692
Short name	T55
Test name
Test status
Simulation time	99760717 ps
CPU time	0.92 seconds
Started	Feb 18 12:54:18 PM PST 24
Finished	Feb 18 12:54:25 PM PST 24
Peak memory	216796 kb
Host	smart-d3693eb4-aa20-4d12-bbab-c5187d299426
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2983508692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2983508692
Directory	/workspace/4.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/4.usbdev_smoke.3679905606
Short name	T297
Test name
Test status
Simulation time	8370161489 ps
CPU time	8.47 seconds
Started	Feb 18 12:53:52 PM PST 24
Finished	Feb 18 12:54:07 PM PST 24
Peak memory	201916 kb
Host	smart-af720bdc-e4b9-4836-80e7-18cd6fc02deb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36799 05606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3679905606
Directory	/workspace/4.usbdev_smoke/latest

Test location	/workspace/coverage/default/40.in_trans.2782261837
Short name	T100
Test name
Test status
Simulation time	8394278350 ps
CPU time	7.41 seconds
Started	Feb 18 12:55:18 PM PST 24
Finished	Feb 18 12:55:35 PM PST 24
Peak memory	202020 kb
Host	smart-9ef2e179-cb80-4561-83e0-60af1d7551e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27822 61837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.in_trans.2782261837
Directory	/workspace/40.in_trans/latest

Test location	/workspace/coverage/default/40.setup_trans_ignored.3712503450
Short name	T333
Test name
Test status
Simulation time	8359733557 ps
CPU time	7.57 seconds
Started	Feb 18 12:55:20 PM PST 24
Finished	Feb 18 12:55:36 PM PST 24
Peak memory	202012 kb
Host	smart-788aa4c6-9a9e-4e16-90ab-7d0f2a73260f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37125 03450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.setup_trans_ignored.3712503450
Directory	/workspace/40.setup_trans_ignored/latest

Test location	/workspace/coverage/default/40.usbdev_av_buffer.2851615871
Short name	T27
Test name
Test status
Simulation time	8367681934 ps
CPU time	8.86 seconds
Started	Feb 18 12:55:20 PM PST 24
Finished	Feb 18 12:55:37 PM PST 24
Peak memory	202024 kb
Host	smart-2b731198-c5dc-449d-942a-0b3d27205e75
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28516 15871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2851615871
Directory	/workspace/40.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/40.usbdev_nak_trans.3964998438
Short name	T190
Test name
Test status
Simulation time	8429059815 ps
CPU time	8.01 seconds
Started	Feb 18 12:55:15 PM PST 24
Finished	Feb 18 12:55:32 PM PST 24
Peak memory	201988 kb
Host	smart-a624c121-abf6-4030-b700-9a6b0d80987d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39649 98438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3964998438
Directory	/workspace/40.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/40.usbdev_pkt_sent.4294575828
Short name	T23
Test name
Test status
Simulation time	8462174773 ps
CPU time	9.11 seconds
Started	Feb 18 12:55:30 PM PST 24
Finished	Feb 18 12:55:47 PM PST 24
Peak memory	202020 kb
Host	smart-c8be53b1-8bad-4f54-ba9d-d4bdf077d215
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42945 75828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.4294575828
Directory	/workspace/40.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/40.usbdev_smoke.250833192
Short name	T59
Test name
Test status
Simulation time	8367212903 ps
CPU time	7.8 seconds
Started	Feb 18 12:55:22 PM PST 24
Finished	Feb 18 12:55:38 PM PST 24
Peak memory	202020 kb
Host	smart-80fbb42c-19d3-4730-9ee6-040387a69de7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25083 3192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.250833192
Directory	/workspace/40.usbdev_smoke/latest

Test location	/workspace/coverage/default/41.in_trans.3955073734
Short name	T174
Test name
Test status
Simulation time	8398967917 ps
CPU time	7.42 seconds
Started	Feb 18 12:55:17 PM PST 24
Finished	Feb 18 12:55:33 PM PST 24
Peak memory	202012 kb
Host	smart-315c60b4-f8f8-4998-8f0f-c5affd5786a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550 73734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.in_trans.3955073734
Directory	/workspace/41.in_trans/latest

Test location	/workspace/coverage/default/41.setup_trans_ignored.1771314688
Short name	T178
Test name
Test status
Simulation time	8355706079 ps
CPU time	7.79 seconds
Started	Feb 18 12:55:17 PM PST 24
Finished	Feb 18 12:55:33 PM PST 24
Peak memory	202028 kb
Host	smart-29ded390-7ccd-4fb0-88a8-2e3c2cc59c32
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17713 14688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.setup_trans_ignored.1771314688
Directory	/workspace/41.setup_trans_ignored/latest

Test location	/workspace/coverage/default/41.usbdev_av_buffer.3899231687
Short name	T231
Test name
Test status
Simulation time	8370850079 ps
CPU time	7.93 seconds
Started	Feb 18 12:55:21 PM PST 24
Finished	Feb 18 12:55:38 PM PST 24
Peak memory	201996 kb
Host	smart-cd85a973-0d49-4eab-aaf7-32bd9d1338c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38992 31687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3899231687
Directory	/workspace/41.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/41.usbdev_pkt_sent.1514738642
Short name	T102
Test name
Test status
Simulation time	8402704960 ps
CPU time	8.29 seconds
Started	Feb 18 12:55:29 PM PST 24
Finished	Feb 18 12:55:45 PM PST 24
Peak memory	202020 kb
Host	smart-41db5009-4b35-4a6f-94f7-d03b7da6b2f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15147 38642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1514738642
Directory	/workspace/41.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/41.usbdev_smoke.735860350
Short name	T200
Test name
Test status
Simulation time	8370168121 ps
CPU time	7.06 seconds
Started	Feb 18 12:55:30 PM PST 24
Finished	Feb 18 12:55:45 PM PST 24
Peak memory	202020 kb
Host	smart-9be969a2-bbfd-4863-8b3c-7431f80de7e6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73586 0350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.735860350
Directory	/workspace/41.usbdev_smoke/latest

Test location	/workspace/coverage/default/42.in_trans.2841318304
Short name	T334
Test name
Test status
Simulation time	8433618730 ps
CPU time	7.92 seconds
Started	Feb 18 12:55:33 PM PST 24
Finished	Feb 18 12:55:49 PM PST 24
Peak memory	201936 kb
Host	smart-f9c9a8b7-538d-4e04-aae4-27061af15367
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28413 18304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.in_trans.2841318304
Directory	/workspace/42.in_trans/latest

Test location	/workspace/coverage/default/42.setup_trans_ignored.1890196629
Short name	T179
Test name
Test status
Simulation time	8371850542 ps
CPU time	7.24 seconds
Started	Feb 18 12:55:29 PM PST 24
Finished	Feb 18 12:55:45 PM PST 24
Peak memory	202024 kb
Host	smart-f57a28fe-7fed-44a9-a422-ec0dc794e7ad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18901 96629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.setup_trans_ignored.1890196629
Directory	/workspace/42.setup_trans_ignored/latest

Test location	/workspace/coverage/default/42.usbdev_av_buffer.3332226072
Short name	T31
Test name
Test status
Simulation time	8372781146 ps
CPU time	7.1 seconds
Started	Feb 18 12:55:27 PM PST 24
Finished	Feb 18 12:55:43 PM PST 24
Peak memory	202024 kb
Host	smart-3c7830ea-deeb-4683-9909-12268f5c312e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33322 26072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3332226072
Directory	/workspace/42.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/42.usbdev_nak_trans.1413667898
Short name	T85
Test name
Test status
Simulation time	8383203310 ps
CPU time	7.67 seconds
Started	Feb 18 12:55:32 PM PST 24
Finished	Feb 18 12:55:48 PM PST 24
Peak memory	201784 kb
Host	smart-f00f7a33-30fb-40bd-816d-ac8e83ed7dde
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14136 67898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1413667898
Directory	/workspace/42.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/42.usbdev_pkt_sent.2377991543
Short name	T326
Test name
Test status
Simulation time	8414313824 ps
CPU time	9.27 seconds
Started	Feb 18 12:55:29 PM PST 24
Finished	Feb 18 12:55:47 PM PST 24
Peak memory	202020 kb
Host	smart-03631c3b-e78e-4e1f-af80-2d0f2ac185ac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779 91543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2377991543
Directory	/workspace/42.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/42.usbdev_smoke.308657472
Short name	T16
Test name
Test status
Simulation time	8379438029 ps
CPU time	7.32 seconds
Started	Feb 18 12:55:33 PM PST 24
Finished	Feb 18 12:55:49 PM PST 24
Peak memory	201916 kb
Host	smart-0139e751-51b2-45d2-9419-b32d49f31de9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865 7472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.308657472
Directory	/workspace/42.usbdev_smoke/latest

Test location	/workspace/coverage/default/43.setup_trans_ignored.1293488523
Short name	T305
Test name
Test status
Simulation time	8358302939 ps
CPU time	8.9 seconds
Started	Feb 18 12:55:33 PM PST 24
Finished	Feb 18 12:55:50 PM PST 24
Peak memory	201940 kb
Host	smart-e081a497-7f93-429d-ab17-818bb466db01
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934 88523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.setup_trans_ignored.1293488523
Directory	/workspace/43.setup_trans_ignored/latest

Test location	/workspace/coverage/default/43.usbdev_av_buffer.2101445751
Short name	T266
Test name
Test status
Simulation time	8374712624 ps
CPU time	7.29 seconds
Started	Feb 18 12:55:29 PM PST 24
Finished	Feb 18 12:55:44 PM PST 24
Peak memory	202024 kb
Host	smart-df2b26e8-0f0e-45ef-99b3-a395f4279ec4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21014 45751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2101445751
Directory	/workspace/43.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/43.usbdev_pkt_sent.1697757074
Short name	T115
Test name
Test status
Simulation time	8394637295 ps
CPU time	7.45 seconds
Started	Feb 18 12:55:18 PM PST 24
Finished	Feb 18 12:55:34 PM PST 24
Peak memory	202008 kb
Host	smart-49527b1e-6522-47aa-b491-6ab4a4f2cdcf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16977 57074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1697757074
Directory	/workspace/43.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/43.usbdev_smoke.3450464779
Short name	T264
Test name
Test status
Simulation time	8371317036 ps
CPU time	7.42 seconds
Started	Feb 18 12:55:30 PM PST 24
Finished	Feb 18 12:55:46 PM PST 24
Peak memory	202016 kb
Host	smart-eeaf1f75-9e07-425f-9571-7969b1374f94
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34504 64779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3450464779
Directory	/workspace/43.usbdev_smoke/latest

Test location	/workspace/coverage/default/44.in_trans.2049596735
Short name	T259
Test name
Test status
Simulation time	8480697600 ps
CPU time	8.88 seconds
Started	Feb 18 12:55:41 PM PST 24
Finished	Feb 18 12:55:54 PM PST 24
Peak memory	202012 kb
Host	smart-a563b708-f283-49f4-83a7-2267e2d97bac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20495 96735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.in_trans.2049596735
Directory	/workspace/44.in_trans/latest

Test location	/workspace/coverage/default/44.setup_trans_ignored.2853541189
Short name	T191
Test name
Test status
Simulation time	8356673361 ps
CPU time	7.99 seconds
Started	Feb 18 12:55:29 PM PST 24
Finished	Feb 18 12:55:46 PM PST 24
Peak memory	202020 kb
Host	smart-89ea01e0-e334-4035-a014-247e7d0d1902
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28535 41189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.setup_trans_ignored.2853541189
Directory	/workspace/44.setup_trans_ignored/latest

Test location	/workspace/coverage/default/44.usbdev_av_buffer.4030713846
Short name	T317
Test name
Test status
Simulation time	8368607105 ps
CPU time	9.55 seconds
Started	Feb 18 12:55:25 PM PST 24
Finished	Feb 18 12:55:44 PM PST 24
Peak memory	202028 kb
Host	smart-1bf40983-3681-410d-80a5-a1e8cbe6e728
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40307 13846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.4030713846
Directory	/workspace/44.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/44.usbdev_nak_trans.117652104
Short name	T90
Test name
Test status
Simulation time	8391784127 ps
CPU time	8.53 seconds
Started	Feb 18 12:55:29 PM PST 24
Finished	Feb 18 12:55:46 PM PST 24
Peak memory	201944 kb
Host	smart-e0cab773-1d2a-4d19-b7c3-154f0ee1bc5d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11765 2104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.117652104
Directory	/workspace/44.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/44.usbdev_pkt_sent.4023201102
Short name	T153
Test name
Test status
Simulation time	8401070819 ps
CPU time	8.28 seconds
Started	Feb 18 12:55:34 PM PST 24
Finished	Feb 18 12:55:50 PM PST 24
Peak memory	202032 kb
Host	smart-64eb2f42-ce9b-4b5c-abf6-6a42d84acbad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40232 01102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.4023201102
Directory	/workspace/44.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/44.usbdev_smoke.3659714986
Short name	T257
Test name
Test status
Simulation time	8370671659 ps
CPU time	9.72 seconds
Started	Feb 18 12:55:39 PM PST 24
Finished	Feb 18 12:55:54 PM PST 24
Peak memory	202020 kb
Host	smart-38eb6a31-c68f-4ac5-9733-74ace4a34c03
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36597 14986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3659714986
Directory	/workspace/44.usbdev_smoke/latest

Test location	/workspace/coverage/default/45.in_trans.3874638942
Short name	T197
Test name
Test status
Simulation time	8388556707 ps
CPU time	7.23 seconds
Started	Feb 18 12:55:31 PM PST 24
Finished	Feb 18 12:55:46 PM PST 24
Peak memory	202024 kb
Host	smart-6e8accd9-cec9-40af-90f8-5b3c181ba451
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38746 38942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.in_trans.3874638942
Directory	/workspace/45.in_trans/latest

Test location	/workspace/coverage/default/45.setup_trans_ignored.169515841
Short name	T277
Test name
Test status
Simulation time	8360292556 ps
CPU time	7.26 seconds
Started	Feb 18 12:55:33 PM PST 24
Finished	Feb 18 12:55:49 PM PST 24
Peak memory	201984 kb
Host	smart-1b5114ae-3a7a-4a2b-962e-33d6de6372dd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16951 5841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.setup_trans_ignored.169515841
Directory	/workspace/45.setup_trans_ignored/latest

Test location	/workspace/coverage/default/45.usbdev_av_buffer.3741670647
Short name	T281
Test name
Test status
Simulation time	8377832223 ps
CPU time	7.16 seconds
Started	Feb 18 12:55:45 PM PST 24
Finished	Feb 18 12:55:56 PM PST 24
Peak memory	202024 kb
Host	smart-2365fed6-61a7-4681-8122-b579097e4cb1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37416 70647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3741670647
Directory	/workspace/45.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/45.usbdev_nak_trans.3636549434
Short name	T75
Test name
Test status
Simulation time	8419772376 ps
CPU time	7.71 seconds
Started	Feb 18 12:55:46 PM PST 24
Finished	Feb 18 12:55:57 PM PST 24
Peak memory	202024 kb
Host	smart-a22bd797-37f0-4d26-a620-cff257ed32d0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36365 49434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3636549434
Directory	/workspace/45.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/45.usbdev_pkt_sent.1806287309
Short name	T276
Test name
Test status
Simulation time	8444191089 ps
CPU time	7.08 seconds
Started	Feb 18 12:55:33 PM PST 24
Finished	Feb 18 12:55:48 PM PST 24
Peak memory	201956 kb
Host	smart-59ec9419-752c-4bae-9992-f40fb7040748
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18062 87309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1806287309
Directory	/workspace/45.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/45.usbdev_smoke.1537530879
Short name	T340
Test name
Test status
Simulation time	8397050698 ps
CPU time	9.43 seconds
Started	Feb 18 12:55:24 PM PST 24
Finished	Feb 18 12:55:43 PM PST 24
Peak memory	202024 kb
Host	smart-9d21e5e9-daa0-4339-a3a4-cf055b28d359
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15375 30879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1537530879
Directory	/workspace/45.usbdev_smoke/latest

Test location	/workspace/coverage/default/46.in_trans.2117041868
Short name	T4
Test name
Test status
Simulation time	8436507319 ps
CPU time	9.46 seconds
Started	Feb 18 12:55:40 PM PST 24
Finished	Feb 18 12:55:54 PM PST 24
Peak memory	202020 kb
Host	smart-1dd22ba0-5070-424e-bc95-75a08d4cc5e8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21170 41868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.in_trans.2117041868
Directory	/workspace/46.in_trans/latest

Test location	/workspace/coverage/default/46.setup_trans_ignored.1283470710
Short name	T307
Test name
Test status
Simulation time	8361417722 ps
CPU time	7.8 seconds
Started	Feb 18 12:55:32 PM PST 24
Finished	Feb 18 12:55:49 PM PST 24
Peak memory	201916 kb
Host	smart-60b8e3bd-6482-44c2-810c-9132a5a4fef4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12834 70710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.setup_trans_ignored.1283470710
Directory	/workspace/46.setup_trans_ignored/latest

Test location	/workspace/coverage/default/46.usbdev_av_buffer.1701159220
Short name	T296
Test name
Test status
Simulation time	8398478350 ps
CPU time	9.08 seconds
Started	Feb 18 12:55:43 PM PST 24
Finished	Feb 18 12:55:57 PM PST 24
Peak memory	201940 kb
Host	smart-ac93671e-0d7c-4925-98fb-77f1f39b7ea5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17011 59220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1701159220
Directory	/workspace/46.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/46.usbdev_nak_trans.980748466
Short name	T198
Test name
Test status
Simulation time	8418653318 ps
CPU time	7.56 seconds
Started	Feb 18 12:55:38 PM PST 24
Finished	Feb 18 12:55:52 PM PST 24
Peak memory	202020 kb
Host	smart-7c3828a6-f426-4b42-b854-6531184e4b4f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98074 8466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.980748466
Directory	/workspace/46.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/46.usbdev_smoke.1261755396
Short name	T255
Test name
Test status
Simulation time	8366910750 ps
CPU time	9.84 seconds
Started	Feb 18 12:55:42 PM PST 24
Finished	Feb 18 12:55:56 PM PST 24
Peak memory	202012 kb
Host	smart-5b46bc95-d92d-4645-b85e-aa83369ff3f5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12617 55396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1261755396
Directory	/workspace/46.usbdev_smoke/latest

Test location	/workspace/coverage/default/47.in_trans.28803986
Short name	T258
Test name
Test status
Simulation time	8457739713 ps
CPU time	7.25 seconds
Started	Feb 18 12:55:56 PM PST 24
Finished	Feb 18 12:56:06 PM PST 24
Peak memory	201936 kb
Host	smart-55b51c95-7580-420f-b60b-d22c80b14482
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28803 986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.in_trans.28803986
Directory	/workspace/47.in_trans/latest

Test location	/workspace/coverage/default/47.setup_trans_ignored.703555059
Short name	T221
Test name
Test status
Simulation time	8366676201 ps
CPU time	8.79 seconds
Started	Feb 18 12:55:38 PM PST 24
Finished	Feb 18 12:55:53 PM PST 24
Peak memory	202004 kb
Host	smart-1b749b2c-9a71-440f-bcee-ef2512c5f9ce
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70355 5059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.setup_trans_ignored.703555059
Directory	/workspace/47.setup_trans_ignored/latest

Test location	/workspace/coverage/default/47.usbdev_av_buffer.3186995276
Short name	T289
Test name
Test status
Simulation time	8377664589 ps
CPU time	6.91 seconds
Started	Feb 18 12:55:50 PM PST 24
Finished	Feb 18 12:56:00 PM PST 24
Peak memory	202028 kb
Host	smart-6d0b20cd-cc6e-4141-84dc-d3df515809f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31869 95276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3186995276
Directory	/workspace/47.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/47.usbdev_nak_trans.1028463841
Short name	T88
Test name
Test status
Simulation time	8421276650 ps
CPU time	9.25 seconds
Started	Feb 18 12:55:32 PM PST 24
Finished	Feb 18 12:55:49 PM PST 24
Peak memory	202024 kb
Host	smart-699cd82e-0fc6-4a21-b6eb-4697156a01c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10284 63841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1028463841
Directory	/workspace/47.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/47.usbdev_smoke.1866063596
Short name	T56
Test name
Test status
Simulation time	8375322515 ps
CPU time	7.3 seconds
Started	Feb 18 12:55:50 PM PST 24
Finished	Feb 18 12:56:01 PM PST 24
Peak memory	202024 kb
Host	smart-583b9620-0d40-4374-a5c1-3e9ec966f2ca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18660 63596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1866063596
Directory	/workspace/47.usbdev_smoke/latest

Test location	/workspace/coverage/default/48.in_trans.2135888683
Short name	T62
Test name
Test status
Simulation time	8396677431 ps
CPU time	7.24 seconds
Started	Feb 18 12:56:00 PM PST 24
Finished	Feb 18 12:56:13 PM PST 24
Peak memory	202020 kb
Host	smart-a19dac0e-1bc6-4e3c-9f28-6b4fed4dd860
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21358 88683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.in_trans.2135888683
Directory	/workspace/48.in_trans/latest

Test location	/workspace/coverage/default/48.setup_trans_ignored.2582170256
Short name	T311
Test name
Test status
Simulation time	8359449119 ps
CPU time	8.04 seconds
Started	Feb 18 12:55:54 PM PST 24
Finished	Feb 18 12:56:05 PM PST 24
Peak memory	202016 kb
Host	smart-002cbca2-83da-4142-8483-a7584f673e09
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25821 70256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.setup_trans_ignored.2582170256
Directory	/workspace/48.setup_trans_ignored/latest

Test location	/workspace/coverage/default/48.usbdev_av_buffer.3141876017
Short name	T185
Test name
Test status
Simulation time	8372875707 ps
CPU time	7.58 seconds
Started	Feb 18 12:55:55 PM PST 24
Finished	Feb 18 12:56:06 PM PST 24
Peak memory	202016 kb
Host	smart-9a748f1f-eb96-4ffc-b07d-2824b7171847
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31418 76017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3141876017
Directory	/workspace/48.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/48.usbdev_nak_trans.3972740432
Short name	T80
Test name
Test status
Simulation time	8416070387 ps
CPU time	7.63 seconds
Started	Feb 18 12:55:59 PM PST 24
Finished	Feb 18 12:56:12 PM PST 24
Peak memory	202024 kb
Host	smart-0d590e5b-415a-422c-af87-86df7628f626
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39727 40432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3972740432
Directory	/workspace/48.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/48.usbdev_pkt_sent.3578992991
Short name	T250
Test name
Test status
Simulation time	8425812029 ps
CPU time	8.05 seconds
Started	Feb 18 12:55:49 PM PST 24
Finished	Feb 18 12:56:01 PM PST 24
Peak memory	202020 kb
Host	smart-93da5ab2-033a-4ba9-9bcf-657e60c549f4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35789 92991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3578992991
Directory	/workspace/48.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/49.in_trans.3598775219
Short name	T98
Test name
Test status
Simulation time	8408945527 ps
CPU time	7.4 seconds
Started	Feb 18 12:56:04 PM PST 24
Finished	Feb 18 12:56:16 PM PST 24
Peak memory	202000 kb
Host	smart-76acda15-4d92-4f45-af79-45f4dd647e93
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987 75219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.in_trans.3598775219
Directory	/workspace/49.in_trans/latest

Test location	/workspace/coverage/default/49.setup_trans_ignored.171128601
Short name	T206
Test name
Test status
Simulation time	8356197314 ps
CPU time	7.95 seconds
Started	Feb 18 12:55:54 PM PST 24
Finished	Feb 18 12:56:05 PM PST 24
Peak memory	202012 kb
Host	smart-0692a53e-6326-423a-accb-47e95e002a1d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17112 8601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.setup_trans_ignored.171128601
Directory	/workspace/49.setup_trans_ignored/latest

Test location	/workspace/coverage/default/49.usbdev_av_buffer.3710952731
Short name	T299
Test name
Test status
Simulation time	8368166949 ps
CPU time	7.32 seconds
Started	Feb 18 12:56:08 PM PST 24
Finished	Feb 18 12:56:21 PM PST 24
Peak memory	202016 kb
Host	smart-c71ee256-65b4-4796-bd07-d45d41636b86
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37109 52731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3710952731
Directory	/workspace/49.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/49.usbdev_nak_trans.1415017389
Short name	T283
Test name
Test status
Simulation time	8412439603 ps
CPU time	7.71 seconds
Started	Feb 18 12:56:05 PM PST 24
Finished	Feb 18 12:56:17 PM PST 24
Peak memory	202016 kb
Host	smart-262a83a9-0046-4e3b-a7ac-051eb9f48114
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150 17389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1415017389
Directory	/workspace/49.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/49.usbdev_pkt_sent.1533602009
Short name	T192
Test name
Test status
Simulation time	8425033029 ps
CPU time	7.45 seconds
Started	Feb 18 12:56:07 PM PST 24
Finished	Feb 18 12:56:19 PM PST 24
Peak memory	202012 kb
Host	smart-4857dc83-b054-4f15-83e7-c784a6ceba4a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15336 02009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1533602009
Directory	/workspace/49.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/49.usbdev_smoke.1187806884
Short name	T7
Test name
Test status
Simulation time	8370237369 ps
CPU time	8.98 seconds
Started	Feb 18 12:56:07 PM PST 24
Finished	Feb 18 12:56:21 PM PST 24
Peak memory	202012 kb
Host	smart-be6ef2ce-e8bf-4c99-8ae9-2738bcf41d0f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11878 06884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1187806884
Directory	/workspace/49.usbdev_smoke/latest

Test location	/workspace/coverage/default/5.in_trans.1170069619
Short name	T275
Test name
Test status
Simulation time	8377988896 ps
CPU time	7.87 seconds
Started	Feb 18 12:54:09 PM PST 24
Finished	Feb 18 12:54:21 PM PST 24
Peak memory	201992 kb
Host	smart-2c6ef5ec-737c-4b86-8941-cb68efc04545
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11700 69619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.in_trans.1170069619
Directory	/workspace/5.in_trans/latest

Test location	/workspace/coverage/default/5.setup_trans_ignored.3957302614
Short name	T216
Test name
Test status
Simulation time	8370278629 ps
CPU time	8.63 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:26 PM PST 24
Peak memory	201956 kb
Host	smart-3ef55a45-b301-41d7-a14c-8b9be30f4151
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573 02614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.setup_trans_ignored.3957302614
Directory	/workspace/5.setup_trans_ignored/latest

Test location	/workspace/coverage/default/5.usbdev_av_buffer.482370833
Short name	T239
Test name
Test status
Simulation time	8368235341 ps
CPU time	8.12 seconds
Started	Feb 18 12:54:08 PM PST 24
Finished	Feb 18 12:54:20 PM PST 24
Peak memory	202020 kb
Host	smart-83cde29b-f414-4817-b3da-6cd714426058
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48237 0833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.482370833
Directory	/workspace/5.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/5.usbdev_nak_trans.1386269562
Short name	T2
Test name
Test status
Simulation time	8405520454 ps
CPU time	7.15 seconds
Started	Feb 18 12:54:08 PM PST 24
Finished	Feb 18 12:54:20 PM PST 24
Peak memory	201876 kb
Host	smart-ce06d8c0-45d9-4022-a781-4816feb33d86
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13862 69562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1386269562
Directory	/workspace/5.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/5.usbdev_pkt_sent.3337491607
Short name	T95
Test name
Test status
Simulation time	8462705355 ps
CPU time	9.24 seconds
Started	Feb 18 12:54:05 PM PST 24
Finished	Feb 18 12:54:19 PM PST 24
Peak memory	202024 kb
Host	smart-030c25be-af91-4b77-8d22-205c35ce23e0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33374 91607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3337491607
Directory	/workspace/5.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/6.setup_trans_ignored.3692331737
Short name	T155
Test name
Test status
Simulation time	8365033613 ps
CPU time	6.93 seconds
Started	Feb 18 12:54:03 PM PST 24
Finished	Feb 18 12:54:15 PM PST 24
Peak memory	201992 kb
Host	smart-c7c27231-b085-40e5-a64f-4c2394a12cc1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36923 31737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.setup_trans_ignored.3692331737
Directory	/workspace/6.setup_trans_ignored/latest

Test location	/workspace/coverage/default/6.usbdev_av_buffer.3761661380
Short name	T215
Test name
Test status
Simulation time	8366759023 ps
CPU time	8.66 seconds
Started	Feb 18 12:54:08 PM PST 24
Finished	Feb 18 12:54:20 PM PST 24
Peak memory	202048 kb
Host	smart-73c4c806-1c81-45b7-980b-c4337368c32f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37616 61380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3761661380
Directory	/workspace/6.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/6.usbdev_nak_trans.984874777
Short name	T11
Test name
Test status
Simulation time	8431046748 ps
CPU time	9.63 seconds
Started	Feb 18 12:54:08 PM PST 24
Finished	Feb 18 12:54:21 PM PST 24
Peak memory	202008 kb
Host	smart-c3a81a15-6f45-461c-b755-bb43ace52ab7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98487 4777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.984874777
Directory	/workspace/6.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/6.usbdev_pkt_sent.1834011298
Short name	T245
Test name
Test status
Simulation time	8436538812 ps
CPU time	7.52 seconds
Started	Feb 18 12:54:15 PM PST 24
Finished	Feb 18 12:54:29 PM PST 24
Peak memory	202012 kb
Host	smart-716702fd-bbfa-4196-9945-6789b6c1376d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340 11298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1834011298
Directory	/workspace/6.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/6.usbdev_smoke.2906957975
Short name	T294
Test name
Test status
Simulation time	8379231487 ps
CPU time	7.53 seconds
Started	Feb 18 12:54:11 PM PST 24
Finished	Feb 18 12:54:24 PM PST 24
Peak memory	201992 kb
Host	smart-92c67e8f-250a-4825-8029-04f2a06f4b31
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29069 57975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2906957975
Directory	/workspace/6.usbdev_smoke/latest

Test location	/workspace/coverage/default/7.in_trans.488470679
Short name	T203
Test name
Test status
Simulation time	8389644472 ps
CPU time	8.56 seconds
Started	Feb 18 12:53:55 PM PST 24
Finished	Feb 18 12:54:12 PM PST 24
Peak memory	201876 kb
Host	smart-1ea4ac01-3855-4701-a299-98e8ccbffe7f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48847 0679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.in_trans.488470679
Directory	/workspace/7.in_trans/latest

Test location	/workspace/coverage/default/7.setup_trans_ignored.3626120121
Short name	T173
Test name
Test status
Simulation time	8359187614 ps
CPU time	9.28 seconds
Started	Feb 18 12:54:01 PM PST 24
Finished	Feb 18 12:54:17 PM PST 24
Peak memory	201840 kb
Host	smart-30138c11-972a-47bf-858a-39d9d32d2e4f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36261 20121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.setup_trans_ignored.3626120121
Directory	/workspace/7.setup_trans_ignored/latest

Test location	/workspace/coverage/default/7.usbdev_av_buffer.3979291016
Short name	T337
Test name
Test status
Simulation time	8373503805 ps
CPU time	9.51 seconds
Started	Feb 18 12:53:55 PM PST 24
Finished	Feb 18 12:54:13 PM PST 24
Peak memory	202012 kb
Host	smart-ba0a9c82-9e0c-42b8-b9ba-184adb8367d9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39792 91016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3979291016
Directory	/workspace/7.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/7.usbdev_nak_trans.1755804291
Short name	T310
Test name
Test status
Simulation time	8379884850 ps
CPU time	7.48 seconds
Started	Feb 18 12:54:10 PM PST 24
Finished	Feb 18 12:54:22 PM PST 24
Peak memory	201956 kb
Host	smart-7c262cfa-372a-487e-bab2-9d784b6b6760
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17558 04291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1755804291
Directory	/workspace/7.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/7.usbdev_pkt_sent.1467200662
Short name	T247
Test name
Test status
Simulation time	8383023343 ps
CPU time	7.24 seconds
Started	Feb 18 12:54:08 PM PST 24
Finished	Feb 18 12:54:20 PM PST 24
Peak memory	202024 kb
Host	smart-02b1ceee-2684-4573-80e9-06890c900164
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14672 00662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1467200662
Directory	/workspace/7.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/7.usbdev_smoke.216460168
Short name	T147
Test name
Test status
Simulation time	8368916218 ps
CPU time	8.22 seconds
Started	Feb 18 12:54:14 PM PST 24
Finished	Feb 18 12:54:28 PM PST 24
Peak memory	202044 kb
Host	smart-7bf567de-7d1a-4522-bb7d-3b3e84a88ec4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21646 0168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.216460168
Directory	/workspace/7.usbdev_smoke/latest

Test location	/workspace/coverage/default/8.in_trans.3173464899
Short name	T96
Test name
Test status
Simulation time	8417107237 ps
CPU time	7.13 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:25 PM PST 24
Peak memory	202020 kb
Host	smart-21b41ef7-bd07-4c89-aba8-47ce263f42c7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734 64899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.in_trans.3173464899
Directory	/workspace/8.in_trans/latest

Test location	/workspace/coverage/default/8.setup_trans_ignored.3162661629
Short name	T58
Test name
Test status
Simulation time	8387702990 ps
CPU time	7.07 seconds
Started	Feb 18 12:54:05 PM PST 24
Finished	Feb 18 12:54:16 PM PST 24
Peak memory	201968 kb
Host	smart-cc5e6652-ee94-46a5-b56f-81c6d3f8b964
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31626 61629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.setup_trans_ignored.3162661629
Directory	/workspace/8.setup_trans_ignored/latest

Test location	/workspace/coverage/default/8.usbdev_av_buffer.901246420
Short name	T291
Test name
Test status
Simulation time	8383624291 ps
CPU time	9 seconds
Started	Feb 18 12:53:55 PM PST 24
Finished	Feb 18 12:54:12 PM PST 24
Peak memory	201928 kb
Host	smart-e5dd7ec2-d285-4dcf-b6a7-080de4ba7f34
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90124 6420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.901246420
Directory	/workspace/8.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/8.usbdev_nak_trans.2327450562
Short name	T20
Test name
Test status
Simulation time	8448249184 ps
CPU time	7.8 seconds
Started	Feb 18 12:54:05 PM PST 24
Finished	Feb 18 12:54:17 PM PST 24
Peak memory	202004 kb
Host	smart-4beca97f-6362-41da-ab37-5b3355d3cc1b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23274 50562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2327450562
Directory	/workspace/8.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/8.usbdev_pkt_sent.3364349277
Short name	T274
Test name
Test status
Simulation time	8387585698 ps
CPU time	7.95 seconds
Started	Feb 18 12:53:59 PM PST 24
Finished	Feb 18 12:54:14 PM PST 24
Peak memory	201976 kb
Host	smart-50c69db5-d44c-4404-8c34-06afb4c940ab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33643 49277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3364349277
Directory	/workspace/8.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/8.usbdev_smoke.1237823690
Short name	T286
Test name
Test status
Simulation time	8372614461 ps
CPU time	8.45 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:26 PM PST 24
Peak memory	201896 kb
Host	smart-fd77aec1-4bc5-446c-8f89-6758b7af3e80
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378 23690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1237823690
Directory	/workspace/8.usbdev_smoke/latest

Test location	/workspace/coverage/default/9.in_trans.1884883448
Short name	T209
Test name
Test status
Simulation time	8455733867 ps
CPU time	8.01 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:26 PM PST 24
Peak memory	202024 kb
Host	smart-bc8b5326-51fd-4ec4-b715-7af529e41684
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18848 83448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.in_trans.1884883448
Directory	/workspace/9.in_trans/latest

Test location	/workspace/coverage/default/9.setup_trans_ignored.1682992266
Short name	T205
Test name
Test status
Simulation time	8361264191 ps
CPU time	9.79 seconds
Started	Feb 18 12:54:14 PM PST 24
Finished	Feb 18 12:54:29 PM PST 24
Peak memory	202024 kb
Host	smart-c458765f-000d-4d45-80c2-dafb9e9ea276
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16829 92266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.setup_trans_ignored.1682992266
Directory	/workspace/9.setup_trans_ignored/latest

Test location	/workspace/coverage/default/9.usbdev_av_buffer.187521776
Short name	T273
Test name
Test status
Simulation time	8378866171 ps
CPU time	7.74 seconds
Started	Feb 18 12:54:11 PM PST 24
Finished	Feb 18 12:54:24 PM PST 24
Peak memory	202024 kb
Host	smart-723c5e01-e906-4898-a543-98a49db7e4d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18752 1776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.187521776
Directory	/workspace/9.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/9.usbdev_nak_trans.3092924636
Short name	T260
Test name
Test status
Simulation time	8422180235 ps
CPU time	7.73 seconds
Started	Feb 18 12:54:18 PM PST 24
Finished	Feb 18 12:54:31 PM PST 24
Peak memory	202032 kb
Host	smart-0655fd4a-2418-4e05-9497-538d919c0342
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929 24636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3092924636
Directory	/workspace/9.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/9.usbdev_pkt_sent.1853930698
Short name	T94
Test name
Test status
Simulation time	8412843791 ps
CPU time	7.89 seconds
Started	Feb 18 12:54:11 PM PST 24
Finished	Feb 18 12:54:25 PM PST 24
Peak memory	202020 kb
Host	smart-98eccc83-6f5b-447f-b275-712a56141ad2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18539 30698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1853930698
Directory	/workspace/9.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/9.usbdev_smoke.2199458882
Short name	T223
Test name
Test status
Simulation time	8367184529 ps
CPU time	7.2 seconds
Started	Feb 18 12:54:12 PM PST 24
Finished	Feb 18 12:54:25 PM PST 24
Peak memory	202000 kb
Host	smart-97eafc90-156f-4d56-9b31-8b850159f7e8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21994 58882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2199458882
Directory	/workspace/9.usbdev_smoke/latest