Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
45.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	51	21	29.17

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	51	21	29.17	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	635	1		T1	2		T2	2		T3	2
all_pins[1]	635	1		T1	2		T2	2		T3	2
all_pins[2]	635	1		T1	2		T2	2		T3	2
all_pins[3]	635	1		T1	2		T2	2		T3	2
all_pins[4]	635	1		T1	2		T2	2		T3	2
all_pins[5]	635	1		T1	2		T2	2		T3	2
all_pins[6]	635	1		T1	2		T2	2		T3	2
all_pins[7]	635	1		T1	2		T2	2		T3	2
all_pins[8]	635	1		T1	2		T2	2		T3	2
all_pins[9]	635	1		T1	2		T2	2		T3	2
all_pins[10]	635	1		T1	2		T2	2		T3	2
all_pins[11]	635	1		T1	2		T2	2		T3	2
all_pins[12]	635	1		T1	2		T2	2		T3	2
all_pins[13]	635	1		T1	2		T2	2		T3	2
all_pins[14]	635	1		T1	2		T2	2		T3	2
all_pins[15]	635	1		T1	2		T2	2		T3	2
all_pins[16]	635	1		T1	2		T2	2		T3	2
all_pins[17]	635	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11336	1		T1	36		T2	36		T3	36
values[0x1]	94	1		T8	1		T11	1		T12	1
transitions[0x0=>0x1]	94	1		T8	1		T11	1		T12	1
transitions[0x1=>0x0]	94	1		T8	1		T11	1		T12	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	51	21	29.17	51

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[0]]	[values[0x1] , transitions[0x0=>0x1]]	--	--	2
[all_pins[1]]	[transitions[0x1=>0x0]]	0	1	1
[all_pins[2] , all_pins[3] , all_pins[4] , all_pins[5] , all_pins[6] , all_pins[7] , all_pins[8] , all_pins[9] , all_pins[10] , all_pins[11] , all_pins[12] , all_pins[13] , all_pins[14] , all_pins[15] , all_pins[16] , all_pins[17]]	[values[0x1] , transitions[0x0=>0x1] , transitions[0x1=>0x0]]	--	--	48

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	94	1		T8	1		T11	1		T12	1
all_pins[1]	values[0x0]	541	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	94	1		T8	1		T11	1		T12	1
all_pins[1]	transitions[0x0=>0x1]	94	1		T8	1		T11	1		T12	1
all_pins[2]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[11]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x0]	635	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x0]	635	1		T1	2		T2	2		T3	2