| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 81.23 | 95.98 | 85.41 | 96.72 | 45.31 | 93.76 | 97.36 | 54.05 |
| T319 | /workspace/coverage/default/28.usbdev_pkt_sent.2467397743 | Feb 21 02:33:56 PM PST 24 | Feb 21 02:34:06 PM PST 24 | 8430930082 ps | ||
| T320 | /workspace/coverage/default/13.usbdev_nak_trans.927433127 | Feb 21 02:33:08 PM PST 24 | Feb 21 02:33:17 PM PST 24 | 8404661286 ps | ||
| T321 | /workspace/coverage/default/39.setup_trans_ignored.1394294797 | Feb 21 02:34:56 PM PST 24 | Feb 21 02:35:06 PM PST 24 | 8358943696 ps | ||
| T74 | /workspace/coverage/default/4.usbdev_nak_trans.1687260843 | Feb 21 02:32:27 PM PST 24 | Feb 21 02:32:35 PM PST 24 | 8445511203 ps | ||
| T322 | /workspace/coverage/default/29.usbdev_nak_trans.2467660551 | Feb 21 02:34:19 PM PST 24 | Feb 21 02:34:27 PM PST 24 | 8430803440 ps | ||
| T199 | /workspace/coverage/default/24.in_trans.1631492768 | Feb 21 02:33:55 PM PST 24 | Feb 21 02:34:02 PM PST 24 | 8423437937 ps | ||
| T323 | /workspace/coverage/default/17.setup_trans_ignored.877459807 | Feb 21 02:33:27 PM PST 24 | Feb 21 02:33:35 PM PST 24 | 8387206897 ps | ||
| T245 | /workspace/coverage/default/17.in_trans.2413659422 | Feb 21 02:33:26 PM PST 24 | Feb 21 02:33:35 PM PST 24 | 8413851232 ps | ||
| T324 | /workspace/coverage/default/47.usbdev_smoke.1169536469 | Feb 21 02:35:15 PM PST 24 | Feb 21 02:35:27 PM PST 24 | 8372332728 ps | ||
| T205 | /workspace/coverage/default/9.in_trans.3136730368 | Feb 21 02:32:50 PM PST 24 | Feb 21 02:32:57 PM PST 24 | 8373966728 ps | ||
| T152 | /workspace/coverage/default/27.usbdev_pkt_sent.2449408868 | Feb 21 02:34:04 PM PST 24 | Feb 21 02:34:11 PM PST 24 | 8437624221 ps | ||
| T325 | /workspace/coverage/default/46.in_trans.955954217 | Feb 21 02:35:01 PM PST 24 | Feb 21 02:35:12 PM PST 24 | 8392781291 ps | ||
| T326 | /workspace/coverage/default/10.usbdev_smoke.2982115285 | Feb 21 02:32:54 PM PST 24 | Feb 21 02:33:01 PM PST 24 | 8371364372 ps | ||
| T225 | /workspace/coverage/default/22.usbdev_nak_trans.672963172 | Feb 21 02:33:51 PM PST 24 | Feb 21 02:33:58 PM PST 24 | 8404330664 ps | ||
| T327 | /workspace/coverage/default/2.setup_trans_ignored.3773265496 | Feb 21 02:32:18 PM PST 24 | Feb 21 02:32:27 PM PST 24 | 8361090447 ps | ||
| T328 | /workspace/coverage/default/38.setup_trans_ignored.2319126466 | Feb 21 02:34:49 PM PST 24 | Feb 21 02:35:01 PM PST 24 | 8358390888 ps | ||
| T329 | /workspace/coverage/default/13.usbdev_pkt_sent.655448774 | Feb 21 02:33:09 PM PST 24 | Feb 21 02:33:18 PM PST 24 | 8399359240 ps | ||
| T220 | /workspace/coverage/default/41.in_trans.3897624859 | Feb 21 02:35:01 PM PST 24 | Feb 21 02:35:13 PM PST 24 | 8402574723 ps | ||
| T330 | /workspace/coverage/default/27.usbdev_smoke.2266589460 | Feb 21 02:33:54 PM PST 24 | Feb 21 02:34:02 PM PST 24 | 8372113713 ps | ||
| T331 | /workspace/coverage/default/40.usbdev_av_buffer.3450867849 | Feb 21 02:34:57 PM PST 24 | Feb 21 02:35:09 PM PST 24 | 8368808973 ps | ||
| T332 | /workspace/coverage/default/34.setup_trans_ignored.3094471486 | Feb 21 02:34:54 PM PST 24 | Feb 21 02:35:07 PM PST 24 | 8360832464 ps | ||
| T79 | /workspace/coverage/default/11.usbdev_nak_trans.2332332121 | Feb 21 02:33:03 PM PST 24 | Feb 21 02:33:11 PM PST 24 | 8419614627 ps | ||
| T333 | /workspace/coverage/default/12.usbdev_smoke.4133882088 | Feb 21 02:33:01 PM PST 24 | Feb 21 02:33:10 PM PST 24 | 8395245505 ps | ||
| T334 | /workspace/coverage/default/16.usbdev_smoke.2660372447 | Feb 21 02:33:27 PM PST 24 | Feb 21 02:33:35 PM PST 24 | 8369896035 ps | ||
| T335 | /workspace/coverage/default/21.usbdev_pkt_sent.379465151 | Feb 21 02:33:47 PM PST 24 | Feb 21 02:33:56 PM PST 24 | 8431550381 ps | ||
| T336 | /workspace/coverage/default/42.usbdev_smoke.2261890137 | Feb 21 02:34:55 PM PST 24 | Feb 21 02:35:06 PM PST 24 | 8396064967 ps | ||
| T337 | /workspace/coverage/default/6.setup_trans_ignored.2761999746 | Feb 21 02:32:47 PM PST 24 | Feb 21 02:32:56 PM PST 24 | 8375497637 ps | ||
| T144 | /workspace/coverage/default/35.setup_trans_ignored.1398581055 | Feb 21 02:35:01 PM PST 24 | Feb 21 02:35:12 PM PST 24 | 8359767399 ps | ||
| T338 | /workspace/coverage/default/32.usbdev_nak_trans.3566973066 | Feb 21 02:34:47 PM PST 24 | Feb 21 02:34:59 PM PST 24 | 8404098325 ps | ||
| T206 | /workspace/coverage/default/7.usbdev_pkt_sent.1752181263 | Feb 21 02:32:45 PM PST 24 | Feb 21 02:32:53 PM PST 24 | 8432656146 ps | ||
| T76 | /workspace/coverage/default/7.usbdev_nak_trans.1655395924 | Feb 21 02:32:43 PM PST 24 | Feb 21 02:32:50 PM PST 24 | 8443465858 ps | ||
| T339 | /workspace/coverage/default/48.usbdev_pkt_sent.649074640 | Feb 21 02:35:39 PM PST 24 | Feb 21 02:35:47 PM PST 24 | 8379021160 ps | ||
| T340 | /workspace/coverage/default/0.usbdev_nak_trans.865372338 | Feb 21 02:31:58 PM PST 24 | Feb 21 02:32:08 PM PST 24 | 8485480373 ps | ||
| T341 | /workspace/coverage/default/45.usbdev_av_buffer.2697022492 | Feb 21 02:34:57 PM PST 24 | Feb 21 02:35:07 PM PST 24 | 8366234259 ps | ||
| T342 | /workspace/coverage/default/20.setup_trans_ignored.1798552794 | Feb 21 02:33:37 PM PST 24 | Feb 21 02:33:45 PM PST 24 | 8366401046 ps | ||
| T343 | /workspace/coverage/default/39.in_trans.500981401 | Feb 21 02:34:55 PM PST 24 | Feb 21 02:35:07 PM PST 24 | 8449065955 ps | ||
| T344 | /workspace/coverage/default/44.usbdev_nak_trans.979746386 | Feb 21 02:35:13 PM PST 24 | Feb 21 02:35:25 PM PST 24 | 8398623598 ps | ||
| T345 | /workspace/coverage/default/14.setup_trans_ignored.2112863586 | Feb 21 02:33:24 PM PST 24 | Feb 21 02:33:33 PM PST 24 | 8354207476 ps | ||
| T346 | /workspace/coverage/default/47.in_trans.54922892 | Feb 21 02:35:08 PM PST 24 | Feb 21 02:35:16 PM PST 24 | 8406909199 ps | ||
| T165 | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.503763105 | Feb 21 12:35:26 PM PST 24 | Feb 21 12:35:29 PM PST 24 | 255787052 ps | ||
| T41 | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1489067758 | Feb 21 12:35:57 PM PST 24 | Feb 21 12:36:00 PM PST 24 | 254060366 ps | ||
| T48 | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.143482833 | Feb 21 12:36:23 PM PST 24 | Feb 21 12:36:25 PM PST 24 | 61192101 ps | ||
| T52 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2411137299 | Feb 21 12:35:32 PM PST 24 | Feb 21 12:35:33 PM PST 24 | 25821121 ps | ||
| T42 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.952868774 | Feb 21 12:35:29 PM PST 24 | Feb 21 12:35:32 PM PST 24 | 110611294 ps | ||
| T43 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1957782974 | Feb 21 12:35:31 PM PST 24 | Feb 21 12:35:33 PM PST 24 | 182974436 ps | ||
| T49 | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.207009041 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:43 PM PST 24 | 334197601 ps | ||
| T50 | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1355203646 | Feb 21 12:35:43 PM PST 24 | Feb 21 12:35:44 PM PST 24 | 40518448 ps | ||
| T122 | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2057682074 | Feb 21 12:35:54 PM PST 24 | Feb 21 12:35:56 PM PST 24 | 39883152 ps | ||
| T123 | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.242640893 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:41 PM PST 24 | 73683200 ps | ||
| T110 | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.320000611 | Feb 21 12:35:53 PM PST 24 | Feb 21 12:35:54 PM PST 24 | 39664986 ps | ||
| T111 | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.900371931 | Feb 21 12:35:41 PM PST 24 | Feb 21 12:35:43 PM PST 24 | 70023872 ps | ||
| T112 | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2769849289 | Feb 21 12:36:23 PM PST 24 | Feb 21 12:36:27 PM PST 24 | 250994816 ps | ||
| T113 | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3495094767 | Feb 21 12:35:46 PM PST 24 | Feb 21 12:35:51 PM PST 24 | 386486871 ps | ||
| T347 | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1043225535 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:42 PM PST 24 | 149715595 ps | ||
| T124 | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2518101642 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:41 PM PST 24 | 161775603 ps | ||
| T114 | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2974957770 | Feb 21 12:35:35 PM PST 24 | Feb 21 12:35:36 PM PST 24 | 57374088 ps | ||
| T51 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3717417988 | Feb 21 12:35:39 PM PST 24 | Feb 21 12:35:40 PM PST 24 | 60699705 ps | ||
| T45 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.943404983 | Feb 21 12:35:52 PM PST 24 | Feb 21 12:35:53 PM PST 24 | 40504036 ps | ||
| T136 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3674860827 | Feb 21 12:35:56 PM PST 24 | Feb 21 12:35:59 PM PST 24 | 314548121 ps | ||
| T115 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4190326918 | Feb 21 12:35:44 PM PST 24 | Feb 21 12:35:52 PM PST 24 | 257401053 ps | ||
| T125 | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.403170036 | Feb 21 12:35:32 PM PST 24 | Feb 21 12:35:34 PM PST 24 | 41344055 ps | ||
| T132 | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2912081477 | Feb 21 12:35:41 PM PST 24 | Feb 21 12:35:42 PM PST 24 | 52889163 ps | ||
| T116 | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3361693636 | Feb 21 12:36:11 PM PST 24 | Feb 21 12:36:13 PM PST 24 | 135052615 ps | ||
| T348 | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.433853189 | Feb 21 12:35:36 PM PST 24 | Feb 21 12:35:40 PM PST 24 | 148324128 ps | ||
| T117 | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4217211164 | Feb 21 12:35:48 PM PST 24 | Feb 21 12:35:50 PM PST 24 | 121711186 ps | ||
| T118 | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4205853757 | Feb 21 12:35:30 PM PST 24 | Feb 21 12:35:33 PM PST 24 | 209755588 ps | ||
| T169 | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1593026252 | Feb 21 12:35:56 PM PST 24 | Feb 21 12:35:59 PM PST 24 | 266024686 ps | ||
| T126 | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.293627297 | Feb 21 12:35:42 PM PST 24 | Feb 21 12:35:43 PM PST 24 | 60361248 ps | ||
| T119 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1946646737 | Feb 21 12:35:50 PM PST 24 | Feb 21 12:35:54 PM PST 24 | 231675189 ps | ||
| T120 | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2490422422 | Feb 21 12:35:53 PM PST 24 | Feb 21 12:35:56 PM PST 24 | 156250138 ps | ||
| T121 | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4161936230 | Feb 21 12:35:33 PM PST 24 | Feb 21 12:35:36 PM PST 24 | 255762365 ps | ||
| T46 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2366788644 | Feb 21 12:35:37 PM PST 24 | Feb 21 12:35:38 PM PST 24 | 54265958 ps | ||
| T157 | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1647485248 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:47 PM PST 24 | 54974389 ps | ||
| T166 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2209432427 | Feb 21 12:35:42 PM PST 24 | Feb 21 12:35:45 PM PST 24 | 275771685 ps | ||
| T133 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1594047803 | Feb 21 12:35:44 PM PST 24 | Feb 21 12:35:46 PM PST 24 | 137972788 ps | ||
| T349 | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1354136356 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:49 PM PST 24 | 110845117 ps | ||
| T127 | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3516852556 | Feb 21 12:35:40 PM PST 24 | Feb 21 12:35:42 PM PST 24 | 175808973 ps | ||
| T350 | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.518612008 | Feb 21 12:35:37 PM PST 24 | Feb 21 12:35:39 PM PST 24 | 248850183 ps | ||
| T351 | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.843114886 | Feb 21 12:35:43 PM PST 24 | Feb 21 12:35:46 PM PST 24 | 84681062 ps | ||
| T352 | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.211298910 | Feb 21 12:35:53 PM PST 24 | Feb 21 12:35:55 PM PST 24 | 59826891 ps | ||
| T162 | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1371860624 | Feb 21 12:36:19 PM PST 24 | Feb 21 12:36:21 PM PST 24 | 56488694 ps | ||
| T353 | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3400213869 | Feb 21 12:35:58 PM PST 24 | Feb 21 12:36:00 PM PST 24 | 40328969 ps | ||
| T168 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1076209906 | Feb 21 12:35:19 PM PST 24 | Feb 21 12:35:22 PM PST 24 | 281843577 ps | ||
| T354 | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2681809626 | Feb 21 12:36:16 PM PST 24 | Feb 21 12:36:18 PM PST 24 | 66037597 ps | ||
| T171 | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1225362497 | Feb 21 12:35:44 PM PST 24 | Feb 21 12:35:51 PM PST 24 | 129907316 ps | ||
| T128 | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3764139849 | Feb 21 12:35:54 PM PST 24 | Feb 21 12:35:55 PM PST 24 | 46538134 ps | ||
| T355 | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3155619839 | Feb 21 12:35:55 PM PST 24 | Feb 21 12:35:56 PM PST 24 | 38924769 ps | ||
| T356 | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3201021035 | Feb 21 12:35:32 PM PST 24 | Feb 21 12:35:33 PM PST 24 | 33259538 ps | ||
| T357 | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.26447800 | Feb 21 12:35:37 PM PST 24 | Feb 21 12:35:38 PM PST 24 | 68106250 ps | ||
| T167 | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1522809915 | Feb 21 12:35:46 PM PST 24 | Feb 21 12:35:47 PM PST 24 | 80367977 ps | ||
| T129 | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2670904576 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:42 PM PST 24 | 122166214 ps | ||
| T358 | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3609395998 | Feb 21 12:35:28 PM PST 24 | Feb 21 12:35:29 PM PST 24 | 37378487 ps | ||
| T164 | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2248858802 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:41 PM PST 24 | 253651905 ps | ||
| T359 | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3818534801 | Feb 21 12:35:31 PM PST 24 | Feb 21 12:35:34 PM PST 24 | 116834775 ps | ||
| T360 | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4159182644 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:40 PM PST 24 | 131782983 ps | ||
| T156 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2650657613 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:47 PM PST 24 | 93505935 ps | ||
| T158 | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3355030798 | Feb 21 12:35:39 PM PST 24 | Feb 21 12:35:41 PM PST 24 | 176822657 ps | ||
| T160 | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3443084703 | Feb 21 12:36:02 PM PST 24 | Feb 21 12:36:09 PM PST 24 | 405400027 ps | ||
| T163 | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3691899708 | Feb 21 12:35:55 PM PST 24 | Feb 21 12:35:58 PM PST 24 | 260334775 ps | ||
| T161 | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.510483291 | Feb 21 12:35:43 PM PST 24 | Feb 21 12:35:45 PM PST 24 | 148476428 ps | ||
| T361 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.627092118 | Feb 21 12:35:39 PM PST 24 | Feb 21 12:35:42 PM PST 24 | 375627576 ps | ||
| T362 | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1665509139 | Feb 21 12:35:50 PM PST 24 | Feb 21 12:35:56 PM PST 24 | 415286990 ps | ||
| T159 | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1043749096 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:46 PM PST 24 | 86508340 ps | ||
| T154 | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2430003211 | Feb 21 12:35:37 PM PST 24 | Feb 21 12:35:40 PM PST 24 | 78230570 ps | ||
| T170 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2953461763 | Feb 21 12:35:41 PM PST 24 | Feb 21 12:35:45 PM PST 24 | 315051221 ps | ||
| T172 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3499913745 | Feb 21 12:35:46 PM PST 24 | Feb 21 12:35:49 PM PST 24 | 314426273 ps | ||
| T363 | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2810654064 | Feb 21 12:35:20 PM PST 24 | Feb 21 12:35:22 PM PST 24 | 211364877 ps | ||
| T130 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1261359129 | Feb 21 12:35:27 PM PST 24 | Feb 21 12:35:29 PM PST 24 | 150177432 ps | ||
| T131 | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3395826857 | Feb 21 12:35:36 PM PST 24 | Feb 21 12:35:38 PM PST 24 | 55446240 ps | ||
| T364 | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2760863185 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:46 PM PST 24 | 108880259 ps | ||
| T365 | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3629285221 | Feb 21 12:35:48 PM PST 24 | Feb 21 12:35:50 PM PST 24 | 68265384 ps | ||
| T366 | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2449008384 | Feb 21 12:35:37 PM PST 24 | Feb 21 12:35:40 PM PST 24 | 87996024 ps | ||
| T367 | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3347975373 | Feb 21 12:35:39 PM PST 24 | Feb 21 12:35:40 PM PST 24 | 79229173 ps | ||
| T368 | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4274126140 | Feb 21 12:35:34 PM PST 24 | Feb 21 12:35:36 PM PST 24 | 179474714 ps | ||
| T369 | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2979889201 | Feb 21 12:35:41 PM PST 24 | Feb 21 12:35:42 PM PST 24 | 48085154 ps | ||
| T370 | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2908140364 | Feb 21 12:35:31 PM PST 24 | Feb 21 12:35:32 PM PST 24 | 64085824 ps | ||
| T371 | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3074159731 | Feb 21 12:35:39 PM PST 24 | Feb 21 12:35:41 PM PST 24 | 45503090 ps | ||
| T372 | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2225714133 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:46 PM PST 24 | 36524880 ps | ||
| T373 | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1896046359 | Feb 21 12:35:52 PM PST 24 | Feb 21 12:35:54 PM PST 24 | 33238391 ps | ||
| T374 | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3580498961 | Feb 21 12:35:40 PM PST 24 | Feb 21 12:35:43 PM PST 24 | 109688302 ps | ||
| T375 | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.328097525 | Feb 21 12:35:53 PM PST 24 | Feb 21 12:35:54 PM PST 24 | 77528108 ps | ||
| T376 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4272113354 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:49 PM PST 24 | 344530645 ps | ||
| T377 | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3497384217 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:41 PM PST 24 | 88944872 ps | ||
| T378 | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1064043172 | Feb 21 12:35:43 PM PST 24 | Feb 21 12:35:45 PM PST 24 | 73480807 ps | ||
| T379 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4195708330 | Feb 21 12:35:30 PM PST 24 | Feb 21 12:35:38 PM PST 24 | 359712549 ps | ||
| T155 | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3808743303 | Feb 21 12:35:40 PM PST 24 | Feb 21 12:35:42 PM PST 24 | 142243539 ps | ||
| T380 | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3222902581 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:49 PM PST 24 | 277979050 ps | ||
| T381 | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.868570936 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:47 PM PST 24 | 108927226 ps | ||
| T382 | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3023768729 | Feb 21 12:36:28 PM PST 24 | Feb 21 12:36:32 PM PST 24 | 111071506 ps | ||
| T173 | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4102563612 | Feb 21 12:35:58 PM PST 24 | Feb 21 12:36:01 PM PST 24 | 175351977 ps | ||
| T383 | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4141872609 | Feb 21 12:35:29 PM PST 24 | Feb 21 12:35:31 PM PST 24 | 53802639 ps | ||
| T384 | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3832924082 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:41 PM PST 24 | 131432171 ps | ||
| T385 | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3703847257 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:48 PM PST 24 | 253384153 ps | ||
| T386 | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3649503125 | Feb 21 12:35:56 PM PST 24 | Feb 21 12:35:57 PM PST 24 | 57152409 ps | ||
| T387 | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.560141856 | Feb 21 12:35:44 PM PST 24 | Feb 21 12:35:50 PM PST 24 | 37495120 ps | ||
| T388 | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.669000929 | Feb 21 12:35:49 PM PST 24 | Feb 21 12:35:51 PM PST 24 | 91845041 ps | ||
| T389 | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4001752697 | Feb 21 12:35:50 PM PST 24 | Feb 21 12:35:52 PM PST 24 | 47017498 ps | ||
| T390 | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3060301545 | Feb 21 12:35:38 PM PST 24 | Feb 21 12:35:39 PM PST 24 | 78414000 ps | ||
| T391 | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2694838770 | Feb 21 12:36:08 PM PST 24 | Feb 21 12:36:10 PM PST 24 | 67840514 ps | ||
| T392 | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3639536949 | Feb 21 12:35:46 PM PST 24 | Feb 21 12:35:51 PM PST 24 | 438224406 ps | ||
| T393 | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2838790785 | Feb 21 12:35:44 PM PST 24 | Feb 21 12:35:45 PM PST 24 | 30543294 ps | ||
| T394 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3496967383 | Feb 21 12:35:40 PM PST 24 | Feb 21 12:35:44 PM PST 24 | 364269877 ps | ||
| T395 | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4236613971 | Feb 21 12:35:54 PM PST 24 | Feb 21 12:35:56 PM PST 24 | 67852075 ps | ||
| T396 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2963480835 | Feb 21 12:35:43 PM PST 24 | Feb 21 12:35:46 PM PST 24 | 84467016 ps | ||
| T397 | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.598457040 | Feb 21 12:35:44 PM PST 24 | Feb 21 12:35:46 PM PST 24 | 146445505 ps | ||
| T47 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2626804312 | Feb 21 12:35:33 PM PST 24 | Feb 21 12:35:34 PM PST 24 | 50701605 ps | ||
| T398 | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3492961462 | Feb 21 12:35:30 PM PST 24 | Feb 21 12:35:31 PM PST 24 | 36313245 ps | ||
| T399 | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4190691253 | Feb 21 12:35:32 PM PST 24 | Feb 21 12:35:35 PM PST 24 | 185269817 ps | ||
| T400 | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2032948061 | Feb 21 12:35:57 PM PST 24 | Feb 21 12:35:59 PM PST 24 | 66771383 ps | ||
| T401 | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.198622824 | Feb 21 12:35:45 PM PST 24 | Feb 21 12:35:48 PM PST 24 | 86903617 ps | ||
| T402 | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.489245137 | Feb 21 12:35:54 PM PST 24 | Feb 21 12:36:01 PM PST 24 | 138239076 ps | ||
| T174 | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4092679193 | Feb 21 12:35:44 PM PST 24 | Feb 21 12:35:47 PM PST 24 | 291656113 ps |
| Test location | /workspace/coverage/default/44.usbdev_pkt_sent.3083938358 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8431417785 ps |
| CPU time | 7.17 seconds |
| Started | Feb 21 02:35:02 PM PST 24 |
| Finished | Feb 21 02:35:11 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-2eed5248-231c-4f00-a327-93ab03eecf6b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30839 38358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3083938358 |
| Directory | /workspace/44.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1489067758 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 254060366 ps |
| CPU time | 2.81 seconds |
| Started | Feb 21 12:35:57 PM PST 24 |
| Finished | Feb 21 12:36:00 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-f481280a-6bfb-4ae8-b5a7-cdc864aa6da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1489067758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1489067758 |
| Directory | /workspace/3.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.usbdev_smoke.3851478755 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8374989416 ps |
| CPU time | 7.1 seconds |
| Started | Feb 21 02:32:04 PM PST 24 |
| Finished | Feb 21 02:32:12 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-28fa5c5c-7829-47b0-95b0-eaf95e6cd3c6 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38514 78755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3851478755 |
| Directory | /workspace/0.usbdev_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.952868774 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 110611294 ps |
| CPU time | 3.17 seconds |
| Started | Feb 21 12:35:29 PM PST 24 |
| Finished | Feb 21 12:35:32 PM PST 24 |
| Peak memory | 202340 kb |
| Host | smart-32ca8a4e-aba4-4202-9945-27e4c3562fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=952868774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.952868774 |
| Directory | /workspace/4.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/default/3.usbdev_sec_cm.46968731 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 209770954 ps |
| CPU time | 1.09 seconds |
| Started | Feb 21 02:32:28 PM PST 24 |
| Finished | Feb 21 02:32:30 PM PST 24 |
| Peak memory | 217560 kb |
| Host | smart-8a9e93c8-77ad-4fae-ad2b-dc02c39740c3 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=46968731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.46968731 |
| Directory | /workspace/3.usbdev_sec_cm/latest |
| Test location | /workspace/coverage/default/18.usbdev_av_buffer.127252254 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8374364000 ps |
| CPU time | 7.19 seconds |
| Started | Feb 21 02:33:26 PM PST 24 |
| Finished | Feb 21 02:33:34 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-8f7bef78-f3f9-47eb-85b0-ee469372892e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12725 2254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.127252254 |
| Directory | /workspace/18.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2366788644 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 54265958 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:35:37 PM PST 24 |
| Finished | Feb 21 12:35:38 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-330cae06-5b8a-45e7-9f32-4b73aea1b78b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366788644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2366788644 |
| Directory | /workspace/2.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/48.usbdev_nak_trans.40092774 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 8424635151 ps |
| CPU time | 8.71 seconds |
| Started | Feb 21 02:35:27 PM PST 24 |
| Finished | Feb 21 02:35:37 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-c8ec0514-d062-4ca1-994b-3132b41aa858 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40092 774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.40092774 |
| Directory | /workspace/48.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3717417988 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 60699705 ps |
| CPU time | 0.8 seconds |
| Started | Feb 21 12:35:39 PM PST 24 |
| Finished | Feb 21 12:35:40 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-8d3eb619-27cd-48b9-bc88-f10944c09b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717417988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3717417988 |
| Directory | /workspace/1.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.503763105 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 255787052 ps |
| CPU time | 2.4 seconds |
| Started | Feb 21 12:35:26 PM PST 24 |
| Finished | Feb 21 12:35:29 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-6b15600d-404a-4824-8f97-d1397b54067d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=503763105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.503763105 |
| Directory | /workspace/1.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/default/9.usbdev_pkt_sent.1609015583 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 8386351728 ps |
| CPU time | 8.88 seconds |
| Started | Feb 21 02:32:49 PM PST 24 |
| Finished | Feb 21 02:32:58 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-15527a93-3b9e-4232-be4b-a96f3f5fd1a3 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16090 15583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1609015583 |
| Directory | /workspace/9.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/1.in_trans.918908257 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8453995348 ps |
| CPU time | 7.99 seconds |
| Started | Feb 21 02:32:12 PM PST 24 |
| Finished | Feb 21 02:32:21 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-e0f48c83-851e-498c-a7dd-9695b297a2fb |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91890 8257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.in_trans.918908257 |
| Directory | /workspace/1.in_trans/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2626804312 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 50701605 ps |
| CPU time | 0.85 seconds |
| Started | Feb 21 12:35:33 PM PST 24 |
| Finished | Feb 21 12:35:34 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-0060887a-31f7-4938-9838-9a4a3b8fed90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626804312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2626804312 |
| Directory | /workspace/0.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4092679193 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 291656113 ps |
| CPU time | 2.48 seconds |
| Started | Feb 21 12:35:44 PM PST 24 |
| Finished | Feb 21 12:35:47 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-648fdf8a-3054-41aa-9ea5-07fe0b42e6f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4092679193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.4092679193 |
| Directory | /workspace/16.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2974957770 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 57374088 ps |
| CPU time | 0.95 seconds |
| Started | Feb 21 12:35:35 PM PST 24 |
| Finished | Feb 21 12:35:36 PM PST 24 |
| Peak memory | 202556 kb |
| Host | smart-3d983ec2-cda0-4bc3-a5bb-16d6396e2e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974957770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2974957770 |
| Directory | /workspace/2.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/default/43.usbdev_pkt_sent.2869794600 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 8398443658 ps |
| CPU time | 7.45 seconds |
| Started | Feb 21 02:34:55 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-dbfee0b7-2b98-4e35-b21e-fdf83c687f2e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28697 94600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2869794600 |
| Directory | /workspace/43.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/40.in_trans.2083360686 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 8417418095 ps |
| CPU time | 7.39 seconds |
| Started | Feb 21 02:35:04 PM PST 24 |
| Finished | Feb 21 02:35:15 PM PST 24 |
| Peak memory | 202124 kb |
| Host | smart-8c018dc4-6013-4a1b-9a59-857f0f9fe532 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20833 60686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.in_trans.2083360686 |
| Directory | /workspace/40.in_trans/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3674860827 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 314548121 ps |
| CPU time | 2.97 seconds |
| Started | Feb 21 12:35:56 PM PST 24 |
| Finished | Feb 21 12:35:59 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-dad57ce3-5f81-4df0-8b1d-77a6df5b917b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3674860827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3674860827 |
| Directory | /workspace/17.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/default/11.usbdev_pkt_sent.2879383749 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8459934976 ps |
| CPU time | 7.13 seconds |
| Started | Feb 21 02:33:03 PM PST 24 |
| Finished | Feb 21 02:33:10 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-eaf21d69-a3aa-47f9-8bf2-c1c781463fb0 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28793 83749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2879383749 |
| Directory | /workspace/11.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3703847257 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 253384153 ps |
| CPU time | 2.75 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:48 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-ee890f0d-2d85-46ee-867e-6383cf460571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3703847257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3703847257 |
| Directory | /workspace/13.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/default/28.in_trans.1868506638 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 8404209944 ps |
| CPU time | 8.26 seconds |
| Started | Feb 21 02:34:17 PM PST 24 |
| Finished | Feb 21 02:34:25 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-8b82fee6-b9cd-4db1-bf59-0b029ad2803d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685 06638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.in_trans.1868506638 |
| Directory | /workspace/28.in_trans/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2411137299 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 25821121 ps |
| CPU time | 0.71 seconds |
| Started | Feb 21 12:35:32 PM PST 24 |
| Finished | Feb 21 12:35:33 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-ae495339-7da9-4691-9928-dfd68e359b93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411137299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2411137299 |
| Directory | /workspace/3.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2953461763 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 315051221 ps |
| CPU time | 3.05 seconds |
| Started | Feb 21 12:35:41 PM PST 24 |
| Finished | Feb 21 12:35:45 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-d439e1a7-d4ab-489b-aabb-3db50b436e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2953461763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2953461763 |
| Directory | /workspace/10.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1225362497 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 129907316 ps |
| CPU time | 2.49 seconds |
| Started | Feb 21 12:35:44 PM PST 24 |
| Finished | Feb 21 12:35:51 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-12247f67-a6bd-4397-8a7e-987835b3a9d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1225362497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1225362497 |
| Directory | /workspace/4.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3499913745 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 314426273 ps |
| CPU time | 2.61 seconds |
| Started | Feb 21 12:35:46 PM PST 24 |
| Finished | Feb 21 12:35:49 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-656dfd86-0f60-48db-9b87-a6a18a413996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3499913745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3499913745 |
| Directory | /workspace/6.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/default/23.in_trans.3662365862 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 8446965207 ps |
| CPU time | 8.4 seconds |
| Started | Feb 21 02:33:43 PM PST 24 |
| Finished | Feb 21 02:33:52 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-4defcd51-6a1a-4e99-be99-33a9ac9d3607 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36623 65862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.in_trans.3662365862 |
| Directory | /workspace/23.in_trans/latest |
| Test location | /workspace/coverage/default/10.in_trans.2547261175 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 8415107841 ps |
| CPU time | 7.69 seconds |
| Started | Feb 21 02:33:02 PM PST 24 |
| Finished | Feb 21 02:33:10 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-9b271811-71e7-4d08-a5c6-8896a835ca50 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25472 61175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.in_trans.2547261175 |
| Directory | /workspace/10.in_trans/latest |
| Test location | /workspace/coverage/default/13.usbdev_pkt_sent.655448774 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 8399359240 ps |
| CPU time | 8.49 seconds |
| Started | Feb 21 02:33:09 PM PST 24 |
| Finished | Feb 21 02:33:18 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-db2db777-dd5c-4b5c-a2e8-03aa1b1f83cc |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65544 8774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.655448774 |
| Directory | /workspace/13.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/14.usbdev_pkt_sent.1023042176 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 8411366882 ps |
| CPU time | 8.34 seconds |
| Started | Feb 21 02:33:23 PM PST 24 |
| Finished | Feb 21 02:33:33 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-43c9cf90-fc9f-4313-9775-309fde0eaaa1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10230 42176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1023042176 |
| Directory | /workspace/14.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/17.in_trans.2413659422 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 8413851232 ps |
| CPU time | 7.95 seconds |
| Started | Feb 21 02:33:26 PM PST 24 |
| Finished | Feb 21 02:33:35 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-15335053-6e7d-4114-b277-18388c6bb09c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24136 59422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.in_trans.2413659422 |
| Directory | /workspace/17.in_trans/latest |
| Test location | /workspace/coverage/default/31.usbdev_pkt_sent.2345643273 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8462576211 ps |
| CPU time | 7.73 seconds |
| Started | Feb 21 02:34:43 PM PST 24 |
| Finished | Feb 21 02:34:51 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-fdab3124-2ef4-49b5-8d26-15268f63c717 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23456 43273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2345643273 |
| Directory | /workspace/31.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/14.usbdev_nak_trans.457080837 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 8388361675 ps |
| CPU time | 7.2 seconds |
| Started | Feb 21 02:33:19 PM PST 24 |
| Finished | Feb 21 02:33:26 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-6db6e90e-ab09-4802-990a-2c7c6ce3724f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45708 0837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.457080837 |
| Directory | /workspace/14.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1946646737 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 231675189 ps |
| CPU time | 2.89 seconds |
| Started | Feb 21 12:35:50 PM PST 24 |
| Finished | Feb 21 12:35:54 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-410f8ae5-f8e5-492d-a794-309418145819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1946646737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1946646737 |
| Directory | /workspace/0.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1355203646 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 40518448 ps |
| CPU time | 1.07 seconds |
| Started | Feb 21 12:35:43 PM PST 24 |
| Finished | Feb 21 12:35:44 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-05b93ddd-c6c6-4e1d-a124-0ba1ca80df2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355203646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.1355203646 |
| Directory | /workspace/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.usbdev_nak_trans.865372338 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 8485480373 ps |
| CPU time | 9.04 seconds |
| Started | Feb 21 02:31:58 PM PST 24 |
| Finished | Feb 21 02:32:08 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-e60d5cab-0c23-4a1a-8781-be1d2c485724 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86537 2338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.865372338 |
| Directory | /workspace/0.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/1.usbdev_nak_trans.254987240 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 8443367983 ps |
| CPU time | 7.93 seconds |
| Started | Feb 21 02:32:09 PM PST 24 |
| Finished | Feb 21 02:32:18 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-d8b2cf8d-e219-4ee7-bd05-188e68b8ec5d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25498 7240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.254987240 |
| Directory | /workspace/1.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/10.setup_trans_ignored.3092719623 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 8364070398 ps |
| CPU time | 7.71 seconds |
| Started | Feb 21 02:33:03 PM PST 24 |
| Finished | Feb 21 02:33:11 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-ccbd6e06-938d-40fa-b994-a002d3fccbbc |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927 19623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.setup_trans_ignored.3092719623 |
| Directory | /workspace/10.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/10.usbdev_nak_trans.1710374188 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 8460811877 ps |
| CPU time | 8.89 seconds |
| Started | Feb 21 02:33:04 PM PST 24 |
| Finished | Feb 21 02:33:13 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-6e8fa462-ed6f-4779-8462-b6028656f707 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17103 74188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1710374188 |
| Directory | /workspace/10.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/12.usbdev_nak_trans.3348829890 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 8378253348 ps |
| CPU time | 7.3 seconds |
| Started | Feb 21 02:33:12 PM PST 24 |
| Finished | Feb 21 02:33:20 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-fa045149-ce69-4689-b236-a43c5b481b02 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33488 29890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3348829890 |
| Directory | /workspace/12.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/2.usbdev_nak_trans.1298547867 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 8451869554 ps |
| CPU time | 7.4 seconds |
| Started | Feb 21 02:32:21 PM PST 24 |
| Finished | Feb 21 02:32:28 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-f9d8c761-ffb0-401f-8e66-048cac8990b1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12985 47867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1298547867 |
| Directory | /workspace/2.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/21.usbdev_nak_trans.506344627 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 8421618574 ps |
| CPU time | 7.05 seconds |
| Started | Feb 21 02:33:34 PM PST 24 |
| Finished | Feb 21 02:33:42 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-0f2de274-52bf-4dff-b055-0403ca3225c5 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50634 4627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.506344627 |
| Directory | /workspace/21.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/28.usbdev_nak_trans.1832388444 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 8434335224 ps |
| CPU time | 7.91 seconds |
| Started | Feb 21 02:34:02 PM PST 24 |
| Finished | Feb 21 02:34:11 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-30fcd9f4-7d44-42a9-b287-88993e6aa01e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18323 88444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1832388444 |
| Directory | /workspace/28.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/35.usbdev_nak_trans.829324961 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 8410456156 ps |
| CPU time | 7.2 seconds |
| Started | Feb 21 02:35:01 PM PST 24 |
| Finished | Feb 21 02:35:12 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-5a7d69c7-4839-4885-8691-308be53b8171 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82932 4961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.829324961 |
| Directory | /workspace/35.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/36.usbdev_nak_trans.2279410866 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 8416234323 ps |
| CPU time | 7.38 seconds |
| Started | Feb 21 02:34:38 PM PST 24 |
| Finished | Feb 21 02:34:47 PM PST 24 |
| Peak memory | 202116 kb |
| Host | smart-2ded0631-beb5-46d5-8373-a4a41e04a523 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22794 10866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2279410866 |
| Directory | /workspace/36.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/40.usbdev_nak_trans.803637635 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 8453866529 ps |
| CPU time | 7.49 seconds |
| Started | Feb 21 02:35:06 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-393a6ce6-4b6d-4e98-be90-46be818df685 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80363 7635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.803637635 |
| Directory | /workspace/40.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4190691253 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 185269817 ps |
| CPU time | 2.15 seconds |
| Started | Feb 21 12:35:32 PM PST 24 |
| Finished | Feb 21 12:35:35 PM PST 24 |
| Peak memory | 202528 kb |
| Host | smart-d079968f-60b0-4900-b72e-4271c29cf28e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190691253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4190691253 |
| Directory | /workspace/0.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4205853757 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 209755588 ps |
| CPU time | 2.91 seconds |
| Started | Feb 21 12:35:30 PM PST 24 |
| Finished | Feb 21 12:35:33 PM PST 24 |
| Peak memory | 210752 kb |
| Host | smart-885bade9-8222-4a44-a04c-53398b4af53f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205853757 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.4205853757 |
| Directory | /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.560141856 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 37495120 ps |
| CPU time | 0.81 seconds |
| Started | Feb 21 12:35:44 PM PST 24 |
| Finished | Feb 21 12:35:50 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-1ad9ecd0-4735-4531-a26b-9133cf7c5ceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560141856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.560141856 |
| Directory | /workspace/0.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4274126140 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 179474714 ps |
| CPU time | 2.37 seconds |
| Started | Feb 21 12:35:34 PM PST 24 |
| Finished | Feb 21 12:35:36 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-aeaa2d8b-ca73-4b8e-b3b1-9a23f4469881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4274126140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.4274126140 |
| Directory | /workspace/0.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.433853189 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 148324128 ps |
| CPU time | 3.87 seconds |
| Started | Feb 21 12:35:36 PM PST 24 |
| Finished | Feb 21 12:35:40 PM PST 24 |
| Peak memory | 202420 kb |
| Host | smart-cb9f86f7-8186-4741-ac9e-e060d2f71e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=433853189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.433853189 |
| Directory | /workspace/0.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.328097525 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 77528108 ps |
| CPU time | 1.11 seconds |
| Started | Feb 21 12:35:53 PM PST 24 |
| Finished | Feb 21 12:35:54 PM PST 24 |
| Peak memory | 202624 kb |
| Host | smart-dadc04fd-bc0c-4fe4-93e6-57db630fc2be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328097525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_cs r_outstanding.328097525 |
| Directory | /workspace/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.900371931 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 70023872 ps |
| CPU time | 1.92 seconds |
| Started | Feb 21 12:35:41 PM PST 24 |
| Finished | Feb 21 12:35:43 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-09a91560-9524-40ba-b2c8-f3cdfc208455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900371931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.900371931 |
| Directory | /workspace/1.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4195708330 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 359712549 ps |
| CPU time | 8.35 seconds |
| Started | Feb 21 12:35:30 PM PST 24 |
| Finished | Feb 21 12:35:38 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-7481365a-fea5-496a-9c2a-dfdd784d949d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195708330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.4195708330 |
| Directory | /workspace/1.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4217211164 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 121711186 ps |
| CPU time | 1.83 seconds |
| Started | Feb 21 12:35:48 PM PST 24 |
| Finished | Feb 21 12:35:50 PM PST 24 |
| Peak memory | 210796 kb |
| Host | smart-1273c4f8-d6d7-46b1-b079-f7b95d0a599d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217211164 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.4217211164 |
| Directory | /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3395826857 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 55446240 ps |
| CPU time | 0.97 seconds |
| Started | Feb 21 12:35:36 PM PST 24 |
| Finished | Feb 21 12:35:38 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-d57d1f5d-a470-4f70-9770-17a0694ef0a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395826857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3395826857 |
| Directory | /workspace/1.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1261359129 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 150177432 ps |
| CPU time | 2.25 seconds |
| Started | Feb 21 12:35:27 PM PST 24 |
| Finished | Feb 21 12:35:29 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-63cd7a86-e1ee-4df3-97c3-32b9bf26e207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1261359129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1261359129 |
| Directory | /workspace/1.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2908140364 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 64085824 ps |
| CPU time | 1.05 seconds |
| Started | Feb 21 12:35:31 PM PST 24 |
| Finished | Feb 21 12:35:32 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-c3e7746b-fe41-4794-8dd9-4b69b0a1ccd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908140364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.2908140364 |
| Directory | /workspace/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1957782974 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 182974436 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 12:35:31 PM PST 24 |
| Finished | Feb 21 12:35:33 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-d514441c-7507-40b6-89f6-65e962d4a346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1957782974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1957782974 |
| Directory | /workspace/1.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3496967383 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 364269877 ps |
| CPU time | 3.23 seconds |
| Started | Feb 21 12:35:40 PM PST 24 |
| Finished | Feb 21 12:35:44 PM PST 24 |
| Peak memory | 202628 kb |
| Host | smart-37731696-8f9a-4c99-99dc-a37d71e0e492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3496967383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3496967383 |
| Directory | /workspace/1.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1665509139 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 415286990 ps |
| CPU time | 4.81 seconds |
| Started | Feb 21 12:35:50 PM PST 24 |
| Finished | Feb 21 12:35:56 PM PST 24 |
| Peak memory | 210252 kb |
| Host | smart-60fc0adf-1598-470b-9d35-a77edb98a62b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665509139 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.1665509139 |
| Directory | /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3347975373 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 79229173 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:35:39 PM PST 24 |
| Finished | Feb 21 12:35:40 PM PST 24 |
| Peak memory | 202472 kb |
| Host | smart-93030345-5ef5-4421-87ac-f7968e86982a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347975373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3347975373 |
| Directory | /workspace/10.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4236613971 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 67852075 ps |
| CPU time | 1.77 seconds |
| Started | Feb 21 12:35:54 PM PST 24 |
| Finished | Feb 21 12:35:56 PM PST 24 |
| Peak memory | 210752 kb |
| Host | smart-08355280-56ff-49cf-b4d2-73ba80dbc3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236613971 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.4236613971 |
| Directory | /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2032948061 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 66771383 ps |
| CPU time | 1.05 seconds |
| Started | Feb 21 12:35:57 PM PST 24 |
| Finished | Feb 21 12:35:59 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-ce001d3d-7c0d-4fe1-8d66-e3d9a762ce39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032948061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2032948061 |
| Directory | /workspace/11.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.489245137 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 138239076 ps |
| CPU time | 1.46 seconds |
| Started | Feb 21 12:35:54 PM PST 24 |
| Finished | Feb 21 12:36:01 PM PST 24 |
| Peak memory | 202520 kb |
| Host | smart-0ab8a1c7-7e52-4b97-b01e-07582a1828ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489245137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_c sr_outstanding.489245137 |
| Directory | /workspace/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1647485248 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 54974389 ps |
| CPU time | 1.49 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:47 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-feadb79f-c790-4970-ad60-4b0f4511b501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1647485248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1647485248 |
| Directory | /workspace/11.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4190326918 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 257401053 ps |
| CPU time | 2.51 seconds |
| Started | Feb 21 12:35:44 PM PST 24 |
| Finished | Feb 21 12:35:52 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-14746cc4-9185-49fd-a592-8489e42dacb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4190326918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4190326918 |
| Directory | /workspace/11.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3443084703 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 405400027 ps |
| CPU time | 4.56 seconds |
| Started | Feb 21 12:36:02 PM PST 24 |
| Finished | Feb 21 12:36:09 PM PST 24 |
| Peak memory | 210788 kb |
| Host | smart-3a2fef57-b474-4277-a74c-170020a34fc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443084703 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.3443084703 |
| Directory | /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1064043172 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 73480807 ps |
| CPU time | 1 seconds |
| Started | Feb 21 12:35:43 PM PST 24 |
| Finished | Feb 21 12:35:45 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-fbc158f5-5ed7-4580-82fe-10c513faa6d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064043172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1064043172 |
| Directory | /workspace/12.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.143482833 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 61192101 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 12:36:23 PM PST 24 |
| Finished | Feb 21 12:36:25 PM PST 24 |
| Peak memory | 202508 kb |
| Host | smart-64bebace-f138-488c-a60f-8f3965b5824b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143482833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c sr_outstanding.143482833 |
| Directory | /workspace/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2963480835 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 84467016 ps |
| CPU time | 2.34 seconds |
| Started | Feb 21 12:35:43 PM PST 24 |
| Finished | Feb 21 12:35:46 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-8c935687-d227-4977-8acd-126c260d87ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2963480835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2963480835 |
| Directory | /workspace/12.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.627092118 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 375627576 ps |
| CPU time | 2.73 seconds |
| Started | Feb 21 12:35:39 PM PST 24 |
| Finished | Feb 21 12:35:42 PM PST 24 |
| Peak memory | 202544 kb |
| Host | smart-28840c3f-de0c-4f01-8930-d18d179b2ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=627092118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.627092118 |
| Directory | /workspace/12.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3361693636 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 135052615 ps |
| CPU time | 1.92 seconds |
| Started | Feb 21 12:36:11 PM PST 24 |
| Finished | Feb 21 12:36:13 PM PST 24 |
| Peak memory | 211068 kb |
| Host | smart-3fceac3f-d582-4c07-9ff8-168828906786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361693636 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.3361693636 |
| Directory | /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3764139849 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 46538134 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:35:54 PM PST 24 |
| Finished | Feb 21 12:35:55 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-f364fcb3-8b8c-437d-8762-8696f359a3c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764139849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3764139849 |
| Directory | /workspace/13.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1522809915 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 80367977 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 12:35:46 PM PST 24 |
| Finished | Feb 21 12:35:47 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-49f0e3f2-6f6e-401b-92b8-c4d972192b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522809915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.1522809915 |
| Directory | /workspace/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1593026252 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 266024686 ps |
| CPU time | 2.75 seconds |
| Started | Feb 21 12:35:56 PM PST 24 |
| Finished | Feb 21 12:35:59 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-339362bd-7be2-47f3-a664-fae76a0e8a85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1593026252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1593026252 |
| Directory | /workspace/13.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2769849289 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 250994816 ps |
| CPU time | 2.91 seconds |
| Started | Feb 21 12:36:23 PM PST 24 |
| Finished | Feb 21 12:36:27 PM PST 24 |
| Peak memory | 210636 kb |
| Host | smart-05ee5891-f745-406e-8bbd-0650c28bed75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769849289 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.2769849289 |
| Directory | /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2225714133 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 36524880 ps |
| CPU time | 0.93 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:46 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-9dde03bf-ef0e-477a-8db1-1c3ac9322a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225714133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2225714133 |
| Directory | /workspace/14.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1594047803 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 137972788 ps |
| CPU time | 1.52 seconds |
| Started | Feb 21 12:35:44 PM PST 24 |
| Finished | Feb 21 12:35:46 PM PST 24 |
| Peak memory | 202512 kb |
| Host | smart-5514c1f3-4663-4dbc-89e1-f8c4bb2ce5fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594047803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.1594047803 |
| Directory | /workspace/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3808743303 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 142243539 ps |
| CPU time | 1.7 seconds |
| Started | Feb 21 12:35:40 PM PST 24 |
| Finished | Feb 21 12:35:42 PM PST 24 |
| Peak memory | 202364 kb |
| Host | smart-af90966f-49f5-403c-8735-74e6209a093a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3808743303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3808743303 |
| Directory | /workspace/14.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4272113354 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 344530645 ps |
| CPU time | 3.2 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:49 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-b8e24beb-2374-4e7d-8723-5cd676ea92b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4272113354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.4272113354 |
| Directory | /workspace/14.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1354136356 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 110845117 ps |
| CPU time | 3.35 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:49 PM PST 24 |
| Peak memory | 210728 kb |
| Host | smart-d3599071-c166-4a3e-b523-25077cc6a6f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354136356 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.1354136356 |
| Directory | /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.320000611 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 39664986 ps |
| CPU time | 0.75 seconds |
| Started | Feb 21 12:35:53 PM PST 24 |
| Finished | Feb 21 12:35:54 PM PST 24 |
| Peak memory | 202268 kb |
| Host | smart-e8a674c2-7ce0-4985-b0cd-51db2f9b6026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320000611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.320000611 |
| Directory | /workspace/15.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2760863185 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 108880259 ps |
| CPU time | 1.44 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:46 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-d092a8d2-6896-4f22-a409-37be58b2d672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760863185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.2760863185 |
| Directory | /workspace/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.669000929 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 91845041 ps |
| CPU time | 2.32 seconds |
| Started | Feb 21 12:35:49 PM PST 24 |
| Finished | Feb 21 12:35:51 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-f7821dfc-1434-4c36-8896-39f46d0e2626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=669000929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.669000929 |
| Directory | /workspace/15.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.843114886 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 84681062 ps |
| CPU time | 2.55 seconds |
| Started | Feb 21 12:35:43 PM PST 24 |
| Finished | Feb 21 12:35:46 PM PST 24 |
| Peak memory | 211032 kb |
| Host | smart-ed774dc8-d8f6-49ec-bda9-370f628af579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843114886 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.843114886 |
| Directory | /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.293627297 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 60361248 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:35:42 PM PST 24 |
| Finished | Feb 21 12:35:43 PM PST 24 |
| Peak memory | 202648 kb |
| Host | smart-b450d710-2f80-472e-b3b1-887f98741b1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293627297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.293627297 |
| Directory | /workspace/16.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3649503125 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 57152409 ps |
| CPU time | 1.33 seconds |
| Started | Feb 21 12:35:56 PM PST 24 |
| Finished | Feb 21 12:35:57 PM PST 24 |
| Peak memory | 202304 kb |
| Host | smart-27a4cbb5-394a-4618-bf87-75b58136cac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649503125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.3649503125 |
| Directory | /workspace/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2650657613 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 93505935 ps |
| CPU time | 1.17 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:47 PM PST 24 |
| Peak memory | 202416 kb |
| Host | smart-7d22da94-1327-4215-8622-5607a6ec7d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2650657613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2650657613 |
| Directory | /workspace/16.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3495094767 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 386486871 ps |
| CPU time | 4.76 seconds |
| Started | Feb 21 12:35:46 PM PST 24 |
| Finished | Feb 21 12:35:51 PM PST 24 |
| Peak memory | 210708 kb |
| Host | smart-e16b3684-b1ac-4939-ab21-718a5d14d79d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495094767 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.3495094767 |
| Directory | /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2838790785 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 30543294 ps |
| CPU time | 0.77 seconds |
| Started | Feb 21 12:35:44 PM PST 24 |
| Finished | Feb 21 12:35:45 PM PST 24 |
| Peak memory | 202180 kb |
| Host | smart-358654ad-9aa4-4cee-9271-d7094b26b93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838790785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2838790785 |
| Directory | /workspace/17.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3155619839 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 38924769 ps |
| CPU time | 0.99 seconds |
| Started | Feb 21 12:35:55 PM PST 24 |
| Finished | Feb 21 12:35:56 PM PST 24 |
| Peak memory | 202612 kb |
| Host | smart-4e756ce7-97e1-4f30-9964-634c0940dc4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155619839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.3155619839 |
| Directory | /workspace/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.598457040 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 146445505 ps |
| CPU time | 2.03 seconds |
| Started | Feb 21 12:35:44 PM PST 24 |
| Finished | Feb 21 12:35:46 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-f1f7650a-236c-4c04-803d-d222a33e8451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=598457040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.598457040 |
| Directory | /workspace/17.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1371860624 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 56488694 ps |
| CPU time | 1.66 seconds |
| Started | Feb 21 12:36:19 PM PST 24 |
| Finished | Feb 21 12:36:21 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-4604fd44-f0f1-4bfb-bd36-1330d0915652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371860624 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.1371860624 |
| Directory | /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2694838770 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 67840514 ps |
| CPU time | 0.98 seconds |
| Started | Feb 21 12:36:08 PM PST 24 |
| Finished | Feb 21 12:36:10 PM PST 24 |
| Peak memory | 202524 kb |
| Host | smart-67448308-65d6-4094-aa07-a3a1aec6eee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694838770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2694838770 |
| Directory | /workspace/18.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3400213869 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 40328969 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:35:58 PM PST 24 |
| Finished | Feb 21 12:36:00 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-35238061-006d-460a-b516-f6db17c54288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400213869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_ csr_outstanding.3400213869 |
| Directory | /workspace/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1043749096 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 86508340 ps |
| CPU time | 1.25 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:46 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-5cfabbf3-afae-4e12-a58f-6f2b1637d9f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1043749096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1043749096 |
| Directory | /workspace/18.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3023768729 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 111071506 ps |
| CPU time | 3.65 seconds |
| Started | Feb 21 12:36:28 PM PST 24 |
| Finished | Feb 21 12:36:32 PM PST 24 |
| Peak memory | 210572 kb |
| Host | smart-94b48f37-c09c-4980-a658-b2113d084a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023768729 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3023768729 |
| Directory | /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2681809626 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 66037597 ps |
| CPU time | 1.47 seconds |
| Started | Feb 21 12:36:16 PM PST 24 |
| Finished | Feb 21 12:36:18 PM PST 24 |
| Peak memory | 202820 kb |
| Host | smart-588a7fd5-b5ad-47d9-8138-e180cf3d2d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681809626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_ csr_outstanding.2681809626 |
| Directory | /workspace/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3691899708 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 260334775 ps |
| CPU time | 2.62 seconds |
| Started | Feb 21 12:35:55 PM PST 24 |
| Finished | Feb 21 12:35:58 PM PST 24 |
| Peak memory | 202380 kb |
| Host | smart-4baa3520-b8f5-4ebb-b1ea-0750218dc164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3691899708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3691899708 |
| Directory | /workspace/19.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4102563612 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 175351977 ps |
| CPU time | 2.45 seconds |
| Started | Feb 21 12:35:58 PM PST 24 |
| Finished | Feb 21 12:36:01 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-44c46477-b177-4be5-8da4-5cf0c21d7bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4102563612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4102563612 |
| Directory | /workspace/19.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2670904576 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 122166214 ps |
| CPU time | 3.49 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:42 PM PST 24 |
| Peak memory | 202768 kb |
| Host | smart-ab5b49e8-e9fd-43fa-9863-015d71fd28a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670904576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2670904576 |
| Directory | /workspace/2.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.207009041 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 334197601 ps |
| CPU time | 4.87 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:43 PM PST 24 |
| Peak memory | 210308 kb |
| Host | smart-5ef5c6ca-9e60-4f9e-b21b-2db082a8b036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207009041 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.207009041 |
| Directory | /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2057682074 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 39883152 ps |
| CPU time | 1.36 seconds |
| Started | Feb 21 12:35:54 PM PST 24 |
| Finished | Feb 21 12:35:56 PM PST 24 |
| Peak memory | 202392 kb |
| Host | smart-2b4b57aa-90b0-4fe5-810f-de2faf6a0f96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2057682074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2057682074 |
| Directory | /workspace/2.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.518612008 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 248850183 ps |
| CPU time | 2.43 seconds |
| Started | Feb 21 12:35:37 PM PST 24 |
| Finished | Feb 21 12:35:39 PM PST 24 |
| Peak memory | 202324 kb |
| Host | smart-948a4e75-6635-4a99-ba18-b25421794c71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=518612008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.518612008 |
| Directory | /workspace/2.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.403170036 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 41344055 ps |
| CPU time | 1.06 seconds |
| Started | Feb 21 12:35:32 PM PST 24 |
| Finished | Feb 21 12:35:34 PM PST 24 |
| Peak memory | 202548 kb |
| Host | smart-aef9c60c-aa50-49c0-a2d2-145306637572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403170036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_cs r_outstanding.403170036 |
| Directory | /workspace/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.510483291 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 148476428 ps |
| CPU time | 2.09 seconds |
| Started | Feb 21 12:35:43 PM PST 24 |
| Finished | Feb 21 12:35:45 PM PST 24 |
| Peak memory | 202356 kb |
| Host | smart-2eec57f9-0974-412d-9c92-66fb7777ec24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=510483291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.510483291 |
| Directory | /workspace/2.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1076209906 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 281843577 ps |
| CPU time | 2.85 seconds |
| Started | Feb 21 12:35:19 PM PST 24 |
| Finished | Feb 21 12:35:22 PM PST 24 |
| Peak memory | 202388 kb |
| Host | smart-8bf129b5-fff6-4b6e-b0d6-bf2e45a43d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1076209906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1076209906 |
| Directory | /workspace/2.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3818534801 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 116834775 ps |
| CPU time | 3.17 seconds |
| Started | Feb 21 12:35:31 PM PST 24 |
| Finished | Feb 21 12:35:34 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-bd390739-1074-4518-befb-614947c634bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818534801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3818534801 |
| Directory | /workspace/3.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2810654064 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 211364877 ps |
| CPU time | 2.64 seconds |
| Started | Feb 21 12:35:20 PM PST 24 |
| Finished | Feb 21 12:35:22 PM PST 24 |
| Peak memory | 210760 kb |
| Host | smart-0de29b88-ce99-453a-aea4-287c130fd574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810654064 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2810654064 |
| Directory | /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3201021035 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 33259538 ps |
| CPU time | 0.82 seconds |
| Started | Feb 21 12:35:32 PM PST 24 |
| Finished | Feb 21 12:35:33 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-89143672-56cd-4db8-a973-52f5ee3a5725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201021035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3201021035 |
| Directory | /workspace/3.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2518101642 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 161775603 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:41 PM PST 24 |
| Peak memory | 202760 kb |
| Host | smart-cd354a41-3e92-4880-ba27-412d315d7ff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2518101642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2518101642 |
| Directory | /workspace/3.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2449008384 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 87996024 ps |
| CPU time | 2.46 seconds |
| Started | Feb 21 12:35:37 PM PST 24 |
| Finished | Feb 21 12:35:40 PM PST 24 |
| Peak memory | 202672 kb |
| Host | smart-8b548ae1-a586-49c2-8c1d-6e45555adccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2449008384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2449008384 |
| Directory | /workspace/3.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.211298910 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 59826891 ps |
| CPU time | 1.33 seconds |
| Started | Feb 21 12:35:53 PM PST 24 |
| Finished | Feb 21 12:35:55 PM PST 24 |
| Peak memory | 202468 kb |
| Host | smart-70deb4ba-0313-4bd0-a795-753e06e2f3d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211298910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_cs r_outstanding.211298910 |
| Directory | /workspace/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3355030798 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 176822657 ps |
| CPU time | 2.37 seconds |
| Started | Feb 21 12:35:39 PM PST 24 |
| Finished | Feb 21 12:35:41 PM PST 24 |
| Peak memory | 202424 kb |
| Host | smart-4fb496bc-0d91-4e13-a1b8-54f66112b85a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3355030798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3355030798 |
| Directory | /workspace/3.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3516852556 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 175808973 ps |
| CPU time | 2.23 seconds |
| Started | Feb 21 12:35:40 PM PST 24 |
| Finished | Feb 21 12:35:42 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-94fd5409-4777-462b-8e9f-d8b3e13eadeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516852556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3516852556 |
| Directory | /workspace/4.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.943404983 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 40504036 ps |
| CPU time | 0.78 seconds |
| Started | Feb 21 12:35:52 PM PST 24 |
| Finished | Feb 21 12:35:53 PM PST 24 |
| Peak memory | 202260 kb |
| Host | smart-8148d1bc-a1a3-484b-91a1-9ff17d247bc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943404983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.943404983 |
| Directory | /workspace/4.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4161936230 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 255762365 ps |
| CPU time | 2.9 seconds |
| Started | Feb 21 12:35:33 PM PST 24 |
| Finished | Feb 21 12:35:36 PM PST 24 |
| Peak memory | 210820 kb |
| Host | smart-45f6499e-04ab-4096-b4c6-b5e34b93087c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161936230 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.4161936230 |
| Directory | /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2912081477 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 52889163 ps |
| CPU time | 1 seconds |
| Started | Feb 21 12:35:41 PM PST 24 |
| Finished | Feb 21 12:35:42 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-50389655-7803-4ed2-be40-561d950a7c57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912081477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2912081477 |
| Directory | /workspace/4.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.242640893 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 73683200 ps |
| CPU time | 2.11 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:41 PM PST 24 |
| Peak memory | 202448 kb |
| Host | smart-882c749a-c91a-4d1d-b1b7-44338ca47112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=242640893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.242640893 |
| Directory | /workspace/4.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1043225535 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 149715595 ps |
| CPU time | 3.69 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:42 PM PST 24 |
| Peak memory | 202360 kb |
| Host | smart-17088b22-2a50-4eff-9fdd-904358fd410d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1043225535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1043225535 |
| Directory | /workspace/4.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.26447800 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 68106250 ps |
| CPU time | 1.03 seconds |
| Started | Feb 21 12:35:37 PM PST 24 |
| Finished | Feb 21 12:35:38 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-2f94691e-5ec3-4779-8db1-d008898d8457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26447800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr _outstanding.26447800 |
| Directory | /workspace/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3497384217 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 88944872 ps |
| CPU time | 2.72 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:41 PM PST 24 |
| Peak memory | 210272 kb |
| Host | smart-8e89b238-cb71-4525-b834-138b40b10e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497384217 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.3497384217 |
| Directory | /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3492961462 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 36313245 ps |
| CPU time | 0.9 seconds |
| Started | Feb 21 12:35:30 PM PST 24 |
| Finished | Feb 21 12:35:31 PM PST 24 |
| Peak memory | 202440 kb |
| Host | smart-3782bde0-e9fd-4df9-8668-8d2099657a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492961462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3492961462 |
| Directory | /workspace/5.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3832924082 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 131432171 ps |
| CPU time | 1.9 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:41 PM PST 24 |
| Peak memory | 202704 kb |
| Host | smart-933efbe0-de83-47cb-b836-418ddf91008c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3832924082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3832924082 |
| Directory | /workspace/5.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2209432427 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 275771685 ps |
| CPU time | 2.82 seconds |
| Started | Feb 21 12:35:42 PM PST 24 |
| Finished | Feb 21 12:35:45 PM PST 24 |
| Peak memory | 202456 kb |
| Host | smart-56df8420-4700-4866-964e-a619dcbcbf3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2209432427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2209432427 |
| Directory | /workspace/5.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3639536949 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 438224406 ps |
| CPU time | 4.7 seconds |
| Started | Feb 21 12:35:46 PM PST 24 |
| Finished | Feb 21 12:35:51 PM PST 24 |
| Peak memory | 210756 kb |
| Host | smart-a06f2ce0-17e0-4563-b0aa-55791abae1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639536949 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3639536949 |
| Directory | /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1896046359 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 33238391 ps |
| CPU time | 1.01 seconds |
| Started | Feb 21 12:35:52 PM PST 24 |
| Finished | Feb 21 12:35:54 PM PST 24 |
| Peak memory | 202476 kb |
| Host | smart-99cdc1ef-cd6c-4fe5-8e88-4b89f03d7774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896046359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1896046359 |
| Directory | /workspace/6.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3629285221 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 68265384 ps |
| CPU time | 1.05 seconds |
| Started | Feb 21 12:35:48 PM PST 24 |
| Finished | Feb 21 12:35:50 PM PST 24 |
| Peak memory | 202492 kb |
| Host | smart-8c13292b-f617-4ed5-97bb-c56be06b35d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629285221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c sr_outstanding.3629285221 |
| Directory | /workspace/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2430003211 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 78230570 ps |
| CPU time | 2.21 seconds |
| Started | Feb 21 12:35:37 PM PST 24 |
| Finished | Feb 21 12:35:40 PM PST 24 |
| Peak memory | 202396 kb |
| Host | smart-c05cc592-e920-4d2e-a03e-cb811f5f2424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2430003211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2430003211 |
| Directory | /workspace/6.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2248858802 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 253651905 ps |
| CPU time | 2.65 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:41 PM PST 24 |
| Peak memory | 210740 kb |
| Host | smart-f3713241-2c58-44b5-a125-c796a3ef4d27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248858802 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.2248858802 |
| Directory | /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3060301545 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 78414000 ps |
| CPU time | 0.97 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:39 PM PST 24 |
| Peak memory | 202516 kb |
| Host | smart-14c9949e-ff7b-486b-ab29-cfb8e540ef07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060301545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3060301545 |
| Directory | /workspace/7.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4159182644 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 131782983 ps |
| CPU time | 1.46 seconds |
| Started | Feb 21 12:35:38 PM PST 24 |
| Finished | Feb 21 12:35:40 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-3f791431-70d3-4481-afd9-ca02c1835e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159182644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.4159182644 |
| Directory | /workspace/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.868570936 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 108927226 ps |
| CPU time | 1.52 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:47 PM PST 24 |
| Peak memory | 202432 kb |
| Host | smart-1324f21a-4a04-449d-8b47-d086d8d3b080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=868570936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.868570936 |
| Directory | /workspace/7.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2490422422 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 156250138 ps |
| CPU time | 2.47 seconds |
| Started | Feb 21 12:35:53 PM PST 24 |
| Finished | Feb 21 12:35:56 PM PST 24 |
| Peak memory | 202500 kb |
| Host | smart-cbc1d691-aeb7-455f-860b-a8ac9e43b65f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2490422422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2490422422 |
| Directory | /workspace/7.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3222902581 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 277979050 ps |
| CPU time | 3.69 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:49 PM PST 24 |
| Peak memory | 213880 kb |
| Host | smart-6e7f2c67-7dd2-4d5c-9e9c-88c515e8f693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222902581 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.3222902581 |
| Directory | /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2979889201 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 48085154 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:35:41 PM PST 24 |
| Finished | Feb 21 12:35:42 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-016ffd61-388d-4010-a5d0-69c2468bc21c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979889201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2979889201 |
| Directory | /workspace/8.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3609395998 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 37378487 ps |
| CPU time | 0.96 seconds |
| Started | Feb 21 12:35:28 PM PST 24 |
| Finished | Feb 21 12:35:29 PM PST 24 |
| Peak memory | 202496 kb |
| Host | smart-2db6a915-cd04-4e97-9f08-e4f8e59c7417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609395998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.3609395998 |
| Directory | /workspace/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3074159731 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 45503090 ps |
| CPU time | 1.46 seconds |
| Started | Feb 21 12:35:39 PM PST 24 |
| Finished | Feb 21 12:35:41 PM PST 24 |
| Peak memory | 202384 kb |
| Host | smart-d5ca12a4-ba9c-4ba4-9f0e-7214e3ca5845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3074159731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3074159731 |
| Directory | /workspace/8.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3580498961 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 109688302 ps |
| CPU time | 2.74 seconds |
| Started | Feb 21 12:35:40 PM PST 24 |
| Finished | Feb 21 12:35:43 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-65a4e750-b84a-4e4f-8b3a-13aac56e570e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580498961 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.3580498961 |
| Directory | /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4001752697 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 47017498 ps |
| CPU time | 0.84 seconds |
| Started | Feb 21 12:35:50 PM PST 24 |
| Finished | Feb 21 12:35:52 PM PST 24 |
| Peak memory | 201848 kb |
| Host | smart-8ed2009a-763e-4eb8-ac92-09eef889adcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001752697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4001752697 |
| Directory | /workspace/9.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4141872609 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 53802639 ps |
| CPU time | 1.42 seconds |
| Started | Feb 21 12:35:29 PM PST 24 |
| Finished | Feb 21 12:35:31 PM PST 24 |
| Peak memory | 202464 kb |
| Host | smart-54edfb4c-cc6e-4283-b783-674910ee9027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141872609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.4141872609 |
| Directory | /workspace/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.198622824 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 86903617 ps |
| CPU time | 2.47 seconds |
| Started | Feb 21 12:35:45 PM PST 24 |
| Finished | Feb 21 12:35:48 PM PST 24 |
| Peak memory | 202552 kb |
| Host | smart-17577316-8291-470a-8cdf-237307675e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=198622824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.198622824 |
| Directory | /workspace/9.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/default/0.setup_trans_ignored.4125686879 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 8360159532 ps |
| CPU time | 6.83 seconds |
| Started | Feb 21 02:31:58 PM PST 24 |
| Finished | Feb 21 02:32:05 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-a42e612d-b872-4150-955c-b3ad03215ffb |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41256 86879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.setup_trans_ignored.4125686879 |
| Directory | /workspace/0.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/0.usbdev_av_buffer.201803304 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 8372219089 ps |
| CPU time | 9.49 seconds |
| Started | Feb 21 02:32:02 PM PST 24 |
| Finished | Feb 21 02:32:12 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-a825a2e6-65d0-447b-9147-2fef72cb7a9d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180 3304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.201803304 |
| Directory | /workspace/0.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/0.usbdev_pkt_sent.757926160 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8444733871 ps |
| CPU time | 9.47 seconds |
| Started | Feb 21 02:32:02 PM PST 24 |
| Finished | Feb 21 02:32:12 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-0e6b39d6-92c4-424d-985c-2e2ee1d872b2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75792 6160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.757926160 |
| Directory | /workspace/0.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/0.usbdev_sec_cm.553978752 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 366899579 ps |
| CPU time | 1.13 seconds |
| Started | Feb 21 02:32:07 PM PST 24 |
| Finished | Feb 21 02:32:09 PM PST 24 |
| Peak memory | 216904 kb |
| Host | smart-4a4a5acf-93f6-4ac9-8be5-c4feb6e9da71 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=553978752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.553978752 |
| Directory | /workspace/0.usbdev_sec_cm/latest |
| Test location | /workspace/coverage/default/1.setup_trans_ignored.4080537728 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 8357386256 ps |
| CPU time | 7.75 seconds |
| Started | Feb 21 02:32:08 PM PST 24 |
| Finished | Feb 21 02:32:17 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-e34f8bea-e426-47eb-a205-7bc1a4dde186 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40805 37728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.setup_trans_ignored.4080537728 |
| Directory | /workspace/1.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/1.usbdev_av_buffer.3979440122 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 8369010377 ps |
| CPU time | 7.33 seconds |
| Started | Feb 21 02:32:09 PM PST 24 |
| Finished | Feb 21 02:32:17 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-f7c152a3-a41d-4193-a7aa-49b3a04e3a80 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39794 40122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3979440122 |
| Directory | /workspace/1.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/1.usbdev_pkt_sent.3751261295 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 8447303707 ps |
| CPU time | 7.36 seconds |
| Started | Feb 21 02:32:08 PM PST 24 |
| Finished | Feb 21 02:32:16 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-2af2e74a-2b37-4f7c-97fc-4ee5bd17f3e6 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37512 61295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3751261295 |
| Directory | /workspace/1.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/1.usbdev_sec_cm.1377131664 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 215922930 ps |
| CPU time | 1.08 seconds |
| Started | Feb 21 02:32:11 PM PST 24 |
| Finished | Feb 21 02:32:12 PM PST 24 |
| Peak memory | 216872 kb |
| Host | smart-bad19a94-e880-4cce-96b7-0973c364e55b |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1377131664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1377131664 |
| Directory | /workspace/1.usbdev_sec_cm/latest |
| Test location | /workspace/coverage/default/1.usbdev_smoke.2773261544 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8370893543 ps |
| CPU time | 7.51 seconds |
| Started | Feb 21 02:32:10 PM PST 24 |
| Finished | Feb 21 02:32:18 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-811081b8-2aa0-43f6-a948-b8a7ae8b49fa |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27732 61544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2773261544 |
| Directory | /workspace/1.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/10.usbdev_av_buffer.3228567336 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8372761856 ps |
| CPU time | 9.07 seconds |
| Started | Feb 21 02:32:54 PM PST 24 |
| Finished | Feb 21 02:33:04 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-7fe5fb59-ce30-4d42-835c-882348e0a19d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32285 67336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3228567336 |
| Directory | /workspace/10.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/10.usbdev_pkt_sent.705664820 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 8445197673 ps |
| CPU time | 7.96 seconds |
| Started | Feb 21 02:33:03 PM PST 24 |
| Finished | Feb 21 02:33:11 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-9d97a604-9569-494f-922c-5048828871f9 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70566 4820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.705664820 |
| Directory | /workspace/10.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/10.usbdev_smoke.2982115285 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 8371364372 ps |
| CPU time | 7.19 seconds |
| Started | Feb 21 02:32:54 PM PST 24 |
| Finished | Feb 21 02:33:01 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-a1d9f4d9-65b4-4018-b865-1a1cfa3d9d3c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29821 15285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2982115285 |
| Directory | /workspace/10.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/11.setup_trans_ignored.4091507315 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8362063607 ps |
| CPU time | 7.15 seconds |
| Started | Feb 21 02:33:00 PM PST 24 |
| Finished | Feb 21 02:33:08 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-7b11777d-7eab-493c-a3ea-1e1114b3bd4a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40915 07315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.setup_trans_ignored.4091507315 |
| Directory | /workspace/11.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/11.usbdev_av_buffer.1887383618 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 8366488533 ps |
| CPU time | 6.98 seconds |
| Started | Feb 21 02:33:02 PM PST 24 |
| Finished | Feb 21 02:33:10 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-375bd08f-d283-4e36-bad8-460d20cf5543 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18873 83618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1887383618 |
| Directory | /workspace/11.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/11.usbdev_nak_trans.2332332121 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 8419614627 ps |
| CPU time | 7.77 seconds |
| Started | Feb 21 02:33:03 PM PST 24 |
| Finished | Feb 21 02:33:11 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-08ca5668-c9c0-4dcd-ae35-9bc4be19fb47 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23323 32121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2332332121 |
| Directory | /workspace/11.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/11.usbdev_smoke.4088837545 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8368123945 ps |
| CPU time | 7.38 seconds |
| Started | Feb 21 02:33:03 PM PST 24 |
| Finished | Feb 21 02:33:11 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-d4191b35-3262-4223-8aaa-b62730fe5478 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40888 37545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.4088837545 |
| Directory | /workspace/11.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/12.in_trans.1433603649 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 8450418835 ps |
| CPU time | 9.48 seconds |
| Started | Feb 21 02:33:11 PM PST 24 |
| Finished | Feb 21 02:33:21 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-95c0d763-4d96-465a-bd6f-8450d1828803 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14336 03649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.in_trans.1433603649 |
| Directory | /workspace/12.in_trans/latest |
| Test location | /workspace/coverage/default/12.setup_trans_ignored.2912280732 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 8357468826 ps |
| CPU time | 10.04 seconds |
| Started | Feb 21 02:33:04 PM PST 24 |
| Finished | Feb 21 02:33:14 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-fe41a5f5-fa2d-4ccd-86f5-d223ceff43c2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29122 80732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.setup_trans_ignored.2912280732 |
| Directory | /workspace/12.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/12.usbdev_av_buffer.2084698787 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 8372184041 ps |
| CPU time | 8.59 seconds |
| Started | Feb 21 02:33:13 PM PST 24 |
| Finished | Feb 21 02:33:22 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-87a16bdb-6a1e-49e1-9169-252bbb5573a9 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20846 98787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2084698787 |
| Directory | /workspace/12.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/12.usbdev_pkt_sent.1337820942 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8397336196 ps |
| CPU time | 7.13 seconds |
| Started | Feb 21 02:33:04 PM PST 24 |
| Finished | Feb 21 02:33:11 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-40a81898-0602-455a-9118-185b56385aee |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13378 20942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1337820942 |
| Directory | /workspace/12.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/12.usbdev_smoke.4133882088 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 8395245505 ps |
| CPU time | 7.69 seconds |
| Started | Feb 21 02:33:01 PM PST 24 |
| Finished | Feb 21 02:33:10 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-9dcc1c5b-03cb-444d-aa77-9544fc872bdc |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41338 82088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.4133882088 |
| Directory | /workspace/12.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/13.in_trans.109001730 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 8404100255 ps |
| CPU time | 7.43 seconds |
| Started | Feb 21 02:33:04 PM PST 24 |
| Finished | Feb 21 02:33:12 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-568bce79-d4f2-463f-90be-eacc1fc9c2c1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10900 1730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.in_trans.109001730 |
| Directory | /workspace/13.in_trans/latest |
| Test location | /workspace/coverage/default/13.setup_trans_ignored.4100237585 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 8361037228 ps |
| CPU time | 7.26 seconds |
| Started | Feb 21 02:33:12 PM PST 24 |
| Finished | Feb 21 02:33:20 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-839a3491-adb5-4dbe-a3e8-9665e231b11a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41002 37585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.setup_trans_ignored.4100237585 |
| Directory | /workspace/13.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/13.usbdev_av_buffer.712473495 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 8370626117 ps |
| CPU time | 7.72 seconds |
| Started | Feb 21 02:33:04 PM PST 24 |
| Finished | Feb 21 02:33:12 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-45b3995e-b007-4564-811a-bd74fec07e6b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71247 3495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.712473495 |
| Directory | /workspace/13.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/13.usbdev_nak_trans.927433127 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 8404661286 ps |
| CPU time | 8.19 seconds |
| Started | Feb 21 02:33:08 PM PST 24 |
| Finished | Feb 21 02:33:17 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-9173e6ab-6d5b-45bb-951c-1d79834f54e6 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92743 3127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.927433127 |
| Directory | /workspace/13.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/13.usbdev_smoke.4085322983 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 8428056320 ps |
| CPU time | 7.77 seconds |
| Started | Feb 21 02:33:05 PM PST 24 |
| Finished | Feb 21 02:33:13 PM PST 24 |
| Peak memory | 202068 kb |
| Host | smart-7a4e8d32-bc15-4b0d-bfff-eed4a31d3dd0 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40853 22983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.4085322983 |
| Directory | /workspace/13.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/14.in_trans.4186854815 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 8459795267 ps |
| CPU time | 8.96 seconds |
| Started | Feb 21 02:33:23 PM PST 24 |
| Finished | Feb 21 02:33:33 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-90081c90-ebc6-4f92-9e0f-f0e7a329d204 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41868 54815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.in_trans.4186854815 |
| Directory | /workspace/14.in_trans/latest |
| Test location | /workspace/coverage/default/14.setup_trans_ignored.2112863586 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 8354207476 ps |
| CPU time | 7.59 seconds |
| Started | Feb 21 02:33:24 PM PST 24 |
| Finished | Feb 21 02:33:33 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-78e56885-0c76-4661-91f3-6d72d20d97cb |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21128 63586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.setup_trans_ignored.2112863586 |
| Directory | /workspace/14.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/14.usbdev_av_buffer.3755236964 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 8384656764 ps |
| CPU time | 6.9 seconds |
| Started | Feb 21 02:33:18 PM PST 24 |
| Finished | Feb 21 02:33:25 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-31d6820e-04c5-43e2-a7e8-d692c1d0ecd6 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37552 36964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3755236964 |
| Directory | /workspace/14.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/14.usbdev_smoke.3921528359 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 8373333584 ps |
| CPU time | 9.71 seconds |
| Started | Feb 21 02:33:24 PM PST 24 |
| Finished | Feb 21 02:33:35 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-38ec4802-8cda-4870-8e34-0460220a6931 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215 28359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3921528359 |
| Directory | /workspace/14.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/15.in_trans.4248010792 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 8385742503 ps |
| CPU time | 8.7 seconds |
| Started | Feb 21 02:33:26 PM PST 24 |
| Finished | Feb 21 02:33:36 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-e9cfc08b-784f-4690-84bb-83cddf11f203 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42480 10792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.in_trans.4248010792 |
| Directory | /workspace/15.in_trans/latest |
| Test location | /workspace/coverage/default/15.setup_trans_ignored.4135659132 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 8377828516 ps |
| CPU time | 8.06 seconds |
| Started | Feb 21 02:33:25 PM PST 24 |
| Finished | Feb 21 02:33:34 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-94b42525-cc7f-4db3-857a-ed0be542d5d4 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41356 59132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.setup_trans_ignored.4135659132 |
| Directory | /workspace/15.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/15.usbdev_av_buffer.2640758992 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8374278826 ps |
| CPU time | 7.33 seconds |
| Started | Feb 21 02:33:25 PM PST 24 |
| Finished | Feb 21 02:33:33 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-afe15596-12c7-497f-920a-5c9e20e622b2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26407 58992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2640758992 |
| Directory | /workspace/15.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/15.usbdev_nak_trans.1169196951 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 8419470471 ps |
| CPU time | 9.24 seconds |
| Started | Feb 21 02:33:25 PM PST 24 |
| Finished | Feb 21 02:33:35 PM PST 24 |
| Peak memory | 202068 kb |
| Host | smart-006002f4-c3f9-4b96-9ab3-9242081b4c79 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11691 96951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1169196951 |
| Directory | /workspace/15.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/15.usbdev_pkt_sent.112219211 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 8428230863 ps |
| CPU time | 7.03 seconds |
| Started | Feb 21 02:33:23 PM PST 24 |
| Finished | Feb 21 02:33:31 PM PST 24 |
| Peak memory | 202180 kb |
| Host | smart-6c2c8983-7e87-4087-9b8d-5c645ede8377 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11221 9211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.112219211 |
| Directory | /workspace/15.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/15.usbdev_smoke.3092137646 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 8375277465 ps |
| CPU time | 7.73 seconds |
| Started | Feb 21 02:33:29 PM PST 24 |
| Finished | Feb 21 02:33:37 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-d7360278-ec5b-4964-95c1-388d928dd2e1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30921 37646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3092137646 |
| Directory | /workspace/15.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/16.in_trans.497283458 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 8378042475 ps |
| CPU time | 8.15 seconds |
| Started | Feb 21 02:33:23 PM PST 24 |
| Finished | Feb 21 02:33:33 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-2f3ad6a0-b2f6-4cc5-8a61-b70ec62d8571 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49728 3458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.in_trans.497283458 |
| Directory | /workspace/16.in_trans/latest |
| Test location | /workspace/coverage/default/16.setup_trans_ignored.1219889577 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 8357383788 ps |
| CPU time | 6.99 seconds |
| Started | Feb 21 02:33:13 PM PST 24 |
| Finished | Feb 21 02:33:21 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-ee98313f-54cc-48e4-8c50-de9ed08e5c78 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12198 89577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.setup_trans_ignored.1219889577 |
| Directory | /workspace/16.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/16.usbdev_av_buffer.3683353851 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 8369802394 ps |
| CPU time | 8.28 seconds |
| Started | Feb 21 02:33:21 PM PST 24 |
| Finished | Feb 21 02:33:30 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-faf619b4-0e6b-4053-920b-db7a2cac9c4a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36833 53851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3683353851 |
| Directory | /workspace/16.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/16.usbdev_nak_trans.404018248 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 8475724005 ps |
| CPU time | 7.08 seconds |
| Started | Feb 21 02:33:21 PM PST 24 |
| Finished | Feb 21 02:33:29 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-52c3bd33-6793-457e-94df-1473c7361772 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40401 8248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.404018248 |
| Directory | /workspace/16.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/16.usbdev_pkt_sent.2481103486 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8427453988 ps |
| CPU time | 7.89 seconds |
| Started | Feb 21 02:33:30 PM PST 24 |
| Finished | Feb 21 02:33:39 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-56a6b051-4b93-4ef3-aec1-9a7834b38da6 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24811 03486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2481103486 |
| Directory | /workspace/16.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/16.usbdev_smoke.2660372447 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 8369896035 ps |
| CPU time | 7.15 seconds |
| Started | Feb 21 02:33:27 PM PST 24 |
| Finished | Feb 21 02:33:35 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-7621f154-75df-434e-8e8d-a89478146246 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603 72447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2660372447 |
| Directory | /workspace/16.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/17.setup_trans_ignored.877459807 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 8387206897 ps |
| CPU time | 7.41 seconds |
| Started | Feb 21 02:33:27 PM PST 24 |
| Finished | Feb 21 02:33:35 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-a9e1d801-bd83-4ce5-8ec4-22b4ada6e5a2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87745 9807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.setup_trans_ignored.877459807 |
| Directory | /workspace/17.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/17.usbdev_av_buffer.1508596868 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 8378427857 ps |
| CPU time | 7.87 seconds |
| Started | Feb 21 02:33:25 PM PST 24 |
| Finished | Feb 21 02:33:34 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-4f92d001-6f55-4468-8e2d-270f8dbe2f84 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15085 96868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1508596868 |
| Directory | /workspace/17.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/17.usbdev_nak_trans.3600140734 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 8424022106 ps |
| CPU time | 7.63 seconds |
| Started | Feb 21 02:33:28 PM PST 24 |
| Finished | Feb 21 02:33:36 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-526308f8-8a57-49b0-b96c-14b7d853d1f8 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36001 40734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3600140734 |
| Directory | /workspace/17.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/17.usbdev_pkt_sent.3331449473 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 8436938160 ps |
| CPU time | 7.59 seconds |
| Started | Feb 21 02:33:29 PM PST 24 |
| Finished | Feb 21 02:33:38 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-2e812b25-2865-4af0-8213-b5b3a816c3da |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33314 49473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3331449473 |
| Directory | /workspace/17.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/17.usbdev_smoke.1772867957 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 8370669363 ps |
| CPU time | 7.87 seconds |
| Started | Feb 21 02:33:27 PM PST 24 |
| Finished | Feb 21 02:33:35 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-11d89d84-5ea0-4189-91f3-978b44c954b2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17728 67957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1772867957 |
| Directory | /workspace/17.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/18.in_trans.3211311340 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 8386783963 ps |
| CPU time | 7.31 seconds |
| Started | Feb 21 02:33:29 PM PST 24 |
| Finished | Feb 21 02:33:36 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-8721988b-7302-4002-aeb8-9e1e9abfa9d7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32113 11340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.in_trans.3211311340 |
| Directory | /workspace/18.in_trans/latest |
| Test location | /workspace/coverage/default/18.setup_trans_ignored.3363605020 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8360395270 ps |
| CPU time | 7.72 seconds |
| Started | Feb 21 02:33:32 PM PST 24 |
| Finished | Feb 21 02:33:41 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-a3280e9d-6993-4e09-a92c-06a96e6c7826 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33636 05020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.setup_trans_ignored.3363605020 |
| Directory | /workspace/18.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/18.usbdev_nak_trans.1901009310 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 8425004232 ps |
| CPU time | 7.23 seconds |
| Started | Feb 21 02:33:28 PM PST 24 |
| Finished | Feb 21 02:33:35 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-d113b3fd-f381-4542-9984-e684f9c90ebe |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19010 09310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1901009310 |
| Directory | /workspace/18.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/18.usbdev_pkt_sent.3871822367 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 8422200042 ps |
| CPU time | 9.35 seconds |
| Started | Feb 21 02:33:32 PM PST 24 |
| Finished | Feb 21 02:33:42 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-ed49c165-0040-4d47-b26b-645ee1d187e3 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38718 22367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3871822367 |
| Directory | /workspace/18.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/18.usbdev_smoke.2047857142 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 8365031442 ps |
| CPU time | 8.05 seconds |
| Started | Feb 21 02:33:28 PM PST 24 |
| Finished | Feb 21 02:33:36 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-2228d3fc-2e43-4f67-ac7a-d02d5eca943a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20478 57142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2047857142 |
| Directory | /workspace/18.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/19.in_trans.3056508153 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 8385778043 ps |
| CPU time | 9.1 seconds |
| Started | Feb 21 02:33:40 PM PST 24 |
| Finished | Feb 21 02:33:49 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-4ad731ed-64ed-4654-aac7-b479d22ed39c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30565 08153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.in_trans.3056508153 |
| Directory | /workspace/19.in_trans/latest |
| Test location | /workspace/coverage/default/19.setup_trans_ignored.2708069122 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 8363412664 ps |
| CPU time | 7.16 seconds |
| Started | Feb 21 02:33:43 PM PST 24 |
| Finished | Feb 21 02:33:51 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-7ecc6268-a553-4931-ae65-f61ed755fbb5 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080 69122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.setup_trans_ignored.2708069122 |
| Directory | /workspace/19.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/19.usbdev_av_buffer.688280682 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 8413721810 ps |
| CPU time | 8.56 seconds |
| Started | Feb 21 02:33:45 PM PST 24 |
| Finished | Feb 21 02:33:54 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-33f18b7d-efc9-4810-b2b2-c01ae76f1279 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68828 0682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.688280682 |
| Directory | /workspace/19.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/19.usbdev_nak_trans.295846616 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8436345376 ps |
| CPU time | 8.67 seconds |
| Started | Feb 21 02:33:39 PM PST 24 |
| Finished | Feb 21 02:33:48 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-d9a4ce20-88c2-4e6c-8613-c7c46789b4cd |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584 6616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.295846616 |
| Directory | /workspace/19.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/19.usbdev_pkt_sent.3536687452 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 8396824481 ps |
| CPU time | 9.17 seconds |
| Started | Feb 21 02:33:51 PM PST 24 |
| Finished | Feb 21 02:34:00 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-37398440-4dcc-4ed6-b060-d4e594ad8a5f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35366 87452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3536687452 |
| Directory | /workspace/19.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/19.usbdev_smoke.2239409559 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 8390324636 ps |
| CPU time | 8.08 seconds |
| Started | Feb 21 02:33:41 PM PST 24 |
| Finished | Feb 21 02:33:50 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-0acd1f88-b4c5-4c1d-8ffb-c9da2896669d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22394 09559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2239409559 |
| Directory | /workspace/19.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/2.in_trans.1084292321 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 8447703925 ps |
| CPU time | 9.42 seconds |
| Started | Feb 21 02:32:20 PM PST 24 |
| Finished | Feb 21 02:32:30 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-ff519efb-250d-428c-a34c-5ac8c0c83f2c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10842 92321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.in_trans.1084292321 |
| Directory | /workspace/2.in_trans/latest |
| Test location | /workspace/coverage/default/2.setup_trans_ignored.3773265496 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 8361090447 ps |
| CPU time | 7.61 seconds |
| Started | Feb 21 02:32:18 PM PST 24 |
| Finished | Feb 21 02:32:27 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-8d6aef4f-f22e-4c31-8f0a-b226822200c7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37732 65496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.setup_trans_ignored.3773265496 |
| Directory | /workspace/2.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/2.usbdev_av_buffer.1464377307 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8387449763 ps |
| CPU time | 7.38 seconds |
| Started | Feb 21 02:32:20 PM PST 24 |
| Finished | Feb 21 02:32:28 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-2996f85c-8910-45ab-8acf-ef52a2d82b8b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14643 77307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1464377307 |
| Directory | /workspace/2.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/2.usbdev_pkt_sent.4294008114 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 8382315186 ps |
| CPU time | 8.48 seconds |
| Started | Feb 21 02:32:21 PM PST 24 |
| Finished | Feb 21 02:32:30 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-5a3f2a4d-ef6d-44d7-bbac-8a0f559d440b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42940 08114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.4294008114 |
| Directory | /workspace/2.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/2.usbdev_sec_cm.2833329324 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 86053369 ps |
| CPU time | 0.92 seconds |
| Started | Feb 21 02:32:24 PM PST 24 |
| Finished | Feb 21 02:32:25 PM PST 24 |
| Peak memory | 216924 kb |
| Host | smart-3bbca6b6-cd14-4d6c-989f-41873090841c |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2833329324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2833329324 |
| Directory | /workspace/2.usbdev_sec_cm/latest |
| Test location | /workspace/coverage/default/2.usbdev_smoke.692189804 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 8368613651 ps |
| CPU time | 7.17 seconds |
| Started | Feb 21 02:32:07 PM PST 24 |
| Finished | Feb 21 02:32:16 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-600e29a4-dfed-4931-8743-409e6255f587 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69218 9804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.692189804 |
| Directory | /workspace/2.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/20.setup_trans_ignored.1798552794 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 8366401046 ps |
| CPU time | 7.15 seconds |
| Started | Feb 21 02:33:37 PM PST 24 |
| Finished | Feb 21 02:33:45 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-e9991c92-27a9-4972-8e3f-79182b91fdb1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17985 52794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.setup_trans_ignored.1798552794 |
| Directory | /workspace/20.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/20.usbdev_av_buffer.4269710718 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 8376657905 ps |
| CPU time | 7.47 seconds |
| Started | Feb 21 02:33:41 PM PST 24 |
| Finished | Feb 21 02:33:49 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-a4b1a262-79ee-432f-8803-4e1afe6117ec |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42697 10718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.4269710718 |
| Directory | /workspace/20.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/20.usbdev_pkt_sent.2693799073 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 8492995318 ps |
| CPU time | 8.1 seconds |
| Started | Feb 21 02:33:54 PM PST 24 |
| Finished | Feb 21 02:34:02 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-3099a6ae-de8b-4999-baeb-3d0503e7bd0d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26937 99073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2693799073 |
| Directory | /workspace/20.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/20.usbdev_smoke.4218457137 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 8366870627 ps |
| CPU time | 9.07 seconds |
| Started | Feb 21 02:33:44 PM PST 24 |
| Finished | Feb 21 02:33:53 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-62e1521f-98ea-4ef0-9798-b5ba032a6cd0 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42184 57137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.4218457137 |
| Directory | /workspace/20.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/21.in_trans.2934981949 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 8425070189 ps |
| CPU time | 7.34 seconds |
| Started | Feb 21 02:33:43 PM PST 24 |
| Finished | Feb 21 02:33:50 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-8654ea43-dad2-4ff5-b19e-b4d2198087e8 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29349 81949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.in_trans.2934981949 |
| Directory | /workspace/21.in_trans/latest |
| Test location | /workspace/coverage/default/21.setup_trans_ignored.2314053949 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 8363884982 ps |
| CPU time | 8.73 seconds |
| Started | Feb 21 02:33:32 PM PST 24 |
| Finished | Feb 21 02:33:41 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-a3b6a5f5-3fbf-4d09-8cc0-0c2ddfbb5de7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23140 53949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.setup_trans_ignored.2314053949 |
| Directory | /workspace/21.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/21.usbdev_av_buffer.1874196011 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 8382414774 ps |
| CPU time | 7.3 seconds |
| Started | Feb 21 02:33:40 PM PST 24 |
| Finished | Feb 21 02:33:48 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-eff24466-4def-4fc5-98fc-0c54fcc70de5 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18741 96011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1874196011 |
| Directory | /workspace/21.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/21.usbdev_pkt_sent.379465151 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 8431550381 ps |
| CPU time | 8.28 seconds |
| Started | Feb 21 02:33:47 PM PST 24 |
| Finished | Feb 21 02:33:56 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-6fba3a41-7c06-47eb-a86c-69a202a5f7ca |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37946 5151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.379465151 |
| Directory | /workspace/21.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/21.usbdev_smoke.3598793692 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 8368352935 ps |
| CPU time | 9.5 seconds |
| Started | Feb 21 02:33:50 PM PST 24 |
| Finished | Feb 21 02:34:00 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-140f26ac-1ead-49d0-966a-4dda268a0817 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987 93692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3598793692 |
| Directory | /workspace/21.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/22.in_trans.1808516534 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 8440431381 ps |
| CPU time | 7.67 seconds |
| Started | Feb 21 02:33:46 PM PST 24 |
| Finished | Feb 21 02:33:54 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-76ebf2ab-2745-41db-9812-6902ac4caf39 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18085 16534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.in_trans.1808516534 |
| Directory | /workspace/22.in_trans/latest |
| Test location | /workspace/coverage/default/22.setup_trans_ignored.2960296932 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 8358288008 ps |
| CPU time | 7.71 seconds |
| Started | Feb 21 02:33:55 PM PST 24 |
| Finished | Feb 21 02:34:04 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-23f1d865-1ac2-4856-8693-9590f04bc39d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29602 96932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.setup_trans_ignored.2960296932 |
| Directory | /workspace/22.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/22.usbdev_av_buffer.1296881404 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 8369479433 ps |
| CPU time | 9.34 seconds |
| Started | Feb 21 02:33:44 PM PST 24 |
| Finished | Feb 21 02:33:54 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-501dfcf2-4035-40cb-a722-4ead14184977 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12968 81404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1296881404 |
| Directory | /workspace/22.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/22.usbdev_nak_trans.672963172 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 8404330664 ps |
| CPU time | 7.25 seconds |
| Started | Feb 21 02:33:51 PM PST 24 |
| Finished | Feb 21 02:33:58 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-fe6b7f1d-0ca4-4ecb-8e10-95bc74ec3439 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67296 3172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.672963172 |
| Directory | /workspace/22.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/22.usbdev_pkt_sent.3235740160 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 8418596247 ps |
| CPU time | 7.43 seconds |
| Started | Feb 21 02:33:46 PM PST 24 |
| Finished | Feb 21 02:33:54 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-148cb7c0-1c4a-4dc2-a67d-646655a16df9 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32357 40160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3235740160 |
| Directory | /workspace/22.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/22.usbdev_smoke.4119390934 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 8390866180 ps |
| CPU time | 6.94 seconds |
| Started | Feb 21 02:33:55 PM PST 24 |
| Finished | Feb 21 02:34:03 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-0f1637d8-1e7f-405e-afd7-46023d1bd928 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41193 90934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4119390934 |
| Directory | /workspace/22.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/23.setup_trans_ignored.1867233875 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 8355029476 ps |
| CPU time | 7.02 seconds |
| Started | Feb 21 02:33:42 PM PST 24 |
| Finished | Feb 21 02:33:49 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-d35d4963-22bc-45d6-8421-7dd12a69bfd3 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672 33875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.setup_trans_ignored.1867233875 |
| Directory | /workspace/23.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/23.usbdev_av_buffer.3411249544 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 8381021593 ps |
| CPU time | 7.4 seconds |
| Started | Feb 21 02:33:43 PM PST 24 |
| Finished | Feb 21 02:33:51 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-c9531042-bc40-4686-ab69-7ca788e4629a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34112 49544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3411249544 |
| Directory | /workspace/23.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/23.usbdev_nak_trans.2607485822 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 8439341525 ps |
| CPU time | 7.7 seconds |
| Started | Feb 21 02:33:53 PM PST 24 |
| Finished | Feb 21 02:34:01 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-87536b7c-83cd-4b1d-ae08-9cf57994cecc |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26074 85822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2607485822 |
| Directory | /workspace/23.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/23.usbdev_pkt_sent.3604484368 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 8399907775 ps |
| CPU time | 7.23 seconds |
| Started | Feb 21 02:33:51 PM PST 24 |
| Finished | Feb 21 02:33:58 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-166a9113-b97b-423e-a6be-cdc7eceaa5af |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36044 84368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3604484368 |
| Directory | /workspace/23.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/23.usbdev_smoke.1315167463 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 8368438542 ps |
| CPU time | 7.56 seconds |
| Started | Feb 21 02:33:52 PM PST 24 |
| Finished | Feb 21 02:34:00 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-3ee46591-d691-4cec-897f-e444227ee57e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13151 67463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1315167463 |
| Directory | /workspace/23.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/24.in_trans.1631492768 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 8423437937 ps |
| CPU time | 7.13 seconds |
| Started | Feb 21 02:33:55 PM PST 24 |
| Finished | Feb 21 02:34:02 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-a64ac911-4bb1-4721-9c54-a96512d90090 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16314 92768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.in_trans.1631492768 |
| Directory | /workspace/24.in_trans/latest |
| Test location | /workspace/coverage/default/24.setup_trans_ignored.4234237469 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 8366458870 ps |
| CPU time | 7.07 seconds |
| Started | Feb 21 02:33:52 PM PST 24 |
| Finished | Feb 21 02:34:00 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-00355965-cc4f-489f-b641-d7f1dd281faf |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42342 37469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.setup_trans_ignored.4234237469 |
| Directory | /workspace/24.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/24.usbdev_av_buffer.1020411635 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 8371980566 ps |
| CPU time | 7.81 seconds |
| Started | Feb 21 02:33:51 PM PST 24 |
| Finished | Feb 21 02:33:59 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-fe97d3bf-df5c-47e7-b9cb-4729ce0dd3a5 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204 11635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1020411635 |
| Directory | /workspace/24.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/24.usbdev_nak_trans.1208387185 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8427929032 ps |
| CPU time | 8.99 seconds |
| Started | Feb 21 02:33:52 PM PST 24 |
| Finished | Feb 21 02:34:02 PM PST 24 |
| Peak memory | 202272 kb |
| Host | smart-bca55a59-6730-43c0-abfc-c257c5b3e956 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12083 87185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1208387185 |
| Directory | /workspace/24.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/24.usbdev_pkt_sent.1567637923 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 8431609280 ps |
| CPU time | 8.45 seconds |
| Started | Feb 21 02:33:57 PM PST 24 |
| Finished | Feb 21 02:34:07 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-9e6a48e0-6049-4544-abae-ea9a3bf3f8d1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15676 37923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1567637923 |
| Directory | /workspace/24.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/25.setup_trans_ignored.1573271407 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8368004540 ps |
| CPU time | 7.21 seconds |
| Started | Feb 21 02:33:51 PM PST 24 |
| Finished | Feb 21 02:33:59 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-740852e0-fead-4caa-ba5f-4de8614413fb |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15732 71407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.setup_trans_ignored.1573271407 |
| Directory | /workspace/25.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/25.usbdev_nak_trans.1714561845 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8411101594 ps |
| CPU time | 7.85 seconds |
| Started | Feb 21 02:33:58 PM PST 24 |
| Finished | Feb 21 02:34:07 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-09f34244-6fd0-4c7d-a15d-3e379f993b72 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17145 61845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1714561845 |
| Directory | /workspace/25.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/25.usbdev_pkt_sent.3764534789 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8413616599 ps |
| CPU time | 8.04 seconds |
| Started | Feb 21 02:33:52 PM PST 24 |
| Finished | Feb 21 02:34:01 PM PST 24 |
| Peak memory | 202256 kb |
| Host | smart-4e544874-fe4e-444c-8fb9-5cda0f516af6 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37645 34789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3764534789 |
| Directory | /workspace/25.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/25.usbdev_smoke.665883835 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 8370335021 ps |
| CPU time | 7.21 seconds |
| Started | Feb 21 02:33:53 PM PST 24 |
| Finished | Feb 21 02:34:00 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-42980bca-a2b8-4974-9104-5b2652620352 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66588 3835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.665883835 |
| Directory | /workspace/25.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/26.in_trans.1592863608 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 8442038492 ps |
| CPU time | 7.51 seconds |
| Started | Feb 21 02:33:57 PM PST 24 |
| Finished | Feb 21 02:34:06 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-51e62f5a-b876-4d2f-b271-082bc3a3c86d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15928 63608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.in_trans.1592863608 |
| Directory | /workspace/26.in_trans/latest |
| Test location | /workspace/coverage/default/26.setup_trans_ignored.3518548048 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8358006432 ps |
| CPU time | 7.32 seconds |
| Started | Feb 21 02:34:09 PM PST 24 |
| Finished | Feb 21 02:34:17 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-1a8f669a-7852-4e64-a143-858a587218f2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185 48048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.setup_trans_ignored.3518548048 |
| Directory | /workspace/26.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/26.usbdev_av_buffer.1625664878 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 8369995661 ps |
| CPU time | 7.58 seconds |
| Started | Feb 21 02:33:55 PM PST 24 |
| Finished | Feb 21 02:34:05 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-81bd252f-6e03-4f38-85b6-d2018f7c6e25 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256 64878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1625664878 |
| Directory | /workspace/26.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/26.usbdev_nak_trans.821461908 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 8474218805 ps |
| CPU time | 7.42 seconds |
| Started | Feb 21 02:33:58 PM PST 24 |
| Finished | Feb 21 02:34:07 PM PST 24 |
| Peak memory | 202260 kb |
| Host | smart-d04c4797-6407-48ed-9d25-a5bb86a89b4f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82146 1908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.821461908 |
| Directory | /workspace/26.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/26.usbdev_pkt_sent.3560139613 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 8441999662 ps |
| CPU time | 7.05 seconds |
| Started | Feb 21 02:33:55 PM PST 24 |
| Finished | Feb 21 02:34:05 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-90856811-206a-4845-9e96-6f91cc69b636 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35601 39613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3560139613 |
| Directory | /workspace/26.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/26.usbdev_smoke.4240884471 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 8374996473 ps |
| CPU time | 8.53 seconds |
| Started | Feb 21 02:33:58 PM PST 24 |
| Finished | Feb 21 02:34:08 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-8506e2da-c461-4d35-a937-cf378b926ebd |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42408 84471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4240884471 |
| Directory | /workspace/26.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/27.in_trans.743008804 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 8412339918 ps |
| CPU time | 8.57 seconds |
| Started | Feb 21 02:34:03 PM PST 24 |
| Finished | Feb 21 02:34:13 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-68247920-33d4-41bb-ae08-1f9496ed6b3e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74300 8804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.in_trans.743008804 |
| Directory | /workspace/27.in_trans/latest |
| Test location | /workspace/coverage/default/27.setup_trans_ignored.3903226726 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 8360652895 ps |
| CPU time | 8.35 seconds |
| Started | Feb 21 02:33:58 PM PST 24 |
| Finished | Feb 21 02:34:08 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-3144dabe-a589-4563-83ea-1d081deb49db |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39032 26726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.setup_trans_ignored.3903226726 |
| Directory | /workspace/27.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/27.usbdev_nak_trans.863092742 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 8440135900 ps |
| CPU time | 8.11 seconds |
| Started | Feb 21 02:33:57 PM PST 24 |
| Finished | Feb 21 02:34:07 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-051872bb-13d4-4550-9797-11259511c6fa |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86309 2742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.863092742 |
| Directory | /workspace/27.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/27.usbdev_pkt_sent.2449408868 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 8437624221 ps |
| CPU time | 7.2 seconds |
| Started | Feb 21 02:34:04 PM PST 24 |
| Finished | Feb 21 02:34:11 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-a6ff8810-4f11-4446-9cfe-b6632680e294 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24494 08868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2449408868 |
| Directory | /workspace/27.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/27.usbdev_smoke.2266589460 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 8372113713 ps |
| CPU time | 8.17 seconds |
| Started | Feb 21 02:33:54 PM PST 24 |
| Finished | Feb 21 02:34:02 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-24267747-591c-4aa5-b9e8-ce306d8a3cfc |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665 89460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2266589460 |
| Directory | /workspace/27.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/28.setup_trans_ignored.3038999876 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 8368532117 ps |
| CPU time | 9.36 seconds |
| Started | Feb 21 02:34:00 PM PST 24 |
| Finished | Feb 21 02:34:10 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-57b7cc7a-b39a-4c2c-bd42-6085cd255ebf |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30389 99876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.setup_trans_ignored.3038999876 |
| Directory | /workspace/28.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/28.usbdev_pkt_sent.2467397743 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 8430930082 ps |
| CPU time | 7.44 seconds |
| Started | Feb 21 02:33:56 PM PST 24 |
| Finished | Feb 21 02:34:06 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-d761e17d-96e5-4a0c-ace5-b2a8f81925de |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24673 97743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2467397743 |
| Directory | /workspace/28.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/28.usbdev_smoke.25368244 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8374057348 ps |
| CPU time | 7.07 seconds |
| Started | Feb 21 02:34:01 PM PST 24 |
| Finished | Feb 21 02:34:09 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-0dae6c81-d167-4380-ba39-5a98bd3f9050 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25368 244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.25368244 |
| Directory | /workspace/28.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/29.in_trans.3774873223 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 8502719898 ps |
| CPU time | 8.35 seconds |
| Started | Feb 21 02:34:15 PM PST 24 |
| Finished | Feb 21 02:34:23 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-27c53d97-7991-4bb5-9aeb-6fa0092ab19b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37748 73223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.in_trans.3774873223 |
| Directory | /workspace/29.in_trans/latest |
| Test location | /workspace/coverage/default/29.setup_trans_ignored.2989649839 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 8358669055 ps |
| CPU time | 8.2 seconds |
| Started | Feb 21 02:34:18 PM PST 24 |
| Finished | Feb 21 02:34:26 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-03461549-327d-4689-994b-50a2fc7a667d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29896 49839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.setup_trans_ignored.2989649839 |
| Directory | /workspace/29.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/29.usbdev_av_buffer.1278975954 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 8374492471 ps |
| CPU time | 7.36 seconds |
| Started | Feb 21 02:34:18 PM PST 24 |
| Finished | Feb 21 02:34:26 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-8883343d-5fcc-4bfa-82fb-8aea14bbcd65 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12789 75954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1278975954 |
| Directory | /workspace/29.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/29.usbdev_nak_trans.2467660551 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 8430803440 ps |
| CPU time | 7.14 seconds |
| Started | Feb 21 02:34:19 PM PST 24 |
| Finished | Feb 21 02:34:27 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-25b2a009-1910-4b34-bd1b-0bb879c24fd0 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676 60551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2467660551 |
| Directory | /workspace/29.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/29.usbdev_pkt_sent.2058175265 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 8440481834 ps |
| CPU time | 8.5 seconds |
| Started | Feb 21 02:34:17 PM PST 24 |
| Finished | Feb 21 02:34:25 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-4e4d728f-e1a5-4367-a39a-3d6cea945047 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20581 75265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2058175265 |
| Directory | /workspace/29.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/29.usbdev_smoke.3280705088 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 8368396447 ps |
| CPU time | 7.23 seconds |
| Started | Feb 21 02:34:23 PM PST 24 |
| Finished | Feb 21 02:34:32 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-14337523-76d7-4598-9d62-f950b9bbedfb |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32807 05088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3280705088 |
| Directory | /workspace/29.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/3.in_trans.3250953502 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8462003055 ps |
| CPU time | 7.49 seconds |
| Started | Feb 21 02:32:19 PM PST 24 |
| Finished | Feb 21 02:32:27 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-b26b9fbb-0d73-4565-8523-663d1078e622 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32509 53502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.in_trans.3250953502 |
| Directory | /workspace/3.in_trans/latest |
| Test location | /workspace/coverage/default/3.setup_trans_ignored.3962294858 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 8365748174 ps |
| CPU time | 7.23 seconds |
| Started | Feb 21 02:32:19 PM PST 24 |
| Finished | Feb 21 02:32:27 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-8559b7eb-104f-4e9f-992a-3a4216db0a32 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39622 94858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.setup_trans_ignored.3962294858 |
| Directory | /workspace/3.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/3.usbdev_av_buffer.3030323299 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 8382119578 ps |
| CPU time | 7.73 seconds |
| Started | Feb 21 02:32:19 PM PST 24 |
| Finished | Feb 21 02:32:28 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-741a01cf-1f5c-4ee1-a442-cc38e1ef1d4c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30303 23299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3030323299 |
| Directory | /workspace/3.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/3.usbdev_nak_trans.2191191150 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8406257832 ps |
| CPU time | 7.41 seconds |
| Started | Feb 21 02:32:21 PM PST 24 |
| Finished | Feb 21 02:32:29 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-67e6f305-0ae2-4d94-9664-69b56b032cd3 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21911 91150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2191191150 |
| Directory | /workspace/3.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/3.usbdev_smoke.1198492459 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 8373548552 ps |
| CPU time | 8.69 seconds |
| Started | Feb 21 02:32:18 PM PST 24 |
| Finished | Feb 21 02:32:28 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-ca5cb311-f9c7-41f9-b29f-5adc12681c30 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11984 92459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1198492459 |
| Directory | /workspace/3.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/30.in_trans.1246342818 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 8429066485 ps |
| CPU time | 7.84 seconds |
| Started | Feb 21 02:34:38 PM PST 24 |
| Finished | Feb 21 02:34:47 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-1ed4ffd1-bcd3-440c-8841-5faa354fc03e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463 42818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.in_trans.1246342818 |
| Directory | /workspace/30.in_trans/latest |
| Test location | /workspace/coverage/default/30.setup_trans_ignored.2581628487 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 8370071846 ps |
| CPU time | 8.34 seconds |
| Started | Feb 21 02:34:40 PM PST 24 |
| Finished | Feb 21 02:34:49 PM PST 24 |
| Peak memory | 202028 kb |
| Host | smart-6a0177c6-7cc8-4a64-8feb-0bcf8662bfde |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25816 28487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.setup_trans_ignored.2581628487 |
| Directory | /workspace/30.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/30.usbdev_av_buffer.2722943160 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 8370116309 ps |
| CPU time | 7.43 seconds |
| Started | Feb 21 02:34:38 PM PST 24 |
| Finished | Feb 21 02:34:47 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-ec87172d-cb02-4482-8813-b07bde5f79cf |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27229 43160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2722943160 |
| Directory | /workspace/30.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/30.usbdev_nak_trans.2170432106 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8420396471 ps |
| CPU time | 7.34 seconds |
| Started | Feb 21 02:34:47 PM PST 24 |
| Finished | Feb 21 02:34:58 PM PST 24 |
| Peak memory | 201976 kb |
| Host | smart-8d2b7764-580e-4c8c-b406-8f14e99d4bbc |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704 32106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2170432106 |
| Directory | /workspace/30.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/30.usbdev_pkt_sent.2583817582 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 8416900708 ps |
| CPU time | 7.51 seconds |
| Started | Feb 21 02:34:41 PM PST 24 |
| Finished | Feb 21 02:34:49 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-6721f17b-8b55-4e11-a5c1-5a4d3fbc1b70 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25838 17582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2583817582 |
| Directory | /workspace/30.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/30.usbdev_smoke.538010263 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 8375600287 ps |
| CPU time | 7.4 seconds |
| Started | Feb 21 02:34:52 PM PST 24 |
| Finished | Feb 21 02:35:00 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-3f622609-b82f-4a66-a969-a5d8a73b0250 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53801 0263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.538010263 |
| Directory | /workspace/30.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/31.in_trans.2600399333 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 8438531689 ps |
| CPU time | 7.68 seconds |
| Started | Feb 21 02:34:44 PM PST 24 |
| Finished | Feb 21 02:34:54 PM PST 24 |
| Peak memory | 202120 kb |
| Host | smart-d5ebbb2d-028b-4335-9f46-873755cfb724 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26003 99333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.in_trans.2600399333 |
| Directory | /workspace/31.in_trans/latest |
| Test location | /workspace/coverage/default/31.setup_trans_ignored.2350932310 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 8363100971 ps |
| CPU time | 7.04 seconds |
| Started | Feb 21 02:34:45 PM PST 24 |
| Finished | Feb 21 02:34:56 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-fd2d2ba9-1ed5-4f99-9c22-01dc0275f67e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509 32310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.setup_trans_ignored.2350932310 |
| Directory | /workspace/31.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/31.usbdev_av_buffer.4006649400 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 8370969296 ps |
| CPU time | 7.1 seconds |
| Started | Feb 21 02:34:54 PM PST 24 |
| Finished | Feb 21 02:35:05 PM PST 24 |
| Peak memory | 201940 kb |
| Host | smart-5efbf8d5-3452-4230-9ffd-ac543c237acd |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066 49400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4006649400 |
| Directory | /workspace/31.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/31.usbdev_smoke.520280131 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 8373033314 ps |
| CPU time | 7.17 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:05 PM PST 24 |
| Peak memory | 202160 kb |
| Host | smart-07c65d05-4f32-4a92-9459-aed54a5153af |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52028 0131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.520280131 |
| Directory | /workspace/31.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/32.in_trans.3068591521 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 8439703763 ps |
| CPU time | 8.46 seconds |
| Started | Feb 21 02:34:48 PM PST 24 |
| Finished | Feb 21 02:34:59 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-5eacc5c4-eb44-4ae0-9825-935b1dc1d8ed |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30685 91521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.in_trans.3068591521 |
| Directory | /workspace/32.in_trans/latest |
| Test location | /workspace/coverage/default/32.setup_trans_ignored.1209182494 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 8362354405 ps |
| CPU time | 8.51 seconds |
| Started | Feb 21 02:34:43 PM PST 24 |
| Finished | Feb 21 02:34:52 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-967ddbaf-72ce-4551-b47d-0f21edb38165 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12091 82494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.setup_trans_ignored.1209182494 |
| Directory | /workspace/32.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/32.usbdev_av_buffer.535300137 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 8373041267 ps |
| CPU time | 7.27 seconds |
| Started | Feb 21 02:34:49 PM PST 24 |
| Finished | Feb 21 02:34:59 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-d7779768-9536-4c19-9884-746293a34070 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53530 0137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.535300137 |
| Directory | /workspace/32.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/32.usbdev_nak_trans.3566973066 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 8404098325 ps |
| CPU time | 9.82 seconds |
| Started | Feb 21 02:34:47 PM PST 24 |
| Finished | Feb 21 02:34:59 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-48df2418-6465-4c21-b228-0a586496e66d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35669 73066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3566973066 |
| Directory | /workspace/32.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/32.usbdev_pkt_sent.2338668033 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8458251022 ps |
| CPU time | 8.33 seconds |
| Started | Feb 21 02:34:40 PM PST 24 |
| Finished | Feb 21 02:34:48 PM PST 24 |
| Peak memory | 202068 kb |
| Host | smart-f1dd7937-56fc-42cc-8cd0-d7a07dfae198 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23386 68033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2338668033 |
| Directory | /workspace/32.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/32.usbdev_smoke.2246465302 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 8373551110 ps |
| CPU time | 7.06 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-17d23280-ff26-4f24-9a4e-6adc5d774d1a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22464 65302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2246465302 |
| Directory | /workspace/32.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/33.in_trans.1931647180 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 8412221304 ps |
| CPU time | 7.47 seconds |
| Started | Feb 21 02:34:45 PM PST 24 |
| Finished | Feb 21 02:34:56 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-942368ec-6be3-403b-9133-5abd64e289a5 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19316 47180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.in_trans.1931647180 |
| Directory | /workspace/33.in_trans/latest |
| Test location | /workspace/coverage/default/33.setup_trans_ignored.1462643184 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 8365650732 ps |
| CPU time | 7.27 seconds |
| Started | Feb 21 02:34:43 PM PST 24 |
| Finished | Feb 21 02:34:50 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-f59fc842-6f04-48f8-9d14-70e67bc8d5b2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14626 43184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.setup_trans_ignored.1462643184 |
| Directory | /workspace/33.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/33.usbdev_av_buffer.1422395115 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 8366666848 ps |
| CPU time | 7.34 seconds |
| Started | Feb 21 02:34:49 PM PST 24 |
| Finished | Feb 21 02:34:59 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-906fd270-1b31-4a74-87b5-8f1651197dc3 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14223 95115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1422395115 |
| Directory | /workspace/33.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/33.usbdev_nak_trans.714851009 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 8392868637 ps |
| CPU time | 7.29 seconds |
| Started | Feb 21 02:34:55 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-5a40f010-35d2-4642-81eb-225c81cf3afc |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71485 1009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.714851009 |
| Directory | /workspace/33.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/33.usbdev_pkt_sent.4034000233 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 8459654664 ps |
| CPU time | 7.13 seconds |
| Started | Feb 21 02:34:48 PM PST 24 |
| Finished | Feb 21 02:34:59 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-49a6d709-1d0d-477d-afa8-fe9b9679b5fd |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40340 00233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.4034000233 |
| Directory | /workspace/33.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/33.usbdev_smoke.158819996 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 8394834481 ps |
| CPU time | 7.99 seconds |
| Started | Feb 21 02:34:54 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-605b9637-9cc6-4161-8f3d-820fd8556eff |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15881 9996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.158819996 |
| Directory | /workspace/33.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/34.in_trans.3104036050 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 8392638550 ps |
| CPU time | 7.26 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-2e4cb44a-5ef5-4acb-ad55-7fe289fe5ad7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31040 36050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.in_trans.3104036050 |
| Directory | /workspace/34.in_trans/latest |
| Test location | /workspace/coverage/default/34.setup_trans_ignored.3094471486 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 8360832464 ps |
| CPU time | 9.11 seconds |
| Started | Feb 21 02:34:54 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-2e3b5f9f-82f0-4984-9148-d2272c9a2e7d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944 71486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.setup_trans_ignored.3094471486 |
| Directory | /workspace/34.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/34.usbdev_av_buffer.16199142 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 8368825020 ps |
| CPU time | 7.37 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-292a63a2-60aa-4429-b7b1-d802475e639c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16199 142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.16199142 |
| Directory | /workspace/34.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/34.usbdev_nak_trans.282780516 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8402709843 ps |
| CPU time | 7.69 seconds |
| Started | Feb 21 02:34:59 PM PST 24 |
| Finished | Feb 21 02:35:11 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-0ca87947-27a0-4986-a375-ff6c768a0f43 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28278 0516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.282780516 |
| Directory | /workspace/34.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/34.usbdev_pkt_sent.1609267524 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 8373936503 ps |
| CPU time | 9.45 seconds |
| Started | Feb 21 02:34:48 PM PST 24 |
| Finished | Feb 21 02:35:01 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-c30d4aeb-0a94-4d31-a64e-a0d7c7f15e33 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16092 67524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1609267524 |
| Directory | /workspace/34.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/34.usbdev_smoke.1177631957 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 8366198395 ps |
| CPU time | 7.39 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-9adbb5f1-be26-47a1-91f2-342b3d207780 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776 31957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1177631957 |
| Directory | /workspace/34.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/35.in_trans.3479751303 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 8412592386 ps |
| CPU time | 7.5 seconds |
| Started | Feb 21 02:35:05 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-5a215a7c-b60c-457f-b453-654d623f2c24 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34797 51303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.in_trans.3479751303 |
| Directory | /workspace/35.in_trans/latest |
| Test location | /workspace/coverage/default/35.setup_trans_ignored.1398581055 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 8359767399 ps |
| CPU time | 7.27 seconds |
| Started | Feb 21 02:35:01 PM PST 24 |
| Finished | Feb 21 02:35:12 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-ce456298-5b21-44e6-a891-082c8138a049 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13985 81055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.setup_trans_ignored.1398581055 |
| Directory | /workspace/35.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/35.usbdev_av_buffer.1821369441 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 8367205819 ps |
| CPU time | 7.17 seconds |
| Started | Feb 21 02:35:04 PM PST 24 |
| Finished | Feb 21 02:35:15 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-f7f26d06-c918-41d8-8b48-7e063a1ad9e1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18213 69441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1821369441 |
| Directory | /workspace/35.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/35.usbdev_pkt_sent.476601864 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 8423939874 ps |
| CPU time | 7.93 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:10 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-76106685-fd3e-41fc-902b-b3768fdca2b6 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47660 1864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.476601864 |
| Directory | /workspace/35.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/35.usbdev_smoke.2748905322 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 8389154683 ps |
| CPU time | 7.64 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:08 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-6ae712a3-5250-44bc-bd9c-8bf1f667c6a0 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489 05322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2748905322 |
| Directory | /workspace/35.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/36.in_trans.3568729486 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 8435450328 ps |
| CPU time | 7.7 seconds |
| Started | Feb 21 02:34:55 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202176 kb |
| Host | smart-6b8e4f30-9242-4c6f-8cec-52365262c8f8 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35687 29486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.in_trans.3568729486 |
| Directory | /workspace/36.in_trans/latest |
| Test location | /workspace/coverage/default/36.setup_trans_ignored.2935254930 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 8362399267 ps |
| CPU time | 7.17 seconds |
| Started | Feb 21 02:34:54 PM PST 24 |
| Finished | Feb 21 02:35:05 PM PST 24 |
| Peak memory | 202180 kb |
| Host | smart-b1e953a5-3892-4249-9494-a1b46edb2adc |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29352 54930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.setup_trans_ignored.2935254930 |
| Directory | /workspace/36.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/36.usbdev_smoke.3555769869 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 8392235330 ps |
| CPU time | 7 seconds |
| Started | Feb 21 02:35:05 PM PST 24 |
| Finished | Feb 21 02:35:15 PM PST 24 |
| Peak memory | 202028 kb |
| Host | smart-660f7e20-7136-4b5b-912f-64d1163f8cd7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557 69869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3555769869 |
| Directory | /workspace/36.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/37.in_trans.3816574281 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 8445094624 ps |
| CPU time | 8 seconds |
| Started | Feb 21 02:34:44 PM PST 24 |
| Finished | Feb 21 02:34:56 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-61acf37d-7ded-4dd6-92c8-15b3c244c864 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38165 74281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.in_trans.3816574281 |
| Directory | /workspace/37.in_trans/latest |
| Test location | /workspace/coverage/default/37.setup_trans_ignored.2282681670 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 8361034197 ps |
| CPU time | 7.55 seconds |
| Started | Feb 21 02:34:44 PM PST 24 |
| Finished | Feb 21 02:34:53 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-44acae93-26a1-4675-9c07-e9e3c4ac4fe1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22826 81670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.setup_trans_ignored.2282681670 |
| Directory | /workspace/37.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/37.usbdev_av_buffer.2955623313 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 8375889817 ps |
| CPU time | 7.02 seconds |
| Started | Feb 21 02:34:54 PM PST 24 |
| Finished | Feb 21 02:35:05 PM PST 24 |
| Peak memory | 201824 kb |
| Host | smart-7035cc3f-2b75-43e0-af49-0ba7d67bb044 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29556 23313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2955623313 |
| Directory | /workspace/37.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/37.usbdev_nak_trans.588647362 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 8428536577 ps |
| CPU time | 9.07 seconds |
| Started | Feb 21 02:34:47 PM PST 24 |
| Finished | Feb 21 02:34:58 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-13e82940-3f9f-4a08-bd2e-2115c38bccdf |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58864 7362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.588647362 |
| Directory | /workspace/37.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/37.usbdev_pkt_sent.117540423 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 8450381076 ps |
| CPU time | 7.81 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-6163411e-7aff-4fe0-a068-cde40225ae53 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11754 0423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.117540423 |
| Directory | /workspace/37.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/37.usbdev_smoke.1930383973 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8368860550 ps |
| CPU time | 8.06 seconds |
| Started | Feb 21 02:34:44 PM PST 24 |
| Finished | Feb 21 02:34:56 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-e3d8ff9f-c6de-424d-81a7-0d641decbcea |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19303 83973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1930383973 |
| Directory | /workspace/37.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/38.in_trans.2728822794 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8442185043 ps |
| CPU time | 8.17 seconds |
| Started | Feb 21 02:34:49 PM PST 24 |
| Finished | Feb 21 02:35:00 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-254f21f5-7aea-403f-b700-71b0fc7ea026 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27288 22794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.in_trans.2728822794 |
| Directory | /workspace/38.in_trans/latest |
| Test location | /workspace/coverage/default/38.setup_trans_ignored.2319126466 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 8358390888 ps |
| CPU time | 8.75 seconds |
| Started | Feb 21 02:34:49 PM PST 24 |
| Finished | Feb 21 02:35:01 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-6c57c117-5646-4b02-8767-83fd8b22c212 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191 26466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.setup_trans_ignored.2319126466 |
| Directory | /workspace/38.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/38.usbdev_av_buffer.526753584 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 8374569756 ps |
| CPU time | 8.02 seconds |
| Started | Feb 21 02:34:45 PM PST 24 |
| Finished | Feb 21 02:34:56 PM PST 24 |
| Peak memory | 202284 kb |
| Host | smart-c20e2475-d78b-4688-a896-adb2deaae7ba |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52675 3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.526753584 |
| Directory | /workspace/38.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/38.usbdev_nak_trans.42692553 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 8435830523 ps |
| CPU time | 8.47 seconds |
| Started | Feb 21 02:34:43 PM PST 24 |
| Finished | Feb 21 02:34:52 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-c6e4c5d1-c551-4a57-b7aa-2afaeb55131c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42692 553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.42692553 |
| Directory | /workspace/38.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/38.usbdev_pkt_sent.158411950 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 8468523072 ps |
| CPU time | 7.17 seconds |
| Started | Feb 21 02:34:54 PM PST 24 |
| Finished | Feb 21 02:35:05 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-07b7e660-1f80-4272-b74d-7f10ea89c185 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15841 1950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.158411950 |
| Directory | /workspace/38.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/38.usbdev_smoke.623785815 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 8386163148 ps |
| CPU time | 9.58 seconds |
| Started | Feb 21 02:34:45 PM PST 24 |
| Finished | Feb 21 02:34:58 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-0c29bfb1-82a5-4a38-a24a-71fe5115368e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62378 5815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.623785815 |
| Directory | /workspace/38.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/39.in_trans.500981401 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 8449065955 ps |
| CPU time | 8.09 seconds |
| Started | Feb 21 02:34:55 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-c19dd0f0-9b2f-4290-99a7-0f85d3416d93 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50098 1401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.in_trans.500981401 |
| Directory | /workspace/39.in_trans/latest |
| Test location | /workspace/coverage/default/39.setup_trans_ignored.1394294797 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 8358943696 ps |
| CPU time | 7.08 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-34489c9e-af10-4096-992c-b9100c8642af |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13942 94797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.setup_trans_ignored.1394294797 |
| Directory | /workspace/39.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/39.usbdev_av_buffer.2689124381 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8374447231 ps |
| CPU time | 7.84 seconds |
| Started | Feb 21 02:34:48 PM PST 24 |
| Finished | Feb 21 02:34:59 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-fd2caed3-1a9d-4cbe-b672-94bb0ce05652 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26891 24381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2689124381 |
| Directory | /workspace/39.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/39.usbdev_nak_trans.854418378 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8414038171 ps |
| CPU time | 7.76 seconds |
| Started | Feb 21 02:34:42 PM PST 24 |
| Finished | Feb 21 02:34:50 PM PST 24 |
| Peak memory | 202084 kb |
| Host | smart-070b5cc7-f9b4-4d65-8c02-662d0cc82584 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85441 8378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.854418378 |
| Directory | /workspace/39.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/39.usbdev_pkt_sent.3413701811 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 8421177681 ps |
| CPU time | 6.96 seconds |
| Started | Feb 21 02:34:55 PM PST 24 |
| Finished | Feb 21 02:35:05 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-19198212-05b2-4562-b2ec-cccd01815ebd |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34137 01811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3413701811 |
| Directory | /workspace/39.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/39.usbdev_smoke.3786882732 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 8373954466 ps |
| CPU time | 7.13 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-f59f6002-b638-40d9-a5b2-e995e828d87e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37868 82732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3786882732 |
| Directory | /workspace/39.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/4.in_trans.3237398955 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 8434954516 ps |
| CPU time | 7.31 seconds |
| Started | Feb 21 02:32:28 PM PST 24 |
| Finished | Feb 21 02:32:36 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-58e60e50-a002-4581-b56b-3d9062e5a058 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32373 98955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.in_trans.3237398955 |
| Directory | /workspace/4.in_trans/latest |
| Test location | /workspace/coverage/default/4.setup_trans_ignored.4012950711 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 8361652765 ps |
| CPU time | 7.5 seconds |
| Started | Feb 21 02:32:26 PM PST 24 |
| Finished | Feb 21 02:32:35 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-a2b4c445-d8c9-4f43-815d-c4f967d8b5aa |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40129 50711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.setup_trans_ignored.4012950711 |
| Directory | /workspace/4.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/4.usbdev_av_buffer.3730900038 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 8365786743 ps |
| CPU time | 7.45 seconds |
| Started | Feb 21 02:32:27 PM PST 24 |
| Finished | Feb 21 02:32:36 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-1c72f7f6-1878-4375-9768-bbac17c8fe16 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37309 00038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3730900038 |
| Directory | /workspace/4.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/4.usbdev_nak_trans.1687260843 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 8445511203 ps |
| CPU time | 7.19 seconds |
| Started | Feb 21 02:32:27 PM PST 24 |
| Finished | Feb 21 02:32:35 PM PST 24 |
| Peak memory | 202260 kb |
| Host | smart-c2cf33a5-681c-4d1f-9888-f1f25ebc13f2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16872 60843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1687260843 |
| Directory | /workspace/4.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/4.usbdev_pkt_sent.227446332 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 8413621245 ps |
| CPU time | 7.18 seconds |
| Started | Feb 21 02:32:26 PM PST 24 |
| Finished | Feb 21 02:32:35 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-531fd772-91bf-4a10-9d93-74d799207320 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22744 6332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.227446332 |
| Directory | /workspace/4.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/4.usbdev_sec_cm.3251228320 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 174427849 ps |
| CPU time | 0.93 seconds |
| Started | Feb 21 02:32:38 PM PST 24 |
| Finished | Feb 21 02:32:39 PM PST 24 |
| Peak memory | 216860 kb |
| Host | smart-586afd4c-d3a9-410c-8cd8-9b4c787ddc34 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3251228320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3251228320 |
| Directory | /workspace/4.usbdev_sec_cm/latest |
| Test location | /workspace/coverage/default/4.usbdev_smoke.2290415182 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 8378508572 ps |
| CPU time | 7.7 seconds |
| Started | Feb 21 02:32:29 PM PST 24 |
| Finished | Feb 21 02:32:37 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-b6e40f8d-7531-4377-ab35-87e639dd5b77 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22904 15182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2290415182 |
| Directory | /workspace/4.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/40.setup_trans_ignored.3523354797 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 8361679182 ps |
| CPU time | 7.77 seconds |
| Started | Feb 21 02:35:03 PM PST 24 |
| Finished | Feb 21 02:35:13 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-cb4fac8e-fdaf-4829-b459-02128a1e8a9d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35233 54797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.setup_trans_ignored.3523354797 |
| Directory | /workspace/40.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/40.usbdev_av_buffer.3450867849 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 8368808973 ps |
| CPU time | 9.29 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:09 PM PST 24 |
| Peak memory | 202264 kb |
| Host | smart-035c3120-7e9d-4cb1-8d01-a093f5535c27 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34508 67849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3450867849 |
| Directory | /workspace/40.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/40.usbdev_pkt_sent.2067150944 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 8419941100 ps |
| CPU time | 7.73 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:08 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-b8010141-1a24-403c-96dc-c5182d063bc7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671 50944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2067150944 |
| Directory | /workspace/40.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/40.usbdev_smoke.1224388700 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 8369712437 ps |
| CPU time | 7.25 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202248 kb |
| Host | smart-aa6fd21b-0921-49de-bfec-7b5643e0cddb |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12243 88700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1224388700 |
| Directory | /workspace/40.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/41.in_trans.3897624859 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 8402574723 ps |
| CPU time | 8.4 seconds |
| Started | Feb 21 02:35:01 PM PST 24 |
| Finished | Feb 21 02:35:13 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-1d29174d-8010-4a59-b392-f530c8582ab3 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38976 24859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.in_trans.3897624859 |
| Directory | /workspace/41.in_trans/latest |
| Test location | /workspace/coverage/default/41.setup_trans_ignored.2488908137 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 8363579488 ps |
| CPU time | 7.12 seconds |
| Started | Feb 21 02:35:02 PM PST 24 |
| Finished | Feb 21 02:35:12 PM PST 24 |
| Peak memory | 202164 kb |
| Host | smart-739a733f-86d5-4a03-aded-a3e95ca134f6 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24889 08137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.setup_trans_ignored.2488908137 |
| Directory | /workspace/41.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/41.usbdev_av_buffer.2424363343 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 8371627983 ps |
| CPU time | 7.48 seconds |
| Started | Feb 21 02:35:06 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 201724 kb |
| Host | smart-e7706b8a-b059-4335-9984-c28138707271 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243 63343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2424363343 |
| Directory | /workspace/41.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/41.usbdev_nak_trans.2991666029 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 8410082877 ps |
| CPU time | 7.41 seconds |
| Started | Feb 21 02:35:06 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-5df44fd0-8582-4327-abd9-4da9021128ab |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29916 66029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2991666029 |
| Directory | /workspace/41.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/41.usbdev_pkt_sent.4012124396 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 8390055458 ps |
| CPU time | 7.28 seconds |
| Started | Feb 21 02:34:59 PM PST 24 |
| Finished | Feb 21 02:35:10 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-9df19c6f-984c-4afa-a0d4-1119f015453b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121 24396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.4012124396 |
| Directory | /workspace/41.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/41.usbdev_smoke.1562898247 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 8374729319 ps |
| CPU time | 6.93 seconds |
| Started | Feb 21 02:35:01 PM PST 24 |
| Finished | Feb 21 02:35:11 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-538efdea-d1c6-42f7-84eb-5e740684d075 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15628 98247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1562898247 |
| Directory | /workspace/41.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/42.in_trans.2254510237 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 8435210215 ps |
| CPU time | 9.57 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:09 PM PST 24 |
| Peak memory | 202252 kb |
| Host | smart-c75dfeb6-0003-4c19-92cb-91166b20af74 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22545 10237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.in_trans.2254510237 |
| Directory | /workspace/42.in_trans/latest |
| Test location | /workspace/coverage/default/42.setup_trans_ignored.2617932772 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 8363488276 ps |
| CPU time | 9.28 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-acd7b59a-50c0-447c-8155-052eb465fe7b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179 32772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.setup_trans_ignored.2617932772 |
| Directory | /workspace/42.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/42.usbdev_av_buffer.1725953276 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8371793313 ps |
| CPU time | 7.8 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:08 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-2f20ecff-7c62-41e8-a66e-6f717210584d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17259 53276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1725953276 |
| Directory | /workspace/42.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/42.usbdev_pkt_sent.2898864268 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8397642983 ps |
| CPU time | 9.81 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:09 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-85ac6aeb-6e68-4743-9c55-7a7ff8a77943 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28988 64268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2898864268 |
| Directory | /workspace/42.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/42.usbdev_smoke.2261890137 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 8396064967 ps |
| CPU time | 7.54 seconds |
| Started | Feb 21 02:34:55 PM PST 24 |
| Finished | Feb 21 02:35:06 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-4e55715c-a998-40d9-b989-c808a63d9ad0 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22618 90137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2261890137 |
| Directory | /workspace/42.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/43.in_trans.3176374528 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 8431655922 ps |
| CPU time | 8.03 seconds |
| Started | Feb 21 02:35:00 PM PST 24 |
| Finished | Feb 21 02:35:12 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-93ca40e0-7494-4189-a312-8e89768675f1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31763 74528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.in_trans.3176374528 |
| Directory | /workspace/43.in_trans/latest |
| Test location | /workspace/coverage/default/43.setup_trans_ignored.784483585 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 8362798517 ps |
| CPU time | 7.43 seconds |
| Started | Feb 21 02:35:02 PM PST 24 |
| Finished | Feb 21 02:35:11 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-9ee10044-624c-444d-a9a2-1d85b6d03e38 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78448 3585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.setup_trans_ignored.784483585 |
| Directory | /workspace/43.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/43.usbdev_av_buffer.1091493613 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 8371358911 ps |
| CPU time | 8.01 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202104 kb |
| Host | smart-2e217e5e-6c18-48b6-b820-ac0f328e098f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10914 93613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1091493613 |
| Directory | /workspace/43.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/43.usbdev_nak_trans.2853899087 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 8449172322 ps |
| CPU time | 7.45 seconds |
| Started | Feb 21 02:35:00 PM PST 24 |
| Finished | Feb 21 02:35:11 PM PST 24 |
| Peak memory | 202172 kb |
| Host | smart-1801393a-b969-4e89-b41c-c40c8a05e1e2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28538 99087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2853899087 |
| Directory | /workspace/43.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/43.usbdev_smoke.2565404980 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 8370831397 ps |
| CPU time | 8.06 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:10 PM PST 24 |
| Peak memory | 202412 kb |
| Host | smart-b9b02553-1fa5-448f-ad8a-aff8ff9b255c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25654 04980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2565404980 |
| Directory | /workspace/43.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/44.in_trans.430613120 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 8417204535 ps |
| CPU time | 8.81 seconds |
| Started | Feb 21 02:35:13 PM PST 24 |
| Finished | Feb 21 02:35:26 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-59ae1ca5-39c6-42ec-8b25-4bcda7fae574 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43061 3120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.in_trans.430613120 |
| Directory | /workspace/44.in_trans/latest |
| Test location | /workspace/coverage/default/44.setup_trans_ignored.1138172942 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 8370622410 ps |
| CPU time | 7.71 seconds |
| Started | Feb 21 02:35:08 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-14b3bbd5-3be5-4eab-aad6-dfc0601682f2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11381 72942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.setup_trans_ignored.1138172942 |
| Directory | /workspace/44.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/44.usbdev_av_buffer.1171894653 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 8370873225 ps |
| CPU time | 7.08 seconds |
| Started | Feb 21 02:35:02 PM PST 24 |
| Finished | Feb 21 02:35:11 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-3d5b5801-e178-4a09-b881-9503025237e7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11718 94653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1171894653 |
| Directory | /workspace/44.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/44.usbdev_nak_trans.979746386 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 8398623598 ps |
| CPU time | 7.76 seconds |
| Started | Feb 21 02:35:13 PM PST 24 |
| Finished | Feb 21 02:35:25 PM PST 24 |
| Peak memory | 202148 kb |
| Host | smart-3442e269-4199-478b-90be-6dd711b1975f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97974 6386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.979746386 |
| Directory | /workspace/44.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/44.usbdev_smoke.4173030111 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8369919995 ps |
| CPU time | 7.81 seconds |
| Started | Feb 21 02:35:03 PM PST 24 |
| Finished | Feb 21 02:35:13 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-ff2f5746-56ea-442e-97b1-c00f667e357f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41730 30111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4173030111 |
| Directory | /workspace/44.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/45.in_trans.3813727733 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 8460621443 ps |
| CPU time | 7.78 seconds |
| Started | Feb 21 02:35:00 PM PST 24 |
| Finished | Feb 21 02:35:12 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-318b3ea7-a539-4108-96dd-38cdc1677811 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137 27733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.in_trans.3813727733 |
| Directory | /workspace/45.in_trans/latest |
| Test location | /workspace/coverage/default/45.setup_trans_ignored.365665126 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 8362140605 ps |
| CPU time | 9.12 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:09 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-29da2861-6c77-4ea4-8884-7433f021b57b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36566 5126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.setup_trans_ignored.365665126 |
| Directory | /workspace/45.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/45.usbdev_av_buffer.2697022492 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 8366234259 ps |
| CPU time | 7.31 seconds |
| Started | Feb 21 02:34:57 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-130bb462-6b8a-4796-9389-4d8c56830a8f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970 22492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2697022492 |
| Directory | /workspace/45.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/45.usbdev_nak_trans.1069838845 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 8424418873 ps |
| CPU time | 7.51 seconds |
| Started | Feb 21 02:35:06 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-be01a01d-73c6-44ce-9145-30e43d17f516 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10698 38845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1069838845 |
| Directory | /workspace/45.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/45.usbdev_pkt_sent.3814556820 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 8436002850 ps |
| CPU time | 7.82 seconds |
| Started | Feb 21 02:34:56 PM PST 24 |
| Finished | Feb 21 02:35:07 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-31a8dde6-b9d5-4cac-a97d-0afdfb921d81 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38145 56820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3814556820 |
| Directory | /workspace/45.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/45.usbdev_smoke.3693931503 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 8372686949 ps |
| CPU time | 7.23 seconds |
| Started | Feb 21 02:35:07 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 202212 kb |
| Host | smart-9295ee1b-1f6a-4f2e-8343-4400ab56fa82 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36939 31503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3693931503 |
| Directory | /workspace/45.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/46.in_trans.955954217 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 8392781291 ps |
| CPU time | 7.38 seconds |
| Started | Feb 21 02:35:01 PM PST 24 |
| Finished | Feb 21 02:35:12 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-af4dd3fe-99f0-46f2-8d97-e636d048f9a7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95595 4217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.in_trans.955954217 |
| Directory | /workspace/46.in_trans/latest |
| Test location | /workspace/coverage/default/46.setup_trans_ignored.3015059354 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 8354114097 ps |
| CPU time | 6.95 seconds |
| Started | Feb 21 02:35:01 PM PST 24 |
| Finished | Feb 21 02:35:11 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-f2a38657-8bd4-4788-aa5c-557c7f28a78b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150 59354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.setup_trans_ignored.3015059354 |
| Directory | /workspace/46.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/46.usbdev_av_buffer.461519197 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8366409830 ps |
| CPU time | 8.06 seconds |
| Started | Feb 21 02:35:01 PM PST 24 |
| Finished | Feb 21 02:35:13 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-75cb141a-4591-48fe-a641-1711ce01332f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46151 9197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.461519197 |
| Directory | /workspace/46.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/46.usbdev_nak_trans.1915618456 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8381897330 ps |
| CPU time | 7.94 seconds |
| Started | Feb 21 02:35:01 PM PST 24 |
| Finished | Feb 21 02:35:13 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-6ead40b9-7038-419f-b413-4dc37079d563 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156 18456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1915618456 |
| Directory | /workspace/46.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/46.usbdev_pkt_sent.87996638 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 8416010618 ps |
| CPU time | 7.21 seconds |
| Started | Feb 21 02:35:03 PM PST 24 |
| Finished | Feb 21 02:35:12 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-18b0df49-8597-46d4-92ef-6b7cdc61b51a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87996 638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.87996638 |
| Directory | /workspace/46.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/46.usbdev_smoke.1323446421 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 8367406172 ps |
| CPU time | 7.91 seconds |
| Started | Feb 21 02:35:04 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 202208 kb |
| Host | smart-92d857de-510f-4d39-b8e9-38a9aaafbfb5 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13234 46421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1323446421 |
| Directory | /workspace/46.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/47.in_trans.54922892 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 8406909199 ps |
| CPU time | 7.23 seconds |
| Started | Feb 21 02:35:08 PM PST 24 |
| Finished | Feb 21 02:35:16 PM PST 24 |
| Peak memory | 202408 kb |
| Host | smart-401841a4-256a-4850-81e4-848505379aac |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54922 892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.in_trans.54922892 |
| Directory | /workspace/47.in_trans/latest |
| Test location | /workspace/coverage/default/47.setup_trans_ignored.2052874098 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8355181428 ps |
| CPU time | 7.6 seconds |
| Started | Feb 21 02:35:03 PM PST 24 |
| Finished | Feb 21 02:35:14 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-b4aa46c5-6fd7-4073-bdfe-f1a11e30fedf |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20528 74098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.setup_trans_ignored.2052874098 |
| Directory | /workspace/47.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/47.usbdev_av_buffer.728228077 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 8376783810 ps |
| CPU time | 7.93 seconds |
| Started | Feb 21 02:35:13 PM PST 24 |
| Finished | Feb 21 02:35:25 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-75f0b58f-4e7d-481d-8721-de3a410a0444 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72822 8077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.728228077 |
| Directory | /workspace/47.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/47.usbdev_nak_trans.1230081819 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 8418235632 ps |
| CPU time | 7.33 seconds |
| Started | Feb 21 02:35:04 PM PST 24 |
| Finished | Feb 21 02:35:13 PM PST 24 |
| Peak memory | 202232 kb |
| Host | smart-ef2ee696-a641-40cc-a144-ae028ab2d83a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300 81819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1230081819 |
| Directory | /workspace/47.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/47.usbdev_pkt_sent.3415270001 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 8415259632 ps |
| CPU time | 7.09 seconds |
| Started | Feb 21 02:35:04 PM PST 24 |
| Finished | Feb 21 02:35:15 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-3dfa3ce2-ca04-4bcc-b08c-2c675d186b31 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34152 70001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3415270001 |
| Directory | /workspace/47.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/47.usbdev_smoke.1169536469 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 8372332728 ps |
| CPU time | 8.88 seconds |
| Started | Feb 21 02:35:15 PM PST 24 |
| Finished | Feb 21 02:35:27 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-c83d07b7-d41e-4175-aacf-a231edf4d0ae |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11695 36469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1169536469 |
| Directory | /workspace/47.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/48.in_trans.2112366599 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8412096958 ps |
| CPU time | 8.08 seconds |
| Started | Feb 21 02:35:25 PM PST 24 |
| Finished | Feb 21 02:35:33 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-9a1969a8-b33b-4f4d-b82c-fcd5b1732dad |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21123 66599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.in_trans.2112366599 |
| Directory | /workspace/48.in_trans/latest |
| Test location | /workspace/coverage/default/48.setup_trans_ignored.1753288773 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 8371973374 ps |
| CPU time | 7.44 seconds |
| Started | Feb 21 02:35:25 PM PST 24 |
| Finished | Feb 21 02:35:34 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-841d97b8-4826-4945-afc6-ee9a5d4f8ba0 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17532 88773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.setup_trans_ignored.1753288773 |
| Directory | /workspace/48.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/48.usbdev_av_buffer.4105669903 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 8370740376 ps |
| CPU time | 7.29 seconds |
| Started | Feb 21 02:35:19 PM PST 24 |
| Finished | Feb 21 02:35:27 PM PST 24 |
| Peak memory | 202228 kb |
| Host | smart-d92da286-7c22-4ddb-8cb8-910d013e736a |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41056 69903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.4105669903 |
| Directory | /workspace/48.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/48.usbdev_pkt_sent.649074640 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 8379021160 ps |
| CPU time | 7.32 seconds |
| Started | Feb 21 02:35:39 PM PST 24 |
| Finished | Feb 21 02:35:47 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-630942d2-6893-4fe6-a3db-caa9ecf35a3b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64907 4640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.649074640 |
| Directory | /workspace/48.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/48.usbdev_smoke.3075888204 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 8370136467 ps |
| CPU time | 7.68 seconds |
| Started | Feb 21 02:35:19 PM PST 24 |
| Finished | Feb 21 02:35:28 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-fb5ec0ff-e7c1-45f5-8e02-f0e0525ac860 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30758 88204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3075888204 |
| Directory | /workspace/48.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/49.in_trans.1710225607 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 8383722625 ps |
| CPU time | 7.43 seconds |
| Started | Feb 21 02:35:26 PM PST 24 |
| Finished | Feb 21 02:35:35 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-e5ad19ed-0348-4670-88e8-cdf593f37a6d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17102 25607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.in_trans.1710225607 |
| Directory | /workspace/49.in_trans/latest |
| Test location | /workspace/coverage/default/49.setup_trans_ignored.193860206 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 8359909325 ps |
| CPU time | 7.94 seconds |
| Started | Feb 21 02:35:28 PM PST 24 |
| Finished | Feb 21 02:35:37 PM PST 24 |
| Peak memory | 202180 kb |
| Host | smart-4d8e012d-49e8-4f5d-af3e-6d7c7a0ec30d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19386 0206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.setup_trans_ignored.193860206 |
| Directory | /workspace/49.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/49.usbdev_av_buffer.2001490626 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8369584625 ps |
| CPU time | 7.66 seconds |
| Started | Feb 21 02:35:27 PM PST 24 |
| Finished | Feb 21 02:35:35 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-45aa847b-0291-46df-a29e-b7115e278f56 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20014 90626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2001490626 |
| Directory | /workspace/49.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/49.usbdev_nak_trans.1419589037 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 8400965377 ps |
| CPU time | 7.25 seconds |
| Started | Feb 21 02:35:26 PM PST 24 |
| Finished | Feb 21 02:35:35 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-250792a5-9dae-4898-9002-c4dcc5186b10 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14195 89037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1419589037 |
| Directory | /workspace/49.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/49.usbdev_pkt_sent.449982833 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 8429408625 ps |
| CPU time | 9.2 seconds |
| Started | Feb 21 02:35:27 PM PST 24 |
| Finished | Feb 21 02:35:36 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-a498124f-07f9-48fe-b593-6c241e247f60 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44998 2833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.449982833 |
| Directory | /workspace/49.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/49.usbdev_smoke.3132951163 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 8373934730 ps |
| CPU time | 8.35 seconds |
| Started | Feb 21 02:35:28 PM PST 24 |
| Finished | Feb 21 02:35:37 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-b404678a-5051-43f0-9438-3b0afbb16bb7 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31329 51163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3132951163 |
| Directory | /workspace/49.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/5.in_trans.2357813589 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8400523492 ps |
| CPU time | 7.8 seconds |
| Started | Feb 21 02:32:42 PM PST 24 |
| Finished | Feb 21 02:32:50 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-64cb08cd-30bb-4bff-a099-12113c1b27f8 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23578 13589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.in_trans.2357813589 |
| Directory | /workspace/5.in_trans/latest |
| Test location | /workspace/coverage/default/5.setup_trans_ignored.4293031641 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8370217679 ps |
| CPU time | 8.64 seconds |
| Started | Feb 21 02:32:40 PM PST 24 |
| Finished | Feb 21 02:32:49 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-79a88398-9d71-48aa-a111-c2d74c7ef51c |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42930 31641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.setup_trans_ignored.4293031641 |
| Directory | /workspace/5.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/5.usbdev_av_buffer.827819729 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 8376905625 ps |
| CPU time | 9.91 seconds |
| Started | Feb 21 02:32:39 PM PST 24 |
| Finished | Feb 21 02:32:49 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-7742de75-642f-493e-be71-5aad76428f4e |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82781 9729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.827819729 |
| Directory | /workspace/5.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/5.usbdev_pkt_sent.2505468276 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 8384277470 ps |
| CPU time | 8.61 seconds |
| Started | Feb 21 02:32:38 PM PST 24 |
| Finished | Feb 21 02:32:47 PM PST 24 |
| Peak memory | 202288 kb |
| Host | smart-5f71225a-24d3-457f-bb7f-5a47aaa77465 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25054 68276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2505468276 |
| Directory | /workspace/5.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/5.usbdev_smoke.2971567686 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 8369228699 ps |
| CPU time | 9.59 seconds |
| Started | Feb 21 02:32:38 PM PST 24 |
| Finished | Feb 21 02:32:48 PM PST 24 |
| Peak memory | 202204 kb |
| Host | smart-3c0b3e86-d511-414f-b511-221043fdd921 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29715 67686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2971567686 |
| Directory | /workspace/5.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/6.in_trans.2976072911 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 8476597582 ps |
| CPU time | 7.91 seconds |
| Started | Feb 21 02:32:44 PM PST 24 |
| Finished | Feb 21 02:32:52 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-e8075027-cb37-4abd-8561-d2cd23f7a989 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760 72911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.in_trans.2976072911 |
| Directory | /workspace/6.in_trans/latest |
| Test location | /workspace/coverage/default/6.setup_trans_ignored.2761999746 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 8375497637 ps |
| CPU time | 8.87 seconds |
| Started | Feb 21 02:32:47 PM PST 24 |
| Finished | Feb 21 02:32:56 PM PST 24 |
| Peak memory | 202032 kb |
| Host | smart-ab162302-7006-43f6-992c-61a788b3260f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27619 99746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.setup_trans_ignored.2761999746 |
| Directory | /workspace/6.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/6.usbdev_av_buffer.3823289674 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8377863065 ps |
| CPU time | 6.89 seconds |
| Started | Feb 21 02:32:38 PM PST 24 |
| Finished | Feb 21 02:32:45 PM PST 24 |
| Peak memory | 202192 kb |
| Host | smart-e03a75ca-a211-4f14-87ef-65626989130f |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38232 89674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3823289674 |
| Directory | /workspace/6.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/6.usbdev_nak_trans.865986419 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8441771023 ps |
| CPU time | 7.51 seconds |
| Started | Feb 21 02:32:43 PM PST 24 |
| Finished | Feb 21 02:32:51 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-b8b12e0e-5c6f-4f6f-8099-ee3290e13341 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86598 6419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.865986419 |
| Directory | /workspace/6.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/6.usbdev_pkt_sent.509253795 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 8381825132 ps |
| CPU time | 7.72 seconds |
| Started | Feb 21 02:32:42 PM PST 24 |
| Finished | Feb 21 02:32:50 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-9d9b6d57-1921-4538-956d-a4ec175c4ec5 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50925 3795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.509253795 |
| Directory | /workspace/6.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/6.usbdev_smoke.2272371961 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 8379351765 ps |
| CPU time | 9.7 seconds |
| Started | Feb 21 02:32:39 PM PST 24 |
| Finished | Feb 21 02:32:49 PM PST 24 |
| Peak memory | 202200 kb |
| Host | smart-8355b19d-53f1-4b45-b60d-8c6af6e58179 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22723 71961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2272371961 |
| Directory | /workspace/6.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/7.in_trans.2014725943 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 8456665241 ps |
| CPU time | 7.97 seconds |
| Started | Feb 21 02:32:43 PM PST 24 |
| Finished | Feb 21 02:32:51 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-eaa04723-2588-462b-aabc-6e3bdb3efb3d |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20147 25943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.in_trans.2014725943 |
| Directory | /workspace/7.in_trans/latest |
| Test location | /workspace/coverage/default/7.setup_trans_ignored.2023503526 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 8359845324 ps |
| CPU time | 7.63 seconds |
| Started | Feb 21 02:32:43 PM PST 24 |
| Finished | Feb 21 02:32:50 PM PST 24 |
| Peak memory | 202196 kb |
| Host | smart-40688168-2350-484e-b915-4f034c712736 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20235 03526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.setup_trans_ignored.2023503526 |
| Directory | /workspace/7.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/7.usbdev_av_buffer.649530559 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 8441590156 ps |
| CPU time | 7.73 seconds |
| Started | Feb 21 02:32:42 PM PST 24 |
| Finished | Feb 21 02:32:50 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-34bfcf09-4a6d-48e5-9ea8-6c8f11634092 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64953 0559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.649530559 |
| Directory | /workspace/7.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/7.usbdev_nak_trans.1655395924 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 8443465858 ps |
| CPU time | 7 seconds |
| Started | Feb 21 02:32:43 PM PST 24 |
| Finished | Feb 21 02:32:50 PM PST 24 |
| Peak memory | 202240 kb |
| Host | smart-ab372475-9053-451d-9b51-cb4e4fd53963 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16553 95924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1655395924 |
| Directory | /workspace/7.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/7.usbdev_pkt_sent.1752181263 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 8432656146 ps |
| CPU time | 7.28 seconds |
| Started | Feb 21 02:32:45 PM PST 24 |
| Finished | Feb 21 02:32:53 PM PST 24 |
| Peak memory | 202188 kb |
| Host | smart-a0d81254-55b8-45b6-a611-7d09b15857cf |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17521 81263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1752181263 |
| Directory | /workspace/7.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/7.usbdev_smoke.522968180 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 8384131665 ps |
| CPU time | 7.31 seconds |
| Started | Feb 21 02:32:44 PM PST 24 |
| Finished | Feb 21 02:32:52 PM PST 24 |
| Peak memory | 202244 kb |
| Host | smart-2c744aa2-d860-4c25-b59b-597a04984535 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52296 8180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.522968180 |
| Directory | /workspace/7.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/8.in_trans.896880230 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 8449282836 ps |
| CPU time | 7.73 seconds |
| Started | Feb 21 02:32:56 PM PST 24 |
| Finished | Feb 21 02:33:04 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-2b245252-7358-4fcd-8586-4b3939d5c380 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89688 0230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.in_trans.896880230 |
| Directory | /workspace/8.in_trans/latest |
| Test location | /workspace/coverage/default/8.usbdev_av_buffer.1994249785 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 8368138871 ps |
| CPU time | 7.99 seconds |
| Started | Feb 21 02:32:39 PM PST 24 |
| Finished | Feb 21 02:32:48 PM PST 24 |
| Peak memory | 202260 kb |
| Host | smart-23ef6bd3-ab2a-40e0-af2e-0fd0e46b7ac1 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19942 49785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1994249785 |
| Directory | /workspace/8.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/8.usbdev_nak_trans.1172547736 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 8398606321 ps |
| CPU time | 7.66 seconds |
| Started | Feb 21 02:32:46 PM PST 24 |
| Finished | Feb 21 02:32:54 PM PST 24 |
| Peak memory | 202184 kb |
| Host | smart-a557070c-faf3-46e1-9ef2-f4fa3a42b172 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11725 47736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1172547736 |
| Directory | /workspace/8.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/8.usbdev_pkt_sent.4116455064 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 8386000425 ps |
| CPU time | 7.9 seconds |
| Started | Feb 21 02:32:42 PM PST 24 |
| Finished | Feb 21 02:32:50 PM PST 24 |
| Peak memory | 202216 kb |
| Host | smart-52bc54c5-1e2f-4f06-a3c0-aa2e5dbecc48 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164 55064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.4116455064 |
| Directory | /workspace/8.usbdev_pkt_sent/latest |
| Test location | /workspace/coverage/default/8.usbdev_smoke.87716460 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 8379856486 ps |
| CPU time | 8.25 seconds |
| Started | Feb 21 02:32:42 PM PST 24 |
| Finished | Feb 21 02:32:51 PM PST 24 |
| Peak memory | 202404 kb |
| Host | smart-3909a97b-1d4f-4b65-a89f-2d718ad07aa4 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87716 460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.87716460 |
| Directory | /workspace/8.usbdev_smoke/latest |
| Test location | /workspace/coverage/default/9.in_trans.3136730368 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 8373966728 ps |
| CPU time | 7.11 seconds |
| Started | Feb 21 02:32:50 PM PST 24 |
| Finished | Feb 21 02:32:57 PM PST 24 |
| Peak memory | 202224 kb |
| Host | smart-e384603b-08de-4d54-8c0e-b407d62f73e2 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367 30368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.in_trans.3136730368 |
| Directory | /workspace/9.in_trans/latest |
| Test location | /workspace/coverage/default/9.setup_trans_ignored.174082619 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 8359129037 ps |
| CPU time | 7.56 seconds |
| Started | Feb 21 02:32:54 PM PST 24 |
| Finished | Feb 21 02:33:01 PM PST 24 |
| Peak memory | 202220 kb |
| Host | smart-71191212-b9e9-4f24-8bca-786376d1d8a5 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17408 2619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.setup_trans_ignored.174082619 |
| Directory | /workspace/9.setup_trans_ignored/latest |
| Test location | /workspace/coverage/default/9.usbdev_av_buffer.2040213842 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 8371605577 ps |
| CPU time | 9.58 seconds |
| Started | Feb 21 02:32:54 PM PST 24 |
| Finished | Feb 21 02:33:04 PM PST 24 |
| Peak memory | 202236 kb |
| Host | smart-1726ce6d-f023-48cc-b6a7-9f3af1ee4c94 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402 13842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2040213842 |
| Directory | /workspace/9.usbdev_av_buffer/latest |
| Test location | /workspace/coverage/default/9.usbdev_nak_trans.3495620556 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 8441697429 ps |
| CPU time | 7.53 seconds |
| Started | Feb 21 02:32:51 PM PST 24 |
| Finished | Feb 21 02:32:59 PM PST 24 |
| Peak memory | 202084 kb |
| Host | smart-8a1d5625-7e35-4aa5-8ae3-560801b0908b |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34956 20556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3495620556 |
| Directory | /workspace/9.usbdev_nak_trans/latest |
| Test location | /workspace/coverage/default/9.usbdev_smoke.525068735 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 8366631424 ps |
| CPU time | 8.03 seconds |
| Started | Feb 21 02:32:49 PM PST 24 |
| Finished | Feb 21 02:32:57 PM PST 24 |
| Peak memory | 202168 kb |
| Host | smart-d9f3bb3e-4560-4a44-92ae-8b1f1a461f31 |
| User | root |
| Command | /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52506 8735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.525068735 |
| Directory | /workspace/9.usbdev_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |