Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	1	21	95.45
Crosses	72	52	20	27.78

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	1	1	50.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	52	20	27.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	633	1		T1	3		T2	2		T3	1
all_values[1]	633	1		T1	3		T2	2		T3	1
all_values[2]	633	1		T1	3		T2	2		T3	1
all_values[3]	633	1		T1	3		T2	2		T3	1
all_values[4]	633	1		T1	3		T2	2		T3	1
all_values[5]	633	1		T1	3		T2	2		T3	1
all_values[6]	633	1		T1	3		T2	2		T3	1
all_values[7]	633	1		T1	3		T2	2		T3	1
all_values[8]	633	1		T1	3		T2	2		T3	1
all_values[9]	633	1		T1	3		T2	2		T3	1
all_values[10]	633	1		T1	3		T2	2		T3	1
all_values[11]	633	1		T1	3		T2	2		T3	1
all_values[12]	633	1		T1	3		T2	2		T3	1
all_values[13]	633	1		T1	3		T2	2		T3	1
all_values[14]	633	1		T1	3		T2	2		T3	1
all_values[15]	633	1		T1	3		T2	2		T3	1
all_values[16]	633	1		T1	3		T2	2		T3	1
all_values[17]	633	1		T1	3		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	11061	1		T1	52		T2	34		T3	18
auto[1]	333	1		T1	2		T2	2		T4	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_intr_state

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	11394	1		T1	54		T2	36		T3	18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	52	20	27.78	52

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[1]]	--	--	4
[all_values[2] , all_values[3] , all_values[4] , all_values[5] , all_values[6] , all_values[7] , all_values[8] , all_values[9] , all_values[10] , all_values[11] , all_values[12] , all_values[13] , all_values[14] , all_values[15] , all_values[16] , all_values[17]]	[auto[1]]	*	--	--	32

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[2] , all_values[3] , all_values[4] , all_values[5] , all_values[6] , all_values[7] , all_values[8] , all_values[9] , all_values[10] , all_values[11] , all_values[12] , all_values[13] , all_values[14] , all_values[15] , all_values[16] , all_values[17]]	[auto[0]]	[auto[1]]	--	--	16

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	490	1		T1	3		T3	1		T4	3
all_values[0]	auto[1]	auto[0]	143	1		T2	2		T5	1		T7	1
all_values[1]	auto[0]	auto[0]	443	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[0]	190	1		T1	2		T4	2		T6	2
all_values[2]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[3]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[4]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[5]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[6]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[7]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[8]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[9]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[10]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[11]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[12]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[13]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[14]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[15]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[16]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1
all_values[17]	auto[0]	auto[0]	633	1		T1	3		T2	2		T3	1