Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	24	0	0.00
Crosses	108	108	0	0.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	18	0	0.00	100	1	1	0
cp_intr_en	2	2	0	0.00	100	1	1	2
cp_intr_state	2	2	0	0.00	100	1	1	2
cp_intr_test	2	2	0	0.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	108	0	0.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	18	0	0.00

User Defined Bins for cp_intr

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
all_values[0]	0	1	1
all_values[1]	0	1	1
all_values[2]	0	1	1
all_values[3]	0	1	1
all_values[4]	0	1	1
all_values[5]	0	1	1
all_values[6]	0	1	1
all_values[7]	0	1	1
all_values[8]	0	1	1
all_values[9]	0	1	1
all_values[10]	0	1	1
all_values[11]	0	1	1
all_values[12]	0	1	1
all_values[13]	0	1	1
all_values[14]	0	1	1
all_values[15]	0	1	1
all_values[16]	0	1	1
all_values[17]	0	1	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_intr_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_intr_state

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_intr_test

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	108	0	0.00	108
Automatically Generated Cross Bins	108	108	0	0.00	108
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
*	[auto[0]]	*	*	--	--	72
*	[auto[1]]	*	[auto[1]]	--	--	36

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal