Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.31 95.69 85.84 97.16 45.31 93.76 97.36 54.05


Total test records in report: 402
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T317 /workspace/coverage/default/5.usbdev_smoke.938093910 Feb 25 12:35:18 PM PST 24 Feb 25 12:35:26 PM PST 24 8372049626 ps
T318 /workspace/coverage/default/36.setup_trans_ignored.2675100877 Feb 25 12:36:20 PM PST 24 Feb 25 12:36:28 PM PST 24 8359563990 ps
T319 /workspace/coverage/default/16.usbdev_av_buffer.3178122323 Feb 25 12:35:46 PM PST 24 Feb 25 12:35:54 PM PST 24 8384480160 ps
T320 /workspace/coverage/default/0.usbdev_pkt_sent.3232290356 Feb 25 12:35:15 PM PST 24 Feb 25 12:35:23 PM PST 24 8447414686 ps
T321 /workspace/coverage/default/6.setup_trans_ignored.2905720239 Feb 25 12:35:16 PM PST 24 Feb 25 12:35:25 PM PST 24 8356487980 ps
T322 /workspace/coverage/default/37.setup_trans_ignored.3535136333 Feb 25 12:36:36 PM PST 24 Feb 25 12:36:44 PM PST 24 8357518563 ps
T234 /workspace/coverage/default/17.usbdev_smoke.185323216 Feb 25 12:35:59 PM PST 24 Feb 25 12:36:09 PM PST 24 8379233185 ps
T93 /workspace/coverage/default/49.usbdev_pkt_sent.3940937264 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:12 PM PST 24 8442070199 ps
T323 /workspace/coverage/default/1.usbdev_smoke.3429222243 Feb 25 12:35:17 PM PST 24 Feb 25 12:35:25 PM PST 24 8373448403 ps
T324 /workspace/coverage/default/3.setup_trans_ignored.1190037966 Feb 25 12:35:16 PM PST 24 Feb 25 12:35:25 PM PST 24 8362466683 ps
T149 /workspace/coverage/default/40.in_trans.1805522456 Feb 25 12:37:06 PM PST 24 Feb 25 12:37:14 PM PST 24 8449265110 ps
T38 /workspace/coverage/default/4.usbdev_sec_cm.3477723472 Feb 25 12:35:29 PM PST 24 Feb 25 12:35:31 PM PST 24 103486132 ps
T210 /workspace/coverage/default/9.usbdev_av_buffer.1821898996 Feb 25 12:35:47 PM PST 24 Feb 25 12:35:54 PM PST 24 8370275186 ps
T75 /workspace/coverage/default/19.usbdev_nak_trans.1664610859 Feb 25 12:35:53 PM PST 24 Feb 25 12:36:01 PM PST 24 8433804920 ps
T325 /workspace/coverage/default/13.setup_trans_ignored.2004375395 Feb 25 12:35:43 PM PST 24 Feb 25 12:35:51 PM PST 24 8358553433 ps
T146 /workspace/coverage/default/10.usbdev_pkt_sent.375895864 Feb 25 12:35:39 PM PST 24 Feb 25 12:35:47 PM PST 24 8441647675 ps
T326 /workspace/coverage/default/10.setup_trans_ignored.988287977 Feb 25 12:35:36 PM PST 24 Feb 25 12:35:43 PM PST 24 8357389445 ps
T327 /workspace/coverage/default/19.usbdev_pkt_sent.3662778273 Feb 25 12:35:52 PM PST 24 Feb 25 12:35:59 PM PST 24 8409172419 ps
T328 /workspace/coverage/default/46.usbdev_pkt_sent.3891346518 Feb 25 12:36:51 PM PST 24 Feb 25 12:36:59 PM PST 24 8403420543 ps
T329 /workspace/coverage/default/8.in_trans.1604196581 Feb 25 12:35:29 PM PST 24 Feb 25 12:35:39 PM PST 24 8444362633 ps
T239 /workspace/coverage/default/11.usbdev_pkt_sent.2962395860 Feb 25 12:35:31 PM PST 24 Feb 25 12:35:43 PM PST 24 8450172280 ps
T330 /workspace/coverage/default/2.usbdev_av_buffer.823003805 Feb 25 12:35:28 PM PST 24 Feb 25 12:35:36 PM PST 24 8463852600 ps
T331 /workspace/coverage/default/43.usbdev_av_buffer.2388926494 Feb 25 12:36:39 PM PST 24 Feb 25 12:36:48 PM PST 24 8396296791 ps
T332 /workspace/coverage/default/21.setup_trans_ignored.3271481950 Feb 25 12:36:06 PM PST 24 Feb 25 12:36:17 PM PST 24 8362766692 ps
T148 /workspace/coverage/default/36.in_trans.2899081307 Feb 25 12:36:35 PM PST 24 Feb 25 12:36:43 PM PST 24 8444515058 ps
T333 /workspace/coverage/default/46.usbdev_smoke.340634027 Feb 25 12:36:45 PM PST 24 Feb 25 12:36:53 PM PST 24 8369178506 ps
T334 /workspace/coverage/default/2.in_trans.2939014562 Feb 25 12:35:20 PM PST 24 Feb 25 12:35:28 PM PST 24 8377582236 ps
T47 /workspace/coverage/default/1.usbdev_sec_cm.1667208592 Feb 25 12:35:16 PM PST 24 Feb 25 12:35:18 PM PST 24 171029587 ps
T245 /workspace/coverage/default/5.usbdev_pkt_sent.2100684496 Feb 25 12:35:39 PM PST 24 Feb 25 12:35:47 PM PST 24 8385300311 ps
T145 /workspace/coverage/default/16.in_trans.3391509043 Feb 25 12:36:04 PM PST 24 Feb 25 12:36:15 PM PST 24 8448453393 ps
T71 /workspace/coverage/default/16.usbdev_nak_trans.1989197836 Feb 25 12:35:54 PM PST 24 Feb 25 12:36:02 PM PST 24 8421962201 ps
T335 /workspace/coverage/default/49.in_trans.651095655 Feb 25 12:37:17 PM PST 24 Feb 25 12:37:24 PM PST 24 8439463466 ps
T336 /workspace/coverage/default/23.usbdev_smoke.197283859 Feb 25 12:36:04 PM PST 24 Feb 25 12:36:12 PM PST 24 8371590874 ps
T337 /workspace/coverage/default/49.usbdev_nak_trans.4285099205 Feb 25 12:36:58 PM PST 24 Feb 25 12:37:05 PM PST 24 8407863699 ps
T338 /workspace/coverage/default/28.usbdev_pkt_sent.379624021 Feb 25 12:36:11 PM PST 24 Feb 25 12:36:21 PM PST 24 8406386516 ps
T339 /workspace/coverage/default/34.usbdev_pkt_sent.481929678 Feb 25 12:36:48 PM PST 24 Feb 25 12:36:58 PM PST 24 8436110296 ps
T340 /workspace/coverage/default/37.usbdev_av_buffer.1243718363 Feb 25 12:37:03 PM PST 24 Feb 25 12:37:10 PM PST 24 8373100174 ps
T121 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2791227241 Feb 25 01:41:05 PM PST 24 Feb 25 01:41:07 PM PST 24 95548078 ps
T34 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3842410614 Feb 25 01:41:41 PM PST 24 Feb 25 01:41:45 PM PST 24 215107825 ps
T42 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2271803022 Feb 25 01:40:42 PM PST 24 Feb 25 01:40:43 PM PST 24 46444920 ps
T43 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2205651290 Feb 25 01:41:16 PM PST 24 Feb 25 01:41:19 PM PST 24 153573455 ps
T35 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1695279715 Feb 25 01:41:22 PM PST 24 Feb 25 01:41:25 PM PST 24 296906586 ps
T44 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2944009196 Feb 25 01:41:17 PM PST 24 Feb 25 01:41:19 PM PST 24 108588492 ps
T36 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2383889642 Feb 25 01:41:27 PM PST 24 Feb 25 01:41:31 PM PST 24 219715988 ps
T56 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2720917230 Feb 25 01:41:39 PM PST 24 Feb 25 01:41:42 PM PST 24 155560612 ps
T57 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1375262833 Feb 25 01:41:13 PM PST 24 Feb 25 01:41:15 PM PST 24 126169534 ps
T58 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1081968041 Feb 25 01:41:43 PM PST 24 Feb 25 01:41:49 PM PST 24 327039745 ps
T59 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2488928714 Feb 25 01:41:17 PM PST 24 Feb 25 01:41:20 PM PST 24 305759988 ps
T114 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.34347905 Feb 25 01:41:15 PM PST 24 Feb 25 01:41:18 PM PST 24 267262842 ps
T138 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1330699532 Feb 25 01:41:14 PM PST 24 Feb 25 01:41:16 PM PST 24 75014950 ps
T115 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2202560232 Feb 25 01:41:29 PM PST 24 Feb 25 01:41:34 PM PST 24 325843307 ps
T116 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4170863420 Feb 25 01:41:47 PM PST 24 Feb 25 01:41:50 PM PST 24 71972788 ps
T117 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.55124287 Feb 25 01:41:29 PM PST 24 Feb 25 01:41:32 PM PST 24 81561489 ps
T122 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.593683504 Feb 25 01:41:31 PM PST 24 Feb 25 01:41:33 PM PST 24 248368627 ps
T139 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1839365179 Feb 25 01:40:46 PM PST 24 Feb 25 01:40:49 PM PST 24 120259687 ps
T123 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4183447475 Feb 25 01:41:37 PM PST 24 Feb 25 01:41:39 PM PST 24 80855241 ps
T118 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2668671015 Feb 25 01:41:17 PM PST 24 Feb 25 01:41:19 PM PST 24 151054200 ps
T158 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4141890231 Feb 25 01:41:29 PM PST 24 Feb 25 01:41:33 PM PST 24 306390818 ps
T119 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.465115237 Feb 25 01:41:42 PM PST 24 Feb 25 01:41:46 PM PST 24 347445730 ps
T120 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.434190871 Feb 25 01:40:45 PM PST 24 Feb 25 01:40:48 PM PST 24 98488397 ps
T157 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2206973732 Feb 25 01:41:41 PM PST 24 Feb 25 01:41:47 PM PST 24 273500129 ps
T124 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3993812231 Feb 25 01:41:32 PM PST 24 Feb 25 01:41:33 PM PST 24 55642552 ps
T341 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3298141860 Feb 25 01:41:42 PM PST 24 Feb 25 01:41:47 PM PST 24 341048157 ps
T342 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.964492156 Feb 25 01:41:31 PM PST 24 Feb 25 01:41:33 PM PST 24 122285191 ps
T125 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1747527949 Feb 25 01:41:02 PM PST 24 Feb 25 01:41:04 PM PST 24 31058924 ps
T155 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.616823809 Feb 25 01:41:30 PM PST 24 Feb 25 01:41:32 PM PST 24 228596274 ps
T126 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1967206058 Feb 25 01:41:38 PM PST 24 Feb 25 01:41:41 PM PST 24 61852843 ps
T343 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1607617811 Feb 25 01:41:13 PM PST 24 Feb 25 01:41:17 PM PST 24 350271377 ps
T127 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1109494883 Feb 25 01:41:20 PM PST 24 Feb 25 01:41:21 PM PST 24 48054617 ps
T159 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3548992179 Feb 25 01:41:28 PM PST 24 Feb 25 01:41:31 PM PST 24 275957817 ps
T153 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1772093738 Feb 25 01:41:28 PM PST 24 Feb 25 01:41:31 PM PST 24 195706262 ps
T344 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3257743650 Feb 25 01:40:44 PM PST 24 Feb 25 01:40:46 PM PST 24 198157532 ps
T128 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1148425194 Feb 25 01:40:43 PM PST 24 Feb 25 01:40:51 PM PST 24 353857363 ps
T129 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3964110536 Feb 25 01:41:15 PM PST 24 Feb 25 01:41:16 PM PST 24 70093261 ps
T163 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2191931419 Feb 25 01:41:00 PM PST 24 Feb 25 01:41:03 PM PST 24 271802405 ps
T345 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2914809557 Feb 25 01:41:18 PM PST 24 Feb 25 01:41:20 PM PST 24 32264459 ps
T346 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.189161656 Feb 25 01:40:59 PM PST 24 Feb 25 01:41:01 PM PST 24 74262659 ps
T347 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2353912226 Feb 25 01:41:28 PM PST 24 Feb 25 01:41:30 PM PST 24 125247121 ps
T348 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3673868174 Feb 25 01:41:28 PM PST 24 Feb 25 01:41:30 PM PST 24 52791220 ps
T154 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3569135604 Feb 25 01:41:13 PM PST 24 Feb 25 01:41:15 PM PST 24 180869311 ps
T349 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3041468693 Feb 25 01:41:29 PM PST 24 Feb 25 01:41:31 PM PST 24 179466626 ps
T350 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1539830484 Feb 25 01:40:42 PM PST 24 Feb 25 01:40:46 PM PST 24 472954569 ps
T130 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1612282237 Feb 25 01:41:14 PM PST 24 Feb 25 01:41:16 PM PST 24 36616485 ps
T351 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.610782751 Feb 25 01:41:12 PM PST 24 Feb 25 01:41:14 PM PST 24 69268987 ps
T352 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2448682034 Feb 25 01:41:17 PM PST 24 Feb 25 01:41:19 PM PST 24 194624416 ps
T131 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2467937858 Feb 25 01:41:14 PM PST 24 Feb 25 01:41:15 PM PST 24 33226421 ps
T46 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.149083201 Feb 25 01:41:05 PM PST 24 Feb 25 01:41:06 PM PST 24 39423907 ps
T353 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3848010260 Feb 25 01:41:01 PM PST 24 Feb 25 01:41:03 PM PST 24 134485000 ps
T132 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3758021405 Feb 25 01:40:42 PM PST 24 Feb 25 01:40:43 PM PST 24 55670548 ps
T354 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.447271039 Feb 25 01:41:38 PM PST 24 Feb 25 01:41:39 PM PST 24 73958881 ps
T355 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2754939224 Feb 25 01:40:58 PM PST 24 Feb 25 01:41:01 PM PST 24 177460027 ps
T160 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.998561888 Feb 25 01:41:13 PM PST 24 Feb 25 01:41:17 PM PST 24 214026584 ps
T356 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2597868483 Feb 25 01:41:42 PM PST 24 Feb 25 01:41:46 PM PST 24 192858183 ps
T357 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1834529582 Feb 25 01:40:42 PM PST 24 Feb 25 01:40:44 PM PST 24 94487367 ps
T358 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4005526039 Feb 25 01:41:20 PM PST 24 Feb 25 01:41:24 PM PST 24 306210470 ps
T359 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2842654712 Feb 25 01:41:28 PM PST 24 Feb 25 01:41:30 PM PST 24 94062088 ps
T360 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.254361967 Feb 25 01:41:12 PM PST 24 Feb 25 01:41:15 PM PST 24 214717328 ps
T361 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.604635741 Feb 25 01:41:32 PM PST 24 Feb 25 01:41:36 PM PST 24 236931717 ps
T362 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3382072601 Feb 25 01:41:13 PM PST 24 Feb 25 01:41:16 PM PST 24 258392824 ps
T363 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1082068256 Feb 25 01:41:30 PM PST 24 Feb 25 01:41:33 PM PST 24 83878725 ps
T133 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3329813636 Feb 25 01:41:00 PM PST 24 Feb 25 01:41:01 PM PST 24 51151545 ps
T161 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2282141059 Feb 25 01:41:28 PM PST 24 Feb 25 01:41:31 PM PST 24 122690920 ps
T364 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2397913280 Feb 25 01:41:04 PM PST 24 Feb 25 01:41:07 PM PST 24 117988053 ps
T365 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3018649327 Feb 25 01:41:18 PM PST 24 Feb 25 01:41:20 PM PST 24 76439843 ps
T134 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2791563697 Feb 25 01:41:13 PM PST 24 Feb 25 01:41:14 PM PST 24 44728561 ps
T366 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.277826128 Feb 25 01:40:42 PM PST 24 Feb 25 01:40:44 PM PST 24 68504241 ps
T135 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2047057963 Feb 25 01:41:15 PM PST 24 Feb 25 01:41:19 PM PST 24 157439326 ps
T367 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4056860856 Feb 25 01:40:41 PM PST 24 Feb 25 01:40:43 PM PST 24 157296804 ps
T368 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1708327504 Feb 25 01:41:17 PM PST 24 Feb 25 01:41:20 PM PST 24 263139993 ps
T369 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.80309771 Feb 25 01:41:18 PM PST 24 Feb 25 01:41:24 PM PST 24 128094779 ps
T370 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1778224491 Feb 25 01:40:42 PM PST 24 Feb 25 01:40:45 PM PST 24 111122827 ps
T371 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2868972213 Feb 25 01:40:44 PM PST 24 Feb 25 01:40:45 PM PST 24 173833112 ps
T372 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2186994756 Feb 25 01:41:29 PM PST 24 Feb 25 01:41:33 PM PST 24 94844442 ps
T373 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3001747954 Feb 25 01:41:12 PM PST 24 Feb 25 01:41:21 PM PST 24 361646748 ps
T374 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4232232992 Feb 25 01:40:43 PM PST 24 Feb 25 01:40:47 PM PST 24 499394221 ps
T136 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.850259923 Feb 25 01:41:33 PM PST 24 Feb 25 01:41:34 PM PST 24 37980508 ps
T164 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3321203776 Feb 25 01:41:04 PM PST 24 Feb 25 01:41:09 PM PST 24 330586833 ps
T162 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.70325854 Feb 25 01:41:33 PM PST 24 Feb 25 01:41:37 PM PST 24 263842681 ps
T375 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3219237755 Feb 25 01:41:03 PM PST 24 Feb 25 01:41:04 PM PST 24 36165252 ps
T376 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2795796648 Feb 25 01:41:17 PM PST 24 Feb 25 01:41:20 PM PST 24 86781957 ps
T377 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.713708955 Feb 25 01:41:12 PM PST 24 Feb 25 01:41:13 PM PST 24 25867436 ps
T378 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4089202527 Feb 25 01:41:14 PM PST 24 Feb 25 01:41:17 PM PST 24 111238599 ps
T379 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.809183681 Feb 25 01:41:13 PM PST 24 Feb 25 01:41:15 PM PST 24 172486270 ps
T380 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1560659313 Feb 25 01:40:41 PM PST 24 Feb 25 01:40:43 PM PST 24 146862612 ps
T381 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1363221056 Feb 25 01:40:42 PM PST 24 Feb 25 01:40:45 PM PST 24 258081317 ps
T382 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.440745762 Feb 25 01:41:00 PM PST 24 Feb 25 01:41:03 PM PST 24 202424766 ps
T383 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.582420636 Feb 25 01:41:31 PM PST 24 Feb 25 01:41:34 PM PST 24 266601762 ps
T39 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1101353171 Feb 25 01:41:04 PM PST 24 Feb 25 01:41:06 PM PST 24 39608561 ps
T384 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1638821438 Feb 25 01:41:20 PM PST 24 Feb 25 01:41:23 PM PST 24 125131069 ps
T385 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1840536778 Feb 25 01:41:18 PM PST 24 Feb 25 01:41:20 PM PST 24 80277608 ps
T386 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.565136149 Feb 25 01:41:30 PM PST 24 Feb 25 01:41:31 PM PST 24 78501222 ps
T387 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1313677929 Feb 25 01:40:41 PM PST 24 Feb 25 01:40:42 PM PST 24 29802868 ps
T388 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3754566943 Feb 25 01:41:27 PM PST 24 Feb 25 01:41:29 PM PST 24 133668802 ps
T40 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2830072020 Feb 25 01:40:46 PM PST 24 Feb 25 01:40:47 PM PST 24 58163680 ps
T389 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.262118593 Feb 25 01:41:14 PM PST 24 Feb 25 01:41:15 PM PST 24 81503258 ps
T137 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1311590517 Feb 25 01:41:33 PM PST 24 Feb 25 01:41:34 PM PST 24 62125775 ps
T140 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.556829546 Feb 25 01:41:15 PM PST 24 Feb 25 01:41:20 PM PST 24 218785348 ps
T390 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1678570136 Feb 25 01:41:30 PM PST 24 Feb 25 01:41:32 PM PST 24 134725668 ps
T391 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2400498298 Feb 25 01:41:03 PM PST 24 Feb 25 01:41:06 PM PST 24 66589547 ps
T392 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4047180385 Feb 25 01:41:14 PM PST 24 Feb 25 01:41:15 PM PST 24 31988328 ps
T393 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2631891241 Feb 25 01:41:14 PM PST 24 Feb 25 01:41:17 PM PST 24 282651956 ps
T394 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1361489872 Feb 25 01:41:06 PM PST 24 Feb 25 01:41:07 PM PST 24 89946649 ps
T395 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.76739199 Feb 25 01:41:32 PM PST 24 Feb 25 01:41:32 PM PST 24 27338644 ps
T45 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.542140956 Feb 25 01:41:13 PM PST 24 Feb 25 01:41:14 PM PST 24 65045635 ps
T396 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2107083932 Feb 25 01:41:20 PM PST 24 Feb 25 01:41:21 PM PST 24 58719115 ps
T397 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3427418984 Feb 25 01:41:17 PM PST 24 Feb 25 01:41:22 PM PST 24 126254993 ps
T398 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.792294653 Feb 25 01:41:32 PM PST 24 Feb 25 01:41:36 PM PST 24 100360200 ps
T399 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.274079725 Feb 25 01:40:43 PM PST 24 Feb 25 01:40:44 PM PST 24 129472388 ps
T400 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2374409885 Feb 25 01:41:28 PM PST 24 Feb 25 01:41:30 PM PST 24 52229178 ps
T41 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1762218236 Feb 25 01:40:41 PM PST 24 Feb 25 01:40:42 PM PST 24 31259824 ps
T401 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1956488781 Feb 25 01:41:03 PM PST 24 Feb 25 01:41:07 PM PST 24 320836440 ps
T402 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1851367867 Feb 25 01:41:25 PM PST 24 Feb 25 01:41:27 PM PST 24 36704734 ps

Test location /workspace/coverage/default/29.in_trans.3135728132
Short name T4
Test name
Test status
Simulation time 8377187827 ps
CPU time 9.23 seconds
Started Feb 25 12:36:21 PM PST 24
Finished Feb 25 12:36:31 PM PST 24
Peak memory 202192 kb
Host smart-c44a26f8-7cd0-403b-9181-50cb3434219e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
28132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.in_trans.3135728132
Directory /workspace/29.in_trans/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1695279715
Short name T35
Test name
Test status
Simulation time 296906586 ps
CPU time 2.53 seconds
Started Feb 25 01:41:22 PM PST 24
Finished Feb 25 01:41:25 PM PST 24
Peak memory 202460 kb
Host smart-fdcf2343-b0a0-4127-9970-26c80ce96139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1695279715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1695279715
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3842410614
Short name T34
Test name
Test status
Simulation time 215107825 ps
CPU time 2.9 seconds
Started Feb 25 01:41:41 PM PST 24
Finished Feb 25 01:41:45 PM PST 24
Peak memory 210588 kb
Host smart-aeccfe98-23b1-4d41-8bba-d36e6c41ca19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842410614 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.3842410614
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2920623962
Short name T5
Test name
Test status
Simulation time 8368699497 ps
CPU time 8.1 seconds
Started Feb 25 12:35:31 PM PST 24
Finished Feb 25 12:35:40 PM PST 24
Peak memory 202192 kb
Host smart-ae7dc9e1-1ae2-40f9-891a-56ef87fd3cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29206
23962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2920623962
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2041184606
Short name T3
Test name
Test status
Simulation time 8368692503 ps
CPU time 9.55 seconds
Started Feb 25 12:35:24 PM PST 24
Finished Feb 25 12:35:34 PM PST 24
Peak memory 202212 kb
Host smart-641d4983-03ff-4a20-b874-a46a27bc4208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20411
84606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2041184606
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2810024904
Short name T33
Test name
Test status
Simulation time 154899575 ps
CPU time 1 seconds
Started Feb 25 12:35:28 PM PST 24
Finished Feb 25 12:35:29 PM PST 24
Peak memory 217908 kb
Host smart-eaefda42-fa99-46b9-845b-3b945cd315d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2810024904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2810024904
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3816360301
Short name T76
Test name
Test status
Simulation time 8440223634 ps
CPU time 7.09 seconds
Started Feb 25 12:36:58 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 202152 kb
Host smart-189ad27e-58a0-4cd1-91d4-d784e6f41f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38163
60301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3816360301
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2791227241
Short name T121
Test name
Test status
Simulation time 95548078 ps
CPU time 1.41 seconds
Started Feb 25 01:41:05 PM PST 24
Finished Feb 25 01:41:07 PM PST 24
Peak memory 202456 kb
Host smart-f1cef544-ccfe-4f3f-b81c-4807917d846b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2791227241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2791227241
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1762218236
Short name T41
Test name
Test status
Simulation time 31259824 ps
CPU time 0.73 seconds
Started Feb 25 01:40:41 PM PST 24
Finished Feb 25 01:40:42 PM PST 24
Peak memory 202200 kb
Host smart-12b2d635-56aa-47dd-9e21-29dc7488c84b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762218236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1762218236
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4170863420
Short name T116
Test name
Test status
Simulation time 71972788 ps
CPU time 2.02 seconds
Started Feb 25 01:41:47 PM PST 24
Finished Feb 25 01:41:50 PM PST 24
Peak memory 202480 kb
Host smart-a04de49a-a3fa-425d-a6d7-13b3061b9079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4170863420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.4170863420
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2376390462
Short name T12
Test name
Test status
Simulation time 8407498986 ps
CPU time 8.52 seconds
Started Feb 25 12:36:28 PM PST 24
Finished Feb 25 12:36:36 PM PST 24
Peak memory 202224 kb
Host smart-5439d3a6-0d96-47ea-8538-1b2587ed6e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23763
90462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2376390462
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.in_trans.4270075812
Short name T281
Test name
Test status
Simulation time 8410592805 ps
CPU time 7.79 seconds
Started Feb 25 12:35:27 PM PST 24
Finished Feb 25 12:35:35 PM PST 24
Peak memory 202196 kb
Host smart-1b1f48cd-0856-4c28-80cb-1914c7611924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700
75812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.in_trans.4270075812
Directory /workspace/14.in_trans/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.542140956
Short name T45
Test name
Test status
Simulation time 65045635 ps
CPU time 0.85 seconds
Started Feb 25 01:41:13 PM PST 24
Finished Feb 25 01:41:14 PM PST 24
Peak memory 202312 kb
Host smart-0cfcb2a0-57b5-4c4c-b5db-94497310bb43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542140956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.542140956
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2383889642
Short name T36
Test name
Test status
Simulation time 219715988 ps
CPU time 4.26 seconds
Started Feb 25 01:41:27 PM PST 24
Finished Feb 25 01:41:31 PM PST 24
Peak memory 202496 kb
Host smart-684da41f-dd9f-4fc7-9edf-dc43b404c450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2383889642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2383889642
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/5.in_trans.2214024759
Short name T13
Test name
Test status
Simulation time 8401550602 ps
CPU time 7.24 seconds
Started Feb 25 12:35:19 PM PST 24
Finished Feb 25 12:35:27 PM PST 24
Peak memory 202192 kb
Host smart-c4939dab-b4f3-45a7-9602-5bc7fd64b90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22140
24759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.in_trans.2214024759
Directory /workspace/5.in_trans/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.998561888
Short name T160
Test name
Test status
Simulation time 214026584 ps
CPU time 4.14 seconds
Started Feb 25 01:41:13 PM PST 24
Finished Feb 25 01:41:17 PM PST 24
Peak memory 202492 kb
Host smart-d3e7e7d5-ab71-417b-b205-80ae1801eb20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=998561888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.998561888
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2963236749
Short name T111
Test name
Test status
Simulation time 8435644387 ps
CPU time 7.32 seconds
Started Feb 25 12:36:57 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 202196 kb
Host smart-5e25f884-7cec-4b05-89a9-1ef5e69eb51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29632
36749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2963236749
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.875614578
Short name T97
Test name
Test status
Simulation time 8451734430 ps
CPU time 8.07 seconds
Started Feb 25 12:36:37 PM PST 24
Finished Feb 25 12:36:45 PM PST 24
Peak memory 202232 kb
Host smart-e2d15976-b2fb-4df6-80d8-a4ff470dd0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87561
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.875614578
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.in_trans.1805522456
Short name T149
Test name
Test status
Simulation time 8449265110 ps
CPU time 7.87 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:14 PM PST 24
Peak memory 202196 kb
Host smart-079e761a-0394-4fdc-9b2f-1816c4fc7703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18055
22456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.in_trans.1805522456
Directory /workspace/40.in_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2271803022
Short name T42
Test name
Test status
Simulation time 46444920 ps
CPU time 0.95 seconds
Started Feb 25 01:40:42 PM PST 24
Finished Feb 25 01:40:43 PM PST 24
Peak memory 202464 kb
Host smart-9b503c4c-c1a7-4fff-b9e7-b8fc8605d9e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271803022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.2271803022
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.4280212552
Short name T209
Test name
Test status
Simulation time 8386550899 ps
CPU time 7.5 seconds
Started Feb 25 12:36:10 PM PST 24
Finished Feb 25 12:36:19 PM PST 24
Peak memory 202216 kb
Host smart-9f44e1ca-f518-41d6-bd2b-55f1a637d30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42802
12552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.4280212552
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2830072020
Short name T40
Test name
Test status
Simulation time 58163680 ps
CPU time 0.83 seconds
Started Feb 25 01:40:46 PM PST 24
Finished Feb 25 01:40:47 PM PST 24
Peak memory 202216 kb
Host smart-efc0cb17-022d-44a3-b1c6-5c7f785f9801
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830072020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2830072020
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1340392325
Short name T82
Test name
Test status
Simulation time 8415547282 ps
CPU time 7.23 seconds
Started Feb 25 12:35:47 PM PST 24
Finished Feb 25 12:35:54 PM PST 24
Peak memory 202216 kb
Host smart-2cc64cb0-f40e-4f43-b0b1-a5068b0305f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13403
92325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1340392325
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.434190871
Short name T120
Test name
Test status
Simulation time 98488397 ps
CPU time 2.85 seconds
Started Feb 25 01:40:45 PM PST 24
Finished Feb 25 01:40:48 PM PST 24
Peak memory 202368 kb
Host smart-0815aa2d-3769-4e6b-b16f-b01873104eb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=434190871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.434190871
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/10.in_trans.2945147676
Short name T90
Test name
Test status
Simulation time 8383562683 ps
CPU time 7.1 seconds
Started Feb 25 12:35:34 PM PST 24
Finished Feb 25 12:35:43 PM PST 24
Peak memory 202128 kb
Host smart-4a4a89c3-bb1e-4bbe-aa46-2bed7a4f4217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29451
47676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.in_trans.2945147676
Directory /workspace/10.in_trans/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.375895864
Short name T146
Test name
Test status
Simulation time 8441647675 ps
CPU time 8.61 seconds
Started Feb 25 12:35:39 PM PST 24
Finished Feb 25 12:35:47 PM PST 24
Peak memory 202188 kb
Host smart-929a2845-93ed-4cd6-b432-8ff5b9d11b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37589
5864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.375895864
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.373393562
Short name T264
Test name
Test status
Simulation time 8476948105 ps
CPU time 7.07 seconds
Started Feb 25 12:35:33 PM PST 24
Finished Feb 25 12:35:40 PM PST 24
Peak memory 202132 kb
Host smart-2d98f271-5dfd-4e87-b73b-d9750cf96cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
3562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.373393562
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.in_trans.1950300959
Short name T91
Test name
Test status
Simulation time 8386572741 ps
CPU time 7.26 seconds
Started Feb 25 12:35:48 PM PST 24
Finished Feb 25 12:36:00 PM PST 24
Peak memory 202084 kb
Host smart-0fd9e101-3211-4ef8-ac7c-93242d7fd103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503
00959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.in_trans.1950300959
Directory /workspace/15.in_trans/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2122357169
Short name T291
Test name
Test status
Simulation time 8396919977 ps
CPU time 7.22 seconds
Started Feb 25 12:35:26 PM PST 24
Finished Feb 25 12:35:34 PM PST 24
Peak memory 202132 kb
Host smart-8f1a5f64-fa80-4b8a-bab4-bc7cf7854762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21223
57169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2122357169
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2070494494
Short name T17
Test name
Test status
Simulation time 8456494964 ps
CPU time 9.1 seconds
Started Feb 25 12:35:58 PM PST 24
Finished Feb 25 12:36:07 PM PST 24
Peak memory 202192 kb
Host smart-a6596634-c473-4f97-a1ca-3e5bfaa792aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20704
94494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2070494494
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1311590517
Short name T137
Test name
Test status
Simulation time 62125775 ps
CPU time 1.06 seconds
Started Feb 25 01:41:33 PM PST 24
Finished Feb 25 01:41:34 PM PST 24
Peak memory 202492 kb
Host smart-9a54d97a-b960-44d7-9720-786cf4b52233
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311590517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1311590517
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1121335722
Short name T80
Test name
Test status
Simulation time 8414157904 ps
CPU time 7.02 seconds
Started Feb 25 12:35:11 PM PST 24
Finished Feb 25 12:35:19 PM PST 24
Peak memory 202208 kb
Host smart-bf26c0a2-05c2-48c6-95f3-438e13c0216a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11213
35722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1121335722
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3033723544
Short name T72
Test name
Test status
Simulation time 8443312914 ps
CPU time 7.3 seconds
Started Feb 25 12:35:23 PM PST 24
Finished Feb 25 12:35:36 PM PST 24
Peak memory 202268 kb
Host smart-42700499-9612-4ccc-9792-22ce60ff0f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30337
23544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3033723544
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.969150186
Short name T87
Test name
Test status
Simulation time 8434477062 ps
CPU time 7.57 seconds
Started Feb 25 12:35:29 PM PST 24
Finished Feb 25 12:35:37 PM PST 24
Peak memory 202212 kb
Host smart-190574c8-2e35-44f3-9940-17cadfe021ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96915
0186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.969150186
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.setup_trans_ignored.1349050225
Short name T19
Test name
Test status
Simulation time 8357828129 ps
CPU time 7.24 seconds
Started Feb 25 12:35:28 PM PST 24
Finished Feb 25 12:35:35 PM PST 24
Peak memory 202196 kb
Host smart-a3560089-8cd5-4cff-86f2-4142f6dc5660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13490
50225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.setup_trans_ignored.1349050225
Directory /workspace/12.setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2043984321
Short name T89
Test name
Test status
Simulation time 8375594057 ps
CPU time 9.47 seconds
Started Feb 25 12:35:26 PM PST 24
Finished Feb 25 12:35:36 PM PST 24
Peak memory 202208 kb
Host smart-290e1725-3f81-44e8-8f32-0b0789778c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20439
84321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2043984321
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3933907103
Short name T67
Test name
Test status
Simulation time 8422785610 ps
CPU time 7.02 seconds
Started Feb 25 12:35:39 PM PST 24
Finished Feb 25 12:35:46 PM PST 24
Peak memory 202132 kb
Host smart-a0224fd7-d350-49f3-b00d-7d6df0836d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39339
07103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3933907103
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1989197836
Short name T71
Test name
Test status
Simulation time 8421962201 ps
CPU time 7.51 seconds
Started Feb 25 12:35:54 PM PST 24
Finished Feb 25 12:36:02 PM PST 24
Peak memory 202140 kb
Host smart-045e4fec-8437-484b-8d92-7a4dad1d9162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19891
97836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1989197836
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1664610859
Short name T75
Test name
Test status
Simulation time 8433804920 ps
CPU time 7.56 seconds
Started Feb 25 12:35:53 PM PST 24
Finished Feb 25 12:36:01 PM PST 24
Peak memory 202212 kb
Host smart-2f75b9e7-9921-43f7-b94f-482972f6f067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16646
10859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1664610859
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2868246651
Short name T64
Test name
Test status
Simulation time 8455337346 ps
CPU time 7.49 seconds
Started Feb 25 12:36:08 PM PST 24
Finished Feb 25 12:36:16 PM PST 24
Peak memory 202116 kb
Host smart-0ca4462b-2066-4098-9069-bb1950418e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28682
46651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2868246651
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2721538591
Short name T79
Test name
Test status
Simulation time 8399598213 ps
CPU time 7.49 seconds
Started Feb 25 12:36:00 PM PST 24
Finished Feb 25 12:36:08 PM PST 24
Peak memory 202212 kb
Host smart-3d65206d-1883-4d0b-9f3a-13c755a19855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27215
38591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2721538591
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3413016670
Short name T277
Test name
Test status
Simulation time 8428276813 ps
CPU time 7.94 seconds
Started Feb 25 12:36:33 PM PST 24
Finished Feb 25 12:36:43 PM PST 24
Peak memory 202192 kb
Host smart-6d3061f5-673b-4e99-ac45-a7f9d7f7b549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34130
16670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3413016670
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1871410071
Short name T24
Test name
Test status
Simulation time 8366379302 ps
CPU time 7.11 seconds
Started Feb 25 12:36:35 PM PST 24
Finished Feb 25 12:36:42 PM PST 24
Peak memory 202108 kb
Host smart-8c9b7140-f91d-4c51-96cc-e60239731d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18714
10071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1871410071
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1839365179
Short name T139
Test name
Test status
Simulation time 120259687 ps
CPU time 3.11 seconds
Started Feb 25 01:40:46 PM PST 24
Finished Feb 25 01:40:49 PM PST 24
Peak memory 202432 kb
Host smart-135fca41-4221-4356-a6b4-9dc14ef84176
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839365179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1839365179
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1148425194
Short name T128
Test name
Test status
Simulation time 353857363 ps
CPU time 8.25 seconds
Started Feb 25 01:40:43 PM PST 24
Finished Feb 25 01:40:51 PM PST 24
Peak memory 202536 kb
Host smart-2d13a6ed-034e-4954-9b81-6978ef1c140f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148425194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1148425194
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1778224491
Short name T370
Test name
Test status
Simulation time 111122827 ps
CPU time 3.64 seconds
Started Feb 25 01:40:42 PM PST 24
Finished Feb 25 01:40:45 PM PST 24
Peak memory 210736 kb
Host smart-3de1b702-1b58-4348-9557-5bc06b470443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778224491 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.1778224491
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1834529582
Short name T357
Test name
Test status
Simulation time 94487367 ps
CPU time 1.07 seconds
Started Feb 25 01:40:42 PM PST 24
Finished Feb 25 01:40:44 PM PST 24
Peak memory 202496 kb
Host smart-48656f7f-b0b3-40ed-8689-cb397632710d
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834529582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1834529582
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3758021405
Short name T132
Test name
Test status
Simulation time 55670548 ps
CPU time 1.29 seconds
Started Feb 25 01:40:42 PM PST 24
Finished Feb 25 01:40:43 PM PST 24
Peak memory 202344 kb
Host smart-8d9a938e-7904-4681-98af-0d57162b4de0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3758021405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3758021405
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4232232992
Short name T374
Test name
Test status
Simulation time 499394221 ps
CPU time 4.14 seconds
Started Feb 25 01:40:43 PM PST 24
Finished Feb 25 01:40:47 PM PST 24
Peak memory 202376 kb
Host smart-11542acd-2a92-453f-98bf-61e41d40158d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4232232992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4232232992
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2868972213
Short name T371
Test name
Test status
Simulation time 173833112 ps
CPU time 1.59 seconds
Started Feb 25 01:40:44 PM PST 24
Finished Feb 25 01:40:45 PM PST 24
Peak memory 202556 kb
Host smart-7b9df6d2-7487-4713-b30e-6ac057cbe0b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868972213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.2868972213
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.274079725
Short name T399
Test name
Test status
Simulation time 129472388 ps
CPU time 1.63 seconds
Started Feb 25 01:40:43 PM PST 24
Finished Feb 25 01:40:44 PM PST 24
Peak memory 202380 kb
Host smart-6b4224df-e377-4360-98ab-c9f38dea855d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=274079725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.274079725
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1363221056
Short name T381
Test name
Test status
Simulation time 258081317 ps
CPU time 2.92 seconds
Started Feb 25 01:40:42 PM PST 24
Finished Feb 25 01:40:45 PM PST 24
Peak memory 202440 kb
Host smart-625f2d78-188d-498a-a939-c86291307752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1363221056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1363221056
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.277826128
Short name T366
Test name
Test status
Simulation time 68504241 ps
CPU time 1.93 seconds
Started Feb 25 01:40:42 PM PST 24
Finished Feb 25 01:40:44 PM PST 24
Peak memory 202516 kb
Host smart-d185c950-1687-4ed9-a1f6-a1d0f10ac8bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277826128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.277826128
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4056860856
Short name T367
Test name
Test status
Simulation time 157296804 ps
CPU time 1.91 seconds
Started Feb 25 01:40:41 PM PST 24
Finished Feb 25 01:40:43 PM PST 24
Peak memory 210624 kb
Host smart-f824846b-ccf2-4cbc-b7f7-5bdecf6c784c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056860856 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.4056860856
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1313677929
Short name T387
Test name
Test status
Simulation time 29802868 ps
CPU time 0.78 seconds
Started Feb 25 01:40:41 PM PST 24
Finished Feb 25 01:40:42 PM PST 24
Peak memory 202312 kb
Host smart-aee5fee9-f0a9-4644-9f12-2ada94b90e8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313677929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1313677929
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1560659313
Short name T380
Test name
Test status
Simulation time 146862612 ps
CPU time 2.3 seconds
Started Feb 25 01:40:41 PM PST 24
Finished Feb 25 01:40:43 PM PST 24
Peak memory 202440 kb
Host smart-be89392e-73ea-4dd3-8afb-28a4bbed3c61
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1560659313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1560659313
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1539830484
Short name T350
Test name
Test status
Simulation time 472954569 ps
CPU time 4.66 seconds
Started Feb 25 01:40:42 PM PST 24
Finished Feb 25 01:40:46 PM PST 24
Peak memory 202388 kb
Host smart-6aa5c100-dac1-4579-ae55-45af44c72637
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1539830484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1539830484
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2668671015
Short name T118
Test name
Test status
Simulation time 151054200 ps
CPU time 1.84 seconds
Started Feb 25 01:41:17 PM PST 24
Finished Feb 25 01:41:19 PM PST 24
Peak memory 210728 kb
Host smart-38564abe-0891-4665-aec9-e5dd8567ce6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668671015 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2668671015
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2914809557
Short name T345
Test name
Test status
Simulation time 32264459 ps
CPU time 0.96 seconds
Started Feb 25 01:41:18 PM PST 24
Finished Feb 25 01:41:20 PM PST 24
Peak memory 202368 kb
Host smart-8cbc333e-ab00-4901-b798-a12e5c2dc493
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914809557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2914809557
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1840536778
Short name T385
Test name
Test status
Simulation time 80277608 ps
CPU time 1.04 seconds
Started Feb 25 01:41:18 PM PST 24
Finished Feb 25 01:41:20 PM PST 24
Peak memory 202484 kb
Host smart-1743d109-d0ec-476f-9dca-24aba23df18b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840536778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.1840536778
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1708327504
Short name T368
Test name
Test status
Simulation time 263139993 ps
CPU time 3.07 seconds
Started Feb 25 01:41:17 PM PST 24
Finished Feb 25 01:41:20 PM PST 24
Peak memory 202440 kb
Host smart-0bc5b203-c655-49c9-b1ea-8d89d93ec3df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1708327504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1708327504
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.80309771
Short name T369
Test name
Test status
Simulation time 128094779 ps
CPU time 4.24 seconds
Started Feb 25 01:41:18 PM PST 24
Finished Feb 25 01:41:24 PM PST 24
Peak memory 210648 kb
Host smart-7d379a02-e4a1-4b84-a1d4-b07caaf82850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80309771 -assert nopostproc +UVM_TESTNAME=usbde
v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.80309771
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1109494883
Short name T127
Test name
Test status
Simulation time 48054617 ps
CPU time 0.83 seconds
Started Feb 25 01:41:20 PM PST 24
Finished Feb 25 01:41:21 PM PST 24
Peak memory 202252 kb
Host smart-ad0a25bb-f2b7-4570-8976-67037ac45218
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109494883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1109494883
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2107083932
Short name T396
Test name
Test status
Simulation time 58719115 ps
CPU time 1.34 seconds
Started Feb 25 01:41:20 PM PST 24
Finished Feb 25 01:41:21 PM PST 24
Peak memory 202452 kb
Host smart-5b14ca7a-f940-4fe8-9c26-b1e26d0a8d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107083932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.2107083932
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1638821438
Short name T384
Test name
Test status
Simulation time 125131069 ps
CPU time 2.46 seconds
Started Feb 25 01:41:20 PM PST 24
Finished Feb 25 01:41:23 PM PST 24
Peak memory 202532 kb
Host smart-dd86e305-0e75-4f14-bed7-31534b85a379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1638821438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1638821438
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1678570136
Short name T390
Test name
Test status
Simulation time 134725668 ps
CPU time 1.87 seconds
Started Feb 25 01:41:30 PM PST 24
Finished Feb 25 01:41:32 PM PST 24
Peak memory 210696 kb
Host smart-fbfd62f3-5945-42a6-a783-8cfc1a9941bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678570136 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.1678570136
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.76739199
Short name T395
Test name
Test status
Simulation time 27338644 ps
CPU time 0.78 seconds
Started Feb 25 01:41:32 PM PST 24
Finished Feb 25 01:41:32 PM PST 24
Peak memory 202312 kb
Host smart-2f3bb654-018a-4059-af1c-91566b1c7a3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76739199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.76739199
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2374409885
Short name T400
Test name
Test status
Simulation time 52229178 ps
CPU time 1.35 seconds
Started Feb 25 01:41:28 PM PST 24
Finished Feb 25 01:41:30 PM PST 24
Peak memory 202416 kb
Host smart-f8d48b12-2f22-479e-a0f5-b647f1733316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374409885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.2374409885
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.55124287
Short name T117
Test name
Test status
Simulation time 81561489 ps
CPU time 2.46 seconds
Started Feb 25 01:41:29 PM PST 24
Finished Feb 25 01:41:32 PM PST 24
Peak memory 202496 kb
Host smart-8206470a-3d6d-4f37-a5d7-7067db69f4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=55124287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.55124287
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2202560232
Short name T115
Test name
Test status
Simulation time 325843307 ps
CPU time 4.2 seconds
Started Feb 25 01:41:29 PM PST 24
Finished Feb 25 01:41:34 PM PST 24
Peak memory 210732 kb
Host smart-da59cbb9-01fc-4624-9170-becec77f583e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202560232 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.2202560232
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1851367867
Short name T402
Test name
Test status
Simulation time 36704734 ps
CPU time 0.99 seconds
Started Feb 25 01:41:25 PM PST 24
Finished Feb 25 01:41:27 PM PST 24
Peak memory 202436 kb
Host smart-74e587d7-d0b0-4fde-8edd-391fdef808e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851367867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1851367867
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3754566943
Short name T388
Test name
Test status
Simulation time 133668802 ps
CPU time 1.58 seconds
Started Feb 25 01:41:27 PM PST 24
Finished Feb 25 01:41:29 PM PST 24
Peak memory 202440 kb
Host smart-73168913-6839-421f-b3bc-d3f64fa5b86a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754566943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.3754566943
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.616823809
Short name T155
Test name
Test status
Simulation time 228596274 ps
CPU time 2.37 seconds
Started Feb 25 01:41:30 PM PST 24
Finished Feb 25 01:41:32 PM PST 24
Peak memory 202444 kb
Host smart-4b6c7a5e-cc01-4c5f-b6a4-c87ae453617d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=616823809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.616823809
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3548992179
Short name T159
Test name
Test status
Simulation time 275957817 ps
CPU time 2.46 seconds
Started Feb 25 01:41:28 PM PST 24
Finished Feb 25 01:41:31 PM PST 24
Peak memory 202492 kb
Host smart-0c717307-0860-4a1f-8f5c-8fd9e8d71b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3548992179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3548992179
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.792294653
Short name T398
Test name
Test status
Simulation time 100360200 ps
CPU time 3.75 seconds
Started Feb 25 01:41:32 PM PST 24
Finished Feb 25 01:41:36 PM PST 24
Peak memory 210748 kb
Host smart-dca0663f-4e2a-4968-b071-e6beef81c40c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792294653 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.792294653
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.850259923
Short name T136
Test name
Test status
Simulation time 37980508 ps
CPU time 0.99 seconds
Started Feb 25 01:41:33 PM PST 24
Finished Feb 25 01:41:34 PM PST 24
Peak memory 202496 kb
Host smart-80ae6d10-1f64-45d1-98b6-c82cf32486c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850259923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.850259923
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2842654712
Short name T359
Test name
Test status
Simulation time 94062088 ps
CPU time 1.01 seconds
Started Feb 25 01:41:28 PM PST 24
Finished Feb 25 01:41:30 PM PST 24
Peak memory 202388 kb
Host smart-b5659a92-fe0b-4d83-80e2-413728e1d3db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842654712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.2842654712
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3673868174
Short name T348
Test name
Test status
Simulation time 52791220 ps
CPU time 1.45 seconds
Started Feb 25 01:41:28 PM PST 24
Finished Feb 25 01:41:30 PM PST 24
Peak memory 202436 kb
Host smart-763ef7eb-c92e-4e75-ab7a-2d6a67ded52f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3673868174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3673868174
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.70325854
Short name T162
Test name
Test status
Simulation time 263842681 ps
CPU time 4.36 seconds
Started Feb 25 01:41:33 PM PST 24
Finished Feb 25 01:41:37 PM PST 24
Peak memory 202512 kb
Host smart-397ef4fb-7ae0-4a3b-a7ca-986495471d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=70325854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.70325854
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.964492156
Short name T342
Test name
Test status
Simulation time 122285191 ps
CPU time 1.8 seconds
Started Feb 25 01:41:31 PM PST 24
Finished Feb 25 01:41:33 PM PST 24
Peak memory 210772 kb
Host smart-51e5aaed-ab7f-4ac8-b0fd-c8a203a682bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964492156 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.964492156
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.565136149
Short name T386
Test name
Test status
Simulation time 78501222 ps
CPU time 0.85 seconds
Started Feb 25 01:41:30 PM PST 24
Finished Feb 25 01:41:31 PM PST 24
Peak memory 202232 kb
Host smart-41e47294-1569-43b7-84bf-40fd1958e358
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565136149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.565136149
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.593683504
Short name T122
Test name
Test status
Simulation time 248368627 ps
CPU time 1.61 seconds
Started Feb 25 01:41:31 PM PST 24
Finished Feb 25 01:41:33 PM PST 24
Peak memory 202476 kb
Host smart-2cea80e9-0563-4cc8-b195-86d6f1a84b40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593683504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_c
sr_outstanding.593683504
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2186994756
Short name T372
Test name
Test status
Simulation time 94844442 ps
CPU time 2.83 seconds
Started Feb 25 01:41:29 PM PST 24
Finished Feb 25 01:41:33 PM PST 24
Peak memory 202508 kb
Host smart-3b8b4ebd-c52b-42ab-8ea6-9ccb0e445820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2186994756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2186994756
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2282141059
Short name T161
Test name
Test status
Simulation time 122690920 ps
CPU time 2.43 seconds
Started Feb 25 01:41:28 PM PST 24
Finished Feb 25 01:41:31 PM PST 24
Peak memory 202524 kb
Host smart-e0461a85-46dd-4214-ae92-a403f3b4ff63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2282141059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2282141059
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1082068256
Short name T363
Test name
Test status
Simulation time 83878725 ps
CPU time 2.6 seconds
Started Feb 25 01:41:30 PM PST 24
Finished Feb 25 01:41:33 PM PST 24
Peak memory 210640 kb
Host smart-4f842b45-6c5c-4efe-ac81-c8d60fbfd77e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082068256 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.1082068256
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2353912226
Short name T347
Test name
Test status
Simulation time 125247121 ps
CPU time 1.1 seconds
Started Feb 25 01:41:28 PM PST 24
Finished Feb 25 01:41:30 PM PST 24
Peak memory 202492 kb
Host smart-c6b800cf-dc3d-49ad-91a2-564f5f8c55ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353912226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.2353912226
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.604635741
Short name T361
Test name
Test status
Simulation time 236931717 ps
CPU time 3.17 seconds
Started Feb 25 01:41:32 PM PST 24
Finished Feb 25 01:41:36 PM PST 24
Peak memory 202388 kb
Host smart-8fd65bf1-6709-4e95-9881-429f33584c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=604635741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.604635741
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.582420636
Short name T383
Test name
Test status
Simulation time 266601762 ps
CPU time 2.58 seconds
Started Feb 25 01:41:31 PM PST 24
Finished Feb 25 01:41:34 PM PST 24
Peak memory 202480 kb
Host smart-b5afc2c5-c5e4-4d71-987b-b8830372c6b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=582420636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.582420636
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3993812231
Short name T124
Test name
Test status
Simulation time 55642552 ps
CPU time 1.03 seconds
Started Feb 25 01:41:32 PM PST 24
Finished Feb 25 01:41:33 PM PST 24
Peak memory 202444 kb
Host smart-63a3a5a6-37ef-4906-9e31-30e06e5dc9ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993812231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3993812231
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3041468693
Short name T349
Test name
Test status
Simulation time 179466626 ps
CPU time 1.62 seconds
Started Feb 25 01:41:29 PM PST 24
Finished Feb 25 01:41:31 PM PST 24
Peak memory 202480 kb
Host smart-2fe2c734-1270-4533-a09c-4e5610ca5266
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041468693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.3041468693
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1772093738
Short name T153
Test name
Test status
Simulation time 195706262 ps
CPU time 2.61 seconds
Started Feb 25 01:41:28 PM PST 24
Finished Feb 25 01:41:31 PM PST 24
Peak memory 202632 kb
Host smart-ede06392-a5c5-49b7-92a2-a64e9cd3993e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1772093738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1772093738
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4141890231
Short name T158
Test name
Test status
Simulation time 306390818 ps
CPU time 2.84 seconds
Started Feb 25 01:41:29 PM PST 24
Finished Feb 25 01:41:33 PM PST 24
Peak memory 202464 kb
Host smart-6c0f54e8-dfc3-4ef7-9f4b-845f4acafb07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4141890231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.4141890231
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2206973732
Short name T157
Test name
Test status
Simulation time 273500129 ps
CPU time 4.44 seconds
Started Feb 25 01:41:41 PM PST 24
Finished Feb 25 01:41:47 PM PST 24
Peak memory 210748 kb
Host smart-4cf9c8a0-d2cf-4b89-aed1-d0e52333f778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206973732 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.2206973732
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4183447475
Short name T123
Test name
Test status
Simulation time 80855241 ps
CPU time 1.08 seconds
Started Feb 25 01:41:37 PM PST 24
Finished Feb 25 01:41:39 PM PST 24
Peak memory 202536 kb
Host smart-4b9d99fc-51ea-4cef-bcb8-a3072d52a933
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183447475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4183447475
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2720917230
Short name T56
Test name
Test status
Simulation time 155560612 ps
CPU time 1.56 seconds
Started Feb 25 01:41:39 PM PST 24
Finished Feb 25 01:41:42 PM PST 24
Peak memory 202488 kb
Host smart-c2e96fd8-0184-4b37-84ad-09cd8f39bfce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720917230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.2720917230
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1081968041
Short name T58
Test name
Test status
Simulation time 327039745 ps
CPU time 4.1 seconds
Started Feb 25 01:41:43 PM PST 24
Finished Feb 25 01:41:49 PM PST 24
Peak memory 202448 kb
Host smart-4a755aec-597d-4925-868e-e9749b5cf415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1081968041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1081968041
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3298141860
Short name T341
Test name
Test status
Simulation time 341048157 ps
CPU time 3.95 seconds
Started Feb 25 01:41:42 PM PST 24
Finished Feb 25 01:41:47 PM PST 24
Peak memory 210680 kb
Host smart-3fdddd09-e896-40a4-a7c0-5f8647b3304a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298141860 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3298141860
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1967206058
Short name T126
Test name
Test status
Simulation time 61852843 ps
CPU time 1.02 seconds
Started Feb 25 01:41:38 PM PST 24
Finished Feb 25 01:41:41 PM PST 24
Peak memory 202476 kb
Host smart-5bdcf160-459e-429e-926b-ed677585a735
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967206058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1967206058
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.447271039
Short name T354
Test name
Test status
Simulation time 73958881 ps
CPU time 1.11 seconds
Started Feb 25 01:41:38 PM PST 24
Finished Feb 25 01:41:39 PM PST 24
Peak memory 202436 kb
Host smart-d809f86a-7de6-40d4-a53c-d0ec7b30ebd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447271039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_c
sr_outstanding.447271039
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2597868483
Short name T356
Test name
Test status
Simulation time 192858183 ps
CPU time 2.56 seconds
Started Feb 25 01:41:42 PM PST 24
Finished Feb 25 01:41:46 PM PST 24
Peak memory 202460 kb
Host smart-4e50a383-6859-4fd3-a378-d022795ecf08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2597868483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2597868483
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.465115237
Short name T119
Test name
Test status
Simulation time 347445730 ps
CPU time 2.65 seconds
Started Feb 25 01:41:42 PM PST 24
Finished Feb 25 01:41:46 PM PST 24
Peak memory 202472 kb
Host smart-5b445e6e-0498-47ad-bc24-122f02c36964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=465115237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.465115237
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1956488781
Short name T401
Test name
Test status
Simulation time 320836440 ps
CPU time 3.62 seconds
Started Feb 25 01:41:03 PM PST 24
Finished Feb 25 01:41:07 PM PST 24
Peak memory 202600 kb
Host smart-55bccdac-4c68-410f-b833-4faa7bf32367
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956488781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1956488781
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1101353171
Short name T39
Test name
Test status
Simulation time 39608561 ps
CPU time 0.8 seconds
Started Feb 25 01:41:04 PM PST 24
Finished Feb 25 01:41:06 PM PST 24
Peak memory 202264 kb
Host smart-7c2c4035-11b6-4cf7-8304-9a250cfc2214
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101353171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1101353171
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.440745762
Short name T382
Test name
Test status
Simulation time 202424766 ps
CPU time 2.66 seconds
Started Feb 25 01:41:00 PM PST 24
Finished Feb 25 01:41:03 PM PST 24
Peak memory 210756 kb
Host smart-9eff391d-2c7e-4f24-83ce-a2a52eef3e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440745762 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.440745762
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3329813636
Short name T133
Test name
Test status
Simulation time 51151545 ps
CPU time 0.83 seconds
Started Feb 25 01:41:00 PM PST 24
Finished Feb 25 01:41:01 PM PST 24
Peak memory 202216 kb
Host smart-b130966d-4844-420d-9148-7bd5804020a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329813636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3329813636
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1361489872
Short name T394
Test name
Test status
Simulation time 89946649 ps
CPU time 1.13 seconds
Started Feb 25 01:41:06 PM PST 24
Finished Feb 25 01:41:07 PM PST 24
Peak memory 202544 kb
Host smart-d60e2102-6da2-49c2-9332-3f3f0f895972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361489872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.1361489872
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3257743650
Short name T344
Test name
Test status
Simulation time 198157532 ps
CPU time 2.29 seconds
Started Feb 25 01:40:44 PM PST 24
Finished Feb 25 01:40:46 PM PST 24
Peak memory 202480 kb
Host smart-4dfda7d6-245a-4475-a264-2748ad880a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3257743650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3257743650
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.189161656
Short name T346
Test name
Test status
Simulation time 74262659 ps
CPU time 1.88 seconds
Started Feb 25 01:40:59 PM PST 24
Finished Feb 25 01:41:01 PM PST 24
Peak memory 202476 kb
Host smart-7aeeea50-e9a8-4936-9de9-0325f5df88f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189161656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.189161656
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.149083201
Short name T46
Test name
Test status
Simulation time 39423907 ps
CPU time 0.72 seconds
Started Feb 25 01:41:05 PM PST 24
Finished Feb 25 01:41:06 PM PST 24
Peak memory 202220 kb
Host smart-0a4023c5-eb72-4b44-85f5-12e07ce4738c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149083201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.149083201
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3848010260
Short name T353
Test name
Test status
Simulation time 134485000 ps
CPU time 1.92 seconds
Started Feb 25 01:41:01 PM PST 24
Finished Feb 25 01:41:03 PM PST 24
Peak memory 210644 kb
Host smart-2e3ad271-d7c9-4d48-8c9b-75e82f109d92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848010260 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.3848010260
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1747527949
Short name T125
Test name
Test status
Simulation time 31058924 ps
CPU time 0.89 seconds
Started Feb 25 01:41:02 PM PST 24
Finished Feb 25 01:41:04 PM PST 24
Peak memory 202192 kb
Host smart-7016fd8a-13db-41b3-9e57-79a69290c2dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747527949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1747527949
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2400498298
Short name T391
Test name
Test status
Simulation time 66589547 ps
CPU time 2.07 seconds
Started Feb 25 01:41:03 PM PST 24
Finished Feb 25 01:41:06 PM PST 24
Peak memory 202412 kb
Host smart-d367f55b-0704-47f6-978b-ad0dfc3f833d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2400498298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2400498298
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3219237755
Short name T375
Test name
Test status
Simulation time 36165252 ps
CPU time 0.98 seconds
Started Feb 25 01:41:03 PM PST 24
Finished Feb 25 01:41:04 PM PST 24
Peak memory 202432 kb
Host smart-d58feb74-dac6-4349-ab46-94a6208a1d5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219237755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.3219237755
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2754939224
Short name T355
Test name
Test status
Simulation time 177460027 ps
CPU time 2.53 seconds
Started Feb 25 01:40:58 PM PST 24
Finished Feb 25 01:41:01 PM PST 24
Peak memory 202476 kb
Host smart-41eeba5b-fa18-4b62-b9a4-53a93be41396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2754939224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2754939224
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3321203776
Short name T164
Test name
Test status
Simulation time 330586833 ps
CPU time 4.18 seconds
Started Feb 25 01:41:04 PM PST 24
Finished Feb 25 01:41:09 PM PST 24
Peak memory 202472 kb
Host smart-e56cf131-af0c-4c54-a3f3-32a4582e40dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3321203776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3321203776
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2448682034
Short name T352
Test name
Test status
Simulation time 194624416 ps
CPU time 2.11 seconds
Started Feb 25 01:41:17 PM PST 24
Finished Feb 25 01:41:19 PM PST 24
Peak memory 202436 kb
Host smart-00bb5b6e-9c7c-499b-9fd0-b5f9e2e78724
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448682034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2448682034
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3001747954
Short name T373
Test name
Test status
Simulation time 361646748 ps
CPU time 8.81 seconds
Started Feb 25 01:41:12 PM PST 24
Finished Feb 25 01:41:21 PM PST 24
Peak memory 202500 kb
Host smart-83120a40-4ac2-4682-a950-a52a514de4b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001747954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3001747954
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.809183681
Short name T379
Test name
Test status
Simulation time 172486270 ps
CPU time 1.76 seconds
Started Feb 25 01:41:13 PM PST 24
Finished Feb 25 01:41:15 PM PST 24
Peak memory 210752 kb
Host smart-55254d5c-7338-4394-98f6-5644558a01c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809183681 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.809183681
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2467937858
Short name T131
Test name
Test status
Simulation time 33226421 ps
CPU time 0.95 seconds
Started Feb 25 01:41:14 PM PST 24
Finished Feb 25 01:41:15 PM PST 24
Peak memory 202552 kb
Host smart-5009a54a-af9a-4dc6-89ca-df605d3f8bc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467937858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2467937858
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2047057963
Short name T135
Test name
Test status
Simulation time 157439326 ps
CPU time 2.27 seconds
Started Feb 25 01:41:15 PM PST 24
Finished Feb 25 01:41:19 PM PST 24
Peak memory 202440 kb
Host smart-a78848e6-7931-4cd9-b0ee-a6e93f12e373
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2047057963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2047057963
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2631891241
Short name T393
Test name
Test status
Simulation time 282651956 ps
CPU time 2.43 seconds
Started Feb 25 01:41:14 PM PST 24
Finished Feb 25 01:41:17 PM PST 24
Peak memory 202284 kb
Host smart-021b42d2-f763-4265-bd0e-b62a2b54cca0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2631891241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2631891241
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1330699532
Short name T138
Test name
Test status
Simulation time 75014950 ps
CPU time 1.48 seconds
Started Feb 25 01:41:14 PM PST 24
Finished Feb 25 01:41:16 PM PST 24
Peak memory 202476 kb
Host smart-bf21b458-ba2a-41bb-9806-26fffa67808d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330699532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.1330699532
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2397913280
Short name T364
Test name
Test status
Simulation time 117988053 ps
CPU time 1.65 seconds
Started Feb 25 01:41:04 PM PST 24
Finished Feb 25 01:41:07 PM PST 24
Peak memory 202492 kb
Host smart-e9b5faed-f2eb-45ba-9734-5f56d04cdcb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2397913280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2397913280
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2191931419
Short name T163
Test name
Test status
Simulation time 271802405 ps
CPU time 2.68 seconds
Started Feb 25 01:41:00 PM PST 24
Finished Feb 25 01:41:03 PM PST 24
Peak memory 202556 kb
Host smart-3d5d88bb-cda7-46ef-8c5c-68ddaaa7e191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2191931419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2191931419
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1607617811
Short name T343
Test name
Test status
Simulation time 350271377 ps
CPU time 3.86 seconds
Started Feb 25 01:41:13 PM PST 24
Finished Feb 25 01:41:17 PM PST 24
Peak memory 210668 kb
Host smart-beeff325-7614-45e9-8148-05d313c469a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607617811 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1607617811
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4047180385
Short name T392
Test name
Test status
Simulation time 31988328 ps
CPU time 0.77 seconds
Started Feb 25 01:41:14 PM PST 24
Finished Feb 25 01:41:15 PM PST 24
Peak memory 202124 kb
Host smart-35dd3eec-e4d0-4353-b319-d3619bfe1c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047180385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.4047180385
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2944009196
Short name T44
Test name
Test status
Simulation time 108588492 ps
CPU time 1.51 seconds
Started Feb 25 01:41:17 PM PST 24
Finished Feb 25 01:41:19 PM PST 24
Peak memory 202476 kb
Host smart-315a9dc4-9d41-48df-80ba-f0c8a337ed2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944009196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.2944009196
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3382072601
Short name T362
Test name
Test status
Simulation time 258392824 ps
CPU time 2.27 seconds
Started Feb 25 01:41:13 PM PST 24
Finished Feb 25 01:41:16 PM PST 24
Peak memory 202600 kb
Host smart-34539751-384a-4cd8-a1fc-e9edaf0d5007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3382072601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3382072601
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.34347905
Short name T114
Test name
Test status
Simulation time 267262842 ps
CPU time 2.96 seconds
Started Feb 25 01:41:15 PM PST 24
Finished Feb 25 01:41:18 PM PST 24
Peak memory 210752 kb
Host smart-442a21d8-74c6-495a-878f-78bcce242e8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34347905 -assert nopostproc +UVM_TESTNAME=usbde
v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.34347905
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2791563697
Short name T134
Test name
Test status
Simulation time 44728561 ps
CPU time 0.8 seconds
Started Feb 25 01:41:13 PM PST 24
Finished Feb 25 01:41:14 PM PST 24
Peak memory 202284 kb
Host smart-c8ff0648-4525-44e9-baf9-4ed81e3ba867
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791563697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2791563697
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.610782751
Short name T351
Test name
Test status
Simulation time 69268987 ps
CPU time 0.98 seconds
Started Feb 25 01:41:12 PM PST 24
Finished Feb 25 01:41:14 PM PST 24
Peak memory 202460 kb
Host smart-10022bb0-2a0a-4cd2-bcd1-8781f94a020d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610782751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_cs
r_outstanding.610782751
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3569135604
Short name T154
Test name
Test status
Simulation time 180869311 ps
CPU time 2.11 seconds
Started Feb 25 01:41:13 PM PST 24
Finished Feb 25 01:41:15 PM PST 24
Peak memory 202460 kb
Host smart-16487458-8a66-4f65-9545-071da4aac02f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3569135604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3569135604
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2488928714
Short name T59
Test name
Test status
Simulation time 305759988 ps
CPU time 3.01 seconds
Started Feb 25 01:41:17 PM PST 24
Finished Feb 25 01:41:20 PM PST 24
Peak memory 202456 kb
Host smart-6c6a89c8-0912-4661-a16e-a19ab232639f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2488928714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2488928714
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3964110536
Short name T129
Test name
Test status
Simulation time 70093261 ps
CPU time 0.99 seconds
Started Feb 25 01:41:15 PM PST 24
Finished Feb 25 01:41:16 PM PST 24
Peak memory 202496 kb
Host smart-12358fe8-c759-4f37-8989-238040af35c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964110536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3964110536
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3018649327
Short name T365
Test name
Test status
Simulation time 76439843 ps
CPU time 1.05 seconds
Started Feb 25 01:41:18 PM PST 24
Finished Feb 25 01:41:20 PM PST 24
Peak memory 202472 kb
Host smart-e421022e-edd3-4322-8daf-f6d46b1f7eec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018649327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.3018649327
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.254361967
Short name T360
Test name
Test status
Simulation time 214717328 ps
CPU time 2.27 seconds
Started Feb 25 01:41:12 PM PST 24
Finished Feb 25 01:41:15 PM PST 24
Peak memory 202432 kb
Host smart-80d4c9ac-8438-4d74-9514-e5fea17f2de8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=254361967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.254361967
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.556829546
Short name T140
Test name
Test status
Simulation time 218785348 ps
CPU time 4 seconds
Started Feb 25 01:41:15 PM PST 24
Finished Feb 25 01:41:20 PM PST 24
Peak memory 202528 kb
Host smart-8153850f-d12a-484a-adc9-95f324441c32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=556829546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.556829546
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3427418984
Short name T397
Test name
Test status
Simulation time 126254993 ps
CPU time 4.38 seconds
Started Feb 25 01:41:17 PM PST 24
Finished Feb 25 01:41:22 PM PST 24
Peak memory 210708 kb
Host smart-3e72490d-ab9a-462d-b0ff-3fcb7384f43c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427418984 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.3427418984
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1612282237
Short name T130
Test name
Test status
Simulation time 36616485 ps
CPU time 0.93 seconds
Started Feb 25 01:41:14 PM PST 24
Finished Feb 25 01:41:16 PM PST 24
Peak memory 202432 kb
Host smart-d3d643c2-59c4-480c-b415-bc0edede9143
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612282237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1612282237
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.262118593
Short name T389
Test name
Test status
Simulation time 81503258 ps
CPU time 1.1 seconds
Started Feb 25 01:41:14 PM PST 24
Finished Feb 25 01:41:15 PM PST 24
Peak memory 202528 kb
Host smart-a7d3cd59-f67f-49fe-8fda-558686b1a23f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262118593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_cs
r_outstanding.262118593
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2795796648
Short name T376
Test name
Test status
Simulation time 86781957 ps
CPU time 2.62 seconds
Started Feb 25 01:41:17 PM PST 24
Finished Feb 25 01:41:20 PM PST 24
Peak memory 202456 kb
Host smart-09ef4b3a-be06-4507-8f64-e0aadeaa5710
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2795796648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2795796648
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4005526039
Short name T358
Test name
Test status
Simulation time 306210470 ps
CPU time 3.71 seconds
Started Feb 25 01:41:20 PM PST 24
Finished Feb 25 01:41:24 PM PST 24
Peak memory 210636 kb
Host smart-c2c90cd8-99a4-4ace-b067-8185144cca2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005526039 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.4005526039
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.713708955
Short name T377
Test name
Test status
Simulation time 25867436 ps
CPU time 0.76 seconds
Started Feb 25 01:41:12 PM PST 24
Finished Feb 25 01:41:13 PM PST 24
Peak memory 202168 kb
Host smart-b25d9055-e9a0-4650-9aa6-33dbda2af187
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713708955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.713708955
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2205651290
Short name T43
Test name
Test status
Simulation time 153573455 ps
CPU time 1.51 seconds
Started Feb 25 01:41:16 PM PST 24
Finished Feb 25 01:41:19 PM PST 24
Peak memory 202496 kb
Host smart-c3f7eed4-2092-48a7-9944-f2ce85eb4ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205651290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.2205651290
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4089202527
Short name T378
Test name
Test status
Simulation time 111238599 ps
CPU time 1.98 seconds
Started Feb 25 01:41:14 PM PST 24
Finished Feb 25 01:41:17 PM PST 24
Peak memory 202416 kb
Host smart-37125b27-cee5-4a47-a245-9f79e1c0f842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4089202527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4089202527
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1375262833
Short name T57
Test name
Test status
Simulation time 126169534 ps
CPU time 2.31 seconds
Started Feb 25 01:41:13 PM PST 24
Finished Feb 25 01:41:15 PM PST 24
Peak memory 202476 kb
Host smart-873e6ad9-bf0e-41f8-bade-a9cf109687b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1375262833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1375262833
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.in_trans.16033554
Short name T213
Test name
Test status
Simulation time 8433240606 ps
CPU time 7.34 seconds
Started Feb 25 12:35:09 PM PST 24
Finished Feb 25 12:35:17 PM PST 24
Peak memory 202116 kb
Host smart-f59f470d-5ee6-49fc-9667-542c07f73922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16033
554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.in_trans.16033554
Directory /workspace/0.in_trans/latest

Test location /workspace/coverage/default/0.setup_trans_ignored.3971228283
Short name T195
Test name
Test status
Simulation time 8363804459 ps
CPU time 8.28 seconds
Started Feb 25 12:35:21 PM PST 24
Finished Feb 25 12:35:30 PM PST 24
Peak memory 202208 kb
Host smart-adb8d0fb-3385-49dc-baf5-592d777cb33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
28283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.setup_trans_ignored.3971228283
Directory /workspace/0.setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.121464369
Short name T27
Test name
Test status
Simulation time 8404979946 ps
CPU time 8.81 seconds
Started Feb 25 12:35:13 PM PST 24
Finished Feb 25 12:35:24 PM PST 24
Peak memory 202168 kb
Host smart-5a091798-9206-4077-a3d3-6459827e4a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12146
4369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.121464369
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3232290356
Short name T320
Test name
Test status
Simulation time 8447414686 ps
CPU time 7.3 seconds
Started Feb 25 12:35:15 PM PST 24
Finished Feb 25 12:35:23 PM PST 24
Peak memory 202164 kb
Host smart-1cb8b7c0-5544-4000-b512-70d91cf75a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32322
90356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3232290356
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1629523206
Short name T177
Test name
Test status
Simulation time 8372437829 ps
CPU time 7.44 seconds
Started Feb 25 12:35:20 PM PST 24
Finished Feb 25 12:35:28 PM PST 24
Peak memory 202140 kb
Host smart-6e29db95-fb66-47d9-8548-46a5bbea14e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16295
23206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1629523206
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.in_trans.2303742138
Short name T10
Test name
Test status
Simulation time 8406972992 ps
CPU time 7.61 seconds
Started Feb 25 12:35:17 PM PST 24
Finished Feb 25 12:35:25 PM PST 24
Peak memory 202192 kb
Host smart-9b30c0da-7765-4fd7-9cac-8d70e2517baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23037
42138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.in_trans.2303742138
Directory /workspace/1.in_trans/latest

Test location /workspace/coverage/default/1.setup_trans_ignored.1176574768
Short name T180
Test name
Test status
Simulation time 8359698254 ps
CPU time 8.81 seconds
Started Feb 25 12:35:17 PM PST 24
Finished Feb 25 12:35:26 PM PST 24
Peak memory 202204 kb
Host smart-3f5395fe-df61-4ea4-8314-0706edb6eaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11765
74768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.setup_trans_ignored.1176574768
Directory /workspace/1.setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.4035758455
Short name T237
Test name
Test status
Simulation time 8369794754 ps
CPU time 8.32 seconds
Started Feb 25 12:35:17 PM PST 24
Finished Feb 25 12:35:26 PM PST 24
Peak memory 202192 kb
Host smart-25275282-e9bb-4f1b-b061-e72ecacafadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40357
58455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.4035758455
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.143460649
Short name T6
Test name
Test status
Simulation time 8452157196 ps
CPU time 7.61 seconds
Started Feb 25 12:35:18 PM PST 24
Finished Feb 25 12:35:26 PM PST 24
Peak memory 202188 kb
Host smart-78a1ccda-761a-4f93-92c4-d73d140ef06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14346
0649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.143460649
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1667208592
Short name T47
Test name
Test status
Simulation time 171029587 ps
CPU time 1.03 seconds
Started Feb 25 12:35:16 PM PST 24
Finished Feb 25 12:35:18 PM PST 24
Peak memory 217884 kb
Host smart-733e7762-2612-49eb-930b-1b42b2dc5f49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1667208592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1667208592
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3429222243
Short name T323
Test name
Test status
Simulation time 8373448403 ps
CPU time 7.89 seconds
Started Feb 25 12:35:17 PM PST 24
Finished Feb 25 12:35:25 PM PST 24
Peak memory 202196 kb
Host smart-e3f04c43-4120-476e-8e08-2480f2d0d47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34292
22243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3429222243
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.setup_trans_ignored.988287977
Short name T326
Test name
Test status
Simulation time 8357389445 ps
CPU time 7.23 seconds
Started Feb 25 12:35:36 PM PST 24
Finished Feb 25 12:35:43 PM PST 24
Peak memory 202192 kb
Host smart-76ae0011-5591-4505-a2d3-014168d94770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98828
7977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.setup_trans_ignored.988287977
Directory /workspace/10.setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3715394625
Short name T192
Test name
Test status
Simulation time 8374269560 ps
CPU time 6.98 seconds
Started Feb 25 12:35:30 PM PST 24
Finished Feb 25 12:35:37 PM PST 24
Peak memory 202208 kb
Host smart-1293d1bc-977b-4202-ae66-54cfdf373b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37153
94625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3715394625
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1717691834
Short name T285
Test name
Test status
Simulation time 8372888578 ps
CPU time 7.86 seconds
Started Feb 25 12:35:50 PM PST 24
Finished Feb 25 12:35:58 PM PST 24
Peak memory 202196 kb
Host smart-81379e62-18a7-4480-bb75-4e2cf8084e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17176
91834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1717691834
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.in_trans.3347554234
Short name T307
Test name
Test status
Simulation time 8453147855 ps
CPU time 7.21 seconds
Started Feb 25 12:35:41 PM PST 24
Finished Feb 25 12:35:49 PM PST 24
Peak memory 202040 kb
Host smart-861c9ac7-1866-488e-8a61-3fa8a3a577bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475
54234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.in_trans.3347554234
Directory /workspace/11.in_trans/latest

Test location /workspace/coverage/default/11.setup_trans_ignored.2273394289
Short name T243
Test name
Test status
Simulation time 8362350084 ps
CPU time 9.25 seconds
Started Feb 25 12:35:19 PM PST 24
Finished Feb 25 12:35:28 PM PST 24
Peak memory 202204 kb
Host smart-40b57f95-1c12-430d-a541-277e6aa584e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22733
94289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.setup_trans_ignored.2273394289
Directory /workspace/11.setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3768379067
Short name T314
Test name
Test status
Simulation time 8374049389 ps
CPU time 7.45 seconds
Started Feb 25 12:35:46 PM PST 24
Finished Feb 25 12:35:54 PM PST 24
Peak memory 202212 kb
Host smart-c8774177-e13e-41b4-aa1f-cf626087b5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37683
79067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3768379067
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2962395860
Short name T239
Test name
Test status
Simulation time 8450172280 ps
CPU time 7.03 seconds
Started Feb 25 12:35:31 PM PST 24
Finished Feb 25 12:35:43 PM PST 24
Peak memory 202192 kb
Host smart-428cf045-63c2-476f-b393-f5bc70bc45ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29623
95860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2962395860
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_smoke.440421213
Short name T286
Test name
Test status
Simulation time 8456207272 ps
CPU time 7.69 seconds
Started Feb 25 12:35:28 PM PST 24
Finished Feb 25 12:35:36 PM PST 24
Peak memory 202192 kb
Host smart-b28bf61e-8b16-40d0-a0c3-d0c54c4a669c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44042
1213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.440421213
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.in_trans.4190028465
Short name T112
Test name
Test status
Simulation time 8519870301 ps
CPU time 8.36 seconds
Started Feb 25 12:35:46 PM PST 24
Finished Feb 25 12:35:55 PM PST 24
Peak memory 202196 kb
Host smart-48629905-cfe2-4214-9a4f-b40a5e88809a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41900
28465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.in_trans.4190028465
Directory /workspace/12.in_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2871283722
Short name T32
Test name
Test status
Simulation time 8375449236 ps
CPU time 7.36 seconds
Started Feb 25 12:35:43 PM PST 24
Finished Feb 25 12:35:51 PM PST 24
Peak memory 202212 kb
Host smart-eef0c553-5648-4427-8eec-e2560fd9c032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28712
83722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2871283722
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2902998361
Short name T101
Test name
Test status
Simulation time 8374361239 ps
CPU time 7.56 seconds
Started Feb 25 12:35:50 PM PST 24
Finished Feb 25 12:35:58 PM PST 24
Peak memory 202196 kb
Host smart-6ceb7ab6-a830-4a84-a7a2-40ed64f2c3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29029
98361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2902998361
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1316436173
Short name T53
Test name
Test status
Simulation time 8369105677 ps
CPU time 7.23 seconds
Started Feb 25 12:35:54 PM PST 24
Finished Feb 25 12:36:01 PM PST 24
Peak memory 202132 kb
Host smart-747194f5-51bf-42cd-a911-5eaad1837615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
36173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1316436173
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.in_trans.2514658153
Short name T279
Test name
Test status
Simulation time 8384325376 ps
CPU time 8.17 seconds
Started Feb 25 12:35:40 PM PST 24
Finished Feb 25 12:35:48 PM PST 24
Peak memory 202192 kb
Host smart-81e30785-4496-43d9-8365-665b35c6b854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25146
58153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.in_trans.2514658153
Directory /workspace/13.in_trans/latest

Test location /workspace/coverage/default/13.setup_trans_ignored.2004375395
Short name T325
Test name
Test status
Simulation time 8358553433 ps
CPU time 8.08 seconds
Started Feb 25 12:35:43 PM PST 24
Finished Feb 25 12:35:51 PM PST 24
Peak memory 202252 kb
Host smart-c18cbf24-8f35-4b6b-8ce2-39bd73a40567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
75395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.setup_trans_ignored.2004375395
Directory /workspace/13.setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3136843310
Short name T309
Test name
Test status
Simulation time 8369761970 ps
CPU time 7.66 seconds
Started Feb 25 12:35:46 PM PST 24
Finished Feb 25 12:35:53 PM PST 24
Peak memory 202212 kb
Host smart-57f9522a-37cc-4e02-a300-4713e090fe0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31368
43310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3136843310
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2804037402
Short name T294
Test name
Test status
Simulation time 8371972209 ps
CPU time 7.46 seconds
Started Feb 25 12:35:41 PM PST 24
Finished Feb 25 12:35:49 PM PST 24
Peak memory 202192 kb
Host smart-f3dc3492-3bd7-488b-b802-12111894fecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28040
37402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2804037402
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.setup_trans_ignored.1160654382
Short name T288
Test name
Test status
Simulation time 8362571926 ps
CPU time 9.94 seconds
Started Feb 25 12:36:00 PM PST 24
Finished Feb 25 12:36:10 PM PST 24
Peak memory 202192 kb
Host smart-d518035f-58ce-41c2-a99c-801138984b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11606
54382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.setup_trans_ignored.1160654382
Directory /workspace/14.setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2561771318
Short name T242
Test name
Test status
Simulation time 8368493438 ps
CPU time 7.14 seconds
Started Feb 25 12:35:48 PM PST 24
Finished Feb 25 12:35:55 PM PST 24
Peak memory 202152 kb
Host smart-ff357649-994f-4296-94a8-f4ce35134a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25617
71318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2561771318
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3946429977
Short name T270
Test name
Test status
Simulation time 8436297264 ps
CPU time 7.1 seconds
Started Feb 25 12:35:44 PM PST 24
Finished Feb 25 12:35:51 PM PST 24
Peak memory 202212 kb
Host smart-dbacf337-aa1e-4930-8845-ed04d5f5a8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39464
29977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3946429977
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.304529442
Short name T274
Test name
Test status
Simulation time 8405751587 ps
CPU time 7.73 seconds
Started Feb 25 12:35:39 PM PST 24
Finished Feb 25 12:35:47 PM PST 24
Peak memory 202192 kb
Host smart-9d35c4c6-9599-4e41-82ee-9d3d908b350c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30452
9442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.304529442
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_smoke.104220702
Short name T201
Test name
Test status
Simulation time 8365732366 ps
CPU time 7.96 seconds
Started Feb 25 12:35:45 PM PST 24
Finished Feb 25 12:35:53 PM PST 24
Peak memory 202176 kb
Host smart-1d249985-271d-4994-961a-5d66731365dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10422
0702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.104220702
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.setup_trans_ignored.2764041677
Short name T276
Test name
Test status
Simulation time 8360819214 ps
CPU time 8.29 seconds
Started Feb 25 12:35:47 PM PST 24
Finished Feb 25 12:36:01 PM PST 24
Peak memory 202192 kb
Host smart-7fd7705a-7f04-406e-9477-c13b23b581c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
41677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.setup_trans_ignored.2764041677
Directory /workspace/15.setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1871662701
Short name T29
Test name
Test status
Simulation time 8375946750 ps
CPU time 9.63 seconds
Started Feb 25 12:35:52 PM PST 24
Finished Feb 25 12:36:02 PM PST 24
Peak memory 202192 kb
Host smart-2b5c60ff-a87a-4a03-9cf1-299287dec8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716
62701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1871662701
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3335590537
Short name T77
Test name
Test status
Simulation time 8459703010 ps
CPU time 8.25 seconds
Started Feb 25 12:35:44 PM PST 24
Finished Feb 25 12:35:53 PM PST 24
Peak memory 202208 kb
Host smart-9878306b-09b3-4096-9a9e-cc7521c45ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33355
90537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3335590537
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_smoke.4220071946
Short name T233
Test name
Test status
Simulation time 8371743840 ps
CPU time 8.68 seconds
Started Feb 25 12:35:45 PM PST 24
Finished Feb 25 12:35:54 PM PST 24
Peak memory 202192 kb
Host smart-c5a5e2d9-950c-4f55-a0b8-0d1402a196ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42200
71946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.4220071946
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.in_trans.3391509043
Short name T145
Test name
Test status
Simulation time 8448453393 ps
CPU time 10.04 seconds
Started Feb 25 12:36:04 PM PST 24
Finished Feb 25 12:36:15 PM PST 24
Peak memory 202196 kb
Host smart-228db818-6e91-41b9-a20d-35af29018035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915
09043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.in_trans.3391509043
Directory /workspace/16.in_trans/latest

Test location /workspace/coverage/default/16.setup_trans_ignored.2076063852
Short name T208
Test name
Test status
Simulation time 8361850684 ps
CPU time 7.23 seconds
Started Feb 25 12:36:03 PM PST 24
Finished Feb 25 12:36:11 PM PST 24
Peak memory 202236 kb
Host smart-81ae61da-5f82-4266-9953-3d78c5195d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20760
63852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.setup_trans_ignored.2076063852
Directory /workspace/16.setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3178122323
Short name T319
Test name
Test status
Simulation time 8384480160 ps
CPU time 7.27 seconds
Started Feb 25 12:35:46 PM PST 24
Finished Feb 25 12:35:54 PM PST 24
Peak memory 202240 kb
Host smart-8a00720d-7671-4efa-96d8-dd4c5f2ac226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31781
22323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3178122323
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1204734322
Short name T113
Test name
Test status
Simulation time 8422402182 ps
CPU time 9.34 seconds
Started Feb 25 12:35:59 PM PST 24
Finished Feb 25 12:36:09 PM PST 24
Peak memory 202196 kb
Host smart-6fcd3d64-4a73-49a6-bb65-58e5a2831964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12047
34322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1204734322
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3795817779
Short name T214
Test name
Test status
Simulation time 8401861830 ps
CPU time 7.15 seconds
Started Feb 25 12:35:30 PM PST 24
Finished Feb 25 12:35:38 PM PST 24
Peak memory 202196 kb
Host smart-4503df9f-907a-4d03-a882-cce181b24763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37958
17779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3795817779
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.in_trans.1523643422
Short name T178
Test name
Test status
Simulation time 8376660954 ps
CPU time 8.52 seconds
Started Feb 25 12:35:52 PM PST 24
Finished Feb 25 12:36:00 PM PST 24
Peak memory 202192 kb
Host smart-d97e635c-f466-45bf-afdf-eae22a3f553c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15236
43422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.in_trans.1523643422
Directory /workspace/17.in_trans/latest

Test location /workspace/coverage/default/17.setup_trans_ignored.2854655222
Short name T269
Test name
Test status
Simulation time 8361432917 ps
CPU time 8.41 seconds
Started Feb 25 12:35:46 PM PST 24
Finished Feb 25 12:35:55 PM PST 24
Peak memory 202196 kb
Host smart-7c98f1eb-6b73-4a9f-80ce-51e30aa374fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28546
55222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.setup_trans_ignored.2854655222
Directory /workspace/17.setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.211698117
Short name T217
Test name
Test status
Simulation time 8369521066 ps
CPU time 7.13 seconds
Started Feb 25 12:35:50 PM PST 24
Finished Feb 25 12:35:57 PM PST 24
Peak memory 202120 kb
Host smart-30442d37-76f3-4f71-a04d-d62f6a64cec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21169
8117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.211698117
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.3036165925
Short name T70
Test name
Test status
Simulation time 8444587875 ps
CPU time 7.57 seconds
Started Feb 25 12:35:50 PM PST 24
Finished Feb 25 12:35:58 PM PST 24
Peak memory 202184 kb
Host smart-a530a77e-e153-4e11-8579-aa1ffbdcc73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30361
65925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.3036165925
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_smoke.185323216
Short name T234
Test name
Test status
Simulation time 8379233185 ps
CPU time 9.41 seconds
Started Feb 25 12:35:59 PM PST 24
Finished Feb 25 12:36:09 PM PST 24
Peak memory 202188 kb
Host smart-939f80e6-deaf-4812-8744-e7106cb32732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18532
3216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.185323216
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.setup_trans_ignored.25980056
Short name T215
Test name
Test status
Simulation time 8366683386 ps
CPU time 7 seconds
Started Feb 25 12:35:44 PM PST 24
Finished Feb 25 12:35:51 PM PST 24
Peak memory 202172 kb
Host smart-8d413dfe-b850-4458-b5a3-d41b6947e9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25980
056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.setup_trans_ignored.25980056
Directory /workspace/18.setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.341637878
Short name T166
Test name
Test status
Simulation time 8373706787 ps
CPU time 7.92 seconds
Started Feb 25 12:36:08 PM PST 24
Finished Feb 25 12:36:16 PM PST 24
Peak memory 202208 kb
Host smart-5488208d-631c-49dd-b4b1-7a6e1727041b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34163
7878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.341637878
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1738674967
Short name T66
Test name
Test status
Simulation time 8447989593 ps
CPU time 7.33 seconds
Started Feb 25 12:35:55 PM PST 24
Finished Feb 25 12:36:02 PM PST 24
Peak memory 202212 kb
Host smart-ae5f0124-2233-4543-b134-06ecf51dbf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17386
74967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1738674967
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3071194832
Short name T96
Test name
Test status
Simulation time 8445968278 ps
CPU time 7.63 seconds
Started Feb 25 12:35:47 PM PST 24
Finished Feb 25 12:35:55 PM PST 24
Peak memory 202184 kb
Host smart-dc66d3d6-e792-4321-a550-af43cbc376f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30711
94832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3071194832
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_smoke.862340799
Short name T168
Test name
Test status
Simulation time 8365843190 ps
CPU time 8.18 seconds
Started Feb 25 12:35:53 PM PST 24
Finished Feb 25 12:36:01 PM PST 24
Peak memory 202188 kb
Host smart-513dd350-4982-46c8-9fab-1f02b21f401a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86234
0799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.862340799
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/19.in_trans.1778787463
Short name T108
Test name
Test status
Simulation time 8405757559 ps
CPU time 7.57 seconds
Started Feb 25 12:35:49 PM PST 24
Finished Feb 25 12:35:56 PM PST 24
Peak memory 202196 kb
Host smart-a16d1920-dda8-4024-8b35-82c90dc43905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17787
87463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.in_trans.1778787463
Directory /workspace/19.in_trans/latest

Test location /workspace/coverage/default/19.setup_trans_ignored.1197046033
Short name T186
Test name
Test status
Simulation time 8358554824 ps
CPU time 7.79 seconds
Started Feb 25 12:35:50 PM PST 24
Finished Feb 25 12:35:58 PM PST 24
Peak memory 202100 kb
Host smart-30c45fb4-5899-42d3-9f5b-fbc1f0ac1ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11970
46033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.setup_trans_ignored.1197046033
Directory /workspace/19.setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1347068155
Short name T308
Test name
Test status
Simulation time 8370120309 ps
CPU time 7.15 seconds
Started Feb 25 12:35:52 PM PST 24
Finished Feb 25 12:36:00 PM PST 24
Peak memory 202192 kb
Host smart-be5d44cd-6167-4313-8e3e-455841bf410f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13470
68155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1347068155
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3662778273
Short name T327
Test name
Test status
Simulation time 8409172419 ps
CPU time 6.94 seconds
Started Feb 25 12:35:52 PM PST 24
Finished Feb 25 12:35:59 PM PST 24
Peak memory 202196 kb
Host smart-62075c6a-b371-4405-8561-3f1b4e2a5b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36627
78273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3662778273
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3779425580
Short name T292
Test name
Test status
Simulation time 8368871458 ps
CPU time 7.25 seconds
Started Feb 25 12:36:06 PM PST 24
Finished Feb 25 12:36:14 PM PST 24
Peak memory 202188 kb
Host smart-19bad22d-d372-4cbe-b1a6-c6b0dcb5cddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37794
25580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3779425580
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.in_trans.2939014562
Short name T334
Test name
Test status
Simulation time 8377582236 ps
CPU time 8.22 seconds
Started Feb 25 12:35:20 PM PST 24
Finished Feb 25 12:35:28 PM PST 24
Peak memory 202196 kb
Host smart-b67be7e2-c7cf-44bf-9416-f06a006196f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29390
14562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.in_trans.2939014562
Directory /workspace/2.in_trans/latest

Test location /workspace/coverage/default/2.setup_trans_ignored.106101326
Short name T198
Test name
Test status
Simulation time 8376901347 ps
CPU time 7.03 seconds
Started Feb 25 12:35:23 PM PST 24
Finished Feb 25 12:35:31 PM PST 24
Peak memory 202012 kb
Host smart-94690573-92ba-4eaa-bf2b-39ba10721839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10610
1326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.setup_trans_ignored.106101326
Directory /workspace/2.setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.823003805
Short name T330
Test name
Test status
Simulation time 8463852600 ps
CPU time 8.08 seconds
Started Feb 25 12:35:28 PM PST 24
Finished Feb 25 12:35:36 PM PST 24
Peak memory 202188 kb
Host smart-8250a0cd-434b-479c-a869-68a492dacf6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82300
3805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.823003805
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1218719405
Short name T74
Test name
Test status
Simulation time 8428640945 ps
CPU time 7.55 seconds
Started Feb 25 12:35:24 PM PST 24
Finished Feb 25 12:35:32 PM PST 24
Peak memory 202212 kb
Host smart-039f1b81-af29-4184-977a-1f65b7aaae7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12187
19405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1218719405
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2003456079
Short name T141
Test name
Test status
Simulation time 8394058474 ps
CPU time 7.6 seconds
Started Feb 25 12:35:11 PM PST 24
Finished Feb 25 12:35:18 PM PST 24
Peak memory 202120 kb
Host smart-9bd7e016-8955-458f-ab73-4d34ea257be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20034
56079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2003456079
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2995408446
Short name T37
Test name
Test status
Simulation time 414336432 ps
CPU time 1.36 seconds
Started Feb 25 12:35:15 PM PST 24
Finished Feb 25 12:35:17 PM PST 24
Peak memory 217828 kb
Host smart-408118ff-a5cf-4da3-9e48-18b711dd4ae0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2995408446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2995408446
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2134305240
Short name T316
Test name
Test status
Simulation time 8397085100 ps
CPU time 7.05 seconds
Started Feb 25 12:35:18 PM PST 24
Finished Feb 25 12:35:25 PM PST 24
Peak memory 202196 kb
Host smart-6274a15d-59c9-48e1-8452-2e2ddf5c4392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21343
05240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2134305240
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.setup_trans_ignored.468407058
Short name T196
Test name
Test status
Simulation time 8361060923 ps
CPU time 7.47 seconds
Started Feb 25 12:35:58 PM PST 24
Finished Feb 25 12:36:06 PM PST 24
Peak memory 202196 kb
Host smart-43e79950-015b-42ba-9c3d-1b87b4d70db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46840
7058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.setup_trans_ignored.468407058
Directory /workspace/20.setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2591157152
Short name T28
Test name
Test status
Simulation time 8458811448 ps
CPU time 7.65 seconds
Started Feb 25 12:35:43 PM PST 24
Finished Feb 25 12:35:51 PM PST 24
Peak memory 202116 kb
Host smart-c8beb2eb-ae6f-4c93-9d7a-a3f7b547272c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25911
57152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2591157152
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.4027172935
Short name T60
Test name
Test status
Simulation time 8398482174 ps
CPU time 8.7 seconds
Started Feb 25 12:35:57 PM PST 24
Finished Feb 25 12:36:07 PM PST 24
Peak memory 202012 kb
Host smart-8834135a-105f-4e54-b1dc-55d7f0ad257a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40271
72935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.4027172935
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2050481783
Short name T273
Test name
Test status
Simulation time 8372533621 ps
CPU time 8.04 seconds
Started Feb 25 12:35:53 PM PST 24
Finished Feb 25 12:36:03 PM PST 24
Peak memory 201240 kb
Host smart-8fa001c4-4d53-4d1b-b266-90a4e19be786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20504
81783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2050481783
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.in_trans.1833652254
Short name T107
Test name
Test status
Simulation time 8513415631 ps
CPU time 7.84 seconds
Started Feb 25 12:35:52 PM PST 24
Finished Feb 25 12:36:00 PM PST 24
Peak memory 202192 kb
Host smart-c62ffc35-a268-432b-9359-fbf7764d819e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
52254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.in_trans.1833652254
Directory /workspace/21.in_trans/latest

Test location /workspace/coverage/default/21.setup_trans_ignored.3271481950
Short name T332
Test name
Test status
Simulation time 8362766692 ps
CPU time 9.86 seconds
Started Feb 25 12:36:06 PM PST 24
Finished Feb 25 12:36:17 PM PST 24
Peak memory 202192 kb
Host smart-20635fdc-9577-4ac8-a0b2-e11800d698da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32714
81950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.setup_trans_ignored.3271481950
Directory /workspace/21.setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2083313558
Short name T313
Test name
Test status
Simulation time 8521783232 ps
CPU time 9.02 seconds
Started Feb 25 12:36:08 PM PST 24
Finished Feb 25 12:36:27 PM PST 24
Peak memory 202208 kb
Host smart-92ace5b1-255e-4fff-bcf1-911936d154cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20833
13558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2083313558
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2262540655
Short name T144
Test name
Test status
Simulation time 8407522393 ps
CPU time 7.08 seconds
Started Feb 25 12:35:58 PM PST 24
Finished Feb 25 12:36:07 PM PST 24
Peak memory 202132 kb
Host smart-b5fbeb52-ac85-44c2-8a7e-c217c3265cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22625
40655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2262540655
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1573832137
Short name T236
Test name
Test status
Simulation time 8367525428 ps
CPU time 8.2 seconds
Started Feb 25 12:36:08 PM PST 24
Finished Feb 25 12:36:16 PM PST 24
Peak memory 202196 kb
Host smart-8c5c849f-7e8e-42ac-9433-6207483316b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15738
32137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1573832137
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.in_trans.2208271333
Short name T256
Test name
Test status
Simulation time 8376895661 ps
CPU time 9.1 seconds
Started Feb 25 12:36:10 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202192 kb
Host smart-6f9753c1-973a-4ff1-a5c0-64f8c338317a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22082
71333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.in_trans.2208271333
Directory /workspace/22.in_trans/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2568630376
Short name T219
Test name
Test status
Simulation time 8448844548 ps
CPU time 9.67 seconds
Started Feb 25 12:36:05 PM PST 24
Finished Feb 25 12:36:15 PM PST 24
Peak memory 202144 kb
Host smart-ed7b0b4f-22e7-4ec3-8270-401307d7597c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25686
30376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2568630376
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1652427630
Short name T238
Test name
Test status
Simulation time 8371474066 ps
CPU time 9.4 seconds
Started Feb 25 12:36:04 PM PST 24
Finished Feb 25 12:36:14 PM PST 24
Peak memory 202016 kb
Host smart-affd436d-d78f-4dca-b1f2-01d7b48e4642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16524
27630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1652427630
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/23.in_trans.4079352230
Short name T263
Test name
Test status
Simulation time 8436085949 ps
CPU time 7.76 seconds
Started Feb 25 12:36:04 PM PST 24
Finished Feb 25 12:36:12 PM PST 24
Peak memory 202192 kb
Host smart-92a457d2-a9ab-42e2-bf11-eb6b9205d717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40793
52230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.in_trans.4079352230
Directory /workspace/23.in_trans/latest

Test location /workspace/coverage/default/23.setup_trans_ignored.2559168862
Short name T272
Test name
Test status
Simulation time 8362261665 ps
CPU time 8.38 seconds
Started Feb 25 12:36:11 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202204 kb
Host smart-9e0b6808-069d-4bfc-b00c-7ec729108304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25591
68862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.setup_trans_ignored.2559168862
Directory /workspace/23.setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1714872117
Short name T258
Test name
Test status
Simulation time 8369199853 ps
CPU time 7.57 seconds
Started Feb 25 12:36:03 PM PST 24
Finished Feb 25 12:36:10 PM PST 24
Peak memory 202152 kb
Host smart-2ccac3b2-8e7b-459d-8aef-06bf746f25a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17148
72117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1714872117
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.4179922356
Short name T188
Test name
Test status
Simulation time 8431911040 ps
CPU time 7.72 seconds
Started Feb 25 12:36:13 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202192 kb
Host smart-285f82c7-4587-4634-ab51-82914f5d96d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41799
22356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.4179922356
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_smoke.197283859
Short name T336
Test name
Test status
Simulation time 8371590874 ps
CPU time 7.82 seconds
Started Feb 25 12:36:04 PM PST 24
Finished Feb 25 12:36:12 PM PST 24
Peak memory 202188 kb
Host smart-320ac2e2-39cf-4867-ac3e-8754804df3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19728
3859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.197283859
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.in_trans.1204002294
Short name T170
Test name
Test status
Simulation time 8389466416 ps
CPU time 7.48 seconds
Started Feb 25 12:36:24 PM PST 24
Finished Feb 25 12:36:32 PM PST 24
Peak memory 202176 kb
Host smart-723f13fc-89c2-467a-9a7c-47f513ed2b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12040
02294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.in_trans.1204002294
Directory /workspace/24.in_trans/latest

Test location /workspace/coverage/default/24.setup_trans_ignored.3442691852
Short name T228
Test name
Test status
Simulation time 8361205867 ps
CPU time 7.65 seconds
Started Feb 25 12:36:02 PM PST 24
Finished Feb 25 12:36:10 PM PST 24
Peak memory 202236 kb
Host smart-ad41ce04-cc96-4b88-b384-50dfa0121696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34426
91852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.setup_trans_ignored.3442691852
Directory /workspace/24.setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1911539987
Short name T83
Test name
Test status
Simulation time 8424599011 ps
CPU time 7.58 seconds
Started Feb 25 12:36:06 PM PST 24
Finished Feb 25 12:36:14 PM PST 24
Peak memory 202212 kb
Host smart-1847624f-695c-4c48-90e5-4264a76f2959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19115
39987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1911539987
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2634123475
Short name T169
Test name
Test status
Simulation time 8395849790 ps
CPU time 7.41 seconds
Started Feb 25 12:36:06 PM PST 24
Finished Feb 25 12:36:20 PM PST 24
Peak memory 202192 kb
Host smart-43dfd7ba-5b68-437b-9d6a-8de87d896552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26341
23475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2634123475
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3955637202
Short name T171
Test name
Test status
Simulation time 8366723230 ps
CPU time 7.52 seconds
Started Feb 25 12:36:10 PM PST 24
Finished Feb 25 12:36:20 PM PST 24
Peak memory 202136 kb
Host smart-82a1ba2c-0e88-4ce9-bd1d-ad6ba93d5a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39556
37202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3955637202
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.in_trans.4189172408
Short name T167
Test name
Test status
Simulation time 8445262609 ps
CPU time 8.65 seconds
Started Feb 25 12:36:08 PM PST 24
Finished Feb 25 12:36:17 PM PST 24
Peak memory 202196 kb
Host smart-9f86cc62-a7da-438b-88d1-5561d57dad15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41891
72408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.in_trans.4189172408
Directory /workspace/25.in_trans/latest

Test location /workspace/coverage/default/25.setup_trans_ignored.23508494
Short name T254
Test name
Test status
Simulation time 8361636169 ps
CPU time 7.82 seconds
Started Feb 25 12:36:05 PM PST 24
Finished Feb 25 12:36:13 PM PST 24
Peak memory 202192 kb
Host smart-94332639-fa5d-48ac-b33b-cf0b0e8d8beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23508
494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.setup_trans_ignored.23508494
Directory /workspace/25.setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1959018672
Short name T305
Test name
Test status
Simulation time 8400931493 ps
CPU time 7.81 seconds
Started Feb 25 12:36:07 PM PST 24
Finished Feb 25 12:36:16 PM PST 24
Peak memory 202208 kb
Host smart-019c052e-1a6a-4bda-9eaf-9cb371cd6f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19590
18672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1959018672
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3691891012
Short name T78
Test name
Test status
Simulation time 8398700881 ps
CPU time 8.48 seconds
Started Feb 25 12:36:15 PM PST 24
Finished Feb 25 12:36:24 PM PST 24
Peak memory 202240 kb
Host smart-9b09ee45-7873-4ed3-807e-598187b77f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36918
91012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3691891012
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2631363274
Short name T16
Test name
Test status
Simulation time 8382328262 ps
CPU time 9.87 seconds
Started Feb 25 12:36:07 PM PST 24
Finished Feb 25 12:36:18 PM PST 24
Peak memory 202196 kb
Host smart-9422a736-9f31-4386-a82f-348cf4e34124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26313
63274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2631363274
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_smoke.20003779
Short name T11
Test name
Test status
Simulation time 8379021683 ps
CPU time 7.7 seconds
Started Feb 25 12:36:06 PM PST 24
Finished Feb 25 12:36:14 PM PST 24
Peak memory 202372 kb
Host smart-c515a742-f103-4ffa-b533-d19b588ed4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20003
779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.20003779
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.in_trans.4220188039
Short name T8
Test name
Test status
Simulation time 8387071529 ps
CPU time 7.69 seconds
Started Feb 25 12:36:11 PM PST 24
Finished Feb 25 12:36:20 PM PST 24
Peak memory 202164 kb
Host smart-a6d3b6be-b90c-4685-8e76-195483aa1990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42201
88039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.in_trans.4220188039
Directory /workspace/26.in_trans/latest

Test location /workspace/coverage/default/26.setup_trans_ignored.70405978
Short name T246
Test name
Test status
Simulation time 8356920862 ps
CPU time 9.01 seconds
Started Feb 25 12:36:09 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202208 kb
Host smart-e5b9d03e-98d8-4c2b-8674-7731b05921cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70405
978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.setup_trans_ignored.70405978
Directory /workspace/26.setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2186693204
Short name T278
Test name
Test status
Simulation time 8376657499 ps
CPU time 7.12 seconds
Started Feb 25 12:36:13 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202148 kb
Host smart-60082974-413f-4f13-8393-c88d7a14618a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21866
93204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2186693204
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1040998285
Short name T86
Test name
Test status
Simulation time 8433940479 ps
CPU time 8.98 seconds
Started Feb 25 12:36:15 PM PST 24
Finished Feb 25 12:36:24 PM PST 24
Peak memory 202184 kb
Host smart-eec38e74-903f-4988-8fe4-313e6623ecf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10409
98285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1040998285
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_smoke.780216884
Short name T156
Test name
Test status
Simulation time 8377341348 ps
CPU time 7.07 seconds
Started Feb 25 12:36:09 PM PST 24
Finished Feb 25 12:36:19 PM PST 24
Peak memory 202192 kb
Host smart-5425a0fb-3159-4cad-a5a6-7e4b412005f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78021
6884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.780216884
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.in_trans.69820689
Short name T175
Test name
Test status
Simulation time 8519221189 ps
CPU time 7.71 seconds
Started Feb 25 12:36:14 PM PST 24
Finished Feb 25 12:36:22 PM PST 24
Peak memory 202188 kb
Host smart-12f2ee89-3240-41dd-89a7-c0beb5635eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69820
689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.in_trans.69820689
Directory /workspace/27.in_trans/latest

Test location /workspace/coverage/default/27.setup_trans_ignored.4242534441
Short name T257
Test name
Test status
Simulation time 8358524648 ps
CPU time 7.93 seconds
Started Feb 25 12:36:38 PM PST 24
Finished Feb 25 12:36:47 PM PST 24
Peak memory 202044 kb
Host smart-ca71c1f5-79b7-48a6-ba4e-ac24297c418a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42425
34441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.setup_trans_ignored.4242534441
Directory /workspace/27.setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3486807937
Short name T174
Test name
Test status
Simulation time 8374201539 ps
CPU time 7.14 seconds
Started Feb 25 12:36:14 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202252 kb
Host smart-5d61a9f2-fab2-464f-9489-a0ce43071741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34868
07937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3486807937
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1845510029
Short name T289
Test name
Test status
Simulation time 8411382811 ps
CPU time 8.44 seconds
Started Feb 25 12:36:21 PM PST 24
Finished Feb 25 12:36:30 PM PST 24
Peak memory 202116 kb
Host smart-3e37df7f-91fc-481f-b716-d4852fcb720b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18455
10029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1845510029
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3987749870
Short name T204
Test name
Test status
Simulation time 8452804912 ps
CPU time 7.46 seconds
Started Feb 25 12:36:25 PM PST 24
Finished Feb 25 12:36:32 PM PST 24
Peak memory 202192 kb
Host smart-b3e441c2-0ca7-4398-9085-ef5fa362b997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
49870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3987749870
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2991206282
Short name T296
Test name
Test status
Simulation time 8372970983 ps
CPU time 7.25 seconds
Started Feb 25 12:36:27 PM PST 24
Finished Feb 25 12:36:34 PM PST 24
Peak memory 202136 kb
Host smart-eb3b6353-78a5-407c-a267-b538f03510e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29912
06282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2991206282
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.in_trans.897027503
Short name T106
Test name
Test status
Simulation time 8471072302 ps
CPU time 9.21 seconds
Started Feb 25 12:36:34 PM PST 24
Finished Feb 25 12:36:44 PM PST 24
Peak memory 201944 kb
Host smart-25c68a07-d8df-4d05-8468-94b02aeb3479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89702
7503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.in_trans.897027503
Directory /workspace/28.in_trans/latest

Test location /workspace/coverage/default/28.setup_trans_ignored.1999193849
Short name T226
Test name
Test status
Simulation time 8359234361 ps
CPU time 7.46 seconds
Started Feb 25 12:36:09 PM PST 24
Finished Feb 25 12:36:19 PM PST 24
Peak memory 202224 kb
Host smart-92a24834-9d27-4947-96dc-90e4fd165fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19991
93849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.setup_trans_ignored.1999193849
Directory /workspace/28.setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.4034905280
Short name T221
Test name
Test status
Simulation time 8369123447 ps
CPU time 7.44 seconds
Started Feb 25 12:36:13 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202208 kb
Host smart-c1ce33df-2b0d-449a-afd5-7e9549ccc821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40349
05280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.4034905280
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.379624021
Short name T338
Test name
Test status
Simulation time 8406386516 ps
CPU time 8.92 seconds
Started Feb 25 12:36:11 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202192 kb
Host smart-b5622638-51d3-46f0-9804-a7b8125acdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37962
4021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.379624021
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3916641974
Short name T248
Test name
Test status
Simulation time 8367169164 ps
CPU time 8.11 seconds
Started Feb 25 12:37:08 PM PST 24
Finished Feb 25 12:37:16 PM PST 24
Peak memory 202080 kb
Host smart-6c85168b-b4f2-483b-96ef-92fb2cc053df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39166
41974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3916641974
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.setup_trans_ignored.1049254079
Short name T18
Test name
Test status
Simulation time 8358814101 ps
CPU time 7.06 seconds
Started Feb 25 12:36:23 PM PST 24
Finished Feb 25 12:36:31 PM PST 24
Peak memory 202132 kb
Host smart-a2aa2f53-88cd-4da0-a888-e8dbba2e4bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10492
54079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.setup_trans_ignored.1049254079
Directory /workspace/29.setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2567550089
Short name T223
Test name
Test status
Simulation time 8367392425 ps
CPU time 7.13 seconds
Started Feb 25 12:36:12 PM PST 24
Finished Feb 25 12:36:20 PM PST 24
Peak memory 202212 kb
Host smart-18500db2-9e26-460d-9ad5-f666651fe9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25675
50089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2567550089
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2075916459
Short name T65
Test name
Test status
Simulation time 8446253963 ps
CPU time 9.13 seconds
Started Feb 25 12:36:23 PM PST 24
Finished Feb 25 12:36:32 PM PST 24
Peak memory 202140 kb
Host smart-639458ec-9f5b-4bf0-9e17-301466dc9f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20759
16459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2075916459
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3688241696
Short name T105
Test name
Test status
Simulation time 8467198601 ps
CPU time 7.18 seconds
Started Feb 25 12:36:13 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202316 kb
Host smart-3e270135-17c6-41f8-ba7f-e74d4729f860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36882
41696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3688241696
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1981226260
Short name T54
Test name
Test status
Simulation time 8374052857 ps
CPU time 7.43 seconds
Started Feb 25 12:36:10 PM PST 24
Finished Feb 25 12:36:20 PM PST 24
Peak memory 202184 kb
Host smart-69c9e237-d3ff-4291-b6f2-d169df2550cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19812
26260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1981226260
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.in_trans.454704173
Short name T293
Test name
Test status
Simulation time 8528505388 ps
CPU time 9.21 seconds
Started Feb 25 12:35:17 PM PST 24
Finished Feb 25 12:35:27 PM PST 24
Peak memory 202196 kb
Host smart-48ed11e2-044d-4405-96ee-9432a21a718a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45470
4173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.in_trans.454704173
Directory /workspace/3.in_trans/latest

Test location /workspace/coverage/default/3.setup_trans_ignored.1190037966
Short name T324
Test name
Test status
Simulation time 8362466683 ps
CPU time 9.1 seconds
Started Feb 25 12:35:16 PM PST 24
Finished Feb 25 12:35:25 PM PST 24
Peak memory 202204 kb
Host smart-41afe2d8-1793-4d8b-9fbd-c10378c0ee90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11900
37966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.setup_trans_ignored.1190037966
Directory /workspace/3.setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3645183236
Short name T265
Test name
Test status
Simulation time 8366996141 ps
CPU time 7.58 seconds
Started Feb 25 12:35:38 PM PST 24
Finished Feb 25 12:35:45 PM PST 24
Peak memory 202116 kb
Host smart-f35e8d86-f990-482f-9539-c75fbce369f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36451
83236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3645183236
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1436395784
Short name T14
Test name
Test status
Simulation time 8426600884 ps
CPU time 8.03 seconds
Started Feb 25 12:35:26 PM PST 24
Finished Feb 25 12:35:35 PM PST 24
Peak memory 202240 kb
Host smart-ab0b173e-c603-421f-9165-b6f20f51474b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363
95784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1436395784
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.933700123
Short name T304
Test name
Test status
Simulation time 8413747892 ps
CPU time 8.25 seconds
Started Feb 25 12:35:24 PM PST 24
Finished Feb 25 12:35:38 PM PST 24
Peak memory 202224 kb
Host smart-114796f1-4995-4c93-93d4-1f94a5ca2d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93370
0123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.933700123
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_smoke.469209928
Short name T250
Test name
Test status
Simulation time 8376663494 ps
CPU time 7.95 seconds
Started Feb 25 12:35:38 PM PST 24
Finished Feb 25 12:35:46 PM PST 24
Peak memory 202120 kb
Host smart-fa04d3d5-00eb-465f-ade0-5a4137807d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46920
9928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.469209928
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.in_trans.1588710268
Short name T22
Test name
Test status
Simulation time 8457925472 ps
CPU time 8.96 seconds
Started Feb 25 12:36:10 PM PST 24
Finished Feb 25 12:36:21 PM PST 24
Peak memory 202252 kb
Host smart-83812423-f364-44fd-a50a-c5f90eb07f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15887
10268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.in_trans.1588710268
Directory /workspace/30.in_trans/latest

Test location /workspace/coverage/default/30.setup_trans_ignored.1346223602
Short name T49
Test name
Test status
Simulation time 8360128283 ps
CPU time 7.96 seconds
Started Feb 25 12:36:25 PM PST 24
Finished Feb 25 12:36:33 PM PST 24
Peak memory 202192 kb
Host smart-480cd4d0-5e39-428a-a00c-59806a561fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13462
23602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.setup_trans_ignored.1346223602
Directory /workspace/30.setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.50825898
Short name T26
Test name
Test status
Simulation time 8373902660 ps
CPU time 8 seconds
Started Feb 25 12:36:14 PM PST 24
Finished Feb 25 12:36:23 PM PST 24
Peak memory 202192 kb
Host smart-2714907d-7964-43be-9f3a-1d56456cf4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50825
898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.50825898
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.63386928
Short name T73
Test name
Test status
Simulation time 8415761960 ps
CPU time 9.73 seconds
Started Feb 25 12:36:17 PM PST 24
Finished Feb 25 12:36:27 PM PST 24
Peak memory 202176 kb
Host smart-9ffc1699-9228-4497-8131-9eec737e884f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63386
928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.63386928
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4131461842
Short name T306
Test name
Test status
Simulation time 8409686421 ps
CPU time 7.69 seconds
Started Feb 25 12:36:09 PM PST 24
Finished Feb 25 12:36:20 PM PST 24
Peak memory 202144 kb
Host smart-91af0f47-077c-4dcc-a132-593c6f7dcf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41314
61842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4131461842
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_smoke.4234594253
Short name T51
Test name
Test status
Simulation time 8372443825 ps
CPU time 7.64 seconds
Started Feb 25 12:36:41 PM PST 24
Finished Feb 25 12:36:49 PM PST 24
Peak memory 202192 kb
Host smart-0cc96080-f0f2-4b93-89d1-243b0f5486c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345
94253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.4234594253
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.in_trans.4019289734
Short name T184
Test name
Test status
Simulation time 8400397129 ps
CPU time 7.75 seconds
Started Feb 25 12:36:30 PM PST 24
Finished Feb 25 12:36:43 PM PST 24
Peak memory 202196 kb
Host smart-4708ad94-8a7a-44fb-9716-039e58f2d974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40192
89734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.in_trans.4019289734
Directory /workspace/31.in_trans/latest

Test location /workspace/coverage/default/31.setup_trans_ignored.3869233142
Short name T249
Test name
Test status
Simulation time 8354688284 ps
CPU time 7.13 seconds
Started Feb 25 12:36:11 PM PST 24
Finished Feb 25 12:36:20 PM PST 24
Peak memory 202180 kb
Host smart-34545800-43b0-4575-8193-b48f7c025fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38692
33142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.setup_trans_ignored.3869233142
Directory /workspace/31.setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1392448441
Short name T152
Test name
Test status
Simulation time 8394187662 ps
CPU time 6.76 seconds
Started Feb 25 12:36:25 PM PST 24
Finished Feb 25 12:36:31 PM PST 24
Peak memory 202148 kb
Host smart-e613bb2e-a29e-4943-9067-dda1c6424a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13924
48441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1392448441
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1113578438
Short name T85
Test name
Test status
Simulation time 8417364275 ps
CPU time 8.09 seconds
Started Feb 25 12:36:28 PM PST 24
Finished Feb 25 12:36:37 PM PST 24
Peak memory 202228 kb
Host smart-6a10510d-9ef9-49c0-888a-e8cb6b252be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
78438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1113578438
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2745457369
Short name T1
Test name
Test status
Simulation time 8375712169 ps
CPU time 7.73 seconds
Started Feb 25 12:36:34 PM PST 24
Finished Feb 25 12:36:43 PM PST 24
Peak memory 202196 kb
Host smart-6b44c4c8-d242-440f-a2e9-d2c6da7c264e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27454
57369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2745457369
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_smoke.799262008
Short name T230
Test name
Test status
Simulation time 8367055958 ps
CPU time 7.45 seconds
Started Feb 25 12:36:36 PM PST 24
Finished Feb 25 12:36:44 PM PST 24
Peak memory 202232 kb
Host smart-e6751f90-601e-4aec-b755-9469151ad3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79926
2008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.799262008
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.in_trans.2426767708
Short name T147
Test name
Test status
Simulation time 8485002702 ps
CPU time 6.93 seconds
Started Feb 25 12:36:11 PM PST 24
Finished Feb 25 12:36:19 PM PST 24
Peak memory 202192 kb
Host smart-5a9af792-e43e-4e0a-a28e-2405ea13dc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24267
67708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.in_trans.2426767708
Directory /workspace/32.in_trans/latest

Test location /workspace/coverage/default/32.setup_trans_ignored.3465304434
Short name T227
Test name
Test status
Simulation time 8389536529 ps
CPU time 7.45 seconds
Started Feb 25 12:36:20 PM PST 24
Finished Feb 25 12:36:28 PM PST 24
Peak memory 202208 kb
Host smart-3f79c108-97d1-4516-9915-d2efd6f0304a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34653
04434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.setup_trans_ignored.3465304434
Directory /workspace/32.setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.4715859
Short name T200
Test name
Test status
Simulation time 8370578253 ps
CPU time 7.57 seconds
Started Feb 25 12:36:41 PM PST 24
Finished Feb 25 12:36:49 PM PST 24
Peak memory 202188 kb
Host smart-74c991eb-ce79-4b5a-ae16-b396219249ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47158
59 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.4715859
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3104981452
Short name T92
Test name
Test status
Simulation time 8423523307 ps
CPU time 8.82 seconds
Started Feb 25 12:36:13 PM PST 24
Finished Feb 25 12:36:22 PM PST 24
Peak memory 202196 kb
Host smart-5e37f1ce-811c-4994-a3ab-220536564281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31049
81452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3104981452
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1888867149
Short name T7
Test name
Test status
Simulation time 8366201048 ps
CPU time 7.62 seconds
Started Feb 25 12:36:32 PM PST 24
Finished Feb 25 12:36:40 PM PST 24
Peak memory 202192 kb
Host smart-b3629703-47a3-43e3-9f63-6edb52624074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18888
67149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1888867149
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.in_trans.951505195
Short name T183
Test name
Test status
Simulation time 8400526743 ps
CPU time 7.47 seconds
Started Feb 25 12:37:14 PM PST 24
Finished Feb 25 12:37:22 PM PST 24
Peak memory 202192 kb
Host smart-651b0b9e-c0fd-449a-a023-9d30cb09d1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95150
5195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.in_trans.951505195
Directory /workspace/33.in_trans/latest

Test location /workspace/coverage/default/33.setup_trans_ignored.2611507045
Short name T303
Test name
Test status
Simulation time 8361008414 ps
CPU time 8.76 seconds
Started Feb 25 12:36:44 PM PST 24
Finished Feb 25 12:36:54 PM PST 24
Peak memory 202192 kb
Host smart-c7496c64-6a57-42a8-a18b-b3b5fd15c044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26115
07045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.setup_trans_ignored.2611507045
Directory /workspace/33.setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.672199385
Short name T185
Test name
Test status
Simulation time 8366654927 ps
CPU time 7.53 seconds
Started Feb 25 12:36:34 PM PST 24
Finished Feb 25 12:36:43 PM PST 24
Peak memory 202228 kb
Host smart-267f1cdd-5b5b-48b6-a55a-2796a5b324a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67219
9385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.672199385
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2066206480
Short name T262
Test name
Test status
Simulation time 8371869307 ps
CPU time 9.99 seconds
Started Feb 25 12:36:25 PM PST 24
Finished Feb 25 12:36:35 PM PST 24
Peak memory 202196 kb
Host smart-955feb28-23f4-4a66-8171-6eef76950d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20662
06480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2066206480
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3625184604
Short name T206
Test name
Test status
Simulation time 8374513412 ps
CPU time 8.86 seconds
Started Feb 25 12:36:19 PM PST 24
Finished Feb 25 12:36:28 PM PST 24
Peak memory 202192 kb
Host smart-613f2c6e-c35e-4f4a-ac1b-e07169b0267f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36251
84604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3625184604
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.in_trans.3265265218
Short name T299
Test name
Test status
Simulation time 8426900883 ps
CPU time 7.4 seconds
Started Feb 25 12:36:15 PM PST 24
Finished Feb 25 12:36:23 PM PST 24
Peak memory 202196 kb
Host smart-aa13eb2a-339e-4f69-bde9-fb312cbdfeea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32652
65218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.in_trans.3265265218
Directory /workspace/34.in_trans/latest

Test location /workspace/coverage/default/34.setup_trans_ignored.2842784414
Short name T251
Test name
Test status
Simulation time 8359982168 ps
CPU time 7.47 seconds
Started Feb 25 12:36:46 PM PST 24
Finished Feb 25 12:36:54 PM PST 24
Peak memory 202092 kb
Host smart-b15f529d-0f8b-4662-8a40-5adb9403f495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
84414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.setup_trans_ignored.2842784414
Directory /workspace/34.setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2453492864
Short name T30
Test name
Test status
Simulation time 8372808374 ps
CPU time 7.4 seconds
Started Feb 25 12:36:27 PM PST 24
Finished Feb 25 12:36:35 PM PST 24
Peak memory 202208 kb
Host smart-76d9c7d0-2c15-40d4-8547-2b6ed5eb1dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24534
92864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2453492864
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3893266623
Short name T81
Test name
Test status
Simulation time 8511375820 ps
CPU time 7.18 seconds
Started Feb 25 12:36:47 PM PST 24
Finished Feb 25 12:36:54 PM PST 24
Peak memory 202132 kb
Host smart-399b5fa7-d78e-456d-ba32-4ba8697e501a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38932
66623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3893266623
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.481929678
Short name T339
Test name
Test status
Simulation time 8436110296 ps
CPU time 9.24 seconds
Started Feb 25 12:36:48 PM PST 24
Finished Feb 25 12:36:58 PM PST 24
Peak memory 202136 kb
Host smart-899a093e-57f0-41ec-90d9-c0bd38717296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48192
9678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.481929678
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_smoke.4193263281
Short name T302
Test name
Test status
Simulation time 8370739991 ps
CPU time 7.54 seconds
Started Feb 25 12:36:34 PM PST 24
Finished Feb 25 12:36:43 PM PST 24
Peak memory 202192 kb
Host smart-dc17c124-1c32-4d34-bd11-9f0420e0295a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
63281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.4193263281
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.in_trans.1898982996
Short name T220
Test name
Test status
Simulation time 8378089183 ps
CPU time 7.7 seconds
Started Feb 25 12:36:43 PM PST 24
Finished Feb 25 12:36:51 PM PST 24
Peak memory 202252 kb
Host smart-113a7a9b-0863-43d3-8b4a-17b9df9c8af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18989
82996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.in_trans.1898982996
Directory /workspace/35.in_trans/latest

Test location /workspace/coverage/default/35.setup_trans_ignored.2232515431
Short name T2
Test name
Test status
Simulation time 8365625577 ps
CPU time 7.27 seconds
Started Feb 25 12:36:43 PM PST 24
Finished Feb 25 12:36:53 PM PST 24
Peak memory 202128 kb
Host smart-e1e2a859-d7b1-463b-8952-45dd651fbdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22325
15431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.setup_trans_ignored.2232515431
Directory /workspace/35.setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1753689468
Short name T181
Test name
Test status
Simulation time 8368551354 ps
CPU time 8.99 seconds
Started Feb 25 12:36:46 PM PST 24
Finished Feb 25 12:36:55 PM PST 24
Peak memory 202040 kb
Host smart-389bbf81-6fde-4256-a779-505ec1532a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17536
89468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1753689468
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.4137393097
Short name T287
Test name
Test status
Simulation time 8437875409 ps
CPU time 7.33 seconds
Started Feb 25 12:36:47 PM PST 24
Finished Feb 25 12:36:54 PM PST 24
Peak memory 202252 kb
Host smart-bab35fd2-7774-4e33-97f7-68cca9803b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41373
93097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.4137393097
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3227166177
Short name T310
Test name
Test status
Simulation time 8369419119 ps
CPU time 7.42 seconds
Started Feb 25 12:36:32 PM PST 24
Finished Feb 25 12:36:40 PM PST 24
Peak memory 202188 kb
Host smart-f78787c6-e75e-4bd4-919c-195cb84d3ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32271
66177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3227166177
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.in_trans.2899081307
Short name T148
Test name
Test status
Simulation time 8444515058 ps
CPU time 6.99 seconds
Started Feb 25 12:36:35 PM PST 24
Finished Feb 25 12:36:43 PM PST 24
Peak memory 202124 kb
Host smart-0f50598d-5b05-4b79-a728-40c4653dbf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28990
81307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.in_trans.2899081307
Directory /workspace/36.in_trans/latest

Test location /workspace/coverage/default/36.setup_trans_ignored.2675100877
Short name T318
Test name
Test status
Simulation time 8359563990 ps
CPU time 8.35 seconds
Started Feb 25 12:36:20 PM PST 24
Finished Feb 25 12:36:28 PM PST 24
Peak memory 202192 kb
Host smart-65446d1e-73d1-424a-9a4a-bfc42cc07029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26751
00877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.setup_trans_ignored.2675100877
Directory /workspace/36.setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2610269735
Short name T31
Test name
Test status
Simulation time 8407468628 ps
CPU time 6.88 seconds
Started Feb 25 12:36:46 PM PST 24
Finished Feb 25 12:36:53 PM PST 24
Peak memory 202180 kb
Host smart-c98119fa-3b2d-426a-83d0-22d6cf55b2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
69735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2610269735
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.984589158
Short name T190
Test name
Test status
Simulation time 8458931768 ps
CPU time 7.77 seconds
Started Feb 25 12:36:48 PM PST 24
Finished Feb 25 12:36:56 PM PST 24
Peak memory 202212 kb
Host smart-4d1322bc-97f5-4c92-bae3-59777f031826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98458
9158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.984589158
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3935670821
Short name T232
Test name
Test status
Simulation time 8448388928 ps
CPU time 7.7 seconds
Started Feb 25 12:36:23 PM PST 24
Finished Feb 25 12:36:31 PM PST 24
Peak memory 202192 kb
Host smart-49b8e1cf-00d5-4ade-a714-ef7f908a6ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39356
70821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3935670821
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_smoke.991591005
Short name T255
Test name
Test status
Simulation time 8368837669 ps
CPU time 7.06 seconds
Started Feb 25 12:36:33 PM PST 24
Finished Feb 25 12:36:42 PM PST 24
Peak memory 202188 kb
Host smart-b995fdd2-99ba-45e0-a76f-7d4a335bad08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99159
1005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.991591005
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.in_trans.2560574753
Short name T110
Test name
Test status
Simulation time 8430219104 ps
CPU time 7.6 seconds
Started Feb 25 12:36:36 PM PST 24
Finished Feb 25 12:36:44 PM PST 24
Peak memory 202196 kb
Host smart-a9239262-2b75-41d2-bd5c-aeed0a97818d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25605
74753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.in_trans.2560574753
Directory /workspace/37.in_trans/latest

Test location /workspace/coverage/default/37.setup_trans_ignored.3535136333
Short name T322
Test name
Test status
Simulation time 8357518563 ps
CPU time 7.37 seconds
Started Feb 25 12:36:36 PM PST 24
Finished Feb 25 12:36:44 PM PST 24
Peak memory 202192 kb
Host smart-366f52b0-3ad6-4e54-9844-b84dd8649b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35351
36333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.setup_trans_ignored.3535136333
Directory /workspace/37.setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1243718363
Short name T340
Test name
Test status
Simulation time 8373100174 ps
CPU time 7.46 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:10 PM PST 24
Peak memory 202204 kb
Host smart-82414696-bf9a-4aa7-aa6f-766972660e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12437
18363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1243718363
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3393722319
Short name T143
Test name
Test status
Simulation time 8423332283 ps
CPU time 8.88 seconds
Started Feb 25 12:36:53 PM PST 24
Finished Feb 25 12:37:02 PM PST 24
Peak memory 202252 kb
Host smart-4f156c8e-655b-4741-b3fa-2043c2f33434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33937
22319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3393722319
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_smoke.4270611836
Short name T240
Test name
Test status
Simulation time 8367440401 ps
CPU time 7.65 seconds
Started Feb 25 12:36:41 PM PST 24
Finished Feb 25 12:36:49 PM PST 24
Peak memory 202176 kb
Host smart-ab6c6ed4-96a4-439a-8498-a69321acd0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42706
11836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.4270611836
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.in_trans.3108637809
Short name T268
Test name
Test status
Simulation time 8421853010 ps
CPU time 8.57 seconds
Started Feb 25 12:36:39 PM PST 24
Finished Feb 25 12:36:48 PM PST 24
Peak memory 202196 kb
Host smart-5df25f6a-37ad-4312-9297-011bf93bec3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31086
37809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.in_trans.3108637809
Directory /workspace/38.in_trans/latest

Test location /workspace/coverage/default/38.setup_trans_ignored.3665407739
Short name T244
Test name
Test status
Simulation time 8360193908 ps
CPU time 7.57 seconds
Started Feb 25 12:36:50 PM PST 24
Finished Feb 25 12:36:57 PM PST 24
Peak memory 202204 kb
Host smart-8204eba0-86bf-4545-8674-7c1888052ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36654
07739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.setup_trans_ignored.3665407739
Directory /workspace/38.setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.562796906
Short name T203
Test name
Test status
Simulation time 8371909943 ps
CPU time 8.89 seconds
Started Feb 25 12:36:44 PM PST 24
Finished Feb 25 12:36:59 PM PST 24
Peak memory 202252 kb
Host smart-ec899d04-86bd-4fd1-8c72-ba5f9f66c886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56279
6906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.562796906
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2248516148
Short name T295
Test name
Test status
Simulation time 8413957043 ps
CPU time 9.12 seconds
Started Feb 25 12:36:56 PM PST 24
Finished Feb 25 12:37:07 PM PST 24
Peak memory 202032 kb
Host smart-5c71b967-38d7-428e-851d-763835fa5d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22485
16148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2248516148
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.4036095728
Short name T102
Test name
Test status
Simulation time 8438494995 ps
CPU time 8.01 seconds
Started Feb 25 12:36:42 PM PST 24
Finished Feb 25 12:36:50 PM PST 24
Peak memory 202196 kb
Host smart-d71d2c14-aa52-46ed-b59a-2096bd6a90c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40360
95728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.4036095728
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3584320494
Short name T231
Test name
Test status
Simulation time 8414022020 ps
CPU time 8.32 seconds
Started Feb 25 12:36:38 PM PST 24
Finished Feb 25 12:36:46 PM PST 24
Peak memory 202376 kb
Host smart-483dd834-7552-4c1d-9726-2bc443a8351f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35843
20494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3584320494
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.in_trans.3005537233
Short name T261
Test name
Test status
Simulation time 8422333013 ps
CPU time 8.41 seconds
Started Feb 25 12:36:44 PM PST 24
Finished Feb 25 12:36:54 PM PST 24
Peak memory 202224 kb
Host smart-1e9bb360-93d8-460f-b73f-e71a6c68b27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30055
37233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.in_trans.3005537233
Directory /workspace/39.in_trans/latest

Test location /workspace/coverage/default/39.setup_trans_ignored.2300631098
Short name T218
Test name
Test status
Simulation time 8461473373 ps
CPU time 9.16 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:20 PM PST 24
Peak memory 202260 kb
Host smart-9aacda7b-af01-4717-bbad-535e6516ebb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23006
31098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.setup_trans_ignored.2300631098
Directory /workspace/39.setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2642475999
Short name T194
Test name
Test status
Simulation time 8367476630 ps
CPU time 7.72 seconds
Started Feb 25 12:36:38 PM PST 24
Finished Feb 25 12:36:47 PM PST 24
Peak memory 202212 kb
Host smart-407f68c5-36f7-4d6a-926d-51f75fc8944b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26424
75999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2642475999
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1578753512
Short name T88
Test name
Test status
Simulation time 8406979327 ps
CPU time 7.54 seconds
Started Feb 25 12:36:59 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 202212 kb
Host smart-c5e34465-097f-425d-86e0-1fa054e28315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
53512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1578753512
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2938749121
Short name T297
Test name
Test status
Simulation time 8376829634 ps
CPU time 7.4 seconds
Started Feb 25 12:36:41 PM PST 24
Finished Feb 25 12:36:49 PM PST 24
Peak memory 202196 kb
Host smart-ca2d5971-76f1-434b-8446-18e8f7747d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29387
49121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2938749121
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3632307338
Short name T55
Test name
Test status
Simulation time 8366388217 ps
CPU time 7.07 seconds
Started Feb 25 12:36:51 PM PST 24
Finished Feb 25 12:36:58 PM PST 24
Peak memory 202244 kb
Host smart-e24d6144-9fa7-49eb-be4a-573a4fff2c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36323
07338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3632307338
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.in_trans.2364357015
Short name T259
Test name
Test status
Simulation time 8421421960 ps
CPU time 7.07 seconds
Started Feb 25 12:35:33 PM PST 24
Finished Feb 25 12:35:40 PM PST 24
Peak memory 202132 kb
Host smart-7426b396-93af-4f95-baec-c965355d3a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23643
57015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.in_trans.2364357015
Directory /workspace/4.in_trans/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1684750907
Short name T290
Test name
Test status
Simulation time 8367112971 ps
CPU time 7.94 seconds
Started Feb 25 12:35:30 PM PST 24
Finished Feb 25 12:35:39 PM PST 24
Peak memory 202212 kb
Host smart-0fcf19db-0de6-4c40-89fa-6c7926ce24ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
50907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1684750907
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3733394775
Short name T199
Test name
Test status
Simulation time 8383646808 ps
CPU time 7.91 seconds
Started Feb 25 12:35:28 PM PST 24
Finished Feb 25 12:35:37 PM PST 24
Peak memory 202188 kb
Host smart-899797fe-f52c-4e91-8e17-26c482b92d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37333
94775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3733394775
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3477723472
Short name T38
Test name
Test status
Simulation time 103486132 ps
CPU time 0.9 seconds
Started Feb 25 12:35:29 PM PST 24
Finished Feb 25 12:35:31 PM PST 24
Peak memory 216924 kb
Host smart-44803b86-ee93-422f-8b7d-32b98347ffa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3477723472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3477723472
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/40.setup_trans_ignored.1021900717
Short name T211
Test name
Test status
Simulation time 8362615397 ps
CPU time 7.09 seconds
Started Feb 25 12:36:48 PM PST 24
Finished Feb 25 12:36:55 PM PST 24
Peak memory 202132 kb
Host smart-23639128-dcf0-4b39-9d88-624672d57618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10219
00717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.setup_trans_ignored.1021900717
Directory /workspace/40.setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3847245334
Short name T241
Test name
Test status
Simulation time 8418107004 ps
CPU time 7.01 seconds
Started Feb 25 12:36:15 PM PST 24
Finished Feb 25 12:36:22 PM PST 24
Peak memory 202104 kb
Host smart-5d5cf7bd-2c6b-4d92-b5d4-aa0284fc380b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38472
45334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3847245334
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3651631175
Short name T197
Test name
Test status
Simulation time 8437507176 ps
CPU time 7.23 seconds
Started Feb 25 12:36:46 PM PST 24
Finished Feb 25 12:36:54 PM PST 24
Peak memory 202040 kb
Host smart-c77243ff-ec86-4355-949f-1b0b73cfb3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36516
31175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3651631175
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1265874636
Short name T260
Test name
Test status
Simulation time 8376712878 ps
CPU time 8.5 seconds
Started Feb 25 12:36:18 PM PST 24
Finished Feb 25 12:36:31 PM PST 24
Peak memory 202188 kb
Host smart-520c368c-3ee6-4c92-bdd9-b90ab3cd483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12658
74636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1265874636
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.in_trans.223210136
Short name T100
Test name
Test status
Simulation time 8399139407 ps
CPU time 7.07 seconds
Started Feb 25 12:36:43 PM PST 24
Finished Feb 25 12:36:52 PM PST 24
Peak memory 202100 kb
Host smart-0bb2d482-6d8b-4c46-a086-711fc922cba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22321
0136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.in_trans.223210136
Directory /workspace/41.in_trans/latest

Test location /workspace/coverage/default/41.setup_trans_ignored.4000533965
Short name T280
Test name
Test status
Simulation time 8355964946 ps
CPU time 9.53 seconds
Started Feb 25 12:36:36 PM PST 24
Finished Feb 25 12:36:46 PM PST 24
Peak memory 202196 kb
Host smart-ed966106-99c6-4ed9-a048-76a09c99e8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40005
33965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.setup_trans_ignored.4000533965
Directory /workspace/41.setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2107268548
Short name T151
Test name
Test status
Simulation time 8375987992 ps
CPU time 7.55 seconds
Started Feb 25 12:36:44 PM PST 24
Finished Feb 25 12:36:53 PM PST 24
Peak memory 202176 kb
Host smart-d8fdb63c-964f-4578-a390-239881bb72e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21072
68548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2107268548
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3922802538
Short name T69
Test name
Test status
Simulation time 8417665388 ps
CPU time 7.56 seconds
Started Feb 25 12:37:01 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 202208 kb
Host smart-f2b20864-161f-406a-b6d1-a11e55977bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39228
02538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3922802538
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2189543919
Short name T229
Test name
Test status
Simulation time 8427693168 ps
CPU time 8.08 seconds
Started Feb 25 12:36:54 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 202196 kb
Host smart-57c20267-5a90-4bbf-982f-d8f20b1def86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21895
43919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2189543919
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1532715482
Short name T311
Test name
Test status
Simulation time 8367564515 ps
CPU time 7.31 seconds
Started Feb 25 12:36:40 PM PST 24
Finished Feb 25 12:36:47 PM PST 24
Peak memory 202196 kb
Host smart-cf923625-39e4-431a-9727-2ddcf098c18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15327
15482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1532715482
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.in_trans.79285280
Short name T94
Test name
Test status
Simulation time 8407007539 ps
CPU time 7.76 seconds
Started Feb 25 12:36:37 PM PST 24
Finished Feb 25 12:36:45 PM PST 24
Peak memory 202188 kb
Host smart-93d70014-8074-4b87-be88-def00d64f31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79285
280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.in_trans.79285280
Directory /workspace/42.in_trans/latest

Test location /workspace/coverage/default/42.setup_trans_ignored.2265040567
Short name T189
Test name
Test status
Simulation time 8409822982 ps
CPU time 7.43 seconds
Started Feb 25 12:36:46 PM PST 24
Finished Feb 25 12:36:54 PM PST 24
Peak memory 202208 kb
Host smart-821eb4ab-d1b0-412b-b3a9-41efe3c17592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22650
40567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.setup_trans_ignored.2265040567
Directory /workspace/42.setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.681725081
Short name T150
Test name
Test status
Simulation time 8443785393 ps
CPU time 8.2 seconds
Started Feb 25 12:36:52 PM PST 24
Finished Feb 25 12:37:00 PM PST 24
Peak memory 202212 kb
Host smart-311ba20d-d050-40b6-a279-06637565280a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68172
5081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.681725081
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.4181423671
Short name T99
Test name
Test status
Simulation time 8457168934 ps
CPU time 8.37 seconds
Started Feb 25 12:36:30 PM PST 24
Finished Feb 25 12:36:39 PM PST 24
Peak memory 202152 kb
Host smart-c6f9c738-67b0-4983-9377-018d2bbc4c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
23671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4181423671
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1590273310
Short name T300
Test name
Test status
Simulation time 8381581223 ps
CPU time 8.02 seconds
Started Feb 25 12:36:40 PM PST 24
Finished Feb 25 12:36:49 PM PST 24
Peak memory 202196 kb
Host smart-97db2acf-f6dc-48ed-b8ce-0ece0a64773a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15902
73310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1590273310
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.in_trans.2179556027
Short name T95
Test name
Test status
Simulation time 8412474133 ps
CPU time 8.85 seconds
Started Feb 25 12:36:48 PM PST 24
Finished Feb 25 12:36:57 PM PST 24
Peak memory 202196 kb
Host smart-426e06b8-de61-459f-83bf-0c99ae5453d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21795
56027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.in_trans.2179556027
Directory /workspace/43.in_trans/latest

Test location /workspace/coverage/default/43.setup_trans_ignored.4213820337
Short name T301
Test name
Test status
Simulation time 8363977104 ps
CPU time 8.18 seconds
Started Feb 25 12:37:00 PM PST 24
Finished Feb 25 12:37:08 PM PST 24
Peak memory 202204 kb
Host smart-a723fc93-8d7f-438a-a92d-977a6a46e302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42138
20337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.setup_trans_ignored.4213820337
Directory /workspace/43.setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2388926494
Short name T331
Test name
Test status
Simulation time 8396296791 ps
CPU time 8.07 seconds
Started Feb 25 12:36:39 PM PST 24
Finished Feb 25 12:36:48 PM PST 24
Peak memory 202192 kb
Host smart-6bf6e47d-ad73-4b9a-8df9-3e91f6b2df4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23889
26494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2388926494
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3875802935
Short name T315
Test name
Test status
Simulation time 8406052758 ps
CPU time 7.81 seconds
Started Feb 25 12:36:36 PM PST 24
Finished Feb 25 12:36:44 PM PST 24
Peak memory 202176 kb
Host smart-44ad2d15-289c-4e52-9211-d18723f7c1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38758
02935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3875802935
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2669178764
Short name T193
Test name
Test status
Simulation time 8446238189 ps
CPU time 7.34 seconds
Started Feb 25 12:36:33 PM PST 24
Finished Feb 25 12:36:40 PM PST 24
Peak memory 202176 kb
Host smart-46305ba7-4e5c-4f1f-bdda-46a70514cace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26691
78764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2669178764
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1110735119
Short name T266
Test name
Test status
Simulation time 8370374033 ps
CPU time 7.65 seconds
Started Feb 25 12:36:23 PM PST 24
Finished Feb 25 12:36:31 PM PST 24
Peak memory 202196 kb
Host smart-a268821d-9bc4-47d4-a87b-c5b73b46b85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11107
35119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1110735119
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.in_trans.2595192561
Short name T98
Test name
Test status
Simulation time 8417923304 ps
CPU time 8.03 seconds
Started Feb 25 12:36:35 PM PST 24
Finished Feb 25 12:36:43 PM PST 24
Peak memory 202100 kb
Host smart-09f80415-03cd-45c5-8e88-e275ce9f312c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25951
92561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.in_trans.2595192561
Directory /workspace/44.in_trans/latest

Test location /workspace/coverage/default/44.setup_trans_ignored.2439341379
Short name T275
Test name
Test status
Simulation time 8363927216 ps
CPU time 7.4 seconds
Started Feb 25 12:36:32 PM PST 24
Finished Feb 25 12:36:40 PM PST 24
Peak memory 202196 kb
Host smart-621c64ec-13d5-41d2-8bbd-6c2a0d34684b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24393
41379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.setup_trans_ignored.2439341379
Directory /workspace/44.setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1547218890
Short name T20
Test name
Test status
Simulation time 8426234789 ps
CPU time 7.03 seconds
Started Feb 25 12:36:33 PM PST 24
Finished Feb 25 12:36:40 PM PST 24
Peak memory 202116 kb
Host smart-fe411ba0-bf31-4464-96b3-00f21890890e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15472
18890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1547218890
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.in_trans.1031734708
Short name T15
Test name
Test status
Simulation time 8418762311 ps
CPU time 7.38 seconds
Started Feb 25 12:37:10 PM PST 24
Finished Feb 25 12:37:18 PM PST 24
Peak memory 202248 kb
Host smart-329e68f2-9572-436e-8aa7-eb56f1bc6379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10317
34708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.in_trans.1031734708
Directory /workspace/45.in_trans/latest

Test location /workspace/coverage/default/45.setup_trans_ignored.1964489658
Short name T172
Test name
Test status
Simulation time 8385036189 ps
CPU time 7.44 seconds
Started Feb 25 12:36:44 PM PST 24
Finished Feb 25 12:36:53 PM PST 24
Peak memory 202248 kb
Host smart-8cd08248-6f19-4534-a8be-eab7f342121b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19644
89658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.setup_trans_ignored.1964489658
Directory /workspace/45.setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3258940038
Short name T202
Test name
Test status
Simulation time 8367350986 ps
CPU time 7.24 seconds
Started Feb 25 12:36:45 PM PST 24
Finished Feb 25 12:36:53 PM PST 24
Peak memory 202208 kb
Host smart-8fdb6f17-11b4-47bb-989b-58725a0d3ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
40038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3258940038
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2115034803
Short name T62
Test name
Test status
Simulation time 8403353637 ps
CPU time 9.69 seconds
Started Feb 25 12:36:42 PM PST 24
Finished Feb 25 12:36:52 PM PST 24
Peak memory 202264 kb
Host smart-0bd359ac-5f60-454a-bac3-78bb09de1138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21150
34803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2115034803
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.159798221
Short name T103
Test name
Test status
Simulation time 8427091527 ps
CPU time 7.16 seconds
Started Feb 25 12:36:31 PM PST 24
Finished Feb 25 12:36:40 PM PST 24
Peak memory 202188 kb
Host smart-732ae875-6318-47e6-8ba4-69d4c62dd36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15979
8221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.159798221
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_smoke.587032511
Short name T191
Test name
Test status
Simulation time 8372544208 ps
CPU time 8.5 seconds
Started Feb 25 12:36:41 PM PST 24
Finished Feb 25 12:36:50 PM PST 24
Peak memory 202192 kb
Host smart-471349fe-12d0-4f70-a4a3-bfe2cd8e136c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58703
2511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.587032511
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.in_trans.2627951948
Short name T267
Test name
Test status
Simulation time 8392074217 ps
CPU time 8.19 seconds
Started Feb 25 12:36:55 PM PST 24
Finished Feb 25 12:37:03 PM PST 24
Peak memory 202100 kb
Host smart-46563da1-c63e-4bd0-9f36-2609838605f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26279
51948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.in_trans.2627951948
Directory /workspace/46.in_trans/latest

Test location /workspace/coverage/default/46.setup_trans_ignored.4151691826
Short name T284
Test name
Test status
Simulation time 8362579328 ps
CPU time 7.28 seconds
Started Feb 25 12:36:52 PM PST 24
Finished Feb 25 12:36:59 PM PST 24
Peak memory 202024 kb
Host smart-3010bf54-ad58-4c48-82e8-76759a4cf67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41516
91826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.setup_trans_ignored.4151691826
Directory /workspace/46.setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1638475970
Short name T224
Test name
Test status
Simulation time 8371019452 ps
CPU time 7.5 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:10 PM PST 24
Peak memory 202172 kb
Host smart-bef6992e-c782-43a4-b5b3-e7e014e8f479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16384
75970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1638475970
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.336377669
Short name T23
Test name
Test status
Simulation time 8430444006 ps
CPU time 7.89 seconds
Started Feb 25 12:36:56 PM PST 24
Finished Feb 25 12:37:04 PM PST 24
Peak memory 202212 kb
Host smart-16164834-424c-434e-ac0d-90a57ff57d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33637
7669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.336377669
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3891346518
Short name T328
Test name
Test status
Simulation time 8403420543 ps
CPU time 7.41 seconds
Started Feb 25 12:36:51 PM PST 24
Finished Feb 25 12:36:59 PM PST 24
Peak memory 202144 kb
Host smart-ee0d395a-3579-47e6-951e-da58c92dbd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38913
46518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3891346518
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_smoke.340634027
Short name T333
Test name
Test status
Simulation time 8369178506 ps
CPU time 7.47 seconds
Started Feb 25 12:36:45 PM PST 24
Finished Feb 25 12:36:53 PM PST 24
Peak memory 202148 kb
Host smart-1a7bd543-6f76-4c0d-9e54-bccf9f3c68ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
4027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.340634027
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.in_trans.215973313
Short name T179
Test name
Test status
Simulation time 8407234790 ps
CPU time 8.73 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 202236 kb
Host smart-be5c9a23-1675-4191-8aee-d26ab3882166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
3313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.in_trans.215973313
Directory /workspace/47.in_trans/latest

Test location /workspace/coverage/default/47.setup_trans_ignored.3185767257
Short name T271
Test name
Test status
Simulation time 8357345402 ps
CPU time 7.07 seconds
Started Feb 25 12:36:59 PM PST 24
Finished Feb 25 12:37:06 PM PST 24
Peak memory 202124 kb
Host smart-0af580c4-ef84-46a5-bd1c-82c76ff9499d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31857
67257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.setup_trans_ignored.3185767257
Directory /workspace/47.setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1035260191
Short name T312
Test name
Test status
Simulation time 8366376889 ps
CPU time 9.45 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:16 PM PST 24
Peak memory 202152 kb
Host smart-676c30ba-9d8d-49e0-9042-e5bf889cecf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10352
60191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1035260191
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1008233225
Short name T21
Test name
Test status
Simulation time 8432606927 ps
CPU time 7.15 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:18 PM PST 24
Peak memory 202180 kb
Host smart-97789a0c-b573-4805-9a63-59322afde8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10082
33225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1008233225
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_smoke.746449598
Short name T205
Test name
Test status
Simulation time 8372097205 ps
CPU time 9.49 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:15 PM PST 24
Peak memory 202152 kb
Host smart-5fb73dcd-4f81-4b04-8824-3a3d1a12971c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74644
9598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.746449598
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.in_trans.2792189307
Short name T253
Test name
Test status
Simulation time 8443403605 ps
CPU time 8.03 seconds
Started Feb 25 12:37:18 PM PST 24
Finished Feb 25 12:37:26 PM PST 24
Peak memory 202236 kb
Host smart-524936f1-933a-44a8-b924-655880cafee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27921
89307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.in_trans.2792189307
Directory /workspace/48.in_trans/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3214695269
Short name T9
Test name
Test status
Simulation time 8369785750 ps
CPU time 7.74 seconds
Started Feb 25 12:37:05 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 202252 kb
Host smart-220b0431-1b3c-4c3f-8707-7f57910bbf6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146
95269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3214695269
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3885181577
Short name T282
Test name
Test status
Simulation time 8399161527 ps
CPU time 7.39 seconds
Started Feb 25 12:37:16 PM PST 24
Finished Feb 25 12:37:23 PM PST 24
Peak memory 202236 kb
Host smart-68732338-4998-4a4b-94f2-d31a69dc09e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38851
81577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3885181577
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_smoke.643974192
Short name T48
Test name
Test status
Simulation time 8385053762 ps
CPU time 7.29 seconds
Started Feb 25 12:37:06 PM PST 24
Finished Feb 25 12:37:13 PM PST 24
Peak memory 202148 kb
Host smart-3415e105-67ce-44d9-a4c5-b448ef2bcfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64397
4192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.643974192
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.in_trans.651095655
Short name T335
Test name
Test status
Simulation time 8439463466 ps
CPU time 7.11 seconds
Started Feb 25 12:37:17 PM PST 24
Finished Feb 25 12:37:24 PM PST 24
Peak memory 202176 kb
Host smart-87ff26dd-fb82-41e8-9f91-15d50d1cc6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65109
5655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.in_trans.651095655
Directory /workspace/49.in_trans/latest

Test location /workspace/coverage/default/49.setup_trans_ignored.3571335720
Short name T165
Test name
Test status
Simulation time 8372505622 ps
CPU time 9.28 seconds
Started Feb 25 12:37:02 PM PST 24
Finished Feb 25 12:37:11 PM PST 24
Peak memory 202184 kb
Host smart-85411ab5-63a6-4a67-8b19-84be1d77f754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35713
35720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.setup_trans_ignored.3571335720
Directory /workspace/49.setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1664817313
Short name T25
Test name
Test status
Simulation time 8371770517 ps
CPU time 7.69 seconds
Started Feb 25 12:36:52 PM PST 24
Finished Feb 25 12:37:00 PM PST 24
Peak memory 202212 kb
Host smart-9c14495d-6fb7-481d-8160-ff608ef70072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16648
17313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1664817313
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.4285099205
Short name T337
Test name
Test status
Simulation time 8407863699 ps
CPU time 7.35 seconds
Started Feb 25 12:36:58 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 202212 kb
Host smart-2c357162-d1c8-4868-b42a-a0fa9c0fa66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42850
99205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4285099205
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3940937264
Short name T93
Test name
Test status
Simulation time 8442070199 ps
CPU time 8.66 seconds
Started Feb 25 12:37:03 PM PST 24
Finished Feb 25 12:37:12 PM PST 24
Peak memory 202196 kb
Host smart-596fd831-7f7b-4722-a1d2-84f736df3fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
37264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3940937264
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2644666374
Short name T50
Test name
Test status
Simulation time 8371483546 ps
CPU time 7.22 seconds
Started Feb 25 12:36:58 PM PST 24
Finished Feb 25 12:37:05 PM PST 24
Peak memory 202236 kb
Host smart-7dff209f-8b80-4133-af03-7a61fcebcaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
66374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2644666374
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.setup_trans_ignored.3064628970
Short name T247
Test name
Test status
Simulation time 8363114180 ps
CPU time 7.29 seconds
Started Feb 25 12:35:23 PM PST 24
Finished Feb 25 12:35:31 PM PST 24
Peak memory 202188 kb
Host smart-8913bb2d-d5d4-493e-8a5f-dd0df514c3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30646
28970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.setup_trans_ignored.3064628970
Directory /workspace/5.setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2867630737
Short name T173
Test name
Test status
Simulation time 8369200623 ps
CPU time 8.93 seconds
Started Feb 25 12:35:27 PM PST 24
Finished Feb 25 12:35:37 PM PST 24
Peak memory 202168 kb
Host smart-e92e64ce-ec93-4269-8f05-ca72a0b8cc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28676
30737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2867630737
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2755415215
Short name T84
Test name
Test status
Simulation time 8430994218 ps
CPU time 7.2 seconds
Started Feb 25 12:35:25 PM PST 24
Finished Feb 25 12:35:33 PM PST 24
Peak memory 202152 kb
Host smart-1cf2e1b9-aa8a-49b2-946f-7338c3e254c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27554
15215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2755415215
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2100684496
Short name T245
Test name
Test status
Simulation time 8385300311 ps
CPU time 7.82 seconds
Started Feb 25 12:35:39 PM PST 24
Finished Feb 25 12:35:47 PM PST 24
Peak memory 202140 kb
Host smart-1601458b-06a7-44df-a6d9-0bcb43ee12d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21006
84496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2100684496
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_smoke.938093910
Short name T317
Test name
Test status
Simulation time 8372049626 ps
CPU time 7.06 seconds
Started Feb 25 12:35:18 PM PST 24
Finished Feb 25 12:35:26 PM PST 24
Peak memory 202184 kb
Host smart-4896cd36-becf-4932-8b53-18bbbc38856c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93809
3910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.938093910
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.setup_trans_ignored.2905720239
Short name T321
Test name
Test status
Simulation time 8356487980 ps
CPU time 9.05 seconds
Started Feb 25 12:35:16 PM PST 24
Finished Feb 25 12:35:25 PM PST 24
Peak memory 202204 kb
Host smart-e9e2d042-0c46-48df-aca0-36c951182425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29057
20239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.setup_trans_ignored.2905720239
Directory /workspace/6.setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2931784225
Short name T68
Test name
Test status
Simulation time 8431620859 ps
CPU time 8.39 seconds
Started Feb 25 12:35:30 PM PST 24
Finished Feb 25 12:35:39 PM PST 24
Peak memory 202212 kb
Host smart-384fa058-2319-448d-b67c-a1a8a847b98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29317
84225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2931784225
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2159682475
Short name T222
Test name
Test status
Simulation time 8423119093 ps
CPU time 8.29 seconds
Started Feb 25 12:35:16 PM PST 24
Finished Feb 25 12:35:25 PM PST 24
Peak memory 202192 kb
Host smart-9d98af2a-0e7c-4446-9ce8-2cd0bea4e735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21596
82475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2159682475
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_smoke.4058603384
Short name T298
Test name
Test status
Simulation time 8374618335 ps
CPU time 7.64 seconds
Started Feb 25 12:35:31 PM PST 24
Finished Feb 25 12:35:39 PM PST 24
Peak memory 202140 kb
Host smart-98040c66-e76f-4a6f-adf0-7350b75eabfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40586
03384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.4058603384
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.in_trans.1996634305
Short name T216
Test name
Test status
Simulation time 8397950638 ps
CPU time 7.31 seconds
Started Feb 25 12:35:41 PM PST 24
Finished Feb 25 12:35:49 PM PST 24
Peak memory 202136 kb
Host smart-24a87ceb-6044-4609-82e2-890f0c93cd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19966
34305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.in_trans.1996634305
Directory /workspace/7.in_trans/latest

Test location /workspace/coverage/default/7.setup_trans_ignored.3480281137
Short name T182
Test name
Test status
Simulation time 8356353897 ps
CPU time 6.97 seconds
Started Feb 25 12:35:34 PM PST 24
Finished Feb 25 12:35:43 PM PST 24
Peak memory 202188 kb
Host smart-9a0faf7b-03fd-45f7-83f6-b74114cba4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
81137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.setup_trans_ignored.3480281137
Directory /workspace/7.setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2011756867
Short name T212
Test name
Test status
Simulation time 8369727939 ps
CPU time 7.22 seconds
Started Feb 25 12:35:19 PM PST 24
Finished Feb 25 12:35:26 PM PST 24
Peak memory 202200 kb
Host smart-48495fe4-1a9d-4ed8-80e8-6950c61de39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20117
56867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2011756867
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.213276990
Short name T207
Test name
Test status
Simulation time 8436671374 ps
CPU time 8.05 seconds
Started Feb 25 12:35:26 PM PST 24
Finished Feb 25 12:35:35 PM PST 24
Peak memory 202184 kb
Host smart-a4b16c35-2501-4d3c-9b31-d3c4c6dd28f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21327
6990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.213276990
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3438833236
Short name T176
Test name
Test status
Simulation time 8409739630 ps
CPU time 7.04 seconds
Started Feb 25 12:35:37 PM PST 24
Finished Feb 25 12:35:44 PM PST 24
Peak memory 202128 kb
Host smart-09f07ff9-e149-424b-9098-b9889b3e432e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34388
33236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3438833236
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2908257209
Short name T52
Test name
Test status
Simulation time 8366802156 ps
CPU time 7.39 seconds
Started Feb 25 12:35:29 PM PST 24
Finished Feb 25 12:35:37 PM PST 24
Peak memory 202212 kb
Host smart-dce955fc-afff-4826-b0d1-82844ea79de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29082
57209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2908257209
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.in_trans.1604196581
Short name T329
Test name
Test status
Simulation time 8444362633 ps
CPU time 10.04 seconds
Started Feb 25 12:35:29 PM PST 24
Finished Feb 25 12:35:39 PM PST 24
Peak memory 202192 kb
Host smart-e6524ca1-6ad9-4869-98e3-57ff38a40ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16041
96581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.in_trans.1604196581
Directory /workspace/8.in_trans/latest

Test location /workspace/coverage/default/8.setup_trans_ignored.499450959
Short name T283
Test name
Test status
Simulation time 8355852987 ps
CPU time 9.49 seconds
Started Feb 25 12:35:33 PM PST 24
Finished Feb 25 12:35:43 PM PST 24
Peak memory 202208 kb
Host smart-761b696b-949f-40d3-920a-36ab3204b5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49945
0959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.setup_trans_ignored.499450959
Directory /workspace/8.setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.4047617882
Short name T252
Test name
Test status
Simulation time 8368385151 ps
CPU time 7.65 seconds
Started Feb 25 12:35:40 PM PST 24
Finished Feb 25 12:35:48 PM PST 24
Peak memory 202160 kb
Host smart-ed8c2e92-9b0a-480e-8179-b809e433173a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40476
17882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.4047617882
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3699918138
Short name T63
Test name
Test status
Simulation time 8414999835 ps
CPU time 7.6 seconds
Started Feb 25 12:35:39 PM PST 24
Finished Feb 25 12:35:47 PM PST 24
Peak memory 202160 kb
Host smart-c0f3b490-3ef7-436c-9fc3-8d081f1955ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36999
18138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3699918138
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.4034780874
Short name T104
Test name
Test status
Simulation time 8396855915 ps
CPU time 6.83 seconds
Started Feb 25 12:35:30 PM PST 24
Finished Feb 25 12:35:37 PM PST 24
Peak memory 202128 kb
Host smart-11376e4a-b333-448e-96a1-c2aba2fd65cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40347
80874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.4034780874
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3115121953
Short name T187
Test name
Test status
Simulation time 8372699672 ps
CPU time 7.36 seconds
Started Feb 25 12:35:50 PM PST 24
Finished Feb 25 12:35:58 PM PST 24
Peak memory 202196 kb
Host smart-891a4aa5-9f92-4eec-9204-d0c377dd8a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31151
21953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3115121953
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.in_trans.1554713244
Short name T109
Test name
Test status
Simulation time 8382768763 ps
CPU time 7.57 seconds
Started Feb 25 12:35:34 PM PST 24
Finished Feb 25 12:35:43 PM PST 24
Peak memory 202100 kb
Host smart-ad3752a2-2b52-461e-b478-43644a54997b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15547
13244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.in_trans.1554713244
Directory /workspace/9.in_trans/latest

Test location /workspace/coverage/default/9.setup_trans_ignored.1481888557
Short name T235
Test name
Test status
Simulation time 8362142897 ps
CPU time 7.13 seconds
Started Feb 25 12:35:38 PM PST 24
Finished Feb 25 12:35:46 PM PST 24
Peak memory 202204 kb
Host smart-db96f6b0-8b01-4c13-836b-0fe4fcf7018a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14818
88557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.setup_trans_ignored.1481888557
Directory /workspace/9.setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1821898996
Short name T210
Test name
Test status
Simulation time 8370275186 ps
CPU time 7.5 seconds
Started Feb 25 12:35:47 PM PST 24
Finished Feb 25 12:35:54 PM PST 24
Peak memory 202212 kb
Host smart-b7c92816-bf96-4ee4-b3b1-72be7b3c1e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18218
98996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1821898996
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.419384207
Short name T61
Test name
Test status
Simulation time 8433364657 ps
CPU time 9.18 seconds
Started Feb 25 12:35:45 PM PST 24
Finished Feb 25 12:35:54 PM PST 24
Peak memory 202196 kb
Host smart-2088e499-e730-443d-8dd5-b7528dcf24ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41938
4207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.419384207
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3638953491
Short name T142
Test name
Test status
Simulation time 8390059992 ps
CPU time 7.29 seconds
Started Feb 25 12:35:45 PM PST 24
Finished Feb 25 12:35:52 PM PST 24
Peak memory 202136 kb
Host smart-82138160-151d-42b4-9908-e28b09fb9505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36389
53491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3638953491
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_smoke.308400400
Short name T225
Test name
Test status
Simulation time 8373223148 ps
CPU time 7.95 seconds
Started Feb 25 12:35:39 PM PST 24
Finished Feb 25 12:35:47 PM PST 24
Peak memory 202232 kb
Host smart-8779d416-7e4e-4117-8e1c-5d3483149846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30840
0400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.308400400
Directory /workspace/9.usbdev_smoke/latest
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