Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.31 95.69 86.08 96.94 45.31 93.76 97.36 54.05


Total test records in report: 396
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T313 /workspace/coverage/default/49.usbdev_av_buffer.647350583 Feb 29 01:06:36 PM PST 24 Feb 29 01:06:44 PM PST 24 8385294260 ps
T314 /workspace/coverage/default/34.usbdev_av_buffer.2720690053 Feb 29 01:05:46 PM PST 24 Feb 29 01:05:54 PM PST 24 8368240393 ps
T315 /workspace/coverage/default/4.usbdev_pkt_sent.3753413097 Feb 29 01:04:02 PM PST 24 Feb 29 01:04:10 PM PST 24 8452268720 ps
T151 /workspace/coverage/default/37.usbdev_pkt_sent.3230114264 Feb 29 01:05:50 PM PST 24 Feb 29 01:05:58 PM PST 24 8450873851 ps
T195 /workspace/coverage/default/39.setup_trans_ignored.2878077119 Feb 29 01:06:00 PM PST 24 Feb 29 01:06:07 PM PST 24 8360738368 ps
T316 /workspace/coverage/default/24.usbdev_smoke.2477831661 Feb 29 01:05:06 PM PST 24 Feb 29 01:05:13 PM PST 24 8369525659 ps
T317 /workspace/coverage/default/27.usbdev_pkt_sent.3284478958 Feb 29 01:05:24 PM PST 24 Feb 29 01:05:31 PM PST 24 8443280380 ps
T318 /workspace/coverage/default/9.usbdev_pkt_sent.1525867036 Feb 29 01:04:14 PM PST 24 Feb 29 01:04:22 PM PST 24 8419353017 ps
T187 /workspace/coverage/default/37.usbdev_smoke.2413874332 Feb 29 01:05:50 PM PST 24 Feb 29 01:05:57 PM PST 24 8365954882 ps
T183 /workspace/coverage/default/46.usbdev_nak_trans.1061847825 Feb 29 01:06:18 PM PST 24 Feb 29 01:06:26 PM PST 24 8458017048 ps
T181 /workspace/coverage/default/5.in_trans.3547894199 Feb 29 01:04:01 PM PST 24 Feb 29 01:04:09 PM PST 24 8500516733 ps
T85 /workspace/coverage/default/43.usbdev_nak_trans.801606473 Feb 29 01:06:06 PM PST 24 Feb 29 01:06:15 PM PST 24 8414375829 ps
T319 /workspace/coverage/default/12.usbdev_smoke.2805272973 Feb 29 01:04:25 PM PST 24 Feb 29 01:04:32 PM PST 24 8368275404 ps
T320 /workspace/coverage/default/1.usbdev_av_buffer.439820914 Feb 29 01:03:45 PM PST 24 Feb 29 01:03:52 PM PST 24 8367184675 ps
T25 /workspace/coverage/default/30.usbdev_pkt_sent.3084377607 Feb 29 01:05:27 PM PST 24 Feb 29 01:05:37 PM PST 24 8464188408 ps
T321 /workspace/coverage/default/21.usbdev_smoke.2127497665 Feb 29 01:05:01 PM PST 24 Feb 29 01:05:09 PM PST 24 8366848071 ps
T322 /workspace/coverage/default/29.setup_trans_ignored.1429799300 Feb 29 01:05:26 PM PST 24 Feb 29 01:05:34 PM PST 24 8362107733 ps
T323 /workspace/coverage/default/4.usbdev_smoke.331531019 Feb 29 01:03:59 PM PST 24 Feb 29 01:04:07 PM PST 24 8398722961 ps
T324 /workspace/coverage/default/31.in_trans.1763894047 Feb 29 01:05:43 PM PST 24 Feb 29 01:05:51 PM PST 24 8406889507 ps
T153 /workspace/coverage/default/7.usbdev_nak_trans.1733719448 Feb 29 01:04:14 PM PST 24 Feb 29 01:04:23 PM PST 24 8409215888 ps
T325 /workspace/coverage/default/44.usbdev_smoke.3186351642 Feb 29 01:06:19 PM PST 24 Feb 29 01:06:27 PM PST 24 8371957681 ps
T326 /workspace/coverage/default/6.setup_trans_ignored.327270309 Feb 29 01:04:11 PM PST 24 Feb 29 01:04:19 PM PST 24 8366779912 ps
T327 /workspace/coverage/default/0.usbdev_smoke.1227112469 Feb 29 01:03:42 PM PST 24 Feb 29 01:03:50 PM PST 24 8367038900 ps
T328 /workspace/coverage/default/3.usbdev_pkt_sent.1118423970 Feb 29 01:04:01 PM PST 24 Feb 29 01:04:09 PM PST 24 8397329084 ps
T175 /workspace/coverage/default/19.usbdev_smoke.1333661541 Feb 29 01:04:55 PM PST 24 Feb 29 01:05:04 PM PST 24 8376897456 ps
T329 /workspace/coverage/default/13.usbdev_nak_trans.1927482470 Feb 29 01:04:38 PM PST 24 Feb 29 01:04:46 PM PST 24 8429832250 ps
T330 /workspace/coverage/default/48.usbdev_smoke.1227312710 Feb 29 01:06:39 PM PST 24 Feb 29 01:06:48 PM PST 24 8371213716 ps
T331 /workspace/coverage/default/47.usbdev_smoke.2694887255 Feb 29 01:06:16 PM PST 24 Feb 29 01:06:24 PM PST 24 8383902493 ps
T332 /workspace/coverage/default/38.usbdev_pkt_sent.1592459242 Feb 29 01:06:04 PM PST 24 Feb 29 01:06:12 PM PST 24 8419575070 ps
T333 /workspace/coverage/default/43.setup_trans_ignored.349536812 Feb 29 01:06:01 PM PST 24 Feb 29 01:06:09 PM PST 24 8359778862 ps
T143 /workspace/coverage/default/17.setup_trans_ignored.2929793902 Feb 29 01:04:53 PM PST 24 Feb 29 01:05:00 PM PST 24 8370184875 ps
T334 /workspace/coverage/default/14.setup_trans_ignored.3327790631 Feb 29 01:04:43 PM PST 24 Feb 29 01:04:51 PM PST 24 8363725389 ps
T335 /workspace/coverage/default/12.usbdev_av_buffer.2507652990 Feb 29 01:04:24 PM PST 24 Feb 29 01:04:32 PM PST 24 8463042981 ps
T336 /workspace/coverage/default/20.usbdev_smoke.693004085 Feb 29 01:04:51 PM PST 24 Feb 29 01:04:58 PM PST 24 8415830616 ps
T337 /workspace/coverage/default/24.usbdev_pkt_sent.2670110988 Feb 29 01:05:06 PM PST 24 Feb 29 01:05:14 PM PST 24 8389568039 ps
T338 /workspace/coverage/default/23.usbdev_pkt_sent.1863257709 Feb 29 01:05:11 PM PST 24 Feb 29 01:05:18 PM PST 24 8425785238 ps
T79 /workspace/coverage/default/5.usbdev_nak_trans.4293832211 Feb 29 01:04:00 PM PST 24 Feb 29 01:04:09 PM PST 24 8410464289 ps
T37 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3613924097 Feb 29 01:11:18 PM PST 24 Feb 29 01:11:21 PM PST 24 233771179 ps
T38 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3016479008 Feb 29 01:11:19 PM PST 24 Feb 29 01:11:22 PM PST 24 53689915 ps
T48 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1379201395 Feb 29 01:11:00 PM PST 24 Feb 29 01:11:01 PM PST 24 69888381 ps
T53 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.75287219 Feb 29 01:10:58 PM PST 24 Feb 29 01:11:00 PM PST 24 49967832 ps
T49 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3502095351 Feb 29 01:11:03 PM PST 24 Feb 29 01:11:04 PM PST 24 80370820 ps
T39 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1606562873 Feb 29 01:11:04 PM PST 24 Feb 29 01:11:06 PM PST 24 61300546 ps
T51 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4225534317 Feb 29 01:10:57 PM PST 24 Feb 29 01:11:02 PM PST 24 314541581 ps
T50 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1249654657 Feb 29 01:11:12 PM PST 24 Feb 29 01:11:13 PM PST 24 67965984 ps
T46 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2431462816 Feb 29 01:11:00 PM PST 24 Feb 29 01:11:02 PM PST 24 45020995 ps
T43 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2313944807 Feb 29 01:11:03 PM PST 24 Feb 29 01:11:04 PM PST 24 55830651 ps
T47 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1407341929 Feb 29 01:11:18 PM PST 24 Feb 29 01:11:20 PM PST 24 125327338 ps
T64 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2353161399 Feb 29 01:11:19 PM PST 24 Feb 29 01:11:21 PM PST 24 75551760 ps
T125 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3981196373 Feb 29 01:11:14 PM PST 24 Feb 29 01:11:15 PM PST 24 54845007 ps
T126 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2209866759 Feb 29 01:10:57 PM PST 24 Feb 29 01:11:02 PM PST 24 133560769 ps
T44 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4155493117 Feb 29 01:11:00 PM PST 24 Feb 29 01:11:01 PM PST 24 45970302 ps
T127 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3364574180 Feb 29 01:10:57 PM PST 24 Feb 29 01:11:02 PM PST 24 346299908 ps
T119 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.208257599 Feb 29 01:10:57 PM PST 24 Feb 29 01:11:01 PM PST 24 79519103 ps
T128 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1516210814 Feb 29 01:11:03 PM PST 24 Feb 29 01:11:05 PM PST 24 175592919 ps
T129 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3382862612 Feb 29 01:11:20 PM PST 24 Feb 29 01:11:21 PM PST 24 32653202 ps
T134 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1325145999 Feb 29 01:10:56 PM PST 24 Feb 29 01:10:58 PM PST 24 87356821 ps
T130 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.868801777 Feb 29 01:10:59 PM PST 24 Feb 29 01:11:02 PM PST 24 201425876 ps
T135 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2300126701 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:16 PM PST 24 37066636 ps
T120 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1191304921 Feb 29 01:11:11 PM PST 24 Feb 29 01:11:12 PM PST 24 41871639 ps
T121 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.201852437 Feb 29 01:10:56 PM PST 24 Feb 29 01:10:59 PM PST 24 50379376 ps
T122 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2411694354 Feb 29 01:11:04 PM PST 24 Feb 29 01:11:06 PM PST 24 73303543 ps
T131 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2284209964 Feb 29 01:11:18 PM PST 24 Feb 29 01:11:19 PM PST 24 58519621 ps
T123 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4035824320 Feb 29 01:11:19 PM PST 24 Feb 29 01:11:21 PM PST 24 119579758 ps
T124 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2208664394 Feb 29 01:11:21 PM PST 24 Feb 29 01:11:25 PM PST 24 86024004 ps
T136 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3786317938 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:19 PM PST 24 87881683 ps
T45 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3976865130 Feb 29 01:10:59 PM PST 24 Feb 29 01:11:01 PM PST 24 56508480 ps
T339 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3086861820 Feb 29 01:10:59 PM PST 24 Feb 29 01:11:01 PM PST 24 43707157 ps
T155 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3996376038 Feb 29 01:11:13 PM PST 24 Feb 29 01:11:15 PM PST 24 58908292 ps
T158 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3002757713 Feb 29 01:11:12 PM PST 24 Feb 29 01:11:14 PM PST 24 121706527 ps
T340 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3083517045 Feb 29 01:11:19 PM PST 24 Feb 29 01:11:21 PM PST 24 63674750 ps
T159 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1306017068 Feb 29 01:11:19 PM PST 24 Feb 29 01:11:20 PM PST 24 85579544 ps
T341 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2947436493 Feb 29 01:11:13 PM PST 24 Feb 29 01:11:14 PM PST 24 30020322 ps
T137 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3605531988 Feb 29 01:10:59 PM PST 24 Feb 29 01:11:03 PM PST 24 346892487 ps
T138 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1595692473 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:20 PM PST 24 218058691 ps
T157 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1086039272 Feb 29 01:10:59 PM PST 24 Feb 29 01:11:02 PM PST 24 174604418 ps
T156 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2107428055 Feb 29 01:11:19 PM PST 24 Feb 29 01:11:21 PM PST 24 46984728 ps
T139 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3278144199 Feb 29 01:11:13 PM PST 24 Feb 29 01:11:16 PM PST 24 307616811 ps
T166 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2919736808 Feb 29 01:10:57 PM PST 24 Feb 29 01:11:02 PM PST 24 263142290 ps
T342 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3988540336 Feb 29 01:11:13 PM PST 24 Feb 29 01:11:15 PM PST 24 60578063 ps
T132 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3751084535 Feb 29 01:11:04 PM PST 24 Feb 29 01:11:05 PM PST 24 41509494 ps
T343 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.463120619 Feb 29 01:11:20 PM PST 24 Feb 29 01:11:23 PM PST 24 89437603 ps
T344 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3958632847 Feb 29 01:11:17 PM PST 24 Feb 29 01:11:19 PM PST 24 73240550 ps
T345 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3701378393 Feb 29 01:11:00 PM PST 24 Feb 29 01:11:04 PM PST 24 122604686 ps
T346 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2755785750 Feb 29 01:10:59 PM PST 24 Feb 29 01:11:03 PM PST 24 78087726 ps
T347 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3942470736 Feb 29 01:10:57 PM PST 24 Feb 29 01:11:01 PM PST 24 249737663 ps
T167 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2943126705 Feb 29 01:11:08 PM PST 24 Feb 29 01:11:13 PM PST 24 350592441 ps
T160 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1622248251 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:17 PM PST 24 138449543 ps
T348 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3321743473 Feb 29 01:10:59 PM PST 24 Feb 29 01:11:01 PM PST 24 33341223 ps
T161 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2774953165 Feb 29 01:10:58 PM PST 24 Feb 29 01:11:00 PM PST 24 72664754 ps
T349 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2047440743 Feb 29 01:11:03 PM PST 24 Feb 29 01:11:04 PM PST 24 70240868 ps
T162 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2557607659 Feb 29 01:10:56 PM PST 24 Feb 29 01:11:00 PM PST 24 136218176 ps
T163 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2827807859 Feb 29 01:11:19 PM PST 24 Feb 29 01:11:21 PM PST 24 73345152 ps
T164 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1984540958 Feb 29 01:11:14 PM PST 24 Feb 29 01:11:15 PM PST 24 41964251 ps
T350 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1484437449 Feb 29 01:10:59 PM PST 24 Feb 29 01:11:01 PM PST 24 92866115 ps
T351 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.754691998 Feb 29 01:11:16 PM PST 24 Feb 29 01:11:18 PM PST 24 36316384 ps
T352 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2609072070 Feb 29 01:11:00 PM PST 24 Feb 29 01:11:05 PM PST 24 476347116 ps
T353 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3374007818 Feb 29 01:11:03 PM PST 24 Feb 29 01:11:07 PM PST 24 469573224 ps
T354 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3862869864 Feb 29 01:11:21 PM PST 24 Feb 29 01:11:24 PM PST 24 132707617 ps
T355 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.581888997 Feb 29 01:11:16 PM PST 24 Feb 29 01:11:19 PM PST 24 258775813 ps
T356 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1996301185 Feb 29 01:10:58 PM PST 24 Feb 29 01:11:01 PM PST 24 193452474 ps
T357 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3822275238 Feb 29 01:11:11 PM PST 24 Feb 29 01:11:13 PM PST 24 62537030 ps
T133 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.570532664 Feb 29 01:11:19 PM PST 24 Feb 29 01:11:20 PM PST 24 64258921 ps
T358 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3066835048 Feb 29 01:11:10 PM PST 24 Feb 29 01:11:12 PM PST 24 138217572 ps
T359 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3406322425 Feb 29 01:11:08 PM PST 24 Feb 29 01:11:11 PM PST 24 260506729 ps
T168 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1224684639 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:20 PM PST 24 267268654 ps
T360 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3887150578 Feb 29 01:11:11 PM PST 24 Feb 29 01:11:13 PM PST 24 114178542 ps
T361 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1626119421 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:17 PM PST 24 244700054 ps
T362 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2943088584 Feb 29 01:11:08 PM PST 24 Feb 29 01:11:09 PM PST 24 129196765 ps
T165 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2450651399 Feb 29 01:11:03 PM PST 24 Feb 29 01:11:07 PM PST 24 236996395 ps
T363 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2000545474 Feb 29 01:11:11 PM PST 24 Feb 29 01:11:13 PM PST 24 133553191 ps
T364 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2955840273 Feb 29 01:10:58 PM PST 24 Feb 29 01:11:01 PM PST 24 161100236 ps
T365 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.485620091 Feb 29 01:11:14 PM PST 24 Feb 29 01:11:16 PM PST 24 54321075 ps
T366 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2566474370 Feb 29 01:11:01 PM PST 24 Feb 29 01:11:03 PM PST 24 148932828 ps
T367 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.284932487 Feb 29 01:11:00 PM PST 24 Feb 29 01:11:02 PM PST 24 51937018 ps
T368 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.411641971 Feb 29 01:11:13 PM PST 24 Feb 29 01:11:14 PM PST 24 147051746 ps
T369 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.769140539 Feb 29 01:11:20 PM PST 24 Feb 29 01:11:21 PM PST 24 77121017 ps
T370 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1169538043 Feb 29 01:10:58 PM PST 24 Feb 29 01:11:01 PM PST 24 63933264 ps
T371 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.700385719 Feb 29 01:11:11 PM PST 24 Feb 29 01:11:12 PM PST 24 28698338 ps
T372 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3561427594 Feb 29 01:11:13 PM PST 24 Feb 29 01:11:14 PM PST 24 82208319 ps
T52 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2581727114 Feb 29 01:11:01 PM PST 24 Feb 29 01:11:02 PM PST 24 65648257 ps
T373 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.426381601 Feb 29 01:11:14 PM PST 24 Feb 29 01:11:17 PM PST 24 79562600 ps
T374 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2580180173 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:16 PM PST 24 75160940 ps
T375 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.113516939 Feb 29 01:10:58 PM PST 24 Feb 29 01:11:02 PM PST 24 206930825 ps
T376 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.210398678 Feb 29 01:11:08 PM PST 24 Feb 29 01:11:10 PM PST 24 113196615 ps
T377 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3332632492 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:16 PM PST 24 69268218 ps
T378 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2921761836 Feb 29 01:11:22 PM PST 24 Feb 29 01:11:25 PM PST 24 67265589 ps
T379 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.861302101 Feb 29 01:11:10 PM PST 24 Feb 29 01:11:13 PM PST 24 446736743 ps
T169 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3161743746 Feb 29 01:10:57 PM PST 24 Feb 29 01:11:04 PM PST 24 489321660 ps
T380 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.82177020 Feb 29 01:11:11 PM PST 24 Feb 29 01:11:13 PM PST 24 233022799 ps
T381 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4222682136 Feb 29 01:10:57 PM PST 24 Feb 29 01:10:59 PM PST 24 86518426 ps
T382 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1408435669 Feb 29 01:11:08 PM PST 24 Feb 29 01:11:09 PM PST 24 108771709 ps
T383 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4112146510 Feb 29 01:11:13 PM PST 24 Feb 29 01:11:15 PM PST 24 62844703 ps
T384 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4159328924 Feb 29 01:11:00 PM PST 24 Feb 29 01:11:02 PM PST 24 85808878 ps
T385 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.201170515 Feb 29 01:11:13 PM PST 24 Feb 29 01:11:14 PM PST 24 35305475 ps
T386 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4150512357 Feb 29 01:10:58 PM PST 24 Feb 29 01:11:03 PM PST 24 252535106 ps
T387 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2252855907 Feb 29 01:11:14 PM PST 24 Feb 29 01:11:16 PM PST 24 120151146 ps
T388 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.540529896 Feb 29 01:10:57 PM PST 24 Feb 29 01:10:59 PM PST 24 39993524 ps
T389 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1498687217 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:16 PM PST 24 53100943 ps
T390 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3694323579 Feb 29 01:11:02 PM PST 24 Feb 29 01:11:05 PM PST 24 86605059 ps
T391 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1011674447 Feb 29 01:11:21 PM PST 24 Feb 29 01:11:23 PM PST 24 72594658 ps
T392 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2126813519 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:17 PM PST 24 154582844 ps
T393 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2629884788 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:16 PM PST 24 32223890 ps
T394 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.585052350 Feb 29 01:11:15 PM PST 24 Feb 29 01:11:17 PM PST 24 103694301 ps
T395 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1846629092 Feb 29 01:11:18 PM PST 24 Feb 29 01:11:20 PM PST 24 56323330 ps
T396 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3063631341 Feb 29 01:10:57 PM PST 24 Feb 29 01:11:01 PM PST 24 164709259 ps

Test location /workspace/coverage/default/19.in_trans.1777832200
Short name T5
Test name
Test status
Simulation time 8425730877 ps
CPU time 9.64 seconds
Started Feb 29 01:04:53 PM PST 24
Finished Feb 29 01:05:02 PM PST 24
Peak memory 202128 kb
Host smart-2b501e64-f822-4522-bc59-a1f7d37176e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17778
32200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.in_trans.1777832200
Directory /workspace/19.in_trans/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4225534317
Short name T51
Test name
Test status
Simulation time 314541581 ps
CPU time 3.64 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202596 kb
Host smart-b186e2f5-d6a9-48af-84ed-1c5073907835
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225534317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.4225534317
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1699248518
Short name T7
Test name
Test status
Simulation time 8371960027 ps
CPU time 9.88 seconds
Started Feb 29 01:06:20 PM PST 24
Finished Feb 29 01:06:30 PM PST 24
Peak memory 202168 kb
Host smart-294b8786-73ef-4f10-9774-f0eaa3ad1e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16992
48518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1699248518
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3016479008
Short name T38
Test name
Test status
Simulation time 53689915 ps
CPU time 1.71 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:22 PM PST 24
Peak memory 210704 kb
Host smart-218b6c59-482c-403c-af22-74aa1bfac6ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016479008 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.3016479008
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3196697531
Short name T60
Test name
Test status
Simulation time 8373156457 ps
CPU time 7.1 seconds
Started Feb 29 01:06:17 PM PST 24
Finished Feb 29 01:06:25 PM PST 24
Peak memory 202160 kb
Host smart-cc0d9b6f-57e1-46c1-b5b8-ca5859589a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31966
97531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3196697531
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1846714408
Short name T40
Test name
Test status
Simulation time 85729850 ps
CPU time 0.88 seconds
Started Feb 29 01:03:49 PM PST 24
Finished Feb 29 01:03:50 PM PST 24
Peak memory 216808 kb
Host smart-2d1e65f9-9909-448a-bbb7-3c04872fed7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1846714408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1846714408
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3976865130
Short name T45
Test name
Test status
Simulation time 56508480 ps
CPU time 0.84 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202264 kb
Host smart-a154bd74-c63f-436b-954b-af73cee47fd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976865130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3976865130
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1918940736
Short name T10
Test name
Test status
Simulation time 8426570418 ps
CPU time 7.68 seconds
Started Feb 29 01:05:53 PM PST 24
Finished Feb 29 01:06:01 PM PST 24
Peak memory 202344 kb
Host smart-784ded8e-1c58-41db-a37d-e437d5203117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19189
40736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1918940736
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1595692473
Short name T138
Test name
Test status
Simulation time 218058691 ps
CPU time 4.15 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:20 PM PST 24
Peak memory 202620 kb
Host smart-86e8520b-e4c1-408a-a1eb-3305592064f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1595692473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1595692473
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1407341929
Short name T47
Test name
Test status
Simulation time 125327338 ps
CPU time 1.78 seconds
Started Feb 29 01:11:18 PM PST 24
Finished Feb 29 01:11:20 PM PST 24
Peak memory 210652 kb
Host smart-bc419024-0558-4e13-a3ce-a37243b4c1f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407341929 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.1407341929
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2313944807
Short name T43
Test name
Test status
Simulation time 55830651 ps
CPU time 0.92 seconds
Started Feb 29 01:11:03 PM PST 24
Finished Feb 29 01:11:04 PM PST 24
Peak memory 202276 kb
Host smart-8cd4c740-d691-45a6-87dc-1452cc41938f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313944807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2313944807
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.in_trans.1891691750
Short name T99
Test name
Test status
Simulation time 8426413921 ps
CPU time 7.56 seconds
Started Feb 29 01:03:44 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 202152 kb
Host smart-5dadd6dd-5413-4aa1-90de-9ef3c7a6bf93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
91750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.in_trans.1891691750
Directory /workspace/0.in_trans/latest

Test location /workspace/coverage/default/37.in_trans.962553103
Short name T145
Test name
Test status
Simulation time 8381572517 ps
CPU time 7.27 seconds
Started Feb 29 01:06:03 PM PST 24
Finished Feb 29 01:06:11 PM PST 24
Peak memory 202144 kb
Host smart-e2363761-f6b8-46b6-8df4-d3f2789d7c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96255
3103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.in_trans.962553103
Directory /workspace/37.in_trans/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3613924097
Short name T37
Test name
Test status
Simulation time 233771179 ps
CPU time 2.94 seconds
Started Feb 29 01:11:18 PM PST 24
Finished Feb 29 01:11:21 PM PST 24
Peak memory 202464 kb
Host smart-727f3506-3c5b-4d54-b8c8-94d66162c8c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3613924097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3613924097
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/default/31.in_trans.1763894047
Short name T324
Test name
Test status
Simulation time 8406889507 ps
CPU time 7.09 seconds
Started Feb 29 01:05:43 PM PST 24
Finished Feb 29 01:05:51 PM PST 24
Peak memory 202140 kb
Host smart-4d57a121-bb61-423a-b041-e3bb52fb227a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17638
94047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.in_trans.1763894047
Directory /workspace/31.in_trans/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.75287219
Short name T53
Test name
Test status
Simulation time 49967832 ps
CPU time 0.85 seconds
Started Feb 29 01:10:58 PM PST 24
Finished Feb 29 01:11:00 PM PST 24
Peak memory 202372 kb
Host smart-5e687577-50d8-4d31-9007-44ca5cf7681f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75287219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.75287219
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.905557646
Short name T147
Test name
Test status
Simulation time 8420574274 ps
CPU time 8.64 seconds
Started Feb 29 01:06:17 PM PST 24
Finished Feb 29 01:06:25 PM PST 24
Peak memory 202152 kb
Host smart-f47bdf23-b308-4ee5-9c54-8388ac6851fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90555
7646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.905557646
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2450651399
Short name T165
Test name
Test status
Simulation time 236996395 ps
CPU time 4.13 seconds
Started Feb 29 01:11:03 PM PST 24
Finished Feb 29 01:11:07 PM PST 24
Peak memory 202516 kb
Host smart-4128a344-95f6-4976-9e07-8c34e46bbdfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2450651399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2450651399
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/41.in_trans.3709551251
Short name T24
Test name
Test status
Simulation time 8458905981 ps
CPU time 7.85 seconds
Started Feb 29 01:06:05 PM PST 24
Finished Feb 29 01:06:13 PM PST 24
Peak memory 202100 kb
Host smart-ec267d62-a331-4c44-b4c5-b5a5b11f952f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37095
51251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.in_trans.3709551251
Directory /workspace/41.in_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.192113130
Short name T29
Test name
Test status
Simulation time 8366200672 ps
CPU time 7.56 seconds
Started Feb 29 01:04:25 PM PST 24
Finished Feb 29 01:04:33 PM PST 24
Peak memory 202100 kb
Host smart-5a34b669-a3e7-4e7e-8130-9a57c656d37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19211
3130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.192113130
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2943126705
Short name T167
Test name
Test status
Simulation time 350592441 ps
CPU time 4.37 seconds
Started Feb 29 01:11:08 PM PST 24
Finished Feb 29 01:11:13 PM PST 24
Peak memory 202564 kb
Host smart-2b2ea7fd-da68-4e2e-a004-cf38ecf9ebc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2943126705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2943126705
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/27.in_trans.1947400496
Short name T152
Test name
Test status
Simulation time 8383320892 ps
CPU time 7.79 seconds
Started Feb 29 01:05:26 PM PST 24
Finished Feb 29 01:05:36 PM PST 24
Peak memory 202140 kb
Host smart-38cb97ad-2a88-422e-aeec-f1211e403482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19474
00496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.in_trans.1947400496
Directory /workspace/27.in_trans/latest

Test location /workspace/coverage/default/35.in_trans.2644665423
Short name T300
Test name
Test status
Simulation time 8443529352 ps
CPU time 7.52 seconds
Started Feb 29 01:05:47 PM PST 24
Finished Feb 29 01:05:55 PM PST 24
Peak memory 202172 kb
Host smart-51a058e1-9e78-4840-9634-3079884b00da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
65423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.in_trans.2644665423
Directory /workspace/35.in_trans/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2581727114
Short name T52
Test name
Test status
Simulation time 65648257 ps
CPU time 0.86 seconds
Started Feb 29 01:11:01 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202324 kb
Host smart-b7270f49-40c6-4f46-9552-566edc91cbfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581727114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2581727114
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/11.in_trans.932188154
Short name T297
Test name
Test status
Simulation time 8441007409 ps
CPU time 7.68 seconds
Started Feb 29 01:04:26 PM PST 24
Finished Feb 29 01:04:34 PM PST 24
Peak memory 202148 kb
Host smart-9bc59bb5-ee4e-4f25-a903-e4fdf75420f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93218
8154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.in_trans.932188154
Directory /workspace/11.in_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3063631341
Short name T396
Test name
Test status
Simulation time 164709259 ps
CPU time 2.16 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202288 kb
Host smart-5bddcbaa-111b-46b2-9c6c-8ca1c51f3912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3063631341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3063631341
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.in_trans.2884778954
Short name T295
Test name
Test status
Simulation time 8394752124 ps
CPU time 8.72 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:54 PM PST 24
Peak memory 202132 kb
Host smart-b78c7790-a30b-4946-91a0-76df33326a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28847
78954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.in_trans.2884778954
Directory /workspace/1.in_trans/latest

Test location /workspace/coverage/default/2.in_trans.2042234883
Short name T102
Test name
Test status
Simulation time 8394272197 ps
CPU time 6.99 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 202196 kb
Host smart-a24c48a6-200d-4f4d-a3f0-e631a71ae09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20422
34883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.in_trans.2042234883
Directory /workspace/2.in_trans/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.631556652
Short name T110
Test name
Test status
Simulation time 8394720155 ps
CPU time 7.44 seconds
Started Feb 29 01:03:46 PM PST 24
Finished Feb 29 01:03:55 PM PST 24
Peak memory 202096 kb
Host smart-a7651c70-9e10-4d11-93d1-b200c53613ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63155
6652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.631556652
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1782104329
Short name T93
Test name
Test status
Simulation time 8440693211 ps
CPU time 6.93 seconds
Started Feb 29 01:04:50 PM PST 24
Finished Feb 29 01:04:57 PM PST 24
Peak memory 202144 kb
Host smart-1e51bda8-3067-49fa-9949-cd10b48553b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17821
04329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1782104329
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3600859107
Short name T14
Test name
Test status
Simulation time 8411301229 ps
CPU time 7.5 seconds
Started Feb 29 01:05:26 PM PST 24
Finished Feb 29 01:05:35 PM PST 24
Peak memory 202144 kb
Host smart-b3a79dd0-ba37-4cf5-9f8f-b15af4352749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36008
59107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3600859107
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1996301185
Short name T356
Test name
Test status
Simulation time 193452474 ps
CPU time 1.82 seconds
Started Feb 29 01:10:58 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202568 kb
Host smart-b84d3691-5e7c-4a97-8f05-190993cc2ef3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996301185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.1996301185
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.setup_trans_ignored.1634934518
Short name T176
Test name
Test status
Simulation time 8359880629 ps
CPU time 7.14 seconds
Started Feb 29 01:03:46 PM PST 24
Finished Feb 29 01:03:54 PM PST 24
Peak memory 202096 kb
Host smart-b67d9c78-f940-4cea-8f37-ba1a7f323072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16349
34518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.setup_trans_ignored.1634934518
Directory /workspace/0.setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1982559868
Short name T71
Test name
Test status
Simulation time 8447621252 ps
CPU time 7.79 seconds
Started Feb 29 01:03:46 PM PST 24
Finished Feb 29 01:03:55 PM PST 24
Peak memory 202168 kb
Host smart-1ced4ed3-ce1e-4cdb-97e4-98bbf8876692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19825
59868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1982559868
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.467784826
Short name T82
Test name
Test status
Simulation time 8513549048 ps
CPU time 7.28 seconds
Started Feb 29 01:04:29 PM PST 24
Finished Feb 29 01:04:36 PM PST 24
Peak memory 202020 kb
Host smart-c0b6dc7c-e116-42b0-b721-1d1211ff8e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46778
4826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.467784826
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1264895108
Short name T84
Test name
Test status
Simulation time 8404276627 ps
CPU time 7.69 seconds
Started Feb 29 01:04:26 PM PST 24
Finished Feb 29 01:04:34 PM PST 24
Peak memory 202036 kb
Host smart-2c5bd96f-38c5-4c44-947d-4388fd66db69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12648
95108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1264895108
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3887321059
Short name T87
Test name
Test status
Simulation time 8433977703 ps
CPU time 7.4 seconds
Started Feb 29 01:05:01 PM PST 24
Finished Feb 29 01:05:09 PM PST 24
Peak memory 202188 kb
Host smart-51fce503-1b5b-4e25-a0e0-ea1a43915b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38873
21059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3887321059
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2213735410
Short name T77
Test name
Test status
Simulation time 8416116205 ps
CPU time 7.4 seconds
Started Feb 29 01:05:30 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 202168 kb
Host smart-6d7a5b57-c2e9-4248-925b-22deb3e6ab88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22137
35410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2213735410
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3574501400
Short name T67
Test name
Test status
Simulation time 8436510190 ps
CPU time 7.95 seconds
Started Feb 29 01:05:24 PM PST 24
Finished Feb 29 01:05:33 PM PST 24
Peak memory 202016 kb
Host smart-efc852f7-4b34-477e-b88d-e7caf05f3661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35745
01400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3574501400
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3446449546
Short name T75
Test name
Test status
Simulation time 8430064975 ps
CPU time 7.69 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202184 kb
Host smart-ef8e84a3-3929-46f5-afc8-e259611a374c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34464
49546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3446449546
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2749909133
Short name T69
Test name
Test status
Simulation time 8413886949 ps
CPU time 7.96 seconds
Started Feb 29 01:05:48 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 202036 kb
Host smart-827ff20a-e06a-40c7-aff1-bd1d7b89186d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27499
09133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2749909133
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3181732034
Short name T78
Test name
Test status
Simulation time 8442637544 ps
CPU time 7.5 seconds
Started Feb 29 01:06:03 PM PST 24
Finished Feb 29 01:06:11 PM PST 24
Peak memory 202144 kb
Host smart-b2ce7915-1314-4ac5-a148-3557a9ce2f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31817
32034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3181732034
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2209866759
Short name T126
Test name
Test status
Simulation time 133560769 ps
CPU time 3.41 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202560 kb
Host smart-3abbadb3-9755-4319-b1bf-9856e24a8db5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209866759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2209866759
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.540529896
Short name T388
Test name
Test status
Simulation time 39993524 ps
CPU time 0.74 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 202336 kb
Host smart-410879da-16b1-4a63-a7b8-5a0dcff2f3c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540529896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.540529896
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2755785750
Short name T346
Test name
Test status
Simulation time 78087726 ps
CPU time 2.69 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:03 PM PST 24
Peak memory 210848 kb
Host smart-e27ecdce-98e9-4341-b600-57ef6bc28b6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755785750 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2755785750
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2774953165
Short name T161
Test name
Test status
Simulation time 72664754 ps
CPU time 1.03 seconds
Started Feb 29 01:10:58 PM PST 24
Finished Feb 29 01:11:00 PM PST 24
Peak memory 202552 kb
Host smart-be74c7d2-ad1a-46be-b7ee-34da676694c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774953165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2774953165
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.868801777
Short name T130
Test name
Test status
Simulation time 201425876 ps
CPU time 2.49 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202408 kb
Host smart-9eb53794-a25a-4751-ac1e-9c6eeaf5edd9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=868801777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.868801777
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3942470736
Short name T347
Test name
Test status
Simulation time 249737663 ps
CPU time 2.53 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202408 kb
Host smart-ed35fe01-807d-4aba-82cb-ecd77b6cf80d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3942470736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3942470736
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1484437449
Short name T350
Test name
Test status
Simulation time 92866115 ps
CPU time 1.26 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202448 kb
Host smart-7d122073-a480-441b-a654-5e9ad83a96ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1484437449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1484437449
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3364574180
Short name T127
Test name
Test status
Simulation time 346299908 ps
CPU time 3.57 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202580 kb
Host smart-f0150824-ccb2-4e5c-a74d-7bd7c643f05e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364574180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3364574180
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4155493117
Short name T44
Test name
Test status
Simulation time 45970302 ps
CPU time 0.85 seconds
Started Feb 29 01:11:00 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202356 kb
Host smart-7d00cd4a-2d8e-494b-9c8a-115287462c36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155493117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4155493117
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.208257599
Short name T119
Test name
Test status
Simulation time 79519103 ps
CPU time 2.08 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 210828 kb
Host smart-38a8f4c0-e46a-42e0-8f1e-f353b18af065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208257599 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.208257599
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1379201395
Short name T48
Test name
Test status
Simulation time 69888381 ps
CPU time 1 seconds
Started Feb 29 01:11:00 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202508 kb
Host smart-0737e7a1-91f9-4f59-ae22-7b3c1ee98261
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379201395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1379201395
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2566474370
Short name T366
Test name
Test status
Simulation time 148932828 ps
CPU time 2.43 seconds
Started Feb 29 01:11:01 PM PST 24
Finished Feb 29 01:11:03 PM PST 24
Peak memory 202508 kb
Host smart-edc1d715-0bc0-4c39-b209-71e4b06ef0b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2566474370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2566474370
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3374007818
Short name T353
Test name
Test status
Simulation time 469573224 ps
CPU time 4.31 seconds
Started Feb 29 01:11:03 PM PST 24
Finished Feb 29 01:11:07 PM PST 24
Peak memory 202428 kb
Host smart-a9fc9076-006e-436e-a127-0712653f6bda
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3374007818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3374007818
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2431462816
Short name T46
Test name
Test status
Simulation time 45020995 ps
CPU time 1.07 seconds
Started Feb 29 01:11:00 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202612 kb
Host smart-d494aa94-1493-49d8-87fa-4169bc5d9e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431462816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.2431462816
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2919736808
Short name T166
Test name
Test status
Simulation time 263142290 ps
CPU time 2.89 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202524 kb
Host smart-0ebbfb94-1e5b-49e9-bb3c-5bb7d8bb117c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2919736808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2919736808
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.426381601
Short name T373
Test name
Test status
Simulation time 79562600 ps
CPU time 2.35 seconds
Started Feb 29 01:11:14 PM PST 24
Finished Feb 29 01:11:17 PM PST 24
Peak memory 210832 kb
Host smart-88a63941-d7bd-40d4-8006-626075cf4b79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426381601 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.426381601
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.700385719
Short name T371
Test name
Test status
Simulation time 28698338 ps
CPU time 0.8 seconds
Started Feb 29 01:11:11 PM PST 24
Finished Feb 29 01:11:12 PM PST 24
Peak memory 202204 kb
Host smart-45239f10-52a8-4dff-aa1d-80d2a3f8744a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700385719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.700385719
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.585052350
Short name T394
Test name
Test status
Simulation time 103694301 ps
CPU time 1.64 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:17 PM PST 24
Peak memory 202500 kb
Host smart-aec2e5d3-7c89-4e69-853f-9a98d2c4474c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=585052350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.585052350
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3958632847
Short name T344
Test name
Test status
Simulation time 73240550 ps
CPU time 2.01 seconds
Started Feb 29 01:11:17 PM PST 24
Finished Feb 29 01:11:19 PM PST 24
Peak memory 210752 kb
Host smart-79ab4726-e74d-41b1-b799-13dad0cdc22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958632847 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3958632847
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3981196373
Short name T125
Test name
Test status
Simulation time 54845007 ps
CPU time 0.91 seconds
Started Feb 29 01:11:14 PM PST 24
Finished Feb 29 01:11:15 PM PST 24
Peak memory 202448 kb
Host smart-8eb49990-f950-41c8-b830-5ea4f0caabc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981196373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3981196373
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2300126701
Short name T135
Test name
Test status
Simulation time 37066636 ps
CPU time 1.01 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:16 PM PST 24
Peak memory 202640 kb
Host smart-717bd4ea-53fd-4af3-b55f-43dd75021586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300126701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.2300126701
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.581888997
Short name T355
Test name
Test status
Simulation time 258775813 ps
CPU time 3.1 seconds
Started Feb 29 01:11:16 PM PST 24
Finished Feb 29 01:11:19 PM PST 24
Peak memory 202532 kb
Host smart-282dc167-9561-4e3f-adbf-afac1eb008e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=581888997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.581888997
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1306017068
Short name T159
Test name
Test status
Simulation time 85579544 ps
CPU time 1.19 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:20 PM PST 24
Peak memory 202560 kb
Host smart-2e3acd27-173d-4f0d-a3f2-83a6ad1fdf80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306017068 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.1306017068
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2943088584
Short name T362
Test name
Test status
Simulation time 129196765 ps
CPU time 1.08 seconds
Started Feb 29 01:11:08 PM PST 24
Finished Feb 29 01:11:09 PM PST 24
Peak memory 202484 kb
Host smart-bf56f7bf-7cb3-470f-bceb-a37e3e971be9
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943088584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2943088584
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.201170515
Short name T385
Test name
Test status
Simulation time 35305475 ps
CPU time 0.96 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:14 PM PST 24
Peak memory 202544 kb
Host smart-7b1c1440-1dc7-43d6-ba7c-978fd0c10caf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201170515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c
sr_outstanding.201170515
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4112146510
Short name T383
Test name
Test status
Simulation time 62844703 ps
CPU time 1.93 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:15 PM PST 24
Peak memory 202600 kb
Host smart-4691048f-df13-4c8d-ac29-52bf721fb3b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4112146510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.4112146510
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1626119421
Short name T361
Test name
Test status
Simulation time 244700054 ps
CPU time 2.52 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:17 PM PST 24
Peak memory 202584 kb
Host smart-df6cd391-fbb7-4014-8204-acacd0581256
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1626119421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1626119421
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1191304921
Short name T120
Test name
Test status
Simulation time 41871639 ps
CPU time 1.27 seconds
Started Feb 29 01:11:11 PM PST 24
Finished Feb 29 01:11:12 PM PST 24
Peak memory 202604 kb
Host smart-5eb99c1a-3f41-46d3-b6c0-935d04e95435
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191304921 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.1191304921
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3332632492
Short name T377
Test name
Test status
Simulation time 69268218 ps
CPU time 0.99 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:16 PM PST 24
Peak memory 202460 kb
Host smart-36badcfb-1aac-4cb5-b5a4-3a961c8c9896
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332632492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3332632492
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3988540336
Short name T342
Test name
Test status
Simulation time 60578063 ps
CPU time 1.41 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:15 PM PST 24
Peak memory 202768 kb
Host smart-2850b339-6817-46e0-9250-8d7bbe51fd4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988540336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.3988540336
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.463120619
Short name T343
Test name
Test status
Simulation time 89437603 ps
CPU time 2.68 seconds
Started Feb 29 01:11:20 PM PST 24
Finished Feb 29 01:11:23 PM PST 24
Peak memory 202500 kb
Host smart-4c715ee2-9385-4e81-979b-1d452318e276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=463120619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.463120619
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.754691998
Short name T351
Test name
Test status
Simulation time 36316384 ps
CPU time 0.96 seconds
Started Feb 29 01:11:16 PM PST 24
Finished Feb 29 01:11:18 PM PST 24
Peak memory 202408 kb
Host smart-d84a5830-1cde-4d50-aee0-ef7cd6d676ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754691998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.754691998
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2580180173
Short name T374
Test name
Test status
Simulation time 75160940 ps
CPU time 1.08 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:16 PM PST 24
Peak memory 202584 kb
Host smart-1c9bcefd-65bd-4616-82ca-7bb002503b0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580180173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.2580180173
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.861302101
Short name T379
Test name
Test status
Simulation time 446736743 ps
CPU time 2.82 seconds
Started Feb 29 01:11:10 PM PST 24
Finished Feb 29 01:11:13 PM PST 24
Peak memory 202524 kb
Host smart-b3690e7e-8411-4bc5-84cf-684211604ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=861302101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.861302101
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3862869864
Short name T354
Test name
Test status
Simulation time 132707617 ps
CPU time 1.84 seconds
Started Feb 29 01:11:21 PM PST 24
Finished Feb 29 01:11:24 PM PST 24
Peak memory 210868 kb
Host smart-66dda1e5-4e84-4b61-a73f-b1de1b41ea36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862869864 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.3862869864
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1984540958
Short name T164
Test name
Test status
Simulation time 41964251 ps
CPU time 0.81 seconds
Started Feb 29 01:11:14 PM PST 24
Finished Feb 29 01:11:15 PM PST 24
Peak memory 202368 kb
Host smart-8e192ea1-1eca-4c88-a059-331f7e616e2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984540958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1984540958
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.485620091
Short name T365
Test name
Test status
Simulation time 54321075 ps
CPU time 1.31 seconds
Started Feb 29 01:11:14 PM PST 24
Finished Feb 29 01:11:16 PM PST 24
Peak memory 202604 kb
Host smart-f6328496-538c-4ac5-b8a9-38d79671e087
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485620091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_c
sr_outstanding.485620091
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3996376038
Short name T155
Test name
Test status
Simulation time 58908292 ps
CPU time 1.82 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:15 PM PST 24
Peak memory 202500 kb
Host smart-ad374cbd-558b-41e8-be24-7f507e74ec69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3996376038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3996376038
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1224684639
Short name T168
Test name
Test status
Simulation time 267268654 ps
CPU time 4.27 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:20 PM PST 24
Peak memory 202476 kb
Host smart-ee7e90ba-c3a9-4b73-992d-55f458a91010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1224684639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1224684639
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2827807859
Short name T163
Test name
Test status
Simulation time 73345152 ps
CPU time 1.1 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:21 PM PST 24
Peak memory 218320 kb
Host smart-bc9f7886-9b8b-400d-87d7-bc749de397d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827807859 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2827807859
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2284209964
Short name T131
Test name
Test status
Simulation time 58519621 ps
CPU time 1.07 seconds
Started Feb 29 01:11:18 PM PST 24
Finished Feb 29 01:11:19 PM PST 24
Peak memory 202532 kb
Host smart-dfff5ed7-2750-4f4a-b15b-bf490687f6e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284209964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2284209964
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1498687217
Short name T389
Test name
Test status
Simulation time 53100943 ps
CPU time 1.46 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:16 PM PST 24
Peak memory 202632 kb
Host smart-04f3293f-1dcc-4ff1-b0cf-9eeb6b684a85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498687217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.1498687217
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3002757713
Short name T158
Test name
Test status
Simulation time 121706527 ps
CPU time 1.86 seconds
Started Feb 29 01:11:12 PM PST 24
Finished Feb 29 01:11:14 PM PST 24
Peak memory 202668 kb
Host smart-41a2d827-f818-4f93-8c86-7a361e20183a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3002757713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3002757713
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3382862612
Short name T129
Test name
Test status
Simulation time 32653202 ps
CPU time 0.95 seconds
Started Feb 29 01:11:20 PM PST 24
Finished Feb 29 01:11:21 PM PST 24
Peak memory 202584 kb
Host smart-b5b0652a-12e1-4232-8683-bc189fd6035b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382862612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3382862612
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1011674447
Short name T391
Test name
Test status
Simulation time 72594658 ps
CPU time 1.04 seconds
Started Feb 29 01:11:21 PM PST 24
Finished Feb 29 01:11:23 PM PST 24
Peak memory 202540 kb
Host smart-22decec6-d0ce-4b4a-bf82-7d610e764a8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011674447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.1011674447
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2126813519
Short name T392
Test name
Test status
Simulation time 154582844 ps
CPU time 2.05 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:17 PM PST 24
Peak memory 202528 kb
Host smart-ed170e3f-bc41-4a2f-a625-438021344297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2126813519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2126813519
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4035824320
Short name T123
Test name
Test status
Simulation time 119579758 ps
CPU time 1.19 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:21 PM PST 24
Peak memory 210688 kb
Host smart-81f9e059-d69c-4478-8814-be39bc4f463e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035824320 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.4035824320
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1249654657
Short name T50
Test name
Test status
Simulation time 67965984 ps
CPU time 1.04 seconds
Started Feb 29 01:11:12 PM PST 24
Finished Feb 29 01:11:13 PM PST 24
Peak memory 202500 kb
Host smart-32037caf-cb66-4a0d-90fc-4a7dfb0fe66c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249654657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1249654657
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2921761836
Short name T378
Test name
Test status
Simulation time 67265589 ps
CPU time 1.41 seconds
Started Feb 29 01:11:22 PM PST 24
Finished Feb 29 01:11:25 PM PST 24
Peak memory 202528 kb
Host smart-97e5a8aa-eb6b-4f8a-937e-00ee66b9ce26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921761836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.2921761836
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2107428055
Short name T156
Test name
Test status
Simulation time 46984728 ps
CPU time 1.3 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:21 PM PST 24
Peak memory 201676 kb
Host smart-b826b1bf-7aee-4f8a-aadb-eff260f20d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2107428055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2107428055
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2353161399
Short name T64
Test name
Test status
Simulation time 75551760 ps
CPU time 1.16 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:21 PM PST 24
Peak memory 202520 kb
Host smart-adb07184-861b-4f17-a490-bda9567b4168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353161399 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.2353161399
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2947436493
Short name T341
Test name
Test status
Simulation time 30020322 ps
CPU time 0.81 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:14 PM PST 24
Peak memory 202548 kb
Host smart-650dc8c6-a04d-4adc-9f92-71d19b5fff35
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947436493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2947436493
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3561427594
Short name T372
Test name
Test status
Simulation time 82208319 ps
CPU time 1.03 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:14 PM PST 24
Peak memory 202584 kb
Host smart-70396542-199b-4d73-8bf2-eed86eddbc7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561427594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.3561427594
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2208664394
Short name T124
Test name
Test status
Simulation time 86024004 ps
CPU time 2.64 seconds
Started Feb 29 01:11:21 PM PST 24
Finished Feb 29 01:11:25 PM PST 24
Peak memory 202528 kb
Host smart-305d8f69-9213-475b-8fa1-ffcf140dbb85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2208664394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2208664394
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3701378393
Short name T345
Test name
Test status
Simulation time 122604686 ps
CPU time 3.25 seconds
Started Feb 29 01:11:00 PM PST 24
Finished Feb 29 01:11:04 PM PST 24
Peak memory 202652 kb
Host smart-f0e6eacc-509d-46a4-b470-d808cc3d1b7d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701378393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3701378393
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3321743473
Short name T348
Test name
Test status
Simulation time 33341223 ps
CPU time 0.93 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202496 kb
Host smart-02da310b-482e-45b4-9e04-e4dde2b1a2cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321743473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3321743473
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2955840273
Short name T364
Test name
Test status
Simulation time 161100236 ps
CPU time 2.26 seconds
Started Feb 29 01:10:58 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202484 kb
Host smart-db284329-585a-4fef-a14c-372d99370bfa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2955840273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2955840273
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4159328924
Short name T384
Test name
Test status
Simulation time 85808878 ps
CPU time 2.42 seconds
Started Feb 29 01:11:00 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202296 kb
Host smart-251023b0-f570-4e7c-8515-224d7e44c8e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4159328924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.4159328924
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1408435669
Short name T382
Test name
Test status
Simulation time 108771709 ps
CPU time 1.11 seconds
Started Feb 29 01:11:08 PM PST 24
Finished Feb 29 01:11:09 PM PST 24
Peak memory 202492 kb
Host smart-e8ef6a3a-3de7-469b-b079-c153890a34c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408435669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.1408435669
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.284932487
Short name T367
Test name
Test status
Simulation time 51937018 ps
CPU time 1.8 seconds
Started Feb 29 01:11:00 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202332 kb
Host smart-57f34ef6-eb42-4cb9-9b23-b35f77e068c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=284932487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.284932487
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1516210814
Short name T128
Test name
Test status
Simulation time 175592919 ps
CPU time 2.22 seconds
Started Feb 29 01:11:03 PM PST 24
Finished Feb 29 01:11:05 PM PST 24
Peak memory 202588 kb
Host smart-247f981a-e79d-4117-a6e5-3f7bc1acd2a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516210814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1516210814
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2411694354
Short name T122
Test name
Test status
Simulation time 73303543 ps
CPU time 2.2 seconds
Started Feb 29 01:11:04 PM PST 24
Finished Feb 29 01:11:06 PM PST 24
Peak memory 211016 kb
Host smart-c8c6c21b-5f88-40a0-a3ed-3863219885e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411694354 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2411694354
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3502095351
Short name T49
Test name
Test status
Simulation time 80370820 ps
CPU time 1.05 seconds
Started Feb 29 01:11:03 PM PST 24
Finished Feb 29 01:11:04 PM PST 24
Peak memory 202532 kb
Host smart-7c9f9291-c87f-46ac-909b-6353c57fda91
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502095351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3502095351
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3751084535
Short name T132
Test name
Test status
Simulation time 41509494 ps
CPU time 1.38 seconds
Started Feb 29 01:11:04 PM PST 24
Finished Feb 29 01:11:05 PM PST 24
Peak memory 202696 kb
Host smart-1884cdce-f4ee-440d-bd36-49fd3ebbc450
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3751084535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3751084535
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3694323579
Short name T390
Test name
Test status
Simulation time 86605059 ps
CPU time 2.34 seconds
Started Feb 29 01:11:02 PM PST 24
Finished Feb 29 01:11:05 PM PST 24
Peak memory 202384 kb
Host smart-180638d9-23d0-44a6-8524-b709a49a2dfe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3694323579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3694323579
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2047440743
Short name T349
Test name
Test status
Simulation time 70240868 ps
CPU time 1.12 seconds
Started Feb 29 01:11:03 PM PST 24
Finished Feb 29 01:11:04 PM PST 24
Peak memory 202476 kb
Host smart-268f6c1a-aff8-4f46-bd46-c034cfd2491b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047440743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.2047440743
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.210398678
Short name T376
Test name
Test status
Simulation time 113196615 ps
CPU time 1.48 seconds
Started Feb 29 01:11:08 PM PST 24
Finished Feb 29 01:11:10 PM PST 24
Peak memory 202496 kb
Host smart-5085f637-8c5e-4683-b1f8-239167f6a47b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=210398678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.210398678
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3406322425
Short name T359
Test name
Test status
Simulation time 260506729 ps
CPU time 2.53 seconds
Started Feb 29 01:11:08 PM PST 24
Finished Feb 29 01:11:11 PM PST 24
Peak memory 202600 kb
Host smart-cef15db3-5335-44f4-a9c0-64d1a44641cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3406322425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3406322425
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4150512357
Short name T386
Test name
Test status
Simulation time 252535106 ps
CPU time 4.67 seconds
Started Feb 29 01:10:58 PM PST 24
Finished Feb 29 01:11:03 PM PST 24
Peak memory 202520 kb
Host smart-abb778ba-b44c-4af9-a7b1-4467adb2421a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150512357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.4150512357
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.201852437
Short name T121
Test name
Test status
Simulation time 50379376 ps
CPU time 1.4 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 210864 kb
Host smart-11d050d8-a496-4a44-a428-124314fcef96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201852437 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.201852437
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1169538043
Short name T370
Test name
Test status
Simulation time 63933264 ps
CPU time 2.15 seconds
Started Feb 29 01:10:58 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202460 kb
Host smart-bf3ac830-63ca-475d-a3c5-6d0edeffb3b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1169538043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1169538043
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2609072070
Short name T352
Test name
Test status
Simulation time 476347116 ps
CPU time 4.55 seconds
Started Feb 29 01:11:00 PM PST 24
Finished Feb 29 01:11:05 PM PST 24
Peak memory 202412 kb
Host smart-e2182e53-25ed-42f4-8e42-0ee21cf1a15b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2609072070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2609072070
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1325145999
Short name T134
Test name
Test status
Simulation time 87356821 ps
CPU time 1.07 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:58 PM PST 24
Peak memory 202592 kb
Host smart-53f690ea-c26a-48f3-b2de-4112487ec53a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325145999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.1325145999
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1606562873
Short name T39
Test name
Test status
Simulation time 61300546 ps
CPU time 2.02 seconds
Started Feb 29 01:11:04 PM PST 24
Finished Feb 29 01:11:06 PM PST 24
Peak memory 202640 kb
Host smart-f1fd89a5-36ff-460a-b38c-3e437dab5e56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606562873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1606562873
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2557607659
Short name T162
Test name
Test status
Simulation time 136218176 ps
CPU time 1.78 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:11:00 PM PST 24
Peak memory 213272 kb
Host smart-dee74704-b93a-4b3f-8d77-e33484d18cb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557607659 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.2557607659
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4222682136
Short name T381
Test name
Test status
Simulation time 86518426 ps
CPU time 1.11 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 202556 kb
Host smart-908e0b3d-aea5-4923-8c6f-9ffa0bdf0b3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222682136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.4222682136
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1086039272
Short name T157
Test name
Test status
Simulation time 174604418 ps
CPU time 1.98 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202408 kb
Host smart-a0daea46-4f68-442f-b74a-ea66df149eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1086039272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1086039272
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3605531988
Short name T137
Test name
Test status
Simulation time 346892487 ps
CPU time 2.64 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:03 PM PST 24
Peak memory 202508 kb
Host smart-33a0155e-f9c1-4635-a1d9-c984de561ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3605531988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3605531988
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2252855907
Short name T387
Test name
Test status
Simulation time 120151146 ps
CPU time 1.87 seconds
Started Feb 29 01:11:14 PM PST 24
Finished Feb 29 01:11:16 PM PST 24
Peak memory 210868 kb
Host smart-c4bb054a-4f31-4f71-91ef-08fc8b74ada7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252855907 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.2252855907
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3086861820
Short name T339
Test name
Test status
Simulation time 43707157 ps
CPU time 0.81 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 202380 kb
Host smart-4423da46-c1a7-4677-a10a-4ff1a4bed8c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086861820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3086861820
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1622248251
Short name T160
Test name
Test status
Simulation time 138449543 ps
CPU time 1.54 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:17 PM PST 24
Peak memory 202536 kb
Host smart-7dfc0774-984e-4ca2-880b-1742a205840a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622248251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.1622248251
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.113516939
Short name T375
Test name
Test status
Simulation time 206930825 ps
CPU time 2.54 seconds
Started Feb 29 01:10:58 PM PST 24
Finished Feb 29 01:11:02 PM PST 24
Peak memory 202492 kb
Host smart-433fae6c-df52-4008-adbb-f5b291272428
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=113516939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.113516939
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3161743746
Short name T169
Test name
Test status
Simulation time 489321660 ps
CPU time 5.07 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:11:04 PM PST 24
Peak memory 202576 kb
Host smart-094459e1-aeba-407a-a1ac-f7ed117e13a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3161743746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3161743746
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1846629092
Short name T395
Test name
Test status
Simulation time 56323330 ps
CPU time 1.72 seconds
Started Feb 29 01:11:18 PM PST 24
Finished Feb 29 01:11:20 PM PST 24
Peak memory 210872 kb
Host smart-608b8166-5602-41ad-a72e-ae779a408f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846629092 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1846629092
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3822275238
Short name T357
Test name
Test status
Simulation time 62537030 ps
CPU time 0.96 seconds
Started Feb 29 01:11:11 PM PST 24
Finished Feb 29 01:11:13 PM PST 24
Peak memory 202460 kb
Host smart-b2c18df1-d225-42ab-a78f-00aae8b416cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822275238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3822275238
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3083517045
Short name T340
Test name
Test status
Simulation time 63674750 ps
CPU time 1.52 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:21 PM PST 24
Peak memory 202600 kb
Host smart-a2bf4440-bd7a-4d01-bc92-47da1aa57b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083517045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.3083517045
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3786317938
Short name T136
Test name
Test status
Simulation time 87881683 ps
CPU time 2.92 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:19 PM PST 24
Peak memory 202420 kb
Host smart-6dfc4d06-4dd0-4c1a-9bc6-1f4dbed2774b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3786317938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3786317938
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3278144199
Short name T139
Test name
Test status
Simulation time 307616811 ps
CPU time 2.89 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:16 PM PST 24
Peak memory 202548 kb
Host smart-a42627f3-652e-4326-ae8b-603ca87f3cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3278144199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3278144199
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3887150578
Short name T360
Test name
Test status
Simulation time 114178542 ps
CPU time 1.79 seconds
Started Feb 29 01:11:11 PM PST 24
Finished Feb 29 01:11:13 PM PST 24
Peak memory 210768 kb
Host smart-2f49d3a5-b9e2-4425-807a-e137c1eae480
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887150578 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.3887150578
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.570532664
Short name T133
Test name
Test status
Simulation time 64258921 ps
CPU time 1.02 seconds
Started Feb 29 01:11:19 PM PST 24
Finished Feb 29 01:11:20 PM PST 24
Peak memory 202540 kb
Host smart-3366e549-c952-45db-a1ae-5080c3b3fb59
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570532664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.570532664
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.411641971
Short name T368
Test name
Test status
Simulation time 147051746 ps
CPU time 1.51 seconds
Started Feb 29 01:11:13 PM PST 24
Finished Feb 29 01:11:14 PM PST 24
Peak memory 202600 kb
Host smart-b5fcd01f-bb58-45d0-a6e2-d9a9bcd8a4a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411641971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_cs
r_outstanding.411641971
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.82177020
Short name T380
Test name
Test status
Simulation time 233022799 ps
CPU time 2.53 seconds
Started Feb 29 01:11:11 PM PST 24
Finished Feb 29 01:11:13 PM PST 24
Peak memory 202456 kb
Host smart-8291e034-bc6f-4c6c-80e4-540d61159c91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=82177020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.82177020
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3066835048
Short name T358
Test name
Test status
Simulation time 138217572 ps
CPU time 1.67 seconds
Started Feb 29 01:11:10 PM PST 24
Finished Feb 29 01:11:12 PM PST 24
Peak memory 210844 kb
Host smart-8741aa3d-c88d-479a-84f2-17b5c6047409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066835048 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.3066835048
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2629884788
Short name T393
Test name
Test status
Simulation time 32223890 ps
CPU time 0.79 seconds
Started Feb 29 01:11:15 PM PST 24
Finished Feb 29 01:11:16 PM PST 24
Peak memory 202172 kb
Host smart-c4facdb1-6282-40ab-a3a3-2391b6f421da
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629884788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2629884788
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2000545474
Short name T363
Test name
Test status
Simulation time 133553191 ps
CPU time 1.61 seconds
Started Feb 29 01:11:11 PM PST 24
Finished Feb 29 01:11:13 PM PST 24
Peak memory 202608 kb
Host smart-46614d8f-1a43-4d15-abad-4653c8f21556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000545474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.2000545474
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.769140539
Short name T369
Test name
Test status
Simulation time 77121017 ps
CPU time 1.28 seconds
Started Feb 29 01:11:20 PM PST 24
Finished Feb 29 01:11:21 PM PST 24
Peak memory 202464 kb
Host smart-5d3835a6-4580-46c8-9559-7e54684c3c74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=769140539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.769140539
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.543331346
Short name T28
Test name
Test status
Simulation time 8374695443 ps
CPU time 7.76 seconds
Started Feb 29 01:03:43 PM PST 24
Finished Feb 29 01:03:51 PM PST 24
Peak memory 202140 kb
Host smart-c9e4db24-fe74-4e17-b576-943df3a1b8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54333
1346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.543331346
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3253277147
Short name T269
Test name
Test status
Simulation time 8433764653 ps
CPU time 6.95 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 202148 kb
Host smart-44ec72de-3f76-4025-ab72-4657b670b676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32532
77147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3253277147
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1227112469
Short name T327
Test name
Test status
Simulation time 8367038900 ps
CPU time 7.55 seconds
Started Feb 29 01:03:42 PM PST 24
Finished Feb 29 01:03:50 PM PST 24
Peak memory 202184 kb
Host smart-5100124c-1cac-4ab5-bd5f-37f4b175e890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12271
12469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1227112469
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.setup_trans_ignored.3659725154
Short name T254
Test name
Test status
Simulation time 8361826609 ps
CPU time 7.07 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 202156 kb
Host smart-8def70a9-c055-4b92-8297-f169f1a6e491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36597
25154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.setup_trans_ignored.3659725154
Directory /workspace/1.setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.439820914
Short name T320
Test name
Test status
Simulation time 8367184675 ps
CPU time 6.99 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 202084 kb
Host smart-444ec0ba-4ddd-49b8-983e-51815497065f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43982
0914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.439820914
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3495946282
Short name T9
Test name
Test status
Simulation time 8414703698 ps
CPU time 8.35 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:54 PM PST 24
Peak memory 202064 kb
Host smart-fefd3f70-1cbf-4747-b1de-eb65bcc1e00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34959
46282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3495946282
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2683291571
Short name T15
Test name
Test status
Simulation time 8415589751 ps
CPU time 7.3 seconds
Started Feb 29 01:03:44 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 202148 kb
Host smart-170f7ae8-d652-4466-bcac-614d09669559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26832
91571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2683291571
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.681850566
Short name T54
Test name
Test status
Simulation time 107799389 ps
CPU time 0.91 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:46 PM PST 24
Peak memory 216848 kb
Host smart-7ced2302-2a6c-46b9-941b-ccda058cc9d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=681850566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.681850566
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3201450813
Short name T141
Test name
Test status
Simulation time 8373744640 ps
CPU time 8.12 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:53 PM PST 24
Peak memory 202076 kb
Host smart-229f1ef0-6883-467f-b7c6-97fe29b62c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
50813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3201450813
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.in_trans.3713041460
Short name T58
Test name
Test status
Simulation time 8439573876 ps
CPU time 7.22 seconds
Started Feb 29 01:04:27 PM PST 24
Finished Feb 29 01:04:35 PM PST 24
Peak memory 201736 kb
Host smart-8d4172fa-35b4-442a-ae9f-68bdddab3e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37130
41460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.in_trans.3713041460
Directory /workspace/10.in_trans/latest

Test location /workspace/coverage/default/10.setup_trans_ignored.3147317236
Short name T190
Test name
Test status
Simulation time 8364132446 ps
CPU time 7.09 seconds
Started Feb 29 01:04:26 PM PST 24
Finished Feb 29 01:04:33 PM PST 24
Peak memory 202084 kb
Host smart-4a4d82c7-4ade-4bd2-b021-bcff17cbabbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31473
17236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.setup_trans_ignored.3147317236
Directory /workspace/10.setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.249413474
Short name T171
Test name
Test status
Simulation time 8384351308 ps
CPU time 8.21 seconds
Started Feb 29 01:04:26 PM PST 24
Finished Feb 29 01:04:35 PM PST 24
Peak memory 202144 kb
Host smart-71215e9a-49e8-43ef-9589-ad9dd540e510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24941
3474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.249413474
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1827668871
Short name T293
Test name
Test status
Simulation time 8375468033 ps
CPU time 7.17 seconds
Started Feb 29 01:04:27 PM PST 24
Finished Feb 29 01:04:35 PM PST 24
Peak memory 201764 kb
Host smart-ace5d20d-1a97-433d-afd2-ebf0004610b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18276
68871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1827668871
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.setup_trans_ignored.1444561567
Short name T225
Test name
Test status
Simulation time 8360792009 ps
CPU time 7.35 seconds
Started Feb 29 01:04:27 PM PST 24
Finished Feb 29 01:04:34 PM PST 24
Peak memory 202124 kb
Host smart-30c7280b-ffca-41e6-b602-695cb02ec77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14445
61567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.setup_trans_ignored.1444561567
Directory /workspace/11.setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2711265906
Short name T299
Test name
Test status
Simulation time 8453499391 ps
CPU time 7.49 seconds
Started Feb 29 01:04:25 PM PST 24
Finished Feb 29 01:04:33 PM PST 24
Peak memory 202216 kb
Host smart-7fcfb15b-dd29-49a1-9fb4-55c3b0b35369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27112
65906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2711265906
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2577216256
Short name T309
Test name
Test status
Simulation time 8432705654 ps
CPU time 8.02 seconds
Started Feb 29 01:04:27 PM PST 24
Finished Feb 29 01:04:36 PM PST 24
Peak memory 201936 kb
Host smart-75c26217-9045-4132-b9ba-298fc55ed2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25772
16256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2577216256
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.10420559
Short name T150
Test name
Test status
Simulation time 8387904360 ps
CPU time 7.51 seconds
Started Feb 29 01:04:25 PM PST 24
Finished Feb 29 01:04:33 PM PST 24
Peak memory 202088 kb
Host smart-313505cb-1712-449a-a871-c6ae47b76b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10420
559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.10420559
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_smoke.919725997
Short name T4
Test name
Test status
Simulation time 8369166048 ps
CPU time 8.22 seconds
Started Feb 29 01:04:37 PM PST 24
Finished Feb 29 01:04:45 PM PST 24
Peak memory 202096 kb
Host smart-f0c9dfb5-8dd8-4d9e-8030-4b2ec7ca5258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91972
5997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.919725997
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.in_trans.2713835688
Short name T259
Test name
Test status
Simulation time 8453049691 ps
CPU time 7.56 seconds
Started Feb 29 01:04:23 PM PST 24
Finished Feb 29 01:04:30 PM PST 24
Peak memory 202144 kb
Host smart-de4e4937-afa8-4fc6-8072-2479058827b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27138
35688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.in_trans.2713835688
Directory /workspace/12.in_trans/latest

Test location /workspace/coverage/default/12.setup_trans_ignored.475621166
Short name T276
Test name
Test status
Simulation time 8357100105 ps
CPU time 7.57 seconds
Started Feb 29 01:04:25 PM PST 24
Finished Feb 29 01:04:33 PM PST 24
Peak memory 202116 kb
Host smart-f0958b98-8b38-43c4-9943-803d93ae8d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47562
1166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.setup_trans_ignored.475621166
Directory /workspace/12.setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2507652990
Short name T335
Test name
Test status
Simulation time 8463042981 ps
CPU time 8 seconds
Started Feb 29 01:04:24 PM PST 24
Finished Feb 29 01:04:32 PM PST 24
Peak memory 202192 kb
Host smart-4f6459e7-f1b2-4610-91a8-bc2ef408fb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25076
52990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2507652990
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2912019078
Short name T279
Test name
Test status
Simulation time 8438299811 ps
CPU time 7.71 seconds
Started Feb 29 01:04:23 PM PST 24
Finished Feb 29 01:04:31 PM PST 24
Peak memory 202144 kb
Host smart-ba077243-9edc-4043-a445-e28a8e9b9626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29120
19078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2912019078
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2805272973
Short name T319
Test name
Test status
Simulation time 8368275404 ps
CPU time 6.93 seconds
Started Feb 29 01:04:25 PM PST 24
Finished Feb 29 01:04:32 PM PST 24
Peak memory 202076 kb
Host smart-5630ebfb-ba64-47f7-a2f9-49b06d0ad604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28052
72973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2805272973
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.in_trans.2298250478
Short name T174
Test name
Test status
Simulation time 8443726103 ps
CPU time 7.83 seconds
Started Feb 29 01:04:37 PM PST 24
Finished Feb 29 01:04:44 PM PST 24
Peak memory 202076 kb
Host smart-9321c2e6-7b1c-4359-8165-24cf13787f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22982
50478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.in_trans.2298250478
Directory /workspace/13.in_trans/latest

Test location /workspace/coverage/default/13.setup_trans_ignored.4210120293
Short name T20
Test name
Test status
Simulation time 8384001688 ps
CPU time 7.29 seconds
Started Feb 29 01:04:23 PM PST 24
Finished Feb 29 01:04:31 PM PST 24
Peak memory 202116 kb
Host smart-63de29f3-0b04-4b1a-a707-ca0cc35c3390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42101
20293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.setup_trans_ignored.4210120293
Directory /workspace/13.setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1927482470
Short name T329
Test name
Test status
Simulation time 8429832250 ps
CPU time 7.35 seconds
Started Feb 29 01:04:38 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 202168 kb
Host smart-92a67dbe-3324-4ac6-a9ad-80b2502e31d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19274
82470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1927482470
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_smoke.814709251
Short name T232
Test name
Test status
Simulation time 8370144132 ps
CPU time 7.63 seconds
Started Feb 29 01:04:25 PM PST 24
Finished Feb 29 01:04:33 PM PST 24
Peak memory 202080 kb
Host smart-b59527f6-da0f-4605-971f-1a4bc5bec23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81470
9251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.814709251
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.in_trans.2989966979
Short name T107
Test name
Test status
Simulation time 8423777491 ps
CPU time 7.49 seconds
Started Feb 29 01:04:38 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 202156 kb
Host smart-1aa44331-1b91-4c83-a844-99d7122935cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29899
66979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.in_trans.2989966979
Directory /workspace/14.in_trans/latest

Test location /workspace/coverage/default/14.setup_trans_ignored.3327790631
Short name T334
Test name
Test status
Simulation time 8363725389 ps
CPU time 7.84 seconds
Started Feb 29 01:04:43 PM PST 24
Finished Feb 29 01:04:51 PM PST 24
Peak memory 202064 kb
Host smart-cc1647c7-2012-4260-b303-c2532a0d268d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
90631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.setup_trans_ignored.3327790631
Directory /workspace/14.setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2040630474
Short name T220
Test name
Test status
Simulation time 8371465051 ps
CPU time 7.14 seconds
Started Feb 29 01:04:35 PM PST 24
Finished Feb 29 01:04:42 PM PST 24
Peak memory 202168 kb
Host smart-a2e01d58-0680-4204-a578-177980a739ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20406
30474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2040630474
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2395940287
Short name T112
Test name
Test status
Simulation time 8377442886 ps
CPU time 7.22 seconds
Started Feb 29 01:04:41 PM PST 24
Finished Feb 29 01:04:48 PM PST 24
Peak memory 202160 kb
Host smart-4edea5e5-3012-40de-9923-5a8e280364e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959
40287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2395940287
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3346138548
Short name T284
Test name
Test status
Simulation time 8372904545 ps
CPU time 7.66 seconds
Started Feb 29 01:04:37 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 202112 kb
Host smart-29a29b53-19ee-408b-9068-4bf72cd76642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461
38548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3346138548
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.in_trans.1270941229
Short name T261
Test name
Test status
Simulation time 8452692810 ps
CPU time 7.6 seconds
Started Feb 29 01:04:40 PM PST 24
Finished Feb 29 01:04:48 PM PST 24
Peak memory 202020 kb
Host smart-448792d3-b072-40b7-8f8b-05d22390fc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12709
41229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.in_trans.1270941229
Directory /workspace/15.in_trans/latest

Test location /workspace/coverage/default/15.setup_trans_ignored.3145063977
Short name T266
Test name
Test status
Simulation time 8360666995 ps
CPU time 7.18 seconds
Started Feb 29 01:04:38 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 202100 kb
Host smart-a3a5cbfb-c6a8-4edc-946d-1cf26b47a250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31450
63977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.setup_trans_ignored.3145063977
Directory /workspace/15.setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1608772283
Short name T35
Test name
Test status
Simulation time 8371774903 ps
CPU time 7.38 seconds
Started Feb 29 01:04:36 PM PST 24
Finished Feb 29 01:04:43 PM PST 24
Peak memory 202152 kb
Host smart-3746c640-b57b-416e-a97d-39bd4bafcae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16087
72283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1608772283
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2718632422
Short name T89
Test name
Test status
Simulation time 8439929609 ps
CPU time 8.35 seconds
Started Feb 29 01:04:35 PM PST 24
Finished Feb 29 01:04:44 PM PST 24
Peak memory 202120 kb
Host smart-5577bf9b-c6d8-40d5-8cfd-a58cb69116f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27186
32422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2718632422
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1533480218
Short name T98
Test name
Test status
Simulation time 8450579367 ps
CPU time 8.61 seconds
Started Feb 29 01:04:38 PM PST 24
Finished Feb 29 01:04:47 PM PST 24
Peak memory 202252 kb
Host smart-0636dfb5-a745-4520-ad37-59c5fcd5544d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15334
80218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1533480218
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1469727643
Short name T173
Test name
Test status
Simulation time 8366047072 ps
CPU time 7.3 seconds
Started Feb 29 01:04:38 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 202212 kb
Host smart-7d040cb1-e227-40d7-9d93-8b2c47d72cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14697
27643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1469727643
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.in_trans.1594091977
Short name T116
Test name
Test status
Simulation time 8374345288 ps
CPU time 7.04 seconds
Started Feb 29 01:04:37 PM PST 24
Finished Feb 29 01:04:44 PM PST 24
Peak memory 202168 kb
Host smart-23637017-f37b-4644-b432-0417b5254e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15940
91977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.in_trans.1594091977
Directory /workspace/16.in_trans/latest

Test location /workspace/coverage/default/16.setup_trans_ignored.3488725783
Short name T260
Test name
Test status
Simulation time 8362963526 ps
CPU time 7.27 seconds
Started Feb 29 01:04:39 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 202112 kb
Host smart-b10b132a-8f39-42a8-81b9-9f4e723546c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34887
25783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.setup_trans_ignored.3488725783
Directory /workspace/16.setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.200942870
Short name T36
Test name
Test status
Simulation time 8369101400 ps
CPU time 7.64 seconds
Started Feb 29 01:04:39 PM PST 24
Finished Feb 29 01:04:47 PM PST 24
Peak memory 202176 kb
Host smart-81026cec-dc34-45a2-9493-e21c457e96e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20094
2870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.200942870
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3575187787
Short name T73
Test name
Test status
Simulation time 8432377245 ps
CPU time 7.33 seconds
Started Feb 29 01:04:44 PM PST 24
Finished Feb 29 01:04:51 PM PST 24
Peak memory 202076 kb
Host smart-ef0c7bf7-085f-4ab1-90b7-6ff2bfc1d385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35751
87787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3575187787
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.973096836
Short name T198
Test name
Test status
Simulation time 8412692109 ps
CPU time 8.58 seconds
Started Feb 29 01:04:38 PM PST 24
Finished Feb 29 01:04:47 PM PST 24
Peak memory 202128 kb
Host smart-18afc461-8210-4632-9297-ef927aecc13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97309
6836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.973096836
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2264286585
Short name T249
Test name
Test status
Simulation time 8374762564 ps
CPU time 7.6 seconds
Started Feb 29 01:04:36 PM PST 24
Finished Feb 29 01:04:43 PM PST 24
Peak memory 202092 kb
Host smart-d5fc1cc3-af57-42f2-9547-a7d2b86fd15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22642
86585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2264286585
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.in_trans.609023081
Short name T95
Test name
Test status
Simulation time 8437276652 ps
CPU time 7.1 seconds
Started Feb 29 01:04:53 PM PST 24
Finished Feb 29 01:05:00 PM PST 24
Peak memory 202128 kb
Host smart-1f438fc0-47de-4932-8812-6f79f9be5579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60902
3081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.in_trans.609023081
Directory /workspace/17.in_trans/latest

Test location /workspace/coverage/default/17.setup_trans_ignored.2929793902
Short name T143
Test name
Test status
Simulation time 8370184875 ps
CPU time 7.45 seconds
Started Feb 29 01:04:53 PM PST 24
Finished Feb 29 01:05:00 PM PST 24
Peak memory 202152 kb
Host smart-fc91147b-13db-4084-8be1-19663db5b8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297
93902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.setup_trans_ignored.2929793902
Directory /workspace/17.setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3894869592
Short name T234
Test name
Test status
Simulation time 8373040110 ps
CPU time 7.31 seconds
Started Feb 29 01:04:51 PM PST 24
Finished Feb 29 01:04:58 PM PST 24
Peak memory 202016 kb
Host smart-0509df18-3234-432a-97cc-a7e9842ae8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38948
69592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3894869592
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2206132091
Short name T117
Test name
Test status
Simulation time 8392933071 ps
CPU time 7.24 seconds
Started Feb 29 01:04:51 PM PST 24
Finished Feb 29 01:04:59 PM PST 24
Peak memory 202152 kb
Host smart-ef274b12-5d1e-4ba8-afe0-156f073a421d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22061
32091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2206132091
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2586490314
Short name T202
Test name
Test status
Simulation time 8368519940 ps
CPU time 7.94 seconds
Started Feb 29 01:04:37 PM PST 24
Finished Feb 29 01:04:45 PM PST 24
Peak memory 202152 kb
Host smart-25792cdd-2516-46b4-af4f-38b0eebf0803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25864
90314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2586490314
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.in_trans.4256802603
Short name T286
Test name
Test status
Simulation time 8461083015 ps
CPU time 7.91 seconds
Started Feb 29 01:04:49 PM PST 24
Finished Feb 29 01:04:58 PM PST 24
Peak memory 202104 kb
Host smart-1035ddc4-99eb-469c-9ec2-723be06d52b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42568
02603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.in_trans.4256802603
Directory /workspace/18.in_trans/latest

Test location /workspace/coverage/default/18.setup_trans_ignored.3305307472
Short name T282
Test name
Test status
Simulation time 8359821025 ps
CPU time 6.97 seconds
Started Feb 29 01:04:51 PM PST 24
Finished Feb 29 01:04:58 PM PST 24
Peak memory 202024 kb
Host smart-3d26f744-0e14-4975-a9d0-149ce3dd8618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33053
07472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.setup_trans_ignored.3305307472
Directory /workspace/18.setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1455931666
Short name T304
Test name
Test status
Simulation time 8371748613 ps
CPU time 7.85 seconds
Started Feb 29 01:04:53 PM PST 24
Finished Feb 29 01:05:01 PM PST 24
Peak memory 202148 kb
Host smart-dbdfcc04-6234-4a1e-96e9-fba5983ab0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14559
31666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1455931666
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.755782992
Short name T182
Test name
Test status
Simulation time 8421479743 ps
CPU time 7.87 seconds
Started Feb 29 01:04:54 PM PST 24
Finished Feb 29 01:05:04 PM PST 24
Peak memory 202148 kb
Host smart-674c701e-0361-4aa6-b994-a59b6d2e4382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75578
2992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.755782992
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3753234873
Short name T258
Test name
Test status
Simulation time 8366215315 ps
CPU time 7.76 seconds
Started Feb 29 01:04:52 PM PST 24
Finished Feb 29 01:05:01 PM PST 24
Peak memory 202048 kb
Host smart-3d2316d8-fb81-41f3-b456-fb3b8a6a6203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37532
34873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3753234873
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/19.setup_trans_ignored.2953761177
Short name T240
Test name
Test status
Simulation time 8362936893 ps
CPU time 8.19 seconds
Started Feb 29 01:04:52 PM PST 24
Finished Feb 29 01:05:01 PM PST 24
Peak memory 202168 kb
Host smart-5b415ee7-7dd8-4492-94ac-283628fbe5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
61177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.setup_trans_ignored.2953761177
Directory /workspace/19.setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.867046263
Short name T3
Test name
Test status
Simulation time 8374282335 ps
CPU time 7.72 seconds
Started Feb 29 01:04:50 PM PST 24
Finished Feb 29 01:04:58 PM PST 24
Peak memory 202084 kb
Host smart-681ba0a6-426c-4c1f-8614-7a3087464e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86704
6263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.867046263
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3132153639
Short name T263
Test name
Test status
Simulation time 8437103428 ps
CPU time 9 seconds
Started Feb 29 01:04:54 PM PST 24
Finished Feb 29 01:05:03 PM PST 24
Peak memory 202048 kb
Host smart-f863bcd0-6bfe-45f5-9b0b-8342d876b1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31321
53639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3132153639
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1333661541
Short name T175
Test name
Test status
Simulation time 8376897456 ps
CPU time 7.61 seconds
Started Feb 29 01:04:55 PM PST 24
Finished Feb 29 01:05:04 PM PST 24
Peak memory 201976 kb
Host smart-c537f776-8c68-4694-b167-960c2e2da602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13336
61541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1333661541
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.setup_trans_ignored.422601148
Short name T255
Test name
Test status
Simulation time 8361640685 ps
CPU time 7.55 seconds
Started Feb 29 01:03:45 PM PST 24
Finished Feb 29 01:03:53 PM PST 24
Peak memory 202160 kb
Host smart-15d6600c-2bfb-4e8c-9e0c-541a8bc52ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
1148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.setup_trans_ignored.422601148
Directory /workspace/2.setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.860189682
Short name T142
Test name
Test status
Simulation time 8400291779 ps
CPU time 7.24 seconds
Started Feb 29 01:03:43 PM PST 24
Finished Feb 29 01:03:51 PM PST 24
Peak memory 202140 kb
Host smart-366b9ab3-b113-4690-be50-b97fbfc24fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86018
9682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.860189682
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1650934219
Short name T91
Test name
Test status
Simulation time 8480791479 ps
CPU time 7.01 seconds
Started Feb 29 01:03:46 PM PST 24
Finished Feb 29 01:03:53 PM PST 24
Peak memory 202080 kb
Host smart-25240cbd-8094-4fce-8c7e-78b7c55b7f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16509
34219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1650934219
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.4168821812
Short name T42
Test name
Test status
Simulation time 88911791 ps
CPU time 0.96 seconds
Started Feb 29 01:04:01 PM PST 24
Finished Feb 29 01:04:03 PM PST 24
Peak memory 216900 kb
Host smart-7349a43d-bbfc-4310-b126-4d69d371ad08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4168821812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.4168821812
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_smoke.640601031
Short name T154
Test name
Test status
Simulation time 8368249097 ps
CPU time 7.16 seconds
Started Feb 29 01:03:44 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 202068 kb
Host smart-2a489600-7f99-45ef-81ee-48d217d07e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64060
1031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.640601031
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.in_trans.3857031401
Short name T106
Test name
Test status
Simulation time 8445386409 ps
CPU time 9.49 seconds
Started Feb 29 01:05:05 PM PST 24
Finished Feb 29 01:05:15 PM PST 24
Peak memory 202144 kb
Host smart-9f0e4448-1a07-43a3-ae03-b3f07ff2ba20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38570
31401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.in_trans.3857031401
Directory /workspace/20.in_trans/latest

Test location /workspace/coverage/default/20.setup_trans_ignored.2647551120
Short name T227
Test name
Test status
Simulation time 8360808311 ps
CPU time 6.99 seconds
Started Feb 29 01:04:52 PM PST 24
Finished Feb 29 01:05:00 PM PST 24
Peak memory 202080 kb
Host smart-b35860ec-174e-4e1e-8c72-d14dca2aa1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26475
51120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.setup_trans_ignored.2647551120
Directory /workspace/20.setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3968795227
Short name T264
Test name
Test status
Simulation time 8376169696 ps
CPU time 9.44 seconds
Started Feb 29 01:04:53 PM PST 24
Finished Feb 29 01:05:02 PM PST 24
Peak memory 202168 kb
Host smart-249a75ad-006b-4b62-9c4d-ff5454e8f5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39687
95227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3968795227
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1323007893
Short name T226
Test name
Test status
Simulation time 8402182218 ps
CPU time 7.33 seconds
Started Feb 29 01:04:54 PM PST 24
Finished Feb 29 01:05:01 PM PST 24
Peak memory 202168 kb
Host smart-da1aaf34-b402-4650-8b79-50c4d82d84f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13230
07893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1323007893
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.201313426
Short name T229
Test name
Test status
Simulation time 8386058580 ps
CPU time 6.9 seconds
Started Feb 29 01:04:55 PM PST 24
Finished Feb 29 01:05:03 PM PST 24
Peak memory 201972 kb
Host smart-8f0b936d-3b76-4550-92f3-0815f0933221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131
3426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.201313426
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_smoke.693004085
Short name T336
Test name
Test status
Simulation time 8415830616 ps
CPU time 7.36 seconds
Started Feb 29 01:04:51 PM PST 24
Finished Feb 29 01:04:58 PM PST 24
Peak memory 202028 kb
Host smart-9536ec02-f641-4789-bbee-9cf52b44334d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69300
4085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.693004085
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.in_trans.1404307353
Short name T285
Test name
Test status
Simulation time 8429018829 ps
CPU time 7.87 seconds
Started Feb 29 01:05:05 PM PST 24
Finished Feb 29 01:05:13 PM PST 24
Peak memory 202192 kb
Host smart-f5aef871-99d2-4173-b81c-4420066cf4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14043
07353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.in_trans.1404307353
Directory /workspace/21.in_trans/latest

Test location /workspace/coverage/default/21.setup_trans_ignored.2658599005
Short name T18
Test name
Test status
Simulation time 8454617729 ps
CPU time 7.95 seconds
Started Feb 29 01:05:04 PM PST 24
Finished Feb 29 01:05:12 PM PST 24
Peak memory 202152 kb
Host smart-78d806d4-28ab-4958-983a-5d1bb88a6203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26585
99005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.setup_trans_ignored.2658599005
Directory /workspace/21.setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1587400318
Short name T253
Test name
Test status
Simulation time 8370184683 ps
CPU time 8.74 seconds
Started Feb 29 01:05:07 PM PST 24
Finished Feb 29 01:05:16 PM PST 24
Peak memory 202356 kb
Host smart-5e41f48d-f564-47c8-aecd-9180c9ed84d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15874
00318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1587400318
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2408805846
Short name T296
Test name
Test status
Simulation time 8450388940 ps
CPU time 7.99 seconds
Started Feb 29 01:05:01 PM PST 24
Finished Feb 29 01:05:09 PM PST 24
Peak memory 202140 kb
Host smart-bffed242-4234-425e-bb12-9a54b5295df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088
05846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2408805846
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2127497665
Short name T321
Test name
Test status
Simulation time 8366848071 ps
CPU time 7.42 seconds
Started Feb 29 01:05:01 PM PST 24
Finished Feb 29 01:05:09 PM PST 24
Peak memory 202084 kb
Host smart-132a017c-3ba9-4fbb-9739-ce03175b1102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21274
97665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2127497665
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.in_trans.459328698
Short name T280
Test name
Test status
Simulation time 8387219569 ps
CPU time 8.93 seconds
Started Feb 29 01:05:03 PM PST 24
Finished Feb 29 01:05:13 PM PST 24
Peak memory 202184 kb
Host smart-cd5b2987-bab8-4967-a5c5-f04c4bc2c691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45932
8698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.in_trans.459328698
Directory /workspace/22.in_trans/latest

Test location /workspace/coverage/default/22.setup_trans_ignored.587415569
Short name T265
Test name
Test status
Simulation time 8361597116 ps
CPU time 8.02 seconds
Started Feb 29 01:05:06 PM PST 24
Finished Feb 29 01:05:15 PM PST 24
Peak memory 202132 kb
Host smart-38cc5f6c-0d13-441d-8234-8126566eadd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58741
5569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.setup_trans_ignored.587415569
Directory /workspace/22.setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.845218342
Short name T30
Test name
Test status
Simulation time 8369796043 ps
CPU time 8.61 seconds
Started Feb 29 01:05:04 PM PST 24
Finished Feb 29 01:05:13 PM PST 24
Peak memory 202044 kb
Host smart-ddf1306b-d91c-4791-b112-0f38a5e740f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84521
8342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.845218342
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1126787382
Short name T199
Test name
Test status
Simulation time 8393336928 ps
CPU time 8.26 seconds
Started Feb 29 01:05:04 PM PST 24
Finished Feb 29 01:05:12 PM PST 24
Peak memory 202120 kb
Host smart-bc1a8a91-9d61-4a7f-9f7e-b3a2fa2fcaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
87382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1126787382
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2333858363
Short name T180
Test name
Test status
Simulation time 8367135311 ps
CPU time 7.62 seconds
Started Feb 29 01:05:04 PM PST 24
Finished Feb 29 01:05:12 PM PST 24
Peak memory 202084 kb
Host smart-11d67a17-c682-47b2-96c5-75901e9d5b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23338
58363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2333858363
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/23.in_trans.4043106274
Short name T13
Test name
Test status
Simulation time 8403900360 ps
CPU time 7.31 seconds
Started Feb 29 01:05:06 PM PST 24
Finished Feb 29 01:05:14 PM PST 24
Peak memory 202132 kb
Host smart-0c4c5d11-3a59-45d5-80d5-13623ee4cca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40431
06274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.in_trans.4043106274
Directory /workspace/23.in_trans/latest

Test location /workspace/coverage/default/23.setup_trans_ignored.1348642881
Short name T217
Test name
Test status
Simulation time 8356792744 ps
CPU time 8.44 seconds
Started Feb 29 01:05:04 PM PST 24
Finished Feb 29 01:05:13 PM PST 24
Peak memory 202192 kb
Host smart-1cefadc3-9736-4be5-accf-4c5bbd2eb4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13486
42881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.setup_trans_ignored.1348642881
Directory /workspace/23.setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.711832362
Short name T287
Test name
Test status
Simulation time 8371417162 ps
CPU time 7.9 seconds
Started Feb 29 01:05:09 PM PST 24
Finished Feb 29 01:05:17 PM PST 24
Peak memory 202220 kb
Host smart-43689558-d0a4-4589-87e3-4e5179b06e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71183
2362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.711832362
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3554859819
Short name T81
Test name
Test status
Simulation time 8421084336 ps
CPU time 8.37 seconds
Started Feb 29 01:05:07 PM PST 24
Finished Feb 29 01:05:16 PM PST 24
Peak memory 202120 kb
Host smart-b57378b7-6cf8-4c12-b373-d09574cfbe09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35548
59819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3554859819
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1863257709
Short name T338
Test name
Test status
Simulation time 8425785238 ps
CPU time 7.21 seconds
Started Feb 29 01:05:11 PM PST 24
Finished Feb 29 01:05:18 PM PST 24
Peak memory 202152 kb
Host smart-9a0b1598-b6bc-428b-8de8-4500693f1620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18632
57709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1863257709
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1173177069
Short name T306
Test name
Test status
Simulation time 8368199983 ps
CPU time 7.1 seconds
Started Feb 29 01:05:10 PM PST 24
Finished Feb 29 01:05:17 PM PST 24
Peak memory 202244 kb
Host smart-b2090eef-8277-43bc-9097-6187820e8253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11731
77069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1173177069
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.in_trans.2079922845
Short name T223
Test name
Test status
Simulation time 8434864535 ps
CPU time 7.19 seconds
Started Feb 29 01:05:10 PM PST 24
Finished Feb 29 01:05:17 PM PST 24
Peak memory 201340 kb
Host smart-b8f8dabf-9bb1-4e11-9d35-30aaac9545ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20799
22845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.in_trans.2079922845
Directory /workspace/24.in_trans/latest

Test location /workspace/coverage/default/24.setup_trans_ignored.676463264
Short name T283
Test name
Test status
Simulation time 8364892692 ps
CPU time 7.5 seconds
Started Feb 29 01:05:07 PM PST 24
Finished Feb 29 01:05:15 PM PST 24
Peak memory 202032 kb
Host smart-17d24397-56f9-42cd-a823-a6edf30f9aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67646
3264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.setup_trans_ignored.676463264
Directory /workspace/24.setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2162348205
Short name T310
Test name
Test status
Simulation time 8367416415 ps
CPU time 7.74 seconds
Started Feb 29 01:05:11 PM PST 24
Finished Feb 29 01:05:19 PM PST 24
Peak memory 202168 kb
Host smart-35882f68-efaa-4782-9e2f-f175d335f930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21623
48205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2162348205
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2803452435
Short name T305
Test name
Test status
Simulation time 8441324357 ps
CPU time 9.86 seconds
Started Feb 29 01:05:06 PM PST 24
Finished Feb 29 01:05:16 PM PST 24
Peak memory 201972 kb
Host smart-b8b398d2-c8d1-4657-9a29-827e581fe56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28034
52435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2803452435
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2670110988
Short name T337
Test name
Test status
Simulation time 8389568039 ps
CPU time 7.39 seconds
Started Feb 29 01:05:06 PM PST 24
Finished Feb 29 01:05:14 PM PST 24
Peak memory 201952 kb
Host smart-e81698c4-989f-48ff-bfb7-49ca6e1ecbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26701
10988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2670110988
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2477831661
Short name T316
Test name
Test status
Simulation time 8369525659 ps
CPU time 7.11 seconds
Started Feb 29 01:05:06 PM PST 24
Finished Feb 29 01:05:13 PM PST 24
Peak memory 202120 kb
Host smart-0599eb95-9e2a-475b-a618-9dc55956c00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24778
31661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2477831661
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.in_trans.1685446944
Short name T209
Test name
Test status
Simulation time 8419571780 ps
CPU time 7.78 seconds
Started Feb 29 01:05:30 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 202152 kb
Host smart-08d12137-8975-4e9e-878f-9bfeb62ba392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16854
46944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.in_trans.1685446944
Directory /workspace/25.in_trans/latest

Test location /workspace/coverage/default/25.setup_trans_ignored.2874153493
Short name T235
Test name
Test status
Simulation time 8362314215 ps
CPU time 7.23 seconds
Started Feb 29 01:05:26 PM PST 24
Finished Feb 29 01:05:35 PM PST 24
Peak memory 202168 kb
Host smart-69408770-fe37-4b31-8d86-6ab3a671319e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28741
53493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.setup_trans_ignored.2874153493
Directory /workspace/25.setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.4112697377
Short name T34
Test name
Test status
Simulation time 8369070084 ps
CPU time 7.24 seconds
Started Feb 29 01:05:27 PM PST 24
Finished Feb 29 01:05:36 PM PST 24
Peak memory 202048 kb
Host smart-782a003f-f209-4dfa-95f8-c1f96b3af6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41126
97377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.4112697377
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.169859125
Short name T311
Test name
Test status
Simulation time 8412128220 ps
CPU time 7.45 seconds
Started Feb 29 01:05:25 PM PST 24
Finished Feb 29 01:05:33 PM PST 24
Peak memory 202152 kb
Host smart-87c39dde-beb6-417f-95b3-828521082644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16985
9125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.169859125
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1687348270
Short name T237
Test name
Test status
Simulation time 8370836828 ps
CPU time 8.58 seconds
Started Feb 29 01:05:28 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 202076 kb
Host smart-9ac8aec5-b400-4172-98a5-44d6d0d9d9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16873
48270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1687348270
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.in_trans.388057400
Short name T23
Test name
Test status
Simulation time 8464227710 ps
CPU time 8.14 seconds
Started Feb 29 01:05:25 PM PST 24
Finished Feb 29 01:05:33 PM PST 24
Peak memory 202160 kb
Host smart-e6b27ccc-a0a5-436a-8390-35395c6018bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38805
7400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.in_trans.388057400
Directory /workspace/26.in_trans/latest

Test location /workspace/coverage/default/26.setup_trans_ignored.3231856940
Short name T204
Test name
Test status
Simulation time 8356334970 ps
CPU time 6.99 seconds
Started Feb 29 01:05:24 PM PST 24
Finished Feb 29 01:05:32 PM PST 24
Peak memory 202156 kb
Host smart-e4b274c0-2a1b-40b2-82d6-5be352976137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32318
56940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.setup_trans_ignored.3231856940
Directory /workspace/26.setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2875183971
Short name T31
Test name
Test status
Simulation time 8372607031 ps
CPU time 7.64 seconds
Started Feb 29 01:05:27 PM PST 24
Finished Feb 29 01:05:37 PM PST 24
Peak memory 202092 kb
Host smart-28a8663a-63ce-4b3e-b419-c4ce3fe1df98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751
83971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2875183971
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2709295448
Short name T108
Test name
Test status
Simulation time 8414564215 ps
CPU time 8.45 seconds
Started Feb 29 01:05:28 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 202152 kb
Host smart-3af2c3ca-185b-4c66-8b4e-b1784c0a97b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27092
95448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2709295448
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3208497803
Short name T268
Test name
Test status
Simulation time 8380172640 ps
CPU time 7.23 seconds
Started Feb 29 01:05:28 PM PST 24
Finished Feb 29 01:05:37 PM PST 24
Peak memory 202216 kb
Host smart-95ca8998-9107-45d0-9a70-fc31f5c93f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32084
97803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3208497803
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.setup_trans_ignored.777730059
Short name T302
Test name
Test status
Simulation time 8370219411 ps
CPU time 6.9 seconds
Started Feb 29 01:05:30 PM PST 24
Finished Feb 29 01:05:37 PM PST 24
Peak memory 202068 kb
Host smart-85b0e9ae-0eb1-426c-825f-dfe431f44e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77773
0059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.setup_trans_ignored.777730059
Directory /workspace/27.setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.229465912
Short name T92
Test name
Test status
Simulation time 8421243418 ps
CPU time 8.68 seconds
Started Feb 29 01:05:27 PM PST 24
Finished Feb 29 01:05:37 PM PST 24
Peak memory 202068 kb
Host smart-61f071ac-8f7a-4021-b41b-eb1e650e1122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22946
5912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.229465912
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3284478958
Short name T317
Test name
Test status
Simulation time 8443280380 ps
CPU time 7.13 seconds
Started Feb 29 01:05:24 PM PST 24
Finished Feb 29 01:05:31 PM PST 24
Peak memory 202136 kb
Host smart-977b8946-72da-40bb-b2da-33c415febef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32844
78958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3284478958
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2012865957
Short name T6
Test name
Test status
Simulation time 8373510275 ps
CPU time 7.11 seconds
Started Feb 29 01:05:26 PM PST 24
Finished Feb 29 01:05:35 PM PST 24
Peak memory 201848 kb
Host smart-b42b8bbf-47d3-418c-8092-97d3569ae05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20128
65957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2012865957
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.in_trans.2147404097
Short name T103
Test name
Test status
Simulation time 8373536029 ps
CPU time 8.04 seconds
Started Feb 29 01:05:29 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 202156 kb
Host smart-f717eeba-34a0-46ac-9170-9c0d66d1a3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21474
04097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.in_trans.2147404097
Directory /workspace/28.in_trans/latest

Test location /workspace/coverage/default/28.setup_trans_ignored.1359395404
Short name T291
Test name
Test status
Simulation time 8366863895 ps
CPU time 7.14 seconds
Started Feb 29 01:05:30 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 202156 kb
Host smart-e197b156-7ef2-4a06-bb53-536c7e63b623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13593
95404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.setup_trans_ignored.1359395404
Directory /workspace/28.setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1140203219
Short name T248
Test name
Test status
Simulation time 8369472720 ps
CPU time 8.99 seconds
Started Feb 29 01:05:31 PM PST 24
Finished Feb 29 01:05:41 PM PST 24
Peak memory 202140 kb
Host smart-fd599c0c-82a3-4009-8a71-c9a17a2aa15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11402
03219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1140203219
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2387002697
Short name T68
Test name
Test status
Simulation time 8402873504 ps
CPU time 8.14 seconds
Started Feb 29 01:05:31 PM PST 24
Finished Feb 29 01:05:40 PM PST 24
Peak memory 202092 kb
Host smart-98bc6805-7fa5-486c-90fd-cd5e95766fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23870
02697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2387002697
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3648406440
Short name T59
Test name
Test status
Simulation time 8449249008 ps
CPU time 7.39 seconds
Started Feb 29 01:05:34 PM PST 24
Finished Feb 29 01:05:41 PM PST 24
Peak memory 202144 kb
Host smart-3fff6a1d-11da-4a74-8b3e-3d7358e9c93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36484
06440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3648406440
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.in_trans.4275362663
Short name T146
Test name
Test status
Simulation time 8386078743 ps
CPU time 7.38 seconds
Started Feb 29 01:05:27 PM PST 24
Finished Feb 29 01:05:35 PM PST 24
Peak memory 202148 kb
Host smart-0754e8b0-6564-4e18-b5ea-51fb92817202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42753
62663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.in_trans.4275362663
Directory /workspace/29.in_trans/latest

Test location /workspace/coverage/default/29.setup_trans_ignored.1429799300
Short name T322
Test name
Test status
Simulation time 8362107733 ps
CPU time 6.99 seconds
Started Feb 29 01:05:26 PM PST 24
Finished Feb 29 01:05:34 PM PST 24
Peak memory 202128 kb
Host smart-78f2186a-94d9-427f-a64e-f80dd47a6207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14297
99300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.setup_trans_ignored.1429799300
Directory /workspace/29.setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1288387848
Short name T201
Test name
Test status
Simulation time 8371928472 ps
CPU time 8.66 seconds
Started Feb 29 01:05:25 PM PST 24
Finished Feb 29 01:05:34 PM PST 24
Peak memory 202160 kb
Host smart-713096be-9e0c-4be2-9e8e-5bc99a938cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12883
87848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1288387848
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.180881910
Short name T188
Test name
Test status
Simulation time 8457715013 ps
CPU time 8.28 seconds
Started Feb 29 01:05:30 PM PST 24
Finished Feb 29 01:05:39 PM PST 24
Peak memory 202144 kb
Host smart-f8a40e92-2d63-4700-8d31-025ba12ce14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18088
1910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.180881910
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2383682111
Short name T281
Test name
Test status
Simulation time 8364726144 ps
CPU time 7.39 seconds
Started Feb 29 01:05:25 PM PST 24
Finished Feb 29 01:05:33 PM PST 24
Peak memory 202168 kb
Host smart-1d59b838-bc35-457c-9adb-06a9b2ef78d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
82111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2383682111
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.setup_trans_ignored.1636839041
Short name T231
Test name
Test status
Simulation time 8358118161 ps
CPU time 7.52 seconds
Started Feb 29 01:04:01 PM PST 24
Finished Feb 29 01:04:09 PM PST 24
Peak memory 202168 kb
Host smart-96b0e16e-50ab-406b-9444-dc378db022e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16368
39041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.setup_trans_ignored.1636839041
Directory /workspace/3.setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3304063880
Short name T178
Test name
Test status
Simulation time 8370046938 ps
CPU time 6.98 seconds
Started Feb 29 01:03:58 PM PST 24
Finished Feb 29 01:04:06 PM PST 24
Peak memory 202144 kb
Host smart-a5d64b2f-0baa-4449-b4e4-115531a30c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040
63880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3304063880
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2927354925
Short name T86
Test name
Test status
Simulation time 8419410817 ps
CPU time 8.59 seconds
Started Feb 29 01:04:00 PM PST 24
Finished Feb 29 01:04:09 PM PST 24
Peak memory 202160 kb
Host smart-ff56a7cf-d375-4401-bdbd-7cc12ca5eef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29273
54925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2927354925
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1118423970
Short name T328
Test name
Test status
Simulation time 8397329084 ps
CPU time 7.52 seconds
Started Feb 29 01:04:01 PM PST 24
Finished Feb 29 01:04:09 PM PST 24
Peak memory 202012 kb
Host smart-090cbb8a-2a12-4b0f-8c90-256b0ebf7906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11184
23970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1118423970
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2435571124
Short name T41
Test name
Test status
Simulation time 98800320 ps
CPU time 0.91 seconds
Started Feb 29 01:03:58 PM PST 24
Finished Feb 29 01:03:59 PM PST 24
Peak memory 216840 kb
Host smart-8e0a9e01-6c2a-469e-9916-40dc9656d379
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2435571124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2435571124
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3065230022
Short name T312
Test name
Test status
Simulation time 8370619455 ps
CPU time 7.42 seconds
Started Feb 29 01:03:58 PM PST 24
Finished Feb 29 01:04:06 PM PST 24
Peak memory 202160 kb
Host smart-eafc2c2d-11f8-4128-ba7f-e445d36478e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30652
30022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3065230022
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.in_trans.820405745
Short name T207
Test name
Test status
Simulation time 8443324517 ps
CPU time 9.59 seconds
Started Feb 29 01:05:30 PM PST 24
Finished Feb 29 01:05:40 PM PST 24
Peak memory 202104 kb
Host smart-df84c486-bdad-4065-92cf-a1fdefe874d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82040
5745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.in_trans.820405745
Directory /workspace/30.in_trans/latest

Test location /workspace/coverage/default/30.setup_trans_ignored.2268578287
Short name T200
Test name
Test status
Simulation time 8357730435 ps
CPU time 7.46 seconds
Started Feb 29 01:05:30 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 202124 kb
Host smart-eade4af1-4d70-44ef-aa57-d1660d1e5791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22685
78287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.setup_trans_ignored.2268578287
Directory /workspace/30.setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1948253829
Short name T292
Test name
Test status
Simulation time 8369639654 ps
CPU time 7.2 seconds
Started Feb 29 01:05:29 PM PST 24
Finished Feb 29 01:05:37 PM PST 24
Peak memory 202156 kb
Host smart-095af58b-eb65-4023-825f-5489ca14dac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19482
53829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1948253829
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3118489610
Short name T94
Test name
Test status
Simulation time 8414295482 ps
CPU time 7.12 seconds
Started Feb 29 01:05:31 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 202176 kb
Host smart-2ae345d8-06c4-4080-954c-5a0794d8e288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31184
89610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3118489610
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3084377607
Short name T25
Test name
Test status
Simulation time 8464188408 ps
CPU time 9.41 seconds
Started Feb 29 01:05:27 PM PST 24
Finished Feb 29 01:05:37 PM PST 24
Peak memory 202188 kb
Host smart-4a9a1115-cbe3-45d6-8465-e979d2960ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30843
77607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3084377607
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_smoke.653668623
Short name T290
Test name
Test status
Simulation time 8388997697 ps
CPU time 7.45 seconds
Started Feb 29 01:05:27 PM PST 24
Finished Feb 29 01:05:36 PM PST 24
Peak memory 202144 kb
Host smart-d9b7c995-8247-4b5a-8810-8ec384166f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65366
8623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.653668623
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.setup_trans_ignored.1716648178
Short name T210
Test name
Test status
Simulation time 8363058085 ps
CPU time 7.22 seconds
Started Feb 29 01:05:43 PM PST 24
Finished Feb 29 01:05:50 PM PST 24
Peak memory 202120 kb
Host smart-c9a27503-48c5-4db8-8dd6-a039ca01ba8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17166
48178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.setup_trans_ignored.1716648178
Directory /workspace/31.setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3195544546
Short name T221
Test name
Test status
Simulation time 8394459694 ps
CPU time 8.56 seconds
Started Feb 29 01:05:44 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202084 kb
Host smart-b29c67ca-15a2-432b-bcf5-407a7c4ef4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31955
44546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3195544546
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1775990066
Short name T177
Test name
Test status
Simulation time 8432151949 ps
CPU time 7 seconds
Started Feb 29 01:05:41 PM PST 24
Finished Feb 29 01:05:48 PM PST 24
Peak memory 202100 kb
Host smart-85eed17d-dea5-4a5d-b6c6-12a3916e41e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17759
90066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1775990066
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1706612785
Short name T96
Test name
Test status
Simulation time 8407104235 ps
CPU time 7.4 seconds
Started Feb 29 01:05:47 PM PST 24
Finished Feb 29 01:05:55 PM PST 24
Peak memory 202144 kb
Host smart-78245873-add5-4681-99cd-fb19b4dc5721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
12785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1706612785
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_smoke.2807094881
Short name T244
Test name
Test status
Simulation time 8380900762 ps
CPU time 6.9 seconds
Started Feb 29 01:05:43 PM PST 24
Finished Feb 29 01:05:50 PM PST 24
Peak memory 202152 kb
Host smart-a4de8cb8-43d5-445f-9f8e-0ac82576ba9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28070
94881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.2807094881
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.in_trans.2644349195
Short name T26
Test name
Test status
Simulation time 8383304549 ps
CPU time 9.81 seconds
Started Feb 29 01:05:46 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 202156 kb
Host smart-fa468df8-661f-4e77-a7fb-8d4160c157ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26443
49195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.in_trans.2644349195
Directory /workspace/32.in_trans/latest

Test location /workspace/coverage/default/32.setup_trans_ignored.1681919303
Short name T294
Test name
Test status
Simulation time 8354917732 ps
CPU time 7.21 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202108 kb
Host smart-30a2bb8a-9fb2-4812-b8dc-54ffab69db8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16819
19303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.setup_trans_ignored.1681919303
Directory /workspace/32.setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1421843953
Short name T149
Test name
Test status
Simulation time 8372343964 ps
CPU time 8.76 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:54 PM PST 24
Peak memory 202168 kb
Host smart-60a5fc5a-3a80-4d3c-9192-6136ffd7f08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14218
43953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1421843953
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.1738191037
Short name T213
Test name
Test status
Simulation time 8401630957 ps
CPU time 7.6 seconds
Started Feb 29 01:05:48 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 202084 kb
Host smart-74fc516d-77f6-4300-800c-96bf4bcabb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17381
91037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1738191037
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_smoke.160626193
Short name T270
Test name
Test status
Simulation time 8370345453 ps
CPU time 7.47 seconds
Started Feb 29 01:05:44 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202124 kb
Host smart-03410f5e-1c9d-4bdc-a704-6159e8e38fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16062
6193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.160626193
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.in_trans.3571224320
Short name T194
Test name
Test status
Simulation time 8414763678 ps
CPU time 7.73 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202128 kb
Host smart-c1dc98aa-afff-4980-9114-0fc506dc00ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
24320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.in_trans.3571224320
Directory /workspace/33.in_trans/latest

Test location /workspace/coverage/default/33.setup_trans_ignored.2657480023
Short name T170
Test name
Test status
Simulation time 8369858445 ps
CPU time 7.46 seconds
Started Feb 29 01:05:44 PM PST 24
Finished Feb 29 01:05:52 PM PST 24
Peak memory 202152 kb
Host smart-ae01f75b-b80e-48f0-8f59-1acd21a35183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26574
80023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.setup_trans_ignored.2657480023
Directory /workspace/33.setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4184541170
Short name T214
Test name
Test status
Simulation time 8368501990 ps
CPU time 7.34 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202144 kb
Host smart-73807980-25ed-45d9-b507-1dd6fa08bd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
41170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4184541170
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2340661322
Short name T88
Test name
Test status
Simulation time 8446292243 ps
CPU time 7.46 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202184 kb
Host smart-9a688f84-8b5f-4627-9eb1-1b7ed17f2a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23406
61322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2340661322
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.109236805
Short name T97
Test name
Test status
Simulation time 8369606953 ps
CPU time 8.51 seconds
Started Feb 29 01:05:44 PM PST 24
Finished Feb 29 01:05:54 PM PST 24
Peak memory 202156 kb
Host smart-564a2e48-c962-461e-a249-a4cb1d622b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10923
6805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.109236805
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3277212493
Short name T257
Test name
Test status
Simulation time 8365541347 ps
CPU time 9.72 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:55 PM PST 24
Peak memory 202152 kb
Host smart-f1543aed-9689-418d-a77f-65d1187e5f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32772
12493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3277212493
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.in_trans.4250048541
Short name T113
Test name
Test status
Simulation time 8397679823 ps
CPU time 8.73 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:55 PM PST 24
Peak memory 202080 kb
Host smart-a3f49e34-d394-48e7-8734-aec4cc0e16e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42500
48541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.in_trans.4250048541
Directory /workspace/34.in_trans/latest

Test location /workspace/coverage/default/34.setup_trans_ignored.2565082200
Short name T140
Test name
Test status
Simulation time 8354013589 ps
CPU time 7.08 seconds
Started Feb 29 01:05:46 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202104 kb
Host smart-b259e39c-e0e0-4869-99ef-486b63f66296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
82200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.setup_trans_ignored.2565082200
Directory /workspace/34.setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2720690053
Short name T314
Test name
Test status
Simulation time 8368240393 ps
CPU time 7.86 seconds
Started Feb 29 01:05:46 PM PST 24
Finished Feb 29 01:05:54 PM PST 24
Peak memory 202072 kb
Host smart-f006ed2a-3749-4a25-aa3b-c14f9956720d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27206
90053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2720690053
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3925333408
Short name T83
Test name
Test status
Simulation time 8392626650 ps
CPU time 8.11 seconds
Started Feb 29 01:05:48 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 202088 kb
Host smart-3ffd8c41-1f95-4202-a2d9-ecd263461558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39253
33408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3925333408
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2132636970
Short name T239
Test name
Test status
Simulation time 8386882551 ps
CPU time 7.08 seconds
Started Feb 29 01:05:44 PM PST 24
Finished Feb 29 01:05:52 PM PST 24
Peak memory 202128 kb
Host smart-cdea4110-520d-4d81-9041-3fc4d9b1a7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21326
36970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2132636970
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2644830572
Short name T262
Test name
Test status
Simulation time 8372180673 ps
CPU time 7.13 seconds
Started Feb 29 01:05:43 PM PST 24
Finished Feb 29 01:05:50 PM PST 24
Peak memory 202020 kb
Host smart-d2f8e051-fd41-4bbb-b74e-f7a6962f38a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26448
30572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2644830572
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.setup_trans_ignored.1390094408
Short name T277
Test name
Test status
Simulation time 8361810693 ps
CPU time 7.72 seconds
Started Feb 29 01:05:47 PM PST 24
Finished Feb 29 01:05:55 PM PST 24
Peak memory 202196 kb
Host smart-e5f4dfc4-338c-4490-96bb-a83292f9f322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13900
94408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.setup_trans_ignored.1390094408
Directory /workspace/35.setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2063863680
Short name T218
Test name
Test status
Simulation time 8375133149 ps
CPU time 7.18 seconds
Started Feb 29 01:05:49 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 202156 kb
Host smart-034af917-c05b-468f-9142-05f3c84e7b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20638
63680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2063863680
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3497203836
Short name T104
Test name
Test status
Simulation time 8452179841 ps
CPU time 7.93 seconds
Started Feb 29 01:05:47 PM PST 24
Finished Feb 29 01:05:55 PM PST 24
Peak memory 202144 kb
Host smart-ea4213e6-dbd8-4dc0-96a1-9ec83beaf0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34972
03836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3497203836
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2187174726
Short name T233
Test name
Test status
Simulation time 8367122949 ps
CPU time 7.6 seconds
Started Feb 29 01:05:44 PM PST 24
Finished Feb 29 01:05:52 PM PST 24
Peak memory 202048 kb
Host smart-c650d4bf-62c2-44c4-9bf7-02d6cc5a5939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21871
74726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2187174726
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.in_trans.3901328272
Short name T12
Test name
Test status
Simulation time 8461730634 ps
CPU time 9.03 seconds
Started Feb 29 01:05:49 PM PST 24
Finished Feb 29 01:05:58 PM PST 24
Peak memory 202104 kb
Host smart-22c86a7d-e22d-493e-a563-a71114c969eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39013
28272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.in_trans.3901328272
Directory /workspace/36.in_trans/latest

Test location /workspace/coverage/default/36.setup_trans_ignored.2482804882
Short name T224
Test name
Test status
Simulation time 8365279202 ps
CPU time 8.78 seconds
Started Feb 29 01:05:48 PM PST 24
Finished Feb 29 01:05:57 PM PST 24
Peak memory 202148 kb
Host smart-672439eb-ebf6-4bb4-b56c-65b16e4e7c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
04882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.setup_trans_ignored.2482804882
Directory /workspace/36.setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3810054638
Short name T219
Test name
Test status
Simulation time 8375598435 ps
CPU time 6.99 seconds
Started Feb 29 01:05:49 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 202160 kb
Host smart-27c7536d-c207-4ad7-b805-6e04a3f01d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100
54638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3810054638
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1841663028
Short name T191
Test name
Test status
Simulation time 8423379951 ps
CPU time 7.03 seconds
Started Feb 29 01:05:53 PM PST 24
Finished Feb 29 01:06:00 PM PST 24
Peak memory 202348 kb
Host smart-ecf37a24-a8a1-4148-8b12-40f7fdcabc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18416
63028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1841663028
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3871030980
Short name T230
Test name
Test status
Simulation time 8373889750 ps
CPU time 7.16 seconds
Started Feb 29 01:05:45 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 202216 kb
Host smart-54e3cb52-5db7-4a74-bd76-1ccf6046a182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38710
30980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3871030980
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.setup_trans_ignored.3268124928
Short name T184
Test name
Test status
Simulation time 8362858385 ps
CPU time 7.89 seconds
Started Feb 29 01:05:48 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 202120 kb
Host smart-f3725bb5-00bb-424a-8d48-47b4e287c242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32681
24928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.setup_trans_ignored.3268124928
Directory /workspace/37.setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2419736062
Short name T307
Test name
Test status
Simulation time 8370041007 ps
CPU time 8.83 seconds
Started Feb 29 01:05:49 PM PST 24
Finished Feb 29 01:05:59 PM PST 24
Peak memory 202184 kb
Host smart-f5c317dc-03b7-4869-a6ee-b87648fdd863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24197
36062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2419736062
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3499125183
Short name T205
Test name
Test status
Simulation time 8386059115 ps
CPU time 7.04 seconds
Started Feb 29 01:05:50 PM PST 24
Finished Feb 29 01:05:57 PM PST 24
Peak memory 202044 kb
Host smart-186a52dc-7c85-45d4-b3f4-6d66a3e71c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34991
25183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3499125183
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3230114264
Short name T151
Test name
Test status
Simulation time 8450873851 ps
CPU time 7.9 seconds
Started Feb 29 01:05:50 PM PST 24
Finished Feb 29 01:05:58 PM PST 24
Peak memory 202152 kb
Host smart-623563b4-f161-49e3-b42b-88334fe877ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32301
14264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3230114264
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2413874332
Short name T187
Test name
Test status
Simulation time 8365954882 ps
CPU time 6.99 seconds
Started Feb 29 01:05:50 PM PST 24
Finished Feb 29 01:05:57 PM PST 24
Peak memory 202100 kb
Host smart-d130555c-8040-4509-b6f4-d48d188ed609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24138
74332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2413874332
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.in_trans.4010771652
Short name T250
Test name
Test status
Simulation time 8398252055 ps
CPU time 6.92 seconds
Started Feb 29 01:05:56 PM PST 24
Finished Feb 29 01:06:03 PM PST 24
Peak memory 202152 kb
Host smart-4812ce79-b573-4ef4-b7a8-861089de2ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40107
71652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.in_trans.4010771652
Directory /workspace/38.in_trans/latest

Test location /workspace/coverage/default/38.setup_trans_ignored.604936091
Short name T238
Test name
Test status
Simulation time 8362534073 ps
CPU time 6.96 seconds
Started Feb 29 01:06:05 PM PST 24
Finished Feb 29 01:06:12 PM PST 24
Peak memory 202152 kb
Host smart-850b9421-6b5f-4c2e-b64a-1c4443fb1389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60493
6091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.setup_trans_ignored.604936091
Directory /workspace/38.setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2042503514
Short name T32
Test name
Test status
Simulation time 8376724841 ps
CPU time 7.06 seconds
Started Feb 29 01:06:02 PM PST 24
Finished Feb 29 01:06:09 PM PST 24
Peak memory 202156 kb
Host smart-c8a15792-d806-4967-a0d6-7919d967597f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20425
03514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2042503514
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1209830391
Short name T16
Test name
Test status
Simulation time 8450405265 ps
CPU time 7.32 seconds
Started Feb 29 01:05:58 PM PST 24
Finished Feb 29 01:06:05 PM PST 24
Peak memory 202200 kb
Host smart-b6f0a589-2274-4e5c-a69f-31c38502fe60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098
30391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1209830391
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1592459242
Short name T332
Test name
Test status
Simulation time 8419575070 ps
CPU time 7.87 seconds
Started Feb 29 01:06:04 PM PST 24
Finished Feb 29 01:06:12 PM PST 24
Peak memory 202152 kb
Host smart-28e09f8b-20a1-48ed-8a08-055ec1a874e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15924
59242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1592459242
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_smoke.984578528
Short name T236
Test name
Test status
Simulation time 8377681312 ps
CPU time 7.04 seconds
Started Feb 29 01:06:00 PM PST 24
Finished Feb 29 01:06:07 PM PST 24
Peak memory 202196 kb
Host smart-d2677c7f-85a1-4b72-a5c6-54131ca4c62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98457
8528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.984578528
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.in_trans.1779267638
Short name T109
Test name
Test status
Simulation time 8423284654 ps
CPU time 8.38 seconds
Started Feb 29 01:05:58 PM PST 24
Finished Feb 29 01:06:07 PM PST 24
Peak memory 202144 kb
Host smart-00b5278c-5f03-4622-95e8-5c7349d34636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17792
67638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.in_trans.1779267638
Directory /workspace/39.in_trans/latest

Test location /workspace/coverage/default/39.setup_trans_ignored.2878077119
Short name T195
Test name
Test status
Simulation time 8360738368 ps
CPU time 7.49 seconds
Started Feb 29 01:06:00 PM PST 24
Finished Feb 29 01:06:07 PM PST 24
Peak memory 202000 kb
Host smart-166d45f4-84ec-402a-bf4f-1f9da1e593fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28780
77119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.setup_trans_ignored.2878077119
Directory /workspace/39.setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.971046634
Short name T252
Test name
Test status
Simulation time 8404041765 ps
CPU time 9.27 seconds
Started Feb 29 01:06:01 PM PST 24
Finished Feb 29 01:06:10 PM PST 24
Peak memory 202148 kb
Host smart-07ce2213-e008-47e0-b48a-52ad4d5c67f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97104
6634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.971046634
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2106863295
Short name T193
Test name
Test status
Simulation time 8437485188 ps
CPU time 8 seconds
Started Feb 29 01:06:00 PM PST 24
Finished Feb 29 01:06:09 PM PST 24
Peak memory 202116 kb
Host smart-8be4e16b-0527-4787-9751-67326292f906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21068
63295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2106863295
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_smoke.925981697
Short name T56
Test name
Test status
Simulation time 8367802203 ps
CPU time 7.74 seconds
Started Feb 29 01:06:08 PM PST 24
Finished Feb 29 01:06:15 PM PST 24
Peak memory 202176 kb
Host smart-573af442-db4b-4571-b97b-868790605406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92598
1697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.925981697
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.setup_trans_ignored.2904926803
Short name T272
Test name
Test status
Simulation time 8356239546 ps
CPU time 7.49 seconds
Started Feb 29 01:04:01 PM PST 24
Finished Feb 29 01:04:09 PM PST 24
Peak memory 202128 kb
Host smart-ea95dd6c-1721-49ee-8cc2-2a897fbfc5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
26803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.setup_trans_ignored.2904926803
Directory /workspace/4.setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1750227834
Short name T228
Test name
Test status
Simulation time 8381242707 ps
CPU time 9.17 seconds
Started Feb 29 01:04:00 PM PST 24
Finished Feb 29 01:04:09 PM PST 24
Peak memory 202184 kb
Host smart-cc1c513e-a5c4-49db-a860-a9aa9efdb37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17502
27834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1750227834
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2079018038
Short name T70
Test name
Test status
Simulation time 8412544151 ps
CPU time 8.79 seconds
Started Feb 29 01:03:59 PM PST 24
Finished Feb 29 01:04:08 PM PST 24
Peak memory 202152 kb
Host smart-052aac94-8d10-4b91-a643-5c6d3b7f9f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20790
18038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2079018038
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3753413097
Short name T315
Test name
Test status
Simulation time 8452268720 ps
CPU time 7.93 seconds
Started Feb 29 01:04:02 PM PST 24
Finished Feb 29 01:04:10 PM PST 24
Peak memory 202148 kb
Host smart-1ba008b9-d83a-485c-8e28-74a644827cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37534
13097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3753413097
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1443662894
Short name T55
Test name
Test status
Simulation time 319398504 ps
CPU time 1.14 seconds
Started Feb 29 01:03:59 PM PST 24
Finished Feb 29 01:04:01 PM PST 24
Peak memory 217912 kb
Host smart-804ea2fe-3db3-438c-a08c-1b69771f7852
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1443662894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1443662894
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_smoke.331531019
Short name T323
Test name
Test status
Simulation time 8398722961 ps
CPU time 7.51 seconds
Started Feb 29 01:03:59 PM PST 24
Finished Feb 29 01:04:07 PM PST 24
Peak memory 202164 kb
Host smart-3b9c30a5-a941-40ab-8bd0-1a80832d5d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33153
1019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.331531019
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.in_trans.137284993
Short name T65
Test name
Test status
Simulation time 8421303184 ps
CPU time 7.32 seconds
Started Feb 29 01:06:03 PM PST 24
Finished Feb 29 01:06:10 PM PST 24
Peak memory 202192 kb
Host smart-d263a8c6-5985-4417-957e-2afea8a2f3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13728
4993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.in_trans.137284993
Directory /workspace/40.in_trans/latest

Test location /workspace/coverage/default/40.setup_trans_ignored.2848163696
Short name T19
Test name
Test status
Simulation time 8367525072 ps
CPU time 8.06 seconds
Started Feb 29 01:06:02 PM PST 24
Finished Feb 29 01:06:10 PM PST 24
Peak memory 202100 kb
Host smart-70705b2a-d0fc-4096-b8f6-2aeada7c0cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28481
63696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.setup_trans_ignored.2848163696
Directory /workspace/40.setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3908790452
Short name T308
Test name
Test status
Simulation time 8374449282 ps
CPU time 7.43 seconds
Started Feb 29 01:06:07 PM PST 24
Finished Feb 29 01:06:15 PM PST 24
Peak memory 202180 kb
Host smart-f7b07c12-02bb-4b68-854b-83055ac7562d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39087
90452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3908790452
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2108700814
Short name T72
Test name
Test status
Simulation time 8414468521 ps
CPU time 7.66 seconds
Started Feb 29 01:06:05 PM PST 24
Finished Feb 29 01:06:12 PM PST 24
Peak memory 202168 kb
Host smart-eb5d8e6a-8be9-4577-8977-b2f468badf6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21087
00814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2108700814
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2869977494
Short name T105
Test name
Test status
Simulation time 8379663048 ps
CPU time 8.26 seconds
Started Feb 29 01:06:03 PM PST 24
Finished Feb 29 01:06:11 PM PST 24
Peak memory 202308 kb
Host smart-746f7904-8581-4408-a44d-2f0b840a00c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
77494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2869977494
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2788192357
Short name T196
Test name
Test status
Simulation time 8371651198 ps
CPU time 7.33 seconds
Started Feb 29 01:05:56 PM PST 24
Finished Feb 29 01:06:04 PM PST 24
Peak memory 202152 kb
Host smart-beb7203c-8458-432f-ad7a-1566488006ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
92357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2788192357
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.setup_trans_ignored.2306664943
Short name T271
Test name
Test status
Simulation time 8361426603 ps
CPU time 7.88 seconds
Started Feb 29 01:06:08 PM PST 24
Finished Feb 29 01:06:15 PM PST 24
Peak memory 202180 kb
Host smart-84c68f14-0a9d-41ae-be59-5d3fefbfd628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23066
64943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.setup_trans_ignored.2306664943
Directory /workspace/41.setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.4170168581
Short name T8
Test name
Test status
Simulation time 8426207808 ps
CPU time 7.23 seconds
Started Feb 29 01:06:07 PM PST 24
Finished Feb 29 01:06:14 PM PST 24
Peak memory 202132 kb
Host smart-d4fc1a5e-2cff-4b42-9569-efb850851a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701
68581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.4170168581
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.941683185
Short name T275
Test name
Test status
Simulation time 8440521680 ps
CPU time 9.17 seconds
Started Feb 29 01:06:06 PM PST 24
Finished Feb 29 01:06:15 PM PST 24
Peak memory 202096 kb
Host smart-2916d77d-f465-4cdc-a286-9943597d9376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94168
3185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.941683185
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2095079778
Short name T57
Test name
Test status
Simulation time 8369537532 ps
CPU time 8.62 seconds
Started Feb 29 01:06:05 PM PST 24
Finished Feb 29 01:06:13 PM PST 24
Peak memory 202152 kb
Host smart-75e88940-7c34-4a74-a191-6fa9e3cd4cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
79778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2095079778
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.in_trans.433856770
Short name T298
Test name
Test status
Simulation time 8470442715 ps
CPU time 7.92 seconds
Started Feb 29 01:06:02 PM PST 24
Finished Feb 29 01:06:10 PM PST 24
Peak memory 202140 kb
Host smart-1db62a85-9fff-458b-83b6-9a2d0bafdb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43385
6770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.in_trans.433856770
Directory /workspace/42.in_trans/latest

Test location /workspace/coverage/default/42.setup_trans_ignored.1351216029
Short name T208
Test name
Test status
Simulation time 8358140987 ps
CPU time 7.13 seconds
Started Feb 29 01:05:59 PM PST 24
Finished Feb 29 01:06:06 PM PST 24
Peak memory 202112 kb
Host smart-0f895744-19e0-403a-a6b6-1118f57d074b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13512
16029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.setup_trans_ignored.1351216029
Directory /workspace/42.setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1575370395
Short name T215
Test name
Test status
Simulation time 8393759081 ps
CPU time 7.19 seconds
Started Feb 29 01:06:06 PM PST 24
Finished Feb 29 01:06:13 PM PST 24
Peak memory 202116 kb
Host smart-a16eedeb-f47b-4414-b63d-a49ff31b21c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15753
70395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1575370395
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3110162071
Short name T246
Test name
Test status
Simulation time 8400743902 ps
CPU time 7.11 seconds
Started Feb 29 01:06:01 PM PST 24
Finished Feb 29 01:06:08 PM PST 24
Peak memory 202000 kb
Host smart-be57f70b-c869-4bf6-b954-22b091ac8bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31101
62071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3110162071
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1979610422
Short name T301
Test name
Test status
Simulation time 8376897251 ps
CPU time 6.92 seconds
Started Feb 29 01:06:12 PM PST 24
Finished Feb 29 01:06:19 PM PST 24
Peak memory 202132 kb
Host smart-c6e48f4c-652b-4beb-b813-1c3b0d42e205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19796
10422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1979610422
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.in_trans.3501273362
Short name T289
Test name
Test status
Simulation time 8412023280 ps
CPU time 7.45 seconds
Started Feb 29 01:06:00 PM PST 24
Finished Feb 29 01:06:08 PM PST 24
Peak memory 202064 kb
Host smart-20dc2e16-5708-4b87-a9eb-4805a88511bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35012
73362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.in_trans.3501273362
Directory /workspace/43.in_trans/latest

Test location /workspace/coverage/default/43.setup_trans_ignored.349536812
Short name T333
Test name
Test status
Simulation time 8359778862 ps
CPU time 7.79 seconds
Started Feb 29 01:06:01 PM PST 24
Finished Feb 29 01:06:09 PM PST 24
Peak memory 202188 kb
Host smart-e7794c36-9bb3-4eb3-a436-0ae8421304b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34953
6812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.setup_trans_ignored.349536812
Directory /workspace/43.setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.801606473
Short name T85
Test name
Test status
Simulation time 8414375829 ps
CPU time 9.29 seconds
Started Feb 29 01:06:06 PM PST 24
Finished Feb 29 01:06:15 PM PST 24
Peak memory 202116 kb
Host smart-1a496ab9-de38-427f-a625-591c59d0dfe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80160
6473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.801606473
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3654375420
Short name T179
Test name
Test status
Simulation time 8419395871 ps
CPU time 6.99 seconds
Started Feb 29 01:06:06 PM PST 24
Finished Feb 29 01:06:13 PM PST 24
Peak memory 202100 kb
Host smart-4d1ccb45-100c-4c43-b8d8-cebfd9aa85ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36543
75420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3654375420
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2937859843
Short name T63
Test name
Test status
Simulation time 8392792559 ps
CPU time 6.85 seconds
Started Feb 29 01:06:02 PM PST 24
Finished Feb 29 01:06:09 PM PST 24
Peak memory 202116 kb
Host smart-9272aec5-edfa-45cc-92cd-a71bbf0b4912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29378
59843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2937859843
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.in_trans.242943032
Short name T197
Test name
Test status
Simulation time 8384796615 ps
CPU time 7.86 seconds
Started Feb 29 01:06:17 PM PST 24
Finished Feb 29 01:06:25 PM PST 24
Peak memory 202132 kb
Host smart-a5c3d4ca-914b-49e2-950d-a7f6bb401aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24294
3032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.in_trans.242943032
Directory /workspace/44.in_trans/latest

Test location /workspace/coverage/default/44.setup_trans_ignored.1316040998
Short name T144
Test name
Test status
Simulation time 8360804704 ps
CPU time 8.42 seconds
Started Feb 29 01:06:16 PM PST 24
Finished Feb 29 01:06:25 PM PST 24
Peak memory 202152 kb
Host smart-84d6bb86-bbcc-4bfc-9660-442e99e32d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13160
40998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.setup_trans_ignored.1316040998
Directory /workspace/44.setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.829636703
Short name T247
Test name
Test status
Simulation time 8372878539 ps
CPU time 7.19 seconds
Started Feb 29 01:06:20 PM PST 24
Finished Feb 29 01:06:27 PM PST 24
Peak memory 202092 kb
Host smart-8f1cd05d-53d6-4da3-a93b-672b8a50e40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82963
6703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.829636703
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2014134999
Short name T80
Test name
Test status
Simulation time 8404978320 ps
CPU time 9.45 seconds
Started Feb 29 01:06:15 PM PST 24
Finished Feb 29 01:06:25 PM PST 24
Peak memory 202168 kb
Host smart-97635d1b-cfd5-496e-b8c0-9fa59a73c0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20141
34999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2014134999
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.4109754074
Short name T115
Test name
Test status
Simulation time 8408372572 ps
CPU time 8.77 seconds
Started Feb 29 01:06:12 PM PST 24
Finished Feb 29 01:06:21 PM PST 24
Peak memory 202072 kb
Host smart-4aa4ed49-b168-4558-9314-634c8eb042a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41097
54074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.4109754074
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3186351642
Short name T325
Test name
Test status
Simulation time 8371957681 ps
CPU time 7.68 seconds
Started Feb 29 01:06:19 PM PST 24
Finished Feb 29 01:06:27 PM PST 24
Peak memory 202148 kb
Host smart-64aca9c2-164d-449f-89d9-155bc04305fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31863
51642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3186351642
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.in_trans.765582902
Short name T101
Test name
Test status
Simulation time 8429824708 ps
CPU time 7.85 seconds
Started Feb 29 01:06:15 PM PST 24
Finished Feb 29 01:06:23 PM PST 24
Peak memory 202136 kb
Host smart-33ff8bf6-af9a-4532-a53b-399826f29cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76558
2902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.in_trans.765582902
Directory /workspace/45.in_trans/latest

Test location /workspace/coverage/default/45.setup_trans_ignored.223036223
Short name T222
Test name
Test status
Simulation time 8356270951 ps
CPU time 7.01 seconds
Started Feb 29 01:06:20 PM PST 24
Finished Feb 29 01:06:28 PM PST 24
Peak memory 201892 kb
Host smart-82a00530-c815-4caf-8ac9-c8d6e7c80ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22303
6223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.setup_trans_ignored.223036223
Directory /workspace/45.setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2285411197
Short name T33
Test name
Test status
Simulation time 8365229088 ps
CPU time 7.15 seconds
Started Feb 29 01:06:18 PM PST 24
Finished Feb 29 01:06:26 PM PST 24
Peak memory 202148 kb
Host smart-7a0f84c0-4084-495d-8c31-2c1a951a98b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22854
11197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2285411197
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.4248782267
Short name T76
Test name
Test status
Simulation time 8393849668 ps
CPU time 7.4 seconds
Started Feb 29 01:06:19 PM PST 24
Finished Feb 29 01:06:27 PM PST 24
Peak memory 202064 kb
Host smart-045e080f-6776-4b79-8d50-380cfcee43cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
82267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.4248782267
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1272795357
Short name T274
Test name
Test status
Simulation time 8406612774 ps
CPU time 8.1 seconds
Started Feb 29 01:06:20 PM PST 24
Finished Feb 29 01:06:29 PM PST 24
Peak memory 202152 kb
Host smart-da43d39f-486d-4796-8a71-636e6f090514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12727
95357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1272795357
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.in_trans.4236063282
Short name T186
Test name
Test status
Simulation time 8453786123 ps
CPU time 8.02 seconds
Started Feb 29 01:06:20 PM PST 24
Finished Feb 29 01:06:28 PM PST 24
Peak memory 202192 kb
Host smart-d68d0056-06d1-442b-b524-79444f736156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42360
63282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.in_trans.4236063282
Directory /workspace/46.in_trans/latest

Test location /workspace/coverage/default/46.setup_trans_ignored.3975496434
Short name T278
Test name
Test status
Simulation time 8375566610 ps
CPU time 7.16 seconds
Started Feb 29 01:06:16 PM PST 24
Finished Feb 29 01:06:24 PM PST 24
Peak memory 202380 kb
Host smart-3d381453-d97c-4cc6-9365-b101f50cd0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
96434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.setup_trans_ignored.3975496434
Directory /workspace/46.setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1061847825
Short name T183
Test name
Test status
Simulation time 8458017048 ps
CPU time 7.74 seconds
Started Feb 29 01:06:18 PM PST 24
Finished Feb 29 01:06:26 PM PST 24
Peak memory 202148 kb
Host smart-85034715-ea54-4acd-b2ad-a98e92936dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618
47825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1061847825
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3439965142
Short name T61
Test name
Test status
Simulation time 8455015072 ps
CPU time 7.17 seconds
Started Feb 29 01:06:15 PM PST 24
Finished Feb 29 01:06:23 PM PST 24
Peak memory 202128 kb
Host smart-579085c8-cb86-4193-8c97-7af6d79af20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
65142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3439965142
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.setup_trans_ignored.1392650998
Short name T212
Test name
Test status
Simulation time 8362880877 ps
CPU time 7.5 seconds
Started Feb 29 01:06:17 PM PST 24
Finished Feb 29 01:06:24 PM PST 24
Peak memory 202072 kb
Host smart-78d61bc7-5545-4d21-9476-ea1deb352807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13926
50998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.setup_trans_ignored.1392650998
Directory /workspace/47.setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3979354940
Short name T1
Test name
Test status
Simulation time 8371110316 ps
CPU time 7.18 seconds
Started Feb 29 01:06:19 PM PST 24
Finished Feb 29 01:06:26 PM PST 24
Peak memory 202116 kb
Host smart-20087dae-410f-453e-a3e5-1223b559b1a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39793
54940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3979354940
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3869603952
Short name T90
Test name
Test status
Simulation time 8447479514 ps
CPU time 10.34 seconds
Started Feb 29 01:06:19 PM PST 24
Finished Feb 29 01:06:30 PM PST 24
Peak memory 201552 kb
Host smart-cfc7ec44-3c5b-4380-ac01-92739e3cc82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696
03952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3869603952
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.519371880
Short name T216
Test name
Test status
Simulation time 8424059767 ps
CPU time 7.32 seconds
Started Feb 29 01:06:23 PM PST 24
Finished Feb 29 01:06:31 PM PST 24
Peak memory 202092 kb
Host smart-34438ab5-ca8a-4738-80ec-f7a4e1a4a802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51937
1880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.519371880
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2694887255
Short name T331
Test name
Test status
Simulation time 8383902493 ps
CPU time 7.62 seconds
Started Feb 29 01:06:16 PM PST 24
Finished Feb 29 01:06:24 PM PST 24
Peak memory 202132 kb
Host smart-5c6480bf-bd94-4881-ad8c-e41e0d235c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
87255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2694887255
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.setup_trans_ignored.652410403
Short name T203
Test name
Test status
Simulation time 8361934388 ps
CPU time 8.32 seconds
Started Feb 29 01:06:31 PM PST 24
Finished Feb 29 01:06:39 PM PST 24
Peak memory 202216 kb
Host smart-5a019482-4042-4036-a2e5-f7138bef1cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65241
0403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.setup_trans_ignored.652410403
Directory /workspace/48.setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.220421857
Short name T303
Test name
Test status
Simulation time 8370651711 ps
CPU time 8.47 seconds
Started Feb 29 01:06:35 PM PST 24
Finished Feb 29 01:06:44 PM PST 24
Peak memory 202092 kb
Host smart-9fad15df-e3fe-440a-a8f1-784f076588c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22042
1857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.220421857
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2353394086
Short name T74
Test name
Test status
Simulation time 8442540587 ps
CPU time 7.4 seconds
Started Feb 29 01:06:35 PM PST 24
Finished Feb 29 01:06:43 PM PST 24
Peak memory 202120 kb
Host smart-8210a96b-44e8-44a4-9724-69c5b0d5beaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23533
94086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2353394086
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.630908758
Short name T148
Test name
Test status
Simulation time 8427683966 ps
CPU time 8.01 seconds
Started Feb 29 01:06:35 PM PST 24
Finished Feb 29 01:06:43 PM PST 24
Peak memory 202148 kb
Host smart-dd2aa429-8c04-4d74-82a3-08df94567748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63090
8758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.630908758
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1227312710
Short name T330
Test name
Test status
Simulation time 8371213716 ps
CPU time 8.37 seconds
Started Feb 29 01:06:39 PM PST 24
Finished Feb 29 01:06:48 PM PST 24
Peak memory 202024 kb
Host smart-21ad5d4d-cfbc-401b-99f5-d884c6affc77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12273
12710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1227312710
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.in_trans.4227404704
Short name T114
Test name
Test status
Simulation time 8401793859 ps
CPU time 7.21 seconds
Started Feb 29 01:06:37 PM PST 24
Finished Feb 29 01:06:44 PM PST 24
Peak memory 202152 kb
Host smart-b4291e99-7eec-4032-96b3-4f598434e134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
04704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.in_trans.4227404704
Directory /workspace/49.in_trans/latest

Test location /workspace/coverage/default/49.setup_trans_ignored.493179932
Short name T243
Test name
Test status
Simulation time 8355185618 ps
CPU time 7.61 seconds
Started Feb 29 01:06:33 PM PST 24
Finished Feb 29 01:06:41 PM PST 24
Peak memory 202144 kb
Host smart-0ac8ce95-8523-436f-8ef3-21c39250a489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49317
9932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.setup_trans_ignored.493179932
Directory /workspace/49.setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.647350583
Short name T313
Test name
Test status
Simulation time 8385294260 ps
CPU time 7.73 seconds
Started Feb 29 01:06:36 PM PST 24
Finished Feb 29 01:06:44 PM PST 24
Peak memory 202148 kb
Host smart-6a7cfd8a-0ba7-4fe1-aa74-d0f7e1fd04a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64735
0583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.647350583
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.995857721
Short name T211
Test name
Test status
Simulation time 8423440176 ps
CPU time 7.62 seconds
Started Feb 29 01:06:34 PM PST 24
Finished Feb 29 01:06:42 PM PST 24
Peak memory 202060 kb
Host smart-cda6c71f-abaf-4855-b18a-3092df0e9edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99585
7721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.995857721
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3735853885
Short name T172
Test name
Test status
Simulation time 8393161595 ps
CPU time 8.15 seconds
Started Feb 29 01:06:33 PM PST 24
Finished Feb 29 01:06:42 PM PST 24
Peak memory 202216 kb
Host smart-b9a9777a-8019-4886-a534-2af463a53c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37358
53885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3735853885
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3851576417
Short name T241
Test name
Test status
Simulation time 8367559399 ps
CPU time 7.03 seconds
Started Feb 29 01:06:32 PM PST 24
Finished Feb 29 01:06:40 PM PST 24
Peak memory 202168 kb
Host smart-561997e1-fda0-4896-a246-194c22651cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38515
76417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3851576417
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.in_trans.3547894199
Short name T181
Test name
Test status
Simulation time 8500516733 ps
CPU time 7.11 seconds
Started Feb 29 01:04:01 PM PST 24
Finished Feb 29 01:04:09 PM PST 24
Peak memory 202144 kb
Host smart-0dc46cb5-5b49-4b58-81a2-2a1aedd7e680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35478
94199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.in_trans.3547894199
Directory /workspace/5.in_trans/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.482572618
Short name T256
Test name
Test status
Simulation time 8367622004 ps
CPU time 7.74 seconds
Started Feb 29 01:03:59 PM PST 24
Finished Feb 29 01:04:07 PM PST 24
Peak memory 202076 kb
Host smart-8392ada3-7508-461b-9f05-9f9d0d92a030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48257
2618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.482572618
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.4293832211
Short name T79
Test name
Test status
Simulation time 8410464289 ps
CPU time 7.73 seconds
Started Feb 29 01:04:00 PM PST 24
Finished Feb 29 01:04:09 PM PST 24
Peak memory 202356 kb
Host smart-d1203490-1b8a-4fe8-88c6-49483aea438e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938
32211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.4293832211
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_smoke.4180088682
Short name T192
Test name
Test status
Simulation time 8373772837 ps
CPU time 7.64 seconds
Started Feb 29 01:03:59 PM PST 24
Finished Feb 29 01:04:08 PM PST 24
Peak memory 202072 kb
Host smart-a75c61d4-d33d-4979-b226-443ef5d54ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41800
88682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.4180088682
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.in_trans.1702244758
Short name T100
Test name
Test status
Simulation time 8387795089 ps
CPU time 7.16 seconds
Started Feb 29 01:04:12 PM PST 24
Finished Feb 29 01:04:19 PM PST 24
Peak memory 202144 kb
Host smart-33950311-00fd-4e46-bbad-cfacfbfacd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17022
44758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.in_trans.1702244758
Directory /workspace/6.in_trans/latest

Test location /workspace/coverage/default/6.setup_trans_ignored.327270309
Short name T326
Test name
Test status
Simulation time 8366779912 ps
CPU time 7.3 seconds
Started Feb 29 01:04:11 PM PST 24
Finished Feb 29 01:04:19 PM PST 24
Peak memory 202120 kb
Host smart-84a03049-c49a-418c-be10-2ecbb6c0f1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32727
0309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.setup_trans_ignored.327270309
Directory /workspace/6.setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.4278186577
Short name T185
Test name
Test status
Simulation time 8375348935 ps
CPU time 8.29 seconds
Started Feb 29 01:04:12 PM PST 24
Finished Feb 29 01:04:21 PM PST 24
Peak memory 202200 kb
Host smart-6efaef89-dd1e-4589-9b60-5041fe95c9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42781
86577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.4278186577
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.987078156
Short name T66
Test name
Test status
Simulation time 8453746779 ps
CPU time 7.85 seconds
Started Feb 29 01:04:14 PM PST 24
Finished Feb 29 01:04:23 PM PST 24
Peak memory 202068 kb
Host smart-9c242144-0fc3-4484-89f6-1a1f9124236e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98707
8156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.987078156
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3596057120
Short name T22
Test name
Test status
Simulation time 8556795399 ps
CPU time 8.31 seconds
Started Feb 29 01:04:13 PM PST 24
Finished Feb 29 01:04:22 PM PST 24
Peak memory 202112 kb
Host smart-432c2073-2fbe-430b-84b4-aabe2dc8f147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35960
57120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3596057120
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3157899828
Short name T62
Test name
Test status
Simulation time 8375710776 ps
CPU time 7.3 seconds
Started Feb 29 01:04:14 PM PST 24
Finished Feb 29 01:04:22 PM PST 24
Peak memory 202068 kb
Host smart-a02d3096-d672-41d7-94b0-5b6c1e43064b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31578
99828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3157899828
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.in_trans.205985838
Short name T118
Test name
Test status
Simulation time 8430888451 ps
CPU time 7.5 seconds
Started Feb 29 01:04:15 PM PST 24
Finished Feb 29 01:04:23 PM PST 24
Peak memory 202128 kb
Host smart-2b912bab-f64c-4997-b82d-c4e650fb1adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20598
5838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.in_trans.205985838
Directory /workspace/7.in_trans/latest

Test location /workspace/coverage/default/7.setup_trans_ignored.3259865686
Short name T206
Test name
Test status
Simulation time 8363251894 ps
CPU time 7.69 seconds
Started Feb 29 01:04:13 PM PST 24
Finished Feb 29 01:04:21 PM PST 24
Peak memory 201976 kb
Host smart-70e01763-cecd-4d2f-839b-f40a4eb0ba62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32598
65686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.setup_trans_ignored.3259865686
Directory /workspace/7.setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.4153155759
Short name T245
Test name
Test status
Simulation time 8372191160 ps
CPU time 9.56 seconds
Started Feb 29 01:04:13 PM PST 24
Finished Feb 29 01:04:23 PM PST 24
Peak memory 202044 kb
Host smart-f262efcd-155e-4dfa-8192-00457e797cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41531
55759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.4153155759
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1733719448
Short name T153
Test name
Test status
Simulation time 8409215888 ps
CPU time 7.52 seconds
Started Feb 29 01:04:14 PM PST 24
Finished Feb 29 01:04:23 PM PST 24
Peak memory 202168 kb
Host smart-0a37f68b-480d-4379-9e30-4b6783cd8b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17337
19448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1733719448
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1391190019
Short name T27
Test name
Test status
Simulation time 8457428754 ps
CPU time 7.57 seconds
Started Feb 29 01:04:11 PM PST 24
Finished Feb 29 01:04:18 PM PST 24
Peak memory 202148 kb
Host smart-e9dcba4c-c5af-4325-9454-eddb39caa915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911
90019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1391190019
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1686918593
Short name T17
Test name
Test status
Simulation time 8401057225 ps
CPU time 7.89 seconds
Started Feb 29 01:04:10 PM PST 24
Finished Feb 29 01:04:18 PM PST 24
Peak memory 202224 kb
Host smart-d968bb31-6fe6-4a9d-95e9-8b1d1dc946d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
18593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1686918593
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.in_trans.3382134676
Short name T21
Test name
Test status
Simulation time 8456693212 ps
CPU time 8.07 seconds
Started Feb 29 01:04:23 PM PST 24
Finished Feb 29 01:04:31 PM PST 24
Peak memory 202156 kb
Host smart-9495c121-6127-4d58-a625-7201e5f2545d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33821
34676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.in_trans.3382134676
Directory /workspace/8.in_trans/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.931064701
Short name T242
Test name
Test status
Simulation time 8371238743 ps
CPU time 6.81 seconds
Started Feb 29 01:04:14 PM PST 24
Finished Feb 29 01:04:21 PM PST 24
Peak memory 202372 kb
Host smart-25e19130-4784-4910-a252-95394fa12ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93106
4701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.931064701
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3882065129
Short name T11
Test name
Test status
Simulation time 8395104196 ps
CPU time 7.4 seconds
Started Feb 29 01:04:15 PM PST 24
Finished Feb 29 01:04:23 PM PST 24
Peak memory 202148 kb
Host smart-d07441ec-7c2a-4288-9c61-71fa3f2ab18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
65129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3882065129
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2733033477
Short name T288
Test name
Test status
Simulation time 8412318662 ps
CPU time 7.31 seconds
Started Feb 29 01:04:13 PM PST 24
Finished Feb 29 01:04:20 PM PST 24
Peak memory 202148 kb
Host smart-1861d1e4-5b0c-4957-974d-eb0d59429e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27330
33477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2733033477
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3717835275
Short name T2
Test name
Test status
Simulation time 8373788035 ps
CPU time 7.39 seconds
Started Feb 29 01:04:14 PM PST 24
Finished Feb 29 01:04:22 PM PST 24
Peak memory 202112 kb
Host smart-d5079431-551f-431e-9fbe-b9945a43a3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37178
35275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3717835275
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.in_trans.1294775409
Short name T111
Test name
Test status
Simulation time 8394848726 ps
CPU time 9.54 seconds
Started Feb 29 01:04:15 PM PST 24
Finished Feb 29 01:04:25 PM PST 24
Peak memory 202156 kb
Host smart-41faebec-a83a-4fb1-a076-c50963695a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12947
75409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.in_trans.1294775409
Directory /workspace/9.in_trans/latest

Test location /workspace/coverage/default/9.setup_trans_ignored.1401630906
Short name T267
Test name
Test status
Simulation time 8379087014 ps
CPU time 6.98 seconds
Started Feb 29 01:04:16 PM PST 24
Finished Feb 29 01:04:24 PM PST 24
Peak memory 202164 kb
Host smart-3eadcd14-9a46-47d8-ac50-3660f542581c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14016
30906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.setup_trans_ignored.1401630906
Directory /workspace/9.setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3029977540
Short name T189
Test name
Test status
Simulation time 8376856127 ps
CPU time 8.32 seconds
Started Feb 29 01:04:13 PM PST 24
Finished Feb 29 01:04:22 PM PST 24
Peak memory 202088 kb
Host smart-0cc39ae9-7460-433b-927a-b2c489af6283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30299
77540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3029977540
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1391200325
Short name T273
Test name
Test status
Simulation time 8424571028 ps
CPU time 7.33 seconds
Started Feb 29 01:04:14 PM PST 24
Finished Feb 29 01:04:22 PM PST 24
Peak memory 202148 kb
Host smart-17364f71-b65c-4a3b-af5f-71de333260e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13912
00325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1391200325
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1525867036
Short name T318
Test name
Test status
Simulation time 8419353017 ps
CPU time 7.28 seconds
Started Feb 29 01:04:14 PM PST 24
Finished Feb 29 01:04:22 PM PST 24
Peak memory 202140 kb
Host smart-ba4160b1-b2e3-4230-b96f-1f1344a84803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15258
67036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1525867036
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2987946311
Short name T251
Test name
Test status
Simulation time 8408910086 ps
CPU time 6.82 seconds
Started Feb 29 01:04:12 PM PST 24
Finished Feb 29 01:04:19 PM PST 24
Peak memory 202132 kb
Host smart-da089a79-33c4-44c3-9b9f-234a2a2f7d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29879
46311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2987946311
Directory /workspace/9.usbdev_smoke/latest
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