Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.44 95.94 86.92 96.73 45.31 93.92 97.36 53.87


Total test records in report: 439
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T312 /workspace/coverage/default/32.usbdev_av_buffer.2699440592 Mar 03 02:24:22 PM PST 24 Mar 03 02:24:31 PM PST 24 8375542710 ps
T313 /workspace/coverage/default/6.usbdev_fifo_rst.2447405429 Mar 03 02:23:19 PM PST 24 Mar 03 02:23:20 PM PST 24 68660063 ps
T314 /workspace/coverage/default/23.usbdev_smoke.3956268018 Mar 03 02:24:06 PM PST 24 Mar 03 02:24:15 PM PST 24 8415460049 ps
T315 /workspace/coverage/default/41.setup_trans_ignored.1254154925 Mar 03 02:24:45 PM PST 24 Mar 03 02:24:52 PM PST 24 8397705000 ps
T316 /workspace/coverage/default/38.usbdev_pkt_sent.3335116911 Mar 03 02:24:29 PM PST 24 Mar 03 02:24:36 PM PST 24 8414470734 ps
T317 /workspace/coverage/default/44.in_trans.3891825231 Mar 03 02:24:53 PM PST 24 Mar 03 02:25:01 PM PST 24 8431415437 ps
T318 /workspace/coverage/default/5.usbdev_smoke.2100262466 Mar 03 02:23:16 PM PST 24 Mar 03 02:23:23 PM PST 24 8370617820 ps
T319 /workspace/coverage/default/44.usbdev_nak_trans.3234567243 Mar 03 02:25:01 PM PST 24 Mar 03 02:25:09 PM PST 24 8505584558 ps
T320 /workspace/coverage/default/47.usbdev_av_buffer.3479196249 Mar 03 02:24:57 PM PST 24 Mar 03 02:25:05 PM PST 24 8373256155 ps
T157 /workspace/coverage/default/32.usbdev_fifo_rst.3684467695 Mar 03 02:24:22 PM PST 24 Mar 03 02:24:25 PM PST 24 161851884 ps
T321 /workspace/coverage/default/46.usbdev_smoke.3252194972 Mar 03 02:24:46 PM PST 24 Mar 03 02:24:54 PM PST 24 8369409259 ps
T322 /workspace/coverage/default/4.usbdev_pkt_sent.3612545429 Mar 03 02:23:16 PM PST 24 Mar 03 02:23:25 PM PST 24 8403360723 ps
T96 /workspace/coverage/default/12.usbdev_nak_trans.1675557005 Mar 03 02:23:31 PM PST 24 Mar 03 02:23:38 PM PST 24 8435080980 ps
T323 /workspace/coverage/default/46.setup_trans_ignored.830945268 Mar 03 02:24:55 PM PST 24 Mar 03 02:25:03 PM PST 24 8379169324 ps
T324 /workspace/coverage/default/7.usbdev_pkt_sent.4168766229 Mar 03 02:23:20 PM PST 24 Mar 03 02:23:27 PM PST 24 8408250493 ps
T325 /workspace/coverage/default/42.usbdev_av_buffer.3351277299 Mar 03 02:24:51 PM PST 24 Mar 03 02:24:59 PM PST 24 8372781617 ps
T326 /workspace/coverage/default/21.setup_trans_ignored.421092 Mar 03 02:23:50 PM PST 24 Mar 03 02:23:59 PM PST 24 8361216086 ps
T327 /workspace/coverage/default/47.usbdev_smoke.3423383549 Mar 03 02:25:12 PM PST 24 Mar 03 02:25:20 PM PST 24 8373991474 ps
T328 /workspace/coverage/default/11.usbdev_fifo_rst.1034403166 Mar 03 02:23:30 PM PST 24 Mar 03 02:23:32 PM PST 24 176793579 ps
T77 /workspace/coverage/default/10.usbdev_nak_trans.925109516 Mar 03 02:23:25 PM PST 24 Mar 03 02:23:33 PM PST 24 8386083496 ps
T329 /workspace/coverage/default/4.usbdev_fifo_rst.2252218841 Mar 03 02:23:15 PM PST 24 Mar 03 02:23:17 PM PST 24 60940998 ps
T330 /workspace/coverage/default/26.usbdev_pkt_sent.1910684972 Mar 03 02:24:06 PM PST 24 Mar 03 02:24:14 PM PST 24 8418772781 ps
T331 /workspace/coverage/default/29.usbdev_nak_trans.4019709462 Mar 03 02:24:20 PM PST 24 Mar 03 02:24:29 PM PST 24 8434007081 ps
T332 /workspace/coverage/default/35.usbdev_av_buffer.3363482169 Mar 03 02:24:22 PM PST 24 Mar 03 02:24:33 PM PST 24 8370398864 ps
T333 /workspace/coverage/default/34.usbdev_pkt_sent.959223756 Mar 03 02:24:23 PM PST 24 Mar 03 02:24:31 PM PST 24 8450094164 ps
T334 /workspace/coverage/default/10.setup_trans_ignored.1679731249 Mar 03 02:23:24 PM PST 24 Mar 03 02:23:32 PM PST 24 8354365818 ps
T335 /workspace/coverage/default/31.usbdev_smoke.620727715 Mar 03 02:24:24 PM PST 24 Mar 03 02:24:34 PM PST 24 8394802278 ps
T336 /workspace/coverage/default/33.setup_trans_ignored.60998578 Mar 03 02:24:21 PM PST 24 Mar 03 02:24:28 PM PST 24 8362209053 ps
T337 /workspace/coverage/default/27.setup_trans_ignored.2709563795 Mar 03 02:24:11 PM PST 24 Mar 03 02:24:19 PM PST 24 8363545192 ps
T164 /workspace/coverage/default/22.usbdev_fifo_rst.4072807602 Mar 03 02:24:02 PM PST 24 Mar 03 02:24:03 PM PST 24 174747873 ps
T338 /workspace/coverage/default/48.usbdev_smoke.3448383670 Mar 03 02:24:51 PM PST 24 Mar 03 02:25:01 PM PST 24 8368654240 ps
T339 /workspace/coverage/default/6.usbdev_pkt_sent.3317762267 Mar 03 02:23:18 PM PST 24 Mar 03 02:23:27 PM PST 24 8523601612 ps
T340 /workspace/coverage/default/8.usbdev_fifo_rst.2370641251 Mar 03 02:23:25 PM PST 24 Mar 03 02:23:27 PM PST 24 172321736 ps
T341 /workspace/coverage/default/28.setup_trans_ignored.904057894 Mar 03 02:24:20 PM PST 24 Mar 03 02:24:29 PM PST 24 8361616255 ps
T342 /workspace/coverage/default/19.usbdev_fifo_rst.497993560 Mar 03 02:24:15 PM PST 24 Mar 03 02:24:17 PM PST 24 54637680 ps
T80 /workspace/coverage/default/49.usbdev_nak_trans.241887270 Mar 03 02:25:16 PM PST 24 Mar 03 02:25:25 PM PST 24 8433603017 ps
T343 /workspace/coverage/default/34.setup_trans_ignored.1030615430 Mar 03 02:24:25 PM PST 24 Mar 03 02:24:33 PM PST 24 8366113862 ps
T344 /workspace/coverage/default/10.usbdev_pkt_sent.3391417533 Mar 03 02:23:26 PM PST 24 Mar 03 02:23:34 PM PST 24 8433791485 ps
T345 /workspace/coverage/default/17.usbdev_fifo_rst.4086268291 Mar 03 02:23:44 PM PST 24 Mar 03 02:23:46 PM PST 24 168637062 ps
T87 /workspace/coverage/default/26.usbdev_nak_trans.2287170417 Mar 03 02:24:16 PM PST 24 Mar 03 02:24:24 PM PST 24 8429283786 ps
T346 /workspace/coverage/default/20.usbdev_fifo_rst.2854025769 Mar 03 02:23:57 PM PST 24 Mar 03 02:23:59 PM PST 24 41599113 ps
T78 /workspace/coverage/default/28.usbdev_nak_trans.574969596 Mar 03 02:24:12 PM PST 24 Mar 03 02:24:21 PM PST 24 8418527563 ps
T347 /workspace/coverage/default/42.setup_trans_ignored.1764519637 Mar 03 02:24:45 PM PST 24 Mar 03 02:24:53 PM PST 24 8361326890 ps
T348 /workspace/coverage/default/30.in_trans.1489467957 Mar 03 02:24:17 PM PST 24 Mar 03 02:24:26 PM PST 24 8418359123 ps
T349 /workspace/coverage/default/14.usbdev_nak_trans.3546664783 Mar 03 02:23:34 PM PST 24 Mar 03 02:23:44 PM PST 24 8418686645 ps
T350 /workspace/coverage/default/35.usbdev_smoke.1744134523 Mar 03 02:24:19 PM PST 24 Mar 03 02:24:28 PM PST 24 8371724696 ps
T351 /workspace/coverage/default/22.usbdev_smoke.2714253662 Mar 03 02:23:58 PM PST 24 Mar 03 02:24:06 PM PST 24 8368016539 ps
T352 /workspace/coverage/default/15.usbdev_pkt_sent.4196849412 Mar 03 02:23:45 PM PST 24 Mar 03 02:23:53 PM PST 24 8436644108 ps
T84 /workspace/coverage/default/6.usbdev_nak_trans.1390299346 Mar 03 02:23:20 PM PST 24 Mar 03 02:23:27 PM PST 24 8433866188 ps
T353 /workspace/coverage/default/17.usbdev_nak_trans.2978209368 Mar 03 02:23:42 PM PST 24 Mar 03 02:23:50 PM PST 24 8455556579 ps
T354 /workspace/coverage/default/49.in_trans.2708940369 Mar 03 02:25:12 PM PST 24 Mar 03 02:25:19 PM PST 24 8378527267 ps
T355 /workspace/coverage/default/20.in_trans.1077409928 Mar 03 02:23:56 PM PST 24 Mar 03 02:24:09 PM PST 24 8405550494 ps
T40 /workspace/coverage/default/2.usbdev_sec_cm.1815248030 Mar 03 02:23:10 PM PST 24 Mar 03 02:23:11 PM PST 24 188210893 ps
T356 /workspace/coverage/default/11.in_trans.2455030895 Mar 03 02:23:33 PM PST 24 Mar 03 02:23:41 PM PST 24 8457623825 ps
T357 /workspace/coverage/default/26.in_trans.3336262966 Mar 03 02:24:12 PM PST 24 Mar 03 02:24:19 PM PST 24 8420355406 ps
T358 /workspace/coverage/default/36.usbdev_pkt_sent.2660292389 Mar 03 02:24:25 PM PST 24 Mar 03 02:24:34 PM PST 24 8398687500 ps
T359 /workspace/coverage/default/31.in_trans.4209609362 Mar 03 02:24:22 PM PST 24 Mar 03 02:24:31 PM PST 24 8454459833 ps
T360 /workspace/coverage/default/38.in_trans.3122882502 Mar 03 02:24:32 PM PST 24 Mar 03 02:24:39 PM PST 24 8409123667 ps
T361 /workspace/coverage/default/14.setup_trans_ignored.1658868466 Mar 03 02:23:37 PM PST 24 Mar 03 02:23:45 PM PST 24 8357881761 ps
T362 /workspace/coverage/default/3.usbdev_pkt_sent.2859909719 Mar 03 02:23:11 PM PST 24 Mar 03 02:23:19 PM PST 24 8449937024 ps
T363 /workspace/coverage/default/27.usbdev_pkt_sent.2658124201 Mar 03 02:24:19 PM PST 24 Mar 03 02:24:29 PM PST 24 8375885341 ps
T364 /workspace/coverage/default/29.in_trans.2940793628 Mar 03 02:24:18 PM PST 24 Mar 03 02:24:26 PM PST 24 8385015157 ps
T365 /workspace/coverage/default/22.setup_trans_ignored.280438838 Mar 03 02:24:04 PM PST 24 Mar 03 02:24:13 PM PST 24 8372638987 ps
T366 /workspace/coverage/default/30.usbdev_smoke.2742187284 Mar 03 02:24:18 PM PST 24 Mar 03 02:24:26 PM PST 24 8370534701 ps
T367 /workspace/coverage/default/7.usbdev_smoke.2664525438 Mar 03 02:23:21 PM PST 24 Mar 03 02:23:29 PM PST 24 8372696099 ps
T368 /workspace/coverage/default/0.usbdev_av_buffer.2162487750 Mar 03 02:22:57 PM PST 24 Mar 03 02:23:07 PM PST 24 8369492501 ps
T369 /workspace/coverage/default/37.usbdev_av_buffer.2895510911 Mar 03 02:24:26 PM PST 24 Mar 03 02:24:34 PM PST 24 8372257826 ps
T370 /workspace/coverage/default/34.usbdev_smoke.1296965124 Mar 03 02:24:22 PM PST 24 Mar 03 02:24:32 PM PST 24 8370617927 ps
T371 /workspace/coverage/default/10.usbdev_fifo_rst.3818102180 Mar 03 02:23:27 PM PST 24 Mar 03 02:23:28 PM PST 24 33713179 ps
T372 /workspace/coverage/default/49.usbdev_av_buffer.426784642 Mar 03 02:25:13 PM PST 24 Mar 03 02:25:22 PM PST 24 8373482147 ps
T373 /workspace/coverage/default/37.usbdev_fifo_rst.1073598290 Mar 03 02:24:43 PM PST 24 Mar 03 02:24:45 PM PST 24 200085517 ps
T374 /workspace/coverage/default/2.usbdev_smoke.981677658 Mar 03 02:23:03 PM PST 24 Mar 03 02:23:10 PM PST 24 8371516572 ps
T375 /workspace/coverage/default/47.setup_trans_ignored.3236602553 Mar 03 02:24:58 PM PST 24 Mar 03 02:25:06 PM PST 24 8359741152 ps
T118 /workspace/coverage/default/17.usbdev_pkt_sent.1767043384 Mar 03 02:23:43 PM PST 24 Mar 03 02:23:53 PM PST 24 8395140630 ps
T376 /workspace/coverage/default/29.usbdev_smoke.3583662606 Mar 03 02:24:10 PM PST 24 Mar 03 02:24:17 PM PST 24 8402604952 ps
T377 /workspace/coverage/default/4.setup_trans_ignored.151359180 Mar 03 02:23:12 PM PST 24 Mar 03 02:23:19 PM PST 24 8356263237 ps
T44 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1409808691 Mar 03 02:04:19 PM PST 24 Mar 03 02:04:21 PM PST 24 59678994 ps
T35 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.854528400 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:05 PM PST 24 335082626 ps
T36 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3406311263 Mar 03 02:03:59 PM PST 24 Mar 03 02:04:02 PM PST 24 143012614 ps
T45 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3581650849 Mar 03 02:04:11 PM PST 24 Mar 03 02:04:12 PM PST 24 43791555 ps
T37 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3904226865 Mar 03 02:04:11 PM PST 24 Mar 03 02:04:15 PM PST 24 265052284 ps
T46 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2067993564 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:26 PM PST 24 81014285 ps
T163 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3304700614 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:06 PM PST 24 157024997 ps
T124 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.125978590 Mar 03 02:04:15 PM PST 24 Mar 03 02:04:19 PM PST 24 190786280 ps
T125 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.890050906 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:27 PM PST 24 342342525 ps
T61 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2686695360 Mar 03 02:04:32 PM PST 24 Mar 03 02:04:33 PM PST 24 91731961 ps
T126 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1941630477 Mar 03 02:04:19 PM PST 24 Mar 03 02:04:23 PM PST 24 199892520 ps
T127 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3248785439 Mar 03 02:03:59 PM PST 24 Mar 03 02:04:03 PM PST 24 99233828 ps
T62 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2746400281 Mar 03 02:04:18 PM PST 24 Mar 03 02:04:20 PM PST 24 159027210 ps
T128 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1536541020 Mar 03 02:04:21 PM PST 24 Mar 03 02:04:23 PM PST 24 54044036 ps
T63 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3550822120 Mar 03 02:04:29 PM PST 24 Mar 03 02:04:31 PM PST 24 54393085 ps
T64 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3100692364 Mar 03 02:04:02 PM PST 24 Mar 03 02:04:04 PM PST 24 160211333 ps
T65 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.290059336 Mar 03 02:04:00 PM PST 24 Mar 03 02:04:06 PM PST 24 191788427 ps
T146 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1037835311 Mar 03 02:04:11 PM PST 24 Mar 03 02:04:12 PM PST 24 69399957 ps
T129 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3860308891 Mar 03 02:04:18 PM PST 24 Mar 03 02:04:20 PM PST 24 120430573 ps
T130 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2541981595 Mar 03 02:04:14 PM PST 24 Mar 03 02:04:16 PM PST 24 91353472 ps
T132 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.918886354 Mar 03 02:04:15 PM PST 24 Mar 03 02:04:17 PM PST 24 155454741 ps
T133 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1334718558 Mar 03 02:04:33 PM PST 24 Mar 03 02:04:35 PM PST 24 65204913 ps
T134 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3929401522 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:03 PM PST 24 65196169 ps
T378 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1405112366 Mar 03 02:04:22 PM PST 24 Mar 03 02:04:23 PM PST 24 150114050 ps
T379 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3792219342 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:06 PM PST 24 473136718 ps
T135 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2889123988 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:24 PM PST 24 66933027 ps
T136 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3862998114 Mar 03 02:04:11 PM PST 24 Mar 03 02:04:13 PM PST 24 76524465 ps
T380 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3761103175 Mar 03 02:04:11 PM PST 24 Mar 03 02:04:12 PM PST 24 63704607 ps
T131 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1589463322 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:25 PM PST 24 119543810 ps
T137 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2441657094 Mar 03 02:04:18 PM PST 24 Mar 03 02:04:20 PM PST 24 170037804 ps
T381 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3690908850 Mar 03 02:04:17 PM PST 24 Mar 03 02:04:20 PM PST 24 119867498 ps
T149 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2006470600 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:05 PM PST 24 293582294 ps
T169 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1154232551 Mar 03 02:04:24 PM PST 24 Mar 03 02:04:29 PM PST 24 295920001 ps
T382 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2883226997 Mar 03 02:04:17 PM PST 24 Mar 03 02:04:19 PM PST 24 66773827 ps
T383 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1822804308 Mar 03 02:04:00 PM PST 24 Mar 03 02:04:02 PM PST 24 95710501 ps
T41 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1199685339 Mar 03 02:04:08 PM PST 24 Mar 03 02:04:09 PM PST 24 39126951 ps
T384 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4206885846 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:25 PM PST 24 75804754 ps
T385 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2200645888 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:25 PM PST 24 51725998 ps
T386 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3190143100 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:12 PM PST 24 186321695 ps
T138 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.448751048 Mar 03 02:04:17 PM PST 24 Mar 03 02:04:19 PM PST 24 47820863 ps
T139 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3659828418 Mar 03 02:04:24 PM PST 24 Mar 03 02:04:25 PM PST 24 29855067 ps
T387 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3808861707 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:03 PM PST 24 58458079 ps
T388 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3811463836 Mar 03 02:04:13 PM PST 24 Mar 03 02:04:15 PM PST 24 146417617 ps
T140 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3584409114 Mar 03 02:04:14 PM PST 24 Mar 03 02:04:16 PM PST 24 66108796 ps
T172 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3680579207 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:26 PM PST 24 174067255 ps
T389 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1326055766 Mar 03 02:04:02 PM PST 24 Mar 03 02:04:05 PM PST 24 196288851 ps
T141 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.268368027 Mar 03 02:04:04 PM PST 24 Mar 03 02:04:10 PM PST 24 210105738 ps
T167 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4073934361 Mar 03 02:04:10 PM PST 24 Mar 03 02:04:13 PM PST 24 265423880 ps
T390 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.734029501 Mar 03 02:04:31 PM PST 24 Mar 03 02:04:32 PM PST 24 29029746 ps
T166 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1976322060 Mar 03 02:04:14 PM PST 24 Mar 03 02:04:16 PM PST 24 159447080 ps
T168 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3412110744 Mar 03 02:04:25 PM PST 24 Mar 03 02:04:26 PM PST 24 44876010 ps
T391 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.287139221 Mar 03 02:04:25 PM PST 24 Mar 03 02:04:27 PM PST 24 79568204 ps
T392 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.942432728 Mar 03 02:04:31 PM PST 24 Mar 03 02:04:33 PM PST 24 60371177 ps
T393 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.677283174 Mar 03 02:04:11 PM PST 24 Mar 03 02:04:13 PM PST 24 42695517 ps
T394 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3508413848 Mar 03 02:04:13 PM PST 24 Mar 03 02:04:14 PM PST 24 163466568 ps
T42 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2887329287 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:03 PM PST 24 54003240 ps
T395 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.917025873 Mar 03 02:04:17 PM PST 24 Mar 03 02:04:20 PM PST 24 43133587 ps
T396 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4043198100 Mar 03 02:04:04 PM PST 24 Mar 03 02:04:07 PM PST 24 54415131 ps
T397 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1588250502 Mar 03 02:04:18 PM PST 24 Mar 03 02:04:19 PM PST 24 43104001 ps
T142 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4056131041 Mar 03 02:03:59 PM PST 24 Mar 03 02:04:03 PM PST 24 337767261 ps
T398 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1146345220 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:11 PM PST 24 125696223 ps
T399 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3093645444 Mar 03 02:04:17 PM PST 24 Mar 03 02:04:22 PM PST 24 277651490 ps
T400 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4261045196 Mar 03 02:04:02 PM PST 24 Mar 03 02:04:04 PM PST 24 129054697 ps
T401 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2122524609 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:24 PM PST 24 31541342 ps
T402 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1268416289 Mar 03 02:04:24 PM PST 24 Mar 03 02:04:25 PM PST 24 56626941 ps
T143 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1847491545 Mar 03 02:03:59 PM PST 24 Mar 03 02:04:01 PM PST 24 44325166 ps
T403 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1265176218 Mar 03 02:04:10 PM PST 24 Mar 03 02:04:12 PM PST 24 123072243 ps
T404 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.222021650 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:11 PM PST 24 51515866 ps
T405 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3874310613 Mar 03 02:04:26 PM PST 24 Mar 03 02:04:29 PM PST 24 252149467 ps
T144 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4230873197 Mar 03 02:04:18 PM PST 24 Mar 03 02:04:20 PM PST 24 88935288 ps
T406 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3900068836 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:11 PM PST 24 87837178 ps
T407 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1401274591 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:03 PM PST 24 162157079 ps
T145 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2419005958 Mar 03 02:04:00 PM PST 24 Mar 03 02:04:01 PM PST 24 32926607 ps
T408 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.410129737 Mar 03 02:04:00 PM PST 24 Mar 03 02:04:02 PM PST 24 94504084 ps
T409 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1812526167 Mar 03 02:04:17 PM PST 24 Mar 03 02:04:20 PM PST 24 47147625 ps
T410 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.390014222 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:11 PM PST 24 57164630 ps
T43 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3825742793 Mar 03 02:04:12 PM PST 24 Mar 03 02:04:13 PM PST 24 37596568 ps
T174 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3674063669 Mar 03 02:04:18 PM PST 24 Mar 03 02:04:21 PM PST 24 160166438 ps
T411 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2335384710 Mar 03 02:04:15 PM PST 24 Mar 03 02:04:16 PM PST 24 58072440 ps
T412 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.814054381 Mar 03 02:04:11 PM PST 24 Mar 03 02:04:14 PM PST 24 234215052 ps
T47 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2939802633 Mar 03 02:04:04 PM PST 24 Mar 03 02:04:05 PM PST 24 41083526 ps
T413 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4055875141 Mar 03 02:04:33 PM PST 24 Mar 03 02:04:36 PM PST 24 139215173 ps
T414 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3719360637 Mar 03 02:04:23 PM PST 24 Mar 03 02:04:24 PM PST 24 66870909 ps
T415 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.282491630 Mar 03 02:04:29 PM PST 24 Mar 03 02:04:32 PM PST 24 49840079 ps
T175 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3334642140 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:11 PM PST 24 172869331 ps
T416 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1763370013 Mar 03 02:03:59 PM PST 24 Mar 03 02:04:03 PM PST 24 336728812 ps
T417 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2275312600 Mar 03 02:03:59 PM PST 24 Mar 03 02:04:04 PM PST 24 339135836 ps
T418 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.832967624 Mar 03 02:04:03 PM PST 24 Mar 03 02:04:05 PM PST 24 98574580 ps
T419 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.231216763 Mar 03 02:04:17 PM PST 24 Mar 03 02:04:21 PM PST 24 189119624 ps
T420 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2574014854 Mar 03 02:04:04 PM PST 24 Mar 03 02:04:07 PM PST 24 74514861 ps
T421 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1441971808 Mar 03 02:04:30 PM PST 24 Mar 03 02:04:32 PM PST 24 86628931 ps
T422 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1020800483 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:10 PM PST 24 39717926 ps
T48 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3752446568 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:02 PM PST 24 62189937 ps
T423 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.216815075 Mar 03 02:04:14 PM PST 24 Mar 03 02:04:17 PM PST 24 364262669 ps
T424 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2711862533 Mar 03 02:04:33 PM PST 24 Mar 03 02:04:35 PM PST 24 161698905 ps
T425 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.291394097 Mar 03 02:04:32 PM PST 24 Mar 03 02:04:33 PM PST 24 33130007 ps
T426 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.4097314603 Mar 03 02:04:24 PM PST 24 Mar 03 02:04:26 PM PST 24 259038498 ps
T427 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3561387786 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:02 PM PST 24 40454945 ps
T428 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1237154271 Mar 03 02:04:18 PM PST 24 Mar 03 02:04:20 PM PST 24 49411060 ps
T429 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4011664923 Mar 03 02:04:15 PM PST 24 Mar 03 02:04:19 PM PST 24 126173787 ps
T430 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3819860931 Mar 03 02:04:25 PM PST 24 Mar 03 02:04:27 PM PST 24 138091890 ps
T170 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2048744113 Mar 03 02:04:16 PM PST 24 Mar 03 02:04:19 PM PST 24 315824149 ps
T431 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.439826534 Mar 03 02:04:11 PM PST 24 Mar 03 02:04:14 PM PST 24 98392420 ps
T432 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3848411730 Mar 03 02:04:14 PM PST 24 Mar 03 02:04:18 PM PST 24 242862093 ps
T173 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2457085345 Mar 03 02:04:33 PM PST 24 Mar 03 02:04:36 PM PST 24 201507170 ps
T171 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1090975207 Mar 03 02:04:22 PM PST 24 Mar 03 02:04:25 PM PST 24 299689424 ps
T433 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1003522268 Mar 03 02:04:12 PM PST 24 Mar 03 02:04:14 PM PST 24 249778190 ps
T434 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2573755024 Mar 03 02:04:19 PM PST 24 Mar 03 02:04:22 PM PST 24 150003672 ps
T435 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.28543216 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:12 PM PST 24 225175737 ps
T436 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3480399146 Mar 03 02:04:01 PM PST 24 Mar 03 02:04:04 PM PST 24 50836553 ps
T437 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.339075138 Mar 03 02:04:13 PM PST 24 Mar 03 02:04:18 PM PST 24 197084161 ps
T438 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1497555457 Mar 03 02:04:25 PM PST 24 Mar 03 02:04:26 PM PST 24 40353051 ps
T439 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.446525511 Mar 03 02:04:09 PM PST 24 Mar 03 02:04:11 PM PST 24 111355540 ps

Test location /workspace/coverage/default/45.in_trans.830637351
Short name T3
Test name
Test status
Simulation time 8403648376 ps
CPU time 8.59 seconds
Started Mar 03 02:25:00 PM PST 24
Finished Mar 03 02:25:09 PM PST 24
Peak memory 202584 kb
Host smart-6aee2af0-1271-442a-a4d0-f1a01dda5255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83063
7351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.in_trans.830637351
Directory /workspace/45.in_trans/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2772352356
Short name T19
Test name
Test status
Simulation time 157069535 ps
CPU time 1.56 seconds
Started Mar 03 02:23:10 PM PST 24
Finished Mar 03 02:23:12 PM PST 24
Peak memory 202660 kb
Host smart-bd77305a-1f24-417d-bf4b-cd83b2cb3e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27723
52356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2772352356
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3406311263
Short name T36
Test name
Test status
Simulation time 143012614 ps
CPU time 2.5 seconds
Started Mar 03 02:03:59 PM PST 24
Finished Mar 03 02:04:02 PM PST 24
Peak memory 202832 kb
Host smart-ed3ca725-2be8-49a8-9e1f-ad03ea76901a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3406311263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3406311263
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.854528400
Short name T35
Test name
Test status
Simulation time 335082626 ps
CPU time 3.55 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:05 PM PST 24
Peak memory 202916 kb
Host smart-cc85c4e5-fb51-4a5c-b07f-27c7aa657894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=854528400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.854528400
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2591426598
Short name T6
Test name
Test status
Simulation time 8460250483 ps
CPU time 7.35 seconds
Started Mar 03 02:24:17 PM PST 24
Finished Mar 03 02:24:25 PM PST 24
Peak memory 202608 kb
Host smart-feff5d38-de27-47cd-a993-e9e8ee2b2b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25914
26598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2591426598
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.221776322
Short name T27
Test name
Test status
Simulation time 8372456988 ps
CPU time 9.99 seconds
Started Mar 03 02:23:26 PM PST 24
Finished Mar 03 02:23:36 PM PST 24
Peak memory 202596 kb
Host smart-2576c68f-ad1d-43eb-87de-7f80e361c30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22177
6322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.221776322
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1381254595
Short name T38
Test name
Test status
Simulation time 145043039 ps
CPU time 0.99 seconds
Started Mar 03 02:23:03 PM PST 24
Finished Mar 03 02:23:05 PM PST 24
Peak memory 217224 kb
Host smart-3e570d2b-bf5c-4e1e-b25f-5ba08699a737
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1381254595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1381254595
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1425162238
Short name T4
Test name
Test status
Simulation time 8423467642 ps
CPU time 7.67 seconds
Started Mar 03 02:24:30 PM PST 24
Finished Mar 03 02:24:38 PM PST 24
Peak memory 202604 kb
Host smart-d69fc7be-e554-4b52-816a-1c61570ea11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14251
62238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1425162238
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1199685339
Short name T41
Test name
Test status
Simulation time 39126951 ps
CPU time 0.79 seconds
Started Mar 03 02:04:08 PM PST 24
Finished Mar 03 02:04:09 PM PST 24
Peak memory 202588 kb
Host smart-800e870c-af5d-422b-a405-fc1946ffeef6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199685339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1199685339
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2025450138
Short name T152
Test name
Test status
Simulation time 244487867 ps
CPU time 2.14 seconds
Started Mar 03 02:23:34 PM PST 24
Finished Mar 03 02:23:37 PM PST 24
Peak memory 202804 kb
Host smart-1b3b2d92-44b4-4627-a1a1-a7acb5c50ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20254
50138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2025450138
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3752446568
Short name T48
Test name
Test status
Simulation time 62189937 ps
CPU time 0.84 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:02 PM PST 24
Peak memory 202556 kb
Host smart-5fd622e9-35e0-41f7-ac70-2889461f43da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752446568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3752446568
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1409808691
Short name T44
Test name
Test status
Simulation time 59678994 ps
CPU time 0.99 seconds
Started Mar 03 02:04:19 PM PST 24
Finished Mar 03 02:04:21 PM PST 24
Peak memory 202912 kb
Host smart-a843a707-d292-43ef-8a3b-fd458ab8f90b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409808691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1409808691
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/default/36.in_trans.2757440234
Short name T22
Test name
Test status
Simulation time 8458038352 ps
CPU time 10.44 seconds
Started Mar 03 02:24:24 PM PST 24
Finished Mar 03 02:24:35 PM PST 24
Peak memory 202656 kb
Host smart-2347a381-c393-4996-b817-00a13ced134e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27574
40234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.in_trans.2757440234
Directory /workspace/36.in_trans/latest

Test location /workspace/coverage/default/19.in_trans.3358911958
Short name T15
Test name
Test status
Simulation time 8432701241 ps
CPU time 7.26 seconds
Started Mar 03 02:23:59 PM PST 24
Finished Mar 03 02:24:06 PM PST 24
Peak memory 202476 kb
Host smart-429863d9-06d9-4ff5-8a08-f34cf259cf18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33589
11958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.in_trans.3358911958
Directory /workspace/19.in_trans/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1154232551
Short name T169
Test name
Test status
Simulation time 295920001 ps
CPU time 4.63 seconds
Started Mar 03 02:04:24 PM PST 24
Finished Mar 03 02:04:29 PM PST 24
Peak memory 202984 kb
Host smart-48f894ee-416b-4389-970e-c504372e5db6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1154232551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1154232551
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.918886354
Short name T132
Test name
Test status
Simulation time 155454741 ps
CPU time 1.54 seconds
Started Mar 03 02:04:15 PM PST 24
Finished Mar 03 02:04:17 PM PST 24
Peak memory 202880 kb
Host smart-7f4c701f-7fc4-4642-9049-d04fae6b2726
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918886354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_c
sr_outstanding.918886354
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3825742793
Short name T43
Test name
Test status
Simulation time 37596568 ps
CPU time 0.73 seconds
Started Mar 03 02:04:12 PM PST 24
Finished Mar 03 02:04:13 PM PST 24
Peak memory 202652 kb
Host smart-d31b1c32-b69c-4442-b02a-d0aeb0fa759c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825742793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3825742793
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2954228191
Short name T39
Test name
Test status
Simulation time 128698811 ps
CPU time 0.96 seconds
Started Mar 03 02:23:04 PM PST 24
Finished Mar 03 02:23:05 PM PST 24
Peak memory 217268 kb
Host smart-d5697bc1-3dc4-49b0-b150-98c2f1bbaa28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2954228191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2954228191
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2939802633
Short name T47
Test name
Test status
Simulation time 41083526 ps
CPU time 0.77 seconds
Started Mar 03 02:04:04 PM PST 24
Finished Mar 03 02:04:05 PM PST 24
Peak memory 202564 kb
Host smart-4975dcdd-e649-43a1-a66b-dfca2b721616
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939802633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2939802633
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2887329287
Short name T42
Test name
Test status
Simulation time 54003240 ps
CPU time 0.89 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 202536 kb
Host smart-37ccfcbe-8853-4b71-97ed-259bd4ec7de4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887329287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2887329287
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2048744113
Short name T170
Test name
Test status
Simulation time 315824149 ps
CPU time 3.03 seconds
Started Mar 03 02:04:16 PM PST 24
Finished Mar 03 02:04:19 PM PST 24
Peak memory 202840 kb
Host smart-e856ebdc-de5e-4d00-abf6-2dcbddbdb218
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2048744113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2048744113
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3680579207
Short name T172
Test name
Test status
Simulation time 174067255 ps
CPU time 2.52 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:26 PM PST 24
Peak memory 202952 kb
Host smart-c07c1bc9-496f-4ebd-8660-82c6abde5d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3680579207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3680579207
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2006470600
Short name T149
Test name
Test status
Simulation time 293582294 ps
CPU time 2.85 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:05 PM PST 24
Peak memory 202836 kb
Host smart-4c0d228f-22fb-41dc-8ed8-b2432f8a91a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2006470600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2006470600
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3334642140
Short name T175
Test name
Test status
Simulation time 172869331 ps
CPU time 2.53 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:11 PM PST 24
Peak memory 202892 kb
Host smart-88048c24-a02f-482f-9b5a-64dd00a05263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3334642140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3334642140
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/18.in_trans.3564399903
Short name T68
Test name
Test status
Simulation time 8507330562 ps
CPU time 7.84 seconds
Started Mar 03 02:23:40 PM PST 24
Finished Mar 03 02:23:48 PM PST 24
Peak memory 202608 kb
Host smart-95c0f200-9d19-4a39-bca8-f62e3ac14514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35643
99903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.in_trans.3564399903
Directory /workspace/18.in_trans/latest

Test location /workspace/coverage/default/23.in_trans.2098364953
Short name T102
Test name
Test status
Simulation time 8443272873 ps
CPU time 7.59 seconds
Started Mar 03 02:23:58 PM PST 24
Finished Mar 03 02:24:06 PM PST 24
Peak memory 202596 kb
Host smart-3e681abe-0ced-4d52-a675-4c38b3afe710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20983
64953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.in_trans.2098364953
Directory /workspace/23.in_trans/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2792384504
Short name T109
Test name
Test status
Simulation time 8453978188 ps
CPU time 8.55 seconds
Started Mar 03 02:23:43 PM PST 24
Finished Mar 03 02:23:52 PM PST 24
Peak memory 202600 kb
Host smart-b094cdb2-6418-477e-962f-c45ef3a2f598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
84504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2792384504
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.4012739738
Short name T114
Test name
Test status
Simulation time 8414316946 ps
CPU time 8.21 seconds
Started Mar 03 02:22:58 PM PST 24
Finished Mar 03 02:23:06 PM PST 24
Peak memory 202604 kb
Host smart-5f445eba-82d7-4099-a552-cc522938d1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40127
39738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.4012739738
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.891955083
Short name T121
Test name
Test status
Simulation time 8449443929 ps
CPU time 7.66 seconds
Started Mar 03 02:23:04 PM PST 24
Finished Mar 03 02:23:12 PM PST 24
Peak memory 202596 kb
Host smart-ff3241c5-316c-4c7c-ac0a-c101495a23d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89195
5083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.891955083
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3077535615
Short name T13
Test name
Test status
Simulation time 8387703852 ps
CPU time 8.81 seconds
Started Mar 03 02:23:32 PM PST 24
Finished Mar 03 02:23:41 PM PST 24
Peak memory 202560 kb
Host smart-87883751-9574-4724-853b-c6e73cf86321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
35615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3077535615
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3409905729
Short name T225
Test name
Test status
Simulation time 8393366351 ps
CPU time 7.46 seconds
Started Mar 03 02:23:33 PM PST 24
Finished Mar 03 02:23:41 PM PST 24
Peak memory 202616 kb
Host smart-34c9b103-1096-41f4-9105-bb8744f4b419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34099
05729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3409905729
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1767043384
Short name T118
Test name
Test status
Simulation time 8395140630 ps
CPU time 9.15 seconds
Started Mar 03 02:23:43 PM PST 24
Finished Mar 03 02:23:53 PM PST 24
Peak memory 202664 kb
Host smart-fe9e0925-b4a2-4140-975f-2a02ce9fb845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17670
43384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1767043384
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2548147720
Short name T216
Test name
Test status
Simulation time 8399764709 ps
CPU time 7.31 seconds
Started Mar 03 02:24:10 PM PST 24
Finished Mar 03 02:24:17 PM PST 24
Peak memory 202568 kb
Host smart-dd0561f0-b3aa-434e-846e-618deef27388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25481
47720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2548147720
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3248785439
Short name T127
Test name
Test status
Simulation time 99233828 ps
CPU time 3.1 seconds
Started Mar 03 02:03:59 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 202856 kb
Host smart-1b2b6ac0-295f-4ad6-9c06-4f43ce9bb8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248785439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3248785439
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3487109450
Short name T311
Test name
Test status
Simulation time 8438664398 ps
CPU time 7.53 seconds
Started Mar 03 02:22:58 PM PST 24
Finished Mar 03 02:23:05 PM PST 24
Peak memory 202600 kb
Host smart-4954b18f-ce73-4ca0-b88d-8c983235977b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34871
09450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3487109450
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.333219182
Short name T86
Test name
Test status
Simulation time 8503740460 ps
CPU time 7.76 seconds
Started Mar 03 02:23:04 PM PST 24
Finished Mar 03 02:23:12 PM PST 24
Peak memory 202592 kb
Host smart-2d40b958-e7a3-4155-940a-b5a5ed106294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33321
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.333219182
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.925109516
Short name T77
Test name
Test status
Simulation time 8386083496 ps
CPU time 7.65 seconds
Started Mar 03 02:23:25 PM PST 24
Finished Mar 03 02:23:33 PM PST 24
Peak memory 202616 kb
Host smart-0b0932fe-2ab9-4988-ac36-139b0f9b09ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92510
9516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.925109516
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.4263899079
Short name T25
Test name
Test status
Simulation time 8449593098 ps
CPU time 10.09 seconds
Started Mar 03 02:23:36 PM PST 24
Finished Mar 03 02:23:46 PM PST 24
Peak memory 202656 kb
Host smart-2f23f01f-9d25-46f1-9b70-000349336dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42638
99079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.4263899079
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1675557005
Short name T96
Test name
Test status
Simulation time 8435080980 ps
CPU time 7.17 seconds
Started Mar 03 02:23:31 PM PST 24
Finished Mar 03 02:23:38 PM PST 24
Peak memory 202564 kb
Host smart-ee07a2c2-56ce-49a9-bb71-26f60dcff97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16755
57005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1675557005
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1721875559
Short name T72
Test name
Test status
Simulation time 8445765043 ps
CPU time 7.84 seconds
Started Mar 03 02:23:35 PM PST 24
Finished Mar 03 02:23:44 PM PST 24
Peak memory 202492 kb
Host smart-9aff03eb-ba31-4ab0-9928-9017a8378d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17218
75559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1721875559
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2978209368
Short name T353
Test name
Test status
Simulation time 8455556579 ps
CPU time 7.91 seconds
Started Mar 03 02:23:42 PM PST 24
Finished Mar 03 02:23:50 PM PST 24
Peak memory 202596 kb
Host smart-768feaa0-4923-4f5b-8b09-ace871cd022a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29782
09368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2978209368
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2899357620
Short name T92
Test name
Test status
Simulation time 8387916321 ps
CPU time 8.91 seconds
Started Mar 03 02:23:40 PM PST 24
Finished Mar 03 02:23:49 PM PST 24
Peak memory 202540 kb
Host smart-2c060de0-2dc7-4826-b170-e5d01a9046e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28993
57620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2899357620
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.setup_trans_ignored.1407658654
Short name T180
Test name
Test status
Simulation time 8354944336 ps
CPU time 7.34 seconds
Started Mar 03 02:23:52 PM PST 24
Finished Mar 03 02:24:00 PM PST 24
Peak memory 202560 kb
Host smart-94f003c9-7a74-4957-ae82-275fbb9140b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14076
58654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.setup_trans_ignored.1407658654
Directory /workspace/19.setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.98160836
Short name T82
Test name
Test status
Simulation time 8418902732 ps
CPU time 8.62 seconds
Started Mar 03 02:24:01 PM PST 24
Finished Mar 03 02:24:10 PM PST 24
Peak memory 202600 kb
Host smart-c11227c2-7c1b-4be5-8a06-92716701722b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98160
836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.98160836
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3311690379
Short name T69
Test name
Test status
Simulation time 8430969328 ps
CPU time 7.71 seconds
Started Mar 03 02:24:16 PM PST 24
Finished Mar 03 02:24:24 PM PST 24
Peak memory 202588 kb
Host smart-b9693451-c105-4f05-b7d2-7064c73e43d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33116
90379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3311690379
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3711795460
Short name T79
Test name
Test status
Simulation time 8406215932 ps
CPU time 7.69 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202596 kb
Host smart-386c63f9-6558-4026-84bc-e83ebdd7614c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37117
95460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3711795460
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2275312600
Short name T417
Test name
Test status
Simulation time 339135836 ps
CPU time 4.11 seconds
Started Mar 03 02:03:59 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 202808 kb
Host smart-aabad9bb-77cf-4d75-b503-c05b200f47d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275312600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2275312600
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.290059336
Short name T65
Test name
Test status
Simulation time 191788427 ps
CPU time 4.74 seconds
Started Mar 03 02:04:00 PM PST 24
Finished Mar 03 02:04:06 PM PST 24
Peak memory 202932 kb
Host smart-a2569a47-db27-4e37-9803-c517f78a08e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290059336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.290059336
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3480399146
Short name T436
Test name
Test status
Simulation time 50836553 ps
CPU time 1.99 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 211208 kb
Host smart-bfaea0e3-2159-42d6-a571-4fec763a2a57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480399146 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.3480399146
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2419005958
Short name T145
Test name
Test status
Simulation time 32926607 ps
CPU time 1.04 seconds
Started Mar 03 02:04:00 PM PST 24
Finished Mar 03 02:04:01 PM PST 24
Peak memory 202864 kb
Host smart-3de4fc75-9bf4-4ac6-bff5-64cf946a5bd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419005958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2419005958
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1847491545
Short name T143
Test name
Test status
Simulation time 44325166 ps
CPU time 1.42 seconds
Started Mar 03 02:03:59 PM PST 24
Finished Mar 03 02:04:01 PM PST 24
Peak memory 202776 kb
Host smart-166dc9a9-be4e-42fa-86c3-998e4c9edb8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1847491545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1847491545
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1822804308
Short name T383
Test name
Test status
Simulation time 95710501 ps
CPU time 1.53 seconds
Started Mar 03 02:04:00 PM PST 24
Finished Mar 03 02:04:02 PM PST 24
Peak memory 202836 kb
Host smart-98ddb608-3662-48df-82ba-ec126f2de60e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822804308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.1822804308
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1763370013
Short name T416
Test name
Test status
Simulation time 336728812 ps
CPU time 3.15 seconds
Started Mar 03 02:03:59 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 202952 kb
Host smart-53a3ccae-5058-48b5-8ab0-bdaae59ab1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1763370013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1763370013
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2574014854
Short name T420
Test name
Test status
Simulation time 74514861 ps
CPU time 2.1 seconds
Started Mar 03 02:04:04 PM PST 24
Finished Mar 03 02:04:07 PM PST 24
Peak memory 202712 kb
Host smart-5c39b0d2-dd30-4618-bb7d-b6da2fa18530
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574014854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2574014854
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3808861707
Short name T387
Test name
Test status
Simulation time 58458079 ps
CPU time 1.75 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 211224 kb
Host smart-2f0e582d-4c0a-46c5-b67a-edd25ee2e042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808861707 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.3808861707
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3561387786
Short name T427
Test name
Test status
Simulation time 40454945 ps
CPU time 0.87 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:02 PM PST 24
Peak memory 202736 kb
Host smart-771826f1-6d44-4059-aeb1-3fd168477a86
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561387786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3561387786
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.832967624
Short name T418
Test name
Test status
Simulation time 98574580 ps
CPU time 1.5 seconds
Started Mar 03 02:04:03 PM PST 24
Finished Mar 03 02:04:05 PM PST 24
Peak memory 202808 kb
Host smart-87cd9acc-2510-42de-85b6-98cd71435af2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=832967624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.832967624
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3304700614
Short name T163
Test name
Test status
Simulation time 157024997 ps
CPU time 4.03 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:06 PM PST 24
Peak memory 202852 kb
Host smart-663d24f8-1c01-402f-959e-f7c1f7e4f4d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3304700614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3304700614
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1401274591
Short name T407
Test name
Test status
Simulation time 162157079 ps
CPU time 1.74 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 202952 kb
Host smart-16e33655-1e96-4ad5-a683-1f8d9d195df3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401274591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.1401274591
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3690908850
Short name T381
Test name
Test status
Simulation time 119867498 ps
CPU time 1.68 seconds
Started Mar 03 02:04:17 PM PST 24
Finished Mar 03 02:04:20 PM PST 24
Peak memory 211200 kb
Host smart-8c5af74a-5b55-41b8-9a4f-967bf78b6c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690908850 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.3690908850
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1588250502
Short name T397
Test name
Test status
Simulation time 43104001 ps
CPU time 0.84 seconds
Started Mar 03 02:04:18 PM PST 24
Finished Mar 03 02:04:19 PM PST 24
Peak memory 202588 kb
Host smart-711d6200-7d27-4f96-9acb-e4142c997f4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588250502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1588250502
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2573755024
Short name T434
Test name
Test status
Simulation time 150003672 ps
CPU time 1.25 seconds
Started Mar 03 02:04:19 PM PST 24
Finished Mar 03 02:04:22 PM PST 24
Peak memory 202880 kb
Host smart-e5aa7f0f-56dc-46e5-973d-fc75bbf9ff60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573755024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.2573755024
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4011664923
Short name T429
Test name
Test status
Simulation time 126173787 ps
CPU time 3.19 seconds
Started Mar 03 02:04:15 PM PST 24
Finished Mar 03 02:04:19 PM PST 24
Peak memory 202804 kb
Host smart-f06eb6a4-dad2-4c3a-b9fb-5ac4dba9bb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4011664923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4011664923
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.231216763
Short name T419
Test name
Test status
Simulation time 189119624 ps
CPU time 2.47 seconds
Started Mar 03 02:04:17 PM PST 24
Finished Mar 03 02:04:21 PM PST 24
Peak memory 202956 kb
Host smart-bc892d3d-dd93-4468-b79a-138dde81624a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=231216763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.231216763
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3860308891
Short name T129
Test name
Test status
Simulation time 120430573 ps
CPU time 1.29 seconds
Started Mar 03 02:04:18 PM PST 24
Finished Mar 03 02:04:20 PM PST 24
Peak memory 211204 kb
Host smart-e85e0314-b635-4307-9aaf-02ee88937d14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860308891 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3860308891
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.448751048
Short name T138
Test name
Test status
Simulation time 47820863 ps
CPU time 0.84 seconds
Started Mar 03 02:04:17 PM PST 24
Finished Mar 03 02:04:19 PM PST 24
Peak memory 202688 kb
Host smart-e43c7ee6-f90f-42ad-a628-65fa0ad6a6a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448751048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.448751048
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2883226997
Short name T382
Test name
Test status
Simulation time 66773827 ps
CPU time 1.88 seconds
Started Mar 03 02:04:17 PM PST 24
Finished Mar 03 02:04:19 PM PST 24
Peak memory 202844 kb
Host smart-40f0bf1c-ecf2-4a8c-8e7e-84c1347aa342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2883226997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2883226997
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4206885846
Short name T384
Test name
Test status
Simulation time 75804754 ps
CPU time 1.3 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:25 PM PST 24
Peak memory 212348 kb
Host smart-b3e254f7-901b-46b3-aea0-0a7438b5796f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206885846 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.4206885846
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3719360637
Short name T414
Test name
Test status
Simulation time 66870909 ps
CPU time 1.06 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:24 PM PST 24
Peak memory 202844 kb
Host smart-4b26caff-f877-4f3b-a5fb-95ab0379fd5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719360637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.3719360637
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1941630477
Short name T126
Test name
Test status
Simulation time 199892520 ps
CPU time 2.75 seconds
Started Mar 03 02:04:19 PM PST 24
Finished Mar 03 02:04:23 PM PST 24
Peak memory 202924 kb
Host smart-ac00d32d-a48c-4b5a-85b6-96a3e093f69a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1941630477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1941630477
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3819860931
Short name T430
Test name
Test status
Simulation time 138091890 ps
CPU time 1.89 seconds
Started Mar 03 02:04:25 PM PST 24
Finished Mar 03 02:04:27 PM PST 24
Peak memory 211256 kb
Host smart-d7a94bd1-14b5-4c1b-9d31-a9cb51415899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819860931 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.3819860931
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2889123988
Short name T135
Test name
Test status
Simulation time 66933027 ps
CPU time 1.1 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:24 PM PST 24
Peak memory 202864 kb
Host smart-9afa5c63-e130-4997-b4f6-71969931ed13
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889123988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2889123988
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1405112366
Short name T378
Test name
Test status
Simulation time 150114050 ps
CPU time 1.55 seconds
Started Mar 03 02:04:22 PM PST 24
Finished Mar 03 02:04:23 PM PST 24
Peak memory 202948 kb
Host smart-44ed0d4f-8fc9-4dd5-94c9-3465a43e6e15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405112366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.1405112366
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1589463322
Short name T131
Test name
Test status
Simulation time 119543810 ps
CPU time 1.85 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:25 PM PST 24
Peak memory 211228 kb
Host smart-459463bd-2b13-49d5-9d3e-39fedee3fc17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589463322 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.1589463322
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3412110744
Short name T168
Test name
Test status
Simulation time 44876010 ps
CPU time 0.83 seconds
Started Mar 03 02:04:25 PM PST 24
Finished Mar 03 02:04:26 PM PST 24
Peak memory 202736 kb
Host smart-346c8b02-1eca-4736-a72c-9f5dc0f9da4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412110744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3412110744
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1268416289
Short name T402
Test name
Test status
Simulation time 56626941 ps
CPU time 1.09 seconds
Started Mar 03 02:04:24 PM PST 24
Finished Mar 03 02:04:25 PM PST 24
Peak memory 202848 kb
Host smart-e5b9a5d4-1e49-4a8a-b221-5456d1c9baf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268416289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.1268416289
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1536541020
Short name T128
Test name
Test status
Simulation time 54044036 ps
CPU time 1.7 seconds
Started Mar 03 02:04:21 PM PST 24
Finished Mar 03 02:04:23 PM PST 24
Peak memory 202952 kb
Host smart-5cfb7a62-a83d-4c2a-a0a2-34382bc3ef9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1536541020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1536541020
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.4097314603
Short name T426
Test name
Test status
Simulation time 259038498 ps
CPU time 1.95 seconds
Started Mar 03 02:04:24 PM PST 24
Finished Mar 03 02:04:26 PM PST 24
Peak memory 213824 kb
Host smart-301bddd5-95c3-4ea0-a83b-b646b61071f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097314603 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.4097314603
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3659828418
Short name T139
Test name
Test status
Simulation time 29855067 ps
CPU time 0.82 seconds
Started Mar 03 02:04:24 PM PST 24
Finished Mar 03 02:04:25 PM PST 24
Peak memory 202636 kb
Host smart-3b93b654-fbe4-49a8-853d-ae0d3c5d9fcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659828418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3659828418
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1497555457
Short name T438
Test name
Test status
Simulation time 40353051 ps
CPU time 1.1 seconds
Started Mar 03 02:04:25 PM PST 24
Finished Mar 03 02:04:26 PM PST 24
Peak memory 202960 kb
Host smart-92c80b06-58f5-4816-a893-8d4f7ab7d237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497555457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.1497555457
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.890050906
Short name T125
Test name
Test status
Simulation time 342342525 ps
CPU time 3.7 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:27 PM PST 24
Peak memory 202940 kb
Host smart-641417c9-feaa-4e94-8c08-d2179bd862a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=890050906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.890050906
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1090975207
Short name T171
Test name
Test status
Simulation time 299689424 ps
CPU time 3.05 seconds
Started Mar 03 02:04:22 PM PST 24
Finished Mar 03 02:04:25 PM PST 24
Peak memory 202812 kb
Host smart-a33f1a5c-e814-4d5e-8dce-c76d8be71af1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1090975207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1090975207
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2067993564
Short name T46
Test name
Test status
Simulation time 81014285 ps
CPU time 2.47 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:26 PM PST 24
Peak memory 211192 kb
Host smart-e122d13d-0e4d-499d-8652-e1b003de77ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067993564 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2067993564
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2122524609
Short name T401
Test name
Test status
Simulation time 31541342 ps
CPU time 0.94 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:24 PM PST 24
Peak memory 202764 kb
Host smart-6e809543-e53c-44f1-aaf9-255483bfbb8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122524609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2122524609
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2200645888
Short name T385
Test name
Test status
Simulation time 51725998 ps
CPU time 1.44 seconds
Started Mar 03 02:04:23 PM PST 24
Finished Mar 03 02:04:25 PM PST 24
Peak memory 202872 kb
Host smart-8691d994-ca1b-45b0-8d00-80c7153a6c58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200645888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.2200645888
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.287139221
Short name T391
Test name
Test status
Simulation time 79568204 ps
CPU time 2.6 seconds
Started Mar 03 02:04:25 PM PST 24
Finished Mar 03 02:04:27 PM PST 24
Peak memory 202900 kb
Host smart-68e7412e-7433-44ad-928a-38129dab29ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=287139221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.287139221
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.942432728
Short name T392
Test name
Test status
Simulation time 60371177 ps
CPU time 1.65 seconds
Started Mar 03 02:04:31 PM PST 24
Finished Mar 03 02:04:33 PM PST 24
Peak memory 211208 kb
Host smart-419fd794-068f-4e48-a694-89e6217bc5ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942432728 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.942432728
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.291394097
Short name T425
Test name
Test status
Simulation time 33130007 ps
CPU time 0.96 seconds
Started Mar 03 02:04:32 PM PST 24
Finished Mar 03 02:04:33 PM PST 24
Peak memory 202912 kb
Host smart-d9b8330f-5b71-4540-b2da-cdeb034d2f26
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291394097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.291394097
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2686695360
Short name T61
Test name
Test status
Simulation time 91731961 ps
CPU time 1.2 seconds
Started Mar 03 02:04:32 PM PST 24
Finished Mar 03 02:04:33 PM PST 24
Peak memory 202920 kb
Host smart-b020bba3-ca2a-481c-870e-30cbe037266f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686695360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.2686695360
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3874310613
Short name T405
Test name
Test status
Simulation time 252149467 ps
CPU time 2.77 seconds
Started Mar 03 02:04:26 PM PST 24
Finished Mar 03 02:04:29 PM PST 24
Peak memory 202844 kb
Host smart-a7d42eb5-6559-467e-9485-8b4504a3ece8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3874310613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3874310613
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2457085345
Short name T173
Test name
Test status
Simulation time 201507170 ps
CPU time 2.5 seconds
Started Mar 03 02:04:33 PM PST 24
Finished Mar 03 02:04:36 PM PST 24
Peak memory 202948 kb
Host smart-d4d91c13-dfd0-4b53-bfa8-ffd1ac203cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2457085345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2457085345
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2711862533
Short name T424
Test name
Test status
Simulation time 161698905 ps
CPU time 1.33 seconds
Started Mar 03 02:04:33 PM PST 24
Finished Mar 03 02:04:35 PM PST 24
Peak memory 211180 kb
Host smart-c6ce0708-ac59-4466-8edb-e4e163fdc6fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711862533 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.2711862533
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.734029501
Short name T390
Test name
Test status
Simulation time 29029746 ps
CPU time 0.81 seconds
Started Mar 03 02:04:31 PM PST 24
Finished Mar 03 02:04:32 PM PST 24
Peak memory 202584 kb
Host smart-b4cb19a8-cc35-4aae-9719-bb9286581d97
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734029501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.734029501
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.282491630
Short name T415
Test name
Test status
Simulation time 49840079 ps
CPU time 1.37 seconds
Started Mar 03 02:04:29 PM PST 24
Finished Mar 03 02:04:32 PM PST 24
Peak memory 202872 kb
Host smart-4f0acbcb-84c8-49e0-bc04-4f3760fb73cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282491630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_c
sr_outstanding.282491630
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4055875141
Short name T413
Test name
Test status
Simulation time 139215173 ps
CPU time 2.02 seconds
Started Mar 03 02:04:33 PM PST 24
Finished Mar 03 02:04:36 PM PST 24
Peak memory 202880 kb
Host smart-2933249a-971c-4de1-84f0-ae5082b1eb5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4055875141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.4055875141
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1441971808
Short name T421
Test name
Test status
Simulation time 86628931 ps
CPU time 1.3 seconds
Started Mar 03 02:04:30 PM PST 24
Finished Mar 03 02:04:32 PM PST 24
Peak memory 211128 kb
Host smart-5618d1a4-d831-45f8-b3d1-15a53e1677ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441971808 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.1441971808
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3550822120
Short name T63
Test name
Test status
Simulation time 54393085 ps
CPU time 0.81 seconds
Started Mar 03 02:04:29 PM PST 24
Finished Mar 03 02:04:31 PM PST 24
Peak memory 202716 kb
Host smart-b1b4f3ca-3ba9-4f49-958c-2f07e5018a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550822120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3550822120
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1334718558
Short name T133
Test name
Test status
Simulation time 65204913 ps
CPU time 1.63 seconds
Started Mar 03 02:04:33 PM PST 24
Finished Mar 03 02:04:35 PM PST 24
Peak memory 202924 kb
Host smart-30f63fbc-1e7d-4912-a0d6-b904acd00610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334718558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.1334718558
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4056131041
Short name T142
Test name
Test status
Simulation time 337767261 ps
CPU time 3.96 seconds
Started Mar 03 02:03:59 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 202852 kb
Host smart-c783c5dd-d661-462c-80d8-c9228e47774d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056131041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.4056131041
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.268368027
Short name T141
Test name
Test status
Simulation time 210105738 ps
CPU time 4.86 seconds
Started Mar 03 02:04:04 PM PST 24
Finished Mar 03 02:04:10 PM PST 24
Peak memory 202892 kb
Host smart-d00771b4-2ec8-4993-ac09-e5e9567a590b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268368027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.268368027
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4261045196
Short name T400
Test name
Test status
Simulation time 129054697 ps
CPU time 2.05 seconds
Started Mar 03 02:04:02 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 211212 kb
Host smart-d0c5ca43-76d3-4bff-9b43-b11b36fabb35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261045196 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.4261045196
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3929401522
Short name T134
Test name
Test status
Simulation time 65196169 ps
CPU time 1.02 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 202912 kb
Host smart-2abd4ab6-8be7-4b0b-9677-3ad73d6a3c23
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929401522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3929401522
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.410129737
Short name T408
Test name
Test status
Simulation time 94504084 ps
CPU time 1.49 seconds
Started Mar 03 02:04:00 PM PST 24
Finished Mar 03 02:04:02 PM PST 24
Peak memory 202740 kb
Host smart-3518db70-d5a3-4504-bcb1-f5c301e8d6e6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=410129737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.410129737
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3792219342
Short name T379
Test name
Test status
Simulation time 473136718 ps
CPU time 4.62 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:06 PM PST 24
Peak memory 202812 kb
Host smart-972b1c1f-8f66-4249-95ca-e5ccafd80e99
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3792219342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3792219342
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3100692364
Short name T64
Test name
Test status
Simulation time 160211333 ps
CPU time 1.63 seconds
Started Mar 03 02:04:02 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 202988 kb
Host smart-f78c9375-9a08-40e0-866b-3058c4ffdfce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100692364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.3100692364
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4043198100
Short name T396
Test name
Test status
Simulation time 54415131 ps
CPU time 1.66 seconds
Started Mar 03 02:04:04 PM PST 24
Finished Mar 03 02:04:07 PM PST 24
Peak memory 202804 kb
Host smart-6566e082-7e55-4274-b2be-a915fd836c68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4043198100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4043198100
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.28543216
Short name T435
Test name
Test status
Simulation time 225175737 ps
CPU time 2.35 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:12 PM PST 24
Peak memory 202812 kb
Host smart-43a0f3d6-7f74-4f99-b1bb-f4fe02bac2f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28543216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.28543216
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.339075138
Short name T437
Test name
Test status
Simulation time 197084161 ps
CPU time 4.95 seconds
Started Mar 03 02:04:13 PM PST 24
Finished Mar 03 02:04:18 PM PST 24
Peak memory 202932 kb
Host smart-356d20f4-49a6-4f44-91fc-d66755880b33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339075138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.339075138
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3900068836
Short name T406
Test name
Test status
Simulation time 87837178 ps
CPU time 1.23 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:11 PM PST 24
Peak memory 212236 kb
Host smart-07317ba5-bd89-465c-8500-66a858c68cde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900068836 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.3900068836
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3581650849
Short name T45
Test name
Test status
Simulation time 43791555 ps
CPU time 1.01 seconds
Started Mar 03 02:04:11 PM PST 24
Finished Mar 03 02:04:12 PM PST 24
Peak memory 202776 kb
Host smart-128465b0-2000-4c9a-b8f4-d4a141a0e87b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581650849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3581650849
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.446525511
Short name T439
Test name
Test status
Simulation time 111355540 ps
CPU time 1.44 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:11 PM PST 24
Peak memory 202780 kb
Host smart-1578b268-281c-4f8a-99cb-59cdc59a4684
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=446525511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.446525511
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.439826534
Short name T431
Test name
Test status
Simulation time 98392420 ps
CPU time 2.58 seconds
Started Mar 03 02:04:11 PM PST 24
Finished Mar 03 02:04:14 PM PST 24
Peak memory 202780 kb
Host smart-663e2ae1-4df6-4d6b-96c6-94880e9b5e5b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=439826534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.439826534
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1265176218
Short name T403
Test name
Test status
Simulation time 123072243 ps
CPU time 1.58 seconds
Started Mar 03 02:04:10 PM PST 24
Finished Mar 03 02:04:12 PM PST 24
Peak memory 202940 kb
Host smart-201fdf0c-b334-41a3-9ad1-4763c2af228e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265176218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.1265176218
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1326055766
Short name T389
Test name
Test status
Simulation time 196288851 ps
CPU time 2.59 seconds
Started Mar 03 02:04:02 PM PST 24
Finished Mar 03 02:04:05 PM PST 24
Peak memory 202936 kb
Host smart-193df1fe-17bb-45fa-801f-b299003d41bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1326055766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1326055766
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3904226865
Short name T37
Test name
Test status
Simulation time 265052284 ps
CPU time 3.05 seconds
Started Mar 03 02:04:11 PM PST 24
Finished Mar 03 02:04:15 PM PST 24
Peak memory 202900 kb
Host smart-81a676f1-6696-4d08-a90b-98cb0ca4f26d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3904226865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3904226865
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.814054381
Short name T412
Test name
Test status
Simulation time 234215052 ps
CPU time 2.31 seconds
Started Mar 03 02:04:11 PM PST 24
Finished Mar 03 02:04:14 PM PST 24
Peak memory 202800 kb
Host smart-ea5aed4c-2043-418f-91f6-88b9e37afabd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814054381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.814054381
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1976322060
Short name T166
Test name
Test status
Simulation time 159447080 ps
CPU time 1.74 seconds
Started Mar 03 02:04:14 PM PST 24
Finished Mar 03 02:04:16 PM PST 24
Peak memory 211148 kb
Host smart-c7f1cbd1-f584-4bb6-9654-a39e7eac2ce5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976322060 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.1976322060
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3584409114
Short name T140
Test name
Test status
Simulation time 66108796 ps
CPU time 2.19 seconds
Started Mar 03 02:04:14 PM PST 24
Finished Mar 03 02:04:16 PM PST 24
Peak memory 202800 kb
Host smart-e5a7e978-c6aa-42a0-ada1-112ae4a97457
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3584409114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3584409114
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1003522268
Short name T433
Test name
Test status
Simulation time 249778190 ps
CPU time 2.6 seconds
Started Mar 03 02:04:12 PM PST 24
Finished Mar 03 02:04:14 PM PST 24
Peak memory 202832 kb
Host smart-317d5334-d700-4935-9caa-f06d895d0a00
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1003522268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1003522268
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3508413848
Short name T394
Test name
Test status
Simulation time 163466568 ps
CPU time 1.09 seconds
Started Mar 03 02:04:13 PM PST 24
Finished Mar 03 02:04:14 PM PST 24
Peak memory 202916 kb
Host smart-a0130520-1a9f-4f62-8ac2-52b0cea461be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508413848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.3508413848
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3190143100
Short name T386
Test name
Test status
Simulation time 186321695 ps
CPU time 2.23 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:12 PM PST 24
Peak memory 202888 kb
Host smart-82d713bf-8f09-4f3c-9cfc-0cfa6cc71532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3190143100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3190143100
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.222021650
Short name T404
Test name
Test status
Simulation time 51515866 ps
CPU time 1.78 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:11 PM PST 24
Peak memory 211152 kb
Host smart-449a9f24-c01c-4d9d-97aa-b5460cbf77e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222021650 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.222021650
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3862998114
Short name T136
Test name
Test status
Simulation time 76524465 ps
CPU time 1.14 seconds
Started Mar 03 02:04:11 PM PST 24
Finished Mar 03 02:04:13 PM PST 24
Peak memory 202772 kb
Host smart-f70f9b94-3ac0-44c9-8fec-2606fca34b4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862998114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3862998114
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3811463836
Short name T388
Test name
Test status
Simulation time 146417617 ps
CPU time 1.75 seconds
Started Mar 03 02:04:13 PM PST 24
Finished Mar 03 02:04:15 PM PST 24
Peak memory 202984 kb
Host smart-2741d74b-c7b5-449d-93a8-3b3b88e660a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811463836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.3811463836
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4073934361
Short name T167
Test name
Test status
Simulation time 265423880 ps
CPU time 2.58 seconds
Started Mar 03 02:04:10 PM PST 24
Finished Mar 03 02:04:13 PM PST 24
Peak memory 202964 kb
Host smart-a6485399-7efd-4e0a-b499-22ceda0b792f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4073934361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4073934361
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.390014222
Short name T410
Test name
Test status
Simulation time 57164630 ps
CPU time 1.48 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:11 PM PST 24
Peak memory 211108 kb
Host smart-60d64c7f-0e4d-4f03-930c-450a97387d36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390014222 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.390014222
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3761103175
Short name T380
Test name
Test status
Simulation time 63704607 ps
CPU time 1.04 seconds
Started Mar 03 02:04:11 PM PST 24
Finished Mar 03 02:04:12 PM PST 24
Peak memory 202804 kb
Host smart-23a146bb-8c36-42e6-b9c2-7a787ffaad8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761103175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3761103175
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1037835311
Short name T146
Test name
Test status
Simulation time 69399957 ps
CPU time 1.14 seconds
Started Mar 03 02:04:11 PM PST 24
Finished Mar 03 02:04:12 PM PST 24
Peak memory 202992 kb
Host smart-30740ce9-8435-468f-b8be-1809da53b368
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037835311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.1037835311
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1146345220
Short name T398
Test name
Test status
Simulation time 125696223 ps
CPU time 1.91 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:11 PM PST 24
Peak memory 202880 kb
Host smart-bae199a8-dc4d-421c-935d-0aaa1df5582c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1146345220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1146345220
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2541981595
Short name T130
Test name
Test status
Simulation time 91353472 ps
CPU time 2.3 seconds
Started Mar 03 02:04:14 PM PST 24
Finished Mar 03 02:04:16 PM PST 24
Peak memory 211132 kb
Host smart-9021d51b-58f4-48c7-b40a-0e35b64b7d1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541981595 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.2541981595
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1020800483
Short name T422
Test name
Test status
Simulation time 39717926 ps
CPU time 0.82 seconds
Started Mar 03 02:04:09 PM PST 24
Finished Mar 03 02:04:10 PM PST 24
Peak memory 202520 kb
Host smart-6453814f-b896-4c8a-8130-4c9d6847ff8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020800483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1020800483
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.677283174
Short name T393
Test name
Test status
Simulation time 42695517 ps
CPU time 0.97 seconds
Started Mar 03 02:04:11 PM PST 24
Finished Mar 03 02:04:13 PM PST 24
Peak memory 202952 kb
Host smart-041c96b2-3fc0-4517-aab6-e1b30457d8f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677283174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_cs
r_outstanding.677283174
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3848411730
Short name T432
Test name
Test status
Simulation time 242862093 ps
CPU time 3.36 seconds
Started Mar 03 02:04:14 PM PST 24
Finished Mar 03 02:04:18 PM PST 24
Peak memory 202908 kb
Host smart-a1352a24-ef4c-4dd5-9e4c-ae26c71ce012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3848411730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3848411730
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.216815075
Short name T423
Test name
Test status
Simulation time 364262669 ps
CPU time 3.17 seconds
Started Mar 03 02:04:14 PM PST 24
Finished Mar 03 02:04:17 PM PST 24
Peak memory 202904 kb
Host smart-e7f210ab-1837-4935-9563-b36643640273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=216815075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.216815075
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.917025873
Short name T395
Test name
Test status
Simulation time 43133587 ps
CPU time 1.24 seconds
Started Mar 03 02:04:17 PM PST 24
Finished Mar 03 02:04:20 PM PST 24
Peak memory 211160 kb
Host smart-26f1678e-ebfb-49d1-8bb5-7f878ab9b99d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917025873 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.917025873
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2335384710
Short name T411
Test name
Test status
Simulation time 58072440 ps
CPU time 0.96 seconds
Started Mar 03 02:04:15 PM PST 24
Finished Mar 03 02:04:16 PM PST 24
Peak memory 202932 kb
Host smart-0c0d7551-e440-4c70-96f4-432ebba1eb01
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335384710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2335384710
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2441657094
Short name T137
Test name
Test status
Simulation time 170037804 ps
CPU time 1.69 seconds
Started Mar 03 02:04:18 PM PST 24
Finished Mar 03 02:04:20 PM PST 24
Peak memory 201576 kb
Host smart-fbb5d242-e0f4-4580-8eea-0bca62efc7e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441657094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.2441657094
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1812526167
Short name T409
Test name
Test status
Simulation time 47147625 ps
CPU time 1.39 seconds
Started Mar 03 02:04:17 PM PST 24
Finished Mar 03 02:04:20 PM PST 24
Peak memory 202844 kb
Host smart-ce3e26b2-19e6-4a47-a454-c204244bef9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1812526167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1812526167
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3674063669
Short name T174
Test name
Test status
Simulation time 160166438 ps
CPU time 2.46 seconds
Started Mar 03 02:04:18 PM PST 24
Finished Mar 03 02:04:21 PM PST 24
Peak memory 202916 kb
Host smart-4f08055f-010a-4458-8bec-fdef637be59f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3674063669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3674063669
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1237154271
Short name T428
Test name
Test status
Simulation time 49411060 ps
CPU time 1.11 seconds
Started Mar 03 02:04:18 PM PST 24
Finished Mar 03 02:04:20 PM PST 24
Peak memory 202912 kb
Host smart-75f4aed8-3206-4ad3-9194-99589f176e66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237154271 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.1237154271
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4230873197
Short name T144
Test name
Test status
Simulation time 88935288 ps
CPU time 1.25 seconds
Started Mar 03 02:04:18 PM PST 24
Finished Mar 03 02:04:20 PM PST 24
Peak memory 202876 kb
Host smart-5715b361-bf98-4393-9d4e-8f03fc58ef9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230873197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4230873197
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2746400281
Short name T62
Test name
Test status
Simulation time 159027210 ps
CPU time 1.69 seconds
Started Mar 03 02:04:18 PM PST 24
Finished Mar 03 02:04:20 PM PST 24
Peak memory 201776 kb
Host smart-52425ebe-7add-4067-af8e-d42d6e0756a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746400281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.2746400281
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.125978590
Short name T124
Test name
Test status
Simulation time 190786280 ps
CPU time 3.37 seconds
Started Mar 03 02:04:15 PM PST 24
Finished Mar 03 02:04:19 PM PST 24
Peak memory 202956 kb
Host smart-fa5f2013-2091-48b8-8db6-866e7ba1f2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=125978590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.125978590
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3093645444
Short name T399
Test name
Test status
Simulation time 277651490 ps
CPU time 3.1 seconds
Started Mar 03 02:04:17 PM PST 24
Finished Mar 03 02:04:22 PM PST 24
Peak memory 202940 kb
Host smart-55ffdf37-6361-45aa-967e-9170e5c42e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3093645444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3093645444
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.in_trans.229466896
Short name T112
Test name
Test status
Simulation time 8388275030 ps
CPU time 8.04 seconds
Started Mar 03 02:22:59 PM PST 24
Finished Mar 03 02:23:07 PM PST 24
Peak memory 202484 kb
Host smart-bd6f0455-7b75-478e-a23d-3e18db85ef1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22946
6896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.in_trans.229466896
Directory /workspace/0.in_trans/latest

Test location /workspace/coverage/default/0.setup_trans_ignored.751236355
Short name T289
Test name
Test status
Simulation time 8357818573 ps
CPU time 7.31 seconds
Started Mar 03 02:23:03 PM PST 24
Finished Mar 03 02:23:10 PM PST 24
Peak memory 202668 kb
Host smart-61ceb793-45c7-4f8f-9985-c17ede7541d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75123
6355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.setup_trans_ignored.751236355
Directory /workspace/0.setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2162487750
Short name T368
Test name
Test status
Simulation time 8369492501 ps
CPU time 9.48 seconds
Started Mar 03 02:22:57 PM PST 24
Finished Mar 03 02:23:07 PM PST 24
Peak memory 202616 kb
Host smart-db698d9e-2d90-4b34-bd6e-b246a40efaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21624
87750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2162487750
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2757094696
Short name T310
Test name
Test status
Simulation time 61296407 ps
CPU time 1.77 seconds
Started Mar 03 02:23:03 PM PST 24
Finished Mar 03 02:23:05 PM PST 24
Peak memory 202784 kb
Host smart-d0276582-33e0-407f-9710-bb60776f4d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27570
94696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2757094696
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1499711711
Short name T259
Test name
Test status
Simulation time 8392061998 ps
CPU time 7.18 seconds
Started Mar 03 02:22:57 PM PST 24
Finished Mar 03 02:23:04 PM PST 24
Peak memory 202608 kb
Host smart-01f0f1c7-e342-4c24-9623-81251c977cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14997
11711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1499711711
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.in_trans.1249779237
Short name T52
Test name
Test status
Simulation time 8401554040 ps
CPU time 7.4 seconds
Started Mar 03 02:23:04 PM PST 24
Finished Mar 03 02:23:11 PM PST 24
Peak memory 202616 kb
Host smart-2ac9ed63-12b4-4700-b95f-70add06704f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12497
79237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.in_trans.1249779237
Directory /workspace/1.in_trans/latest

Test location /workspace/coverage/default/1.setup_trans_ignored.3352003513
Short name T196
Test name
Test status
Simulation time 8364765079 ps
CPU time 7.1 seconds
Started Mar 03 02:23:03 PM PST 24
Finished Mar 03 02:23:10 PM PST 24
Peak memory 202620 kb
Host smart-9aa20dca-dc6a-400d-b720-5fc925c3367d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33520
03513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.setup_trans_ignored.3352003513
Directory /workspace/1.setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2082067441
Short name T239
Test name
Test status
Simulation time 8371600919 ps
CPU time 9.55 seconds
Started Mar 03 02:23:01 PM PST 24
Finished Mar 03 02:23:10 PM PST 24
Peak memory 202524 kb
Host smart-284286e9-d79a-467d-b684-0b14294562eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20820
67441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2082067441
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3922177197
Short name T158
Test name
Test status
Simulation time 91647068 ps
CPU time 1.26 seconds
Started Mar 03 02:23:05 PM PST 24
Finished Mar 03 02:23:07 PM PST 24
Peak memory 202780 kb
Host smart-1c1f0f65-640f-40d7-bf8a-c4288e1ed9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39221
77197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3922177197
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_smoke.472810837
Short name T255
Test name
Test status
Simulation time 8369657516 ps
CPU time 8.05 seconds
Started Mar 03 02:23:04 PM PST 24
Finished Mar 03 02:23:12 PM PST 24
Peak memory 202608 kb
Host smart-3783bf1d-455f-415b-b925-84f4bff04907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47281
0837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.472810837
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.in_trans.1044424848
Short name T247
Test name
Test status
Simulation time 8413170440 ps
CPU time 7.31 seconds
Started Mar 03 02:23:25 PM PST 24
Finished Mar 03 02:23:32 PM PST 24
Peak memory 202540 kb
Host smart-2c1afe31-8889-4e4b-9066-28266e61fe31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10444
24848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.in_trans.1044424848
Directory /workspace/10.in_trans/latest

Test location /workspace/coverage/default/10.setup_trans_ignored.1679731249
Short name T334
Test name
Test status
Simulation time 8354365818 ps
CPU time 7.57 seconds
Started Mar 03 02:23:24 PM PST 24
Finished Mar 03 02:23:32 PM PST 24
Peak memory 202580 kb
Host smart-58662677-e1f7-42b6-af11-e80e912f2cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16797
31249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.setup_trans_ignored.1679731249
Directory /workspace/10.setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.4279219257
Short name T31
Test name
Test status
Simulation time 8370985498 ps
CPU time 7.75 seconds
Started Mar 03 02:23:28 PM PST 24
Finished Mar 03 02:23:36 PM PST 24
Peak memory 202608 kb
Host smart-89d77c09-64e9-4247-bdd6-933839429929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42792
19257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.4279219257
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3818102180
Short name T371
Test name
Test status
Simulation time 33713179 ps
CPU time 1.04 seconds
Started Mar 03 02:23:27 PM PST 24
Finished Mar 03 02:23:28 PM PST 24
Peak memory 202724 kb
Host smart-8eb817ae-36cc-4a33-8afe-4d4088ec1e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38181
02180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3818102180
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3391417533
Short name T344
Test name
Test status
Simulation time 8433791485 ps
CPU time 7.43 seconds
Started Mar 03 02:23:26 PM PST 24
Finished Mar 03 02:23:34 PM PST 24
Peak memory 202604 kb
Host smart-d7385033-6cef-4801-a209-5293de1bcfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33914
17533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3391417533
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.in_trans.2455030895
Short name T356
Test name
Test status
Simulation time 8457623825 ps
CPU time 7.52 seconds
Started Mar 03 02:23:33 PM PST 24
Finished Mar 03 02:23:41 PM PST 24
Peak memory 202608 kb
Host smart-f667f198-ea91-46b7-b777-a11dbc8b8c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24550
30895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.in_trans.2455030895
Directory /workspace/11.in_trans/latest

Test location /workspace/coverage/default/11.setup_trans_ignored.3406938965
Short name T268
Test name
Test status
Simulation time 8359536211 ps
CPU time 7.54 seconds
Started Mar 03 02:23:29 PM PST 24
Finished Mar 03 02:23:37 PM PST 24
Peak memory 202572 kb
Host smart-3ac2f82b-3ec9-4b71-9f3d-6e81b7dd6ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
38965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.setup_trans_ignored.3406938965
Directory /workspace/11.setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.873550432
Short name T28
Test name
Test status
Simulation time 8393275434 ps
CPU time 7.16 seconds
Started Mar 03 02:23:31 PM PST 24
Finished Mar 03 02:23:38 PM PST 24
Peak memory 202616 kb
Host smart-ef0c7266-566f-4992-a9bf-4dae86c84831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87355
0432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.873550432
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1034403166
Short name T328
Test name
Test status
Simulation time 176793579 ps
CPU time 1.94 seconds
Started Mar 03 02:23:30 PM PST 24
Finished Mar 03 02:23:32 PM PST 24
Peak memory 202756 kb
Host smart-dc4bfc94-5e1e-4bae-8490-bbe779ad9335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10344
03166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1034403166
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1371726537
Short name T243
Test name
Test status
Simulation time 8369366615 ps
CPU time 9.41 seconds
Started Mar 03 02:23:29 PM PST 24
Finished Mar 03 02:23:39 PM PST 24
Peak memory 202644 kb
Host smart-62e99830-d2b3-4f73-934b-d08f9b53cd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717
26537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1371726537
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.in_trans.2200558283
Short name T113
Test name
Test status
Simulation time 8437196389 ps
CPU time 7.97 seconds
Started Mar 03 02:23:31 PM PST 24
Finished Mar 03 02:23:39 PM PST 24
Peak memory 202600 kb
Host smart-c94efed8-5dad-4673-acaa-5e7b23a62155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22005
58283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.in_trans.2200558283
Directory /workspace/12.in_trans/latest

Test location /workspace/coverage/default/12.setup_trans_ignored.2680467580
Short name T218
Test name
Test status
Simulation time 8355801404 ps
CPU time 7.96 seconds
Started Mar 03 02:23:31 PM PST 24
Finished Mar 03 02:23:39 PM PST 24
Peak memory 202652 kb
Host smart-893d5627-9a03-413c-935d-94f2dc33a21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26804
67580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.setup_trans_ignored.2680467580
Directory /workspace/12.setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1019973946
Short name T309
Test name
Test status
Simulation time 8381365646 ps
CPU time 7.4 seconds
Started Mar 03 02:23:32 PM PST 24
Finished Mar 03 02:23:40 PM PST 24
Peak memory 202628 kb
Host smart-90d95d57-0bc8-45b7-b97b-8df10e3db678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10199
73946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1019973946
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.170494539
Short name T204
Test name
Test status
Simulation time 168958091 ps
CPU time 1.99 seconds
Started Mar 03 02:23:30 PM PST 24
Finished Mar 03 02:23:32 PM PST 24
Peak memory 202652 kb
Host smart-c3c6606c-5ba8-484c-ade3-9e077cff0fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17049
4539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.170494539
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3569647771
Short name T273
Test name
Test status
Simulation time 8371854613 ps
CPU time 7.19 seconds
Started Mar 03 02:23:31 PM PST 24
Finished Mar 03 02:23:39 PM PST 24
Peak memory 202640 kb
Host smart-aad0174a-840d-4926-bcba-ee0e47a04c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35696
47771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3569647771
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.in_trans.58158446
Short name T107
Test name
Test status
Simulation time 8399851323 ps
CPU time 7.41 seconds
Started Mar 03 02:23:35 PM PST 24
Finished Mar 03 02:23:43 PM PST 24
Peak memory 202656 kb
Host smart-e22f1f53-cac9-4659-8bfa-77ebc4caef38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58158
446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.in_trans.58158446
Directory /workspace/13.in_trans/latest

Test location /workspace/coverage/default/13.setup_trans_ignored.1256322140
Short name T210
Test name
Test status
Simulation time 8371274733 ps
CPU time 9.58 seconds
Started Mar 03 02:23:32 PM PST 24
Finished Mar 03 02:23:43 PM PST 24
Peak memory 202632 kb
Host smart-6d7c2a90-31da-4bd6-9a1a-f89cf222dbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12563
22140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.setup_trans_ignored.1256322140
Directory /workspace/13.setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.692746087
Short name T215
Test name
Test status
Simulation time 8376848113 ps
CPU time 8.47 seconds
Started Mar 03 02:23:34 PM PST 24
Finished Mar 03 02:23:43 PM PST 24
Peak memory 202628 kb
Host smart-94124ba1-abc9-45b1-84b6-027b50a98c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69274
6087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.692746087
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2948999353
Short name T275
Test name
Test status
Simulation time 168789093 ps
CPU time 1.92 seconds
Started Mar 03 02:23:45 PM PST 24
Finished Mar 03 02:23:47 PM PST 24
Peak memory 202892 kb
Host smart-624062c9-9bc9-49d7-83b8-19b020d5d0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29489
99353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2948999353
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2038807906
Short name T303
Test name
Test status
Simulation time 8448718371 ps
CPU time 7.2 seconds
Started Mar 03 02:23:35 PM PST 24
Finished Mar 03 02:23:43 PM PST 24
Peak memory 202552 kb
Host smart-3f9575f8-4aee-4153-901b-1eae8cae727f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20388
07906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2038807906
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1385325369
Short name T188
Test name
Test status
Simulation time 8400635633 ps
CPU time 9.1 seconds
Started Mar 03 02:23:33 PM PST 24
Finished Mar 03 02:23:42 PM PST 24
Peak memory 202596 kb
Host smart-bbe8a92e-41b6-4a61-a768-b1402e8e9f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13853
25369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1385325369
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.in_trans.2929022566
Short name T119
Test name
Test status
Simulation time 8443156018 ps
CPU time 9.87 seconds
Started Mar 03 02:23:34 PM PST 24
Finished Mar 03 02:23:45 PM PST 24
Peak memory 202560 kb
Host smart-eb8e4240-1f54-4047-811e-ef04eedc63a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29290
22566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.in_trans.2929022566
Directory /workspace/14.in_trans/latest

Test location /workspace/coverage/default/14.setup_trans_ignored.1658868466
Short name T361
Test name
Test status
Simulation time 8357881761 ps
CPU time 8.03 seconds
Started Mar 03 02:23:37 PM PST 24
Finished Mar 03 02:23:45 PM PST 24
Peak memory 202640 kb
Host smart-c7537cb6-b4ee-40f2-be0f-8ff02240f7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16588
68466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.setup_trans_ignored.1658868466
Directory /workspace/14.setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2305244759
Short name T30
Test name
Test status
Simulation time 8368910281 ps
CPU time 7.35 seconds
Started Mar 03 02:23:35 PM PST 24
Finished Mar 03 02:23:42 PM PST 24
Peak memory 202548 kb
Host smart-414fb32b-03d8-4465-8603-9db7f88da45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
44759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2305244759
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3546664783
Short name T349
Test name
Test status
Simulation time 8418686645 ps
CPU time 8.79 seconds
Started Mar 03 02:23:34 PM PST 24
Finished Mar 03 02:23:44 PM PST 24
Peak memory 202592 kb
Host smart-9f7578d0-5f51-4425-89a4-3ada4d746967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35466
64783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3546664783
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2777755540
Short name T181
Test name
Test status
Simulation time 8377041127 ps
CPU time 7.07 seconds
Started Mar 03 02:23:35 PM PST 24
Finished Mar 03 02:23:43 PM PST 24
Peak memory 202584 kb
Host smart-916c7467-d998-456a-88ad-82609fe0ae4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27777
55540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2777755540
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.in_trans.1173864673
Short name T106
Test name
Test status
Simulation time 8449298180 ps
CPU time 8.14 seconds
Started Mar 03 02:23:41 PM PST 24
Finished Mar 03 02:23:49 PM PST 24
Peak memory 202628 kb
Host smart-320ba600-b9bf-4897-8245-3dbbf926c0e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11738
64673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.in_trans.1173864673
Directory /workspace/15.in_trans/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2455086303
Short name T8
Test name
Test status
Simulation time 8377628873 ps
CPU time 10.05 seconds
Started Mar 03 02:23:45 PM PST 24
Finished Mar 03 02:23:55 PM PST 24
Peak memory 202848 kb
Host smart-7eb30d1a-d53a-4d14-9bdf-61d79e233599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24550
86303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2455086303
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1125733305
Short name T153
Test name
Test status
Simulation time 258693470 ps
CPU time 2.23 seconds
Started Mar 03 02:23:38 PM PST 24
Finished Mar 03 02:23:45 PM PST 24
Peak memory 202792 kb
Host smart-2ace41b1-62b0-4fdd-90a4-76c05f0d684b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11257
33305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1125733305
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.4196849412
Short name T352
Test name
Test status
Simulation time 8436644108 ps
CPU time 7.72 seconds
Started Mar 03 02:23:45 PM PST 24
Finished Mar 03 02:23:53 PM PST 24
Peak memory 202764 kb
Host smart-b71cc688-6110-4cea-91dd-9df492fc301a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41968
49412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.4196849412
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2303221650
Short name T236
Test name
Test status
Simulation time 8372420147 ps
CPU time 8.11 seconds
Started Mar 03 02:23:39 PM PST 24
Finished Mar 03 02:23:47 PM PST 24
Peak memory 202604 kb
Host smart-53e694ab-b469-4558-b7fe-82c9f2209dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23032
21650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2303221650
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.in_trans.564350978
Short name T206
Test name
Test status
Simulation time 8432810263 ps
CPU time 9.24 seconds
Started Mar 03 02:23:36 PM PST 24
Finished Mar 03 02:23:46 PM PST 24
Peak memory 202496 kb
Host smart-8731533a-d7cc-4f60-bcb3-38d708e8be61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56435
0978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.in_trans.564350978
Directory /workspace/16.in_trans/latest

Test location /workspace/coverage/default/16.setup_trans_ignored.2045208702
Short name T226
Test name
Test status
Simulation time 8369110117 ps
CPU time 7.88 seconds
Started Mar 03 02:23:45 PM PST 24
Finished Mar 03 02:23:53 PM PST 24
Peak memory 202824 kb
Host smart-2b80d379-3a7a-4e1e-bcd1-ba3c7f9f6a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20452
08702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.setup_trans_ignored.2045208702
Directory /workspace/16.setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3995173607
Short name T198
Test name
Test status
Simulation time 8373677650 ps
CPU time 7.68 seconds
Started Mar 03 02:23:41 PM PST 24
Finished Mar 03 02:23:49 PM PST 24
Peak memory 202608 kb
Host smart-1eddea22-ebc8-4966-be45-5b7bf7471aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39951
73607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3995173607
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.940044049
Short name T266
Test name
Test status
Simulation time 172323754 ps
CPU time 1.46 seconds
Started Mar 03 02:23:42 PM PST 24
Finished Mar 03 02:23:43 PM PST 24
Peak memory 202716 kb
Host smart-aaa33f9b-7273-478c-ab15-9db5f51be551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94004
4049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.940044049
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2453391314
Short name T85
Test name
Test status
Simulation time 8430686399 ps
CPU time 7.61 seconds
Started Mar 03 02:23:41 PM PST 24
Finished Mar 03 02:23:48 PM PST 24
Peak memory 202596 kb
Host smart-7bca2a8a-9ff5-437d-906a-bdcdf7af063f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24533
91314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2453391314
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2114189119
Short name T294
Test name
Test status
Simulation time 8379018578 ps
CPU time 8.99 seconds
Started Mar 03 02:23:34 PM PST 24
Finished Mar 03 02:23:44 PM PST 24
Peak memory 202612 kb
Host smart-c681b816-e486-44a5-8713-34098dd5d18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21141
89119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2114189119
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3038784607
Short name T221
Test name
Test status
Simulation time 8371828958 ps
CPU time 7.11 seconds
Started Mar 03 02:23:34 PM PST 24
Finished Mar 03 02:23:42 PM PST 24
Peak memory 202616 kb
Host smart-5616eb1a-8fa2-455b-9813-6c98d5397a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30387
84607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3038784607
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.in_trans.3210964979
Short name T122
Test name
Test status
Simulation time 8413297874 ps
CPU time 7.7 seconds
Started Mar 03 02:23:42 PM PST 24
Finished Mar 03 02:23:50 PM PST 24
Peak memory 202560 kb
Host smart-b8f26159-a8c1-45cc-a61b-9c582dcd9520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
64979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.in_trans.3210964979
Directory /workspace/17.in_trans/latest

Test location /workspace/coverage/default/17.setup_trans_ignored.3372484602
Short name T302
Test name
Test status
Simulation time 8359535600 ps
CPU time 7.6 seconds
Started Mar 03 02:23:40 PM PST 24
Finished Mar 03 02:23:48 PM PST 24
Peak memory 202640 kb
Host smart-9a6b8124-5ab6-4f39-81e2-028ce69c97e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33724
84602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.setup_trans_ignored.3372484602
Directory /workspace/17.setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.598399981
Short name T305
Test name
Test status
Simulation time 8377470564 ps
CPU time 7.05 seconds
Started Mar 03 02:23:41 PM PST 24
Finished Mar 03 02:23:48 PM PST 24
Peak memory 202580 kb
Host smart-e3bf7fce-db8d-4e58-af29-7aa4a7ca4240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59839
9981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.598399981
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.4086268291
Short name T345
Test name
Test status
Simulation time 168637062 ps
CPU time 1.41 seconds
Started Mar 03 02:23:44 PM PST 24
Finished Mar 03 02:23:46 PM PST 24
Peak memory 202720 kb
Host smart-9fb449cb-edb8-4218-b726-98b64b039467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40862
68291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4086268291
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3152211669
Short name T251
Test name
Test status
Simulation time 8363678164 ps
CPU time 7.8 seconds
Started Mar 03 02:23:43 PM PST 24
Finished Mar 03 02:23:51 PM PST 24
Peak memory 202604 kb
Host smart-52314a90-b785-4309-a891-996a28103f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31522
11669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3152211669
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.setup_trans_ignored.270749829
Short name T274
Test name
Test status
Simulation time 8359320100 ps
CPU time 7.99 seconds
Started Mar 03 02:23:44 PM PST 24
Finished Mar 03 02:23:52 PM PST 24
Peak memory 202640 kb
Host smart-a8fccf4d-5b7c-465f-beb0-66c0569cb2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27074
9829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.setup_trans_ignored.270749829
Directory /workspace/18.setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.902618335
Short name T271
Test name
Test status
Simulation time 8374486952 ps
CPU time 9.5 seconds
Started Mar 03 02:23:43 PM PST 24
Finished Mar 03 02:23:52 PM PST 24
Peak memory 202648 kb
Host smart-619b162b-c0cc-4de6-92a8-078261663d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90261
8335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.902618335
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.779076985
Short name T212
Test name
Test status
Simulation time 196440337 ps
CPU time 2.1 seconds
Started Mar 03 02:23:41 PM PST 24
Finished Mar 03 02:23:43 PM PST 24
Peak memory 202724 kb
Host smart-5721981f-93d6-483c-adb3-02b7c2c059a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77907
6985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.779076985
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3797733177
Short name T254
Test name
Test status
Simulation time 8371004960 ps
CPU time 7.81 seconds
Started Mar 03 02:24:19 PM PST 24
Finished Mar 03 02:24:27 PM PST 24
Peak memory 202616 kb
Host smart-01ba2fe4-52aa-4c00-8053-aaee07c44a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37977
33177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3797733177
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.497993560
Short name T342
Test name
Test status
Simulation time 54637680 ps
CPU time 1.48 seconds
Started Mar 03 02:24:15 PM PST 24
Finished Mar 03 02:24:17 PM PST 24
Peak memory 202724 kb
Host smart-be4a7616-3911-4eef-9d50-f7b95341ebda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49799
3560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.497993560
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.4051251936
Short name T14
Test name
Test status
Simulation time 8448125172 ps
CPU time 9.17 seconds
Started Mar 03 02:23:53 PM PST 24
Finished Mar 03 02:24:03 PM PST 24
Peak memory 202540 kb
Host smart-58563af5-151c-4421-a331-19ae43653c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40512
51936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.4051251936
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1059119735
Short name T240
Test name
Test status
Simulation time 8427348035 ps
CPU time 7.86 seconds
Started Mar 03 02:24:03 PM PST 24
Finished Mar 03 02:24:12 PM PST 24
Peak memory 202616 kb
Host smart-d184c591-e5d4-46a4-b0d4-aec625bb5b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10591
19735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1059119735
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1941537059
Short name T238
Test name
Test status
Simulation time 8374479200 ps
CPU time 7.93 seconds
Started Mar 03 02:23:43 PM PST 24
Finished Mar 03 02:23:52 PM PST 24
Peak memory 202608 kb
Host smart-1762acda-f96e-49f7-8dc4-8f4b35f79634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19415
37059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1941537059
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.in_trans.2652344750
Short name T105
Test name
Test status
Simulation time 8398078437 ps
CPU time 8.98 seconds
Started Mar 03 02:23:10 PM PST 24
Finished Mar 03 02:23:19 PM PST 24
Peak memory 202596 kb
Host smart-44c2af70-6331-4a40-9b3f-13fbc82f5a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26523
44750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.in_trans.2652344750
Directory /workspace/2.in_trans/latest

Test location /workspace/coverage/default/2.setup_trans_ignored.1370965378
Short name T214
Test name
Test status
Simulation time 8360132185 ps
CPU time 7.72 seconds
Started Mar 03 02:23:02 PM PST 24
Finished Mar 03 02:23:10 PM PST 24
Peak memory 202640 kb
Host smart-1875af36-46fa-42df-a9f2-00f35d823b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13709
65378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.setup_trans_ignored.1370965378
Directory /workspace/2.setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3786476791
Short name T265
Test name
Test status
Simulation time 8383388132 ps
CPU time 7.03 seconds
Started Mar 03 02:23:03 PM PST 24
Finished Mar 03 02:23:10 PM PST 24
Peak memory 202592 kb
Host smart-9297db61-2968-4c64-89e7-52b9ac5979e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37864
76791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3786476791
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3237560098
Short name T76
Test name
Test status
Simulation time 8391890603 ps
CPU time 7.8 seconds
Started Mar 03 02:23:08 PM PST 24
Finished Mar 03 02:23:16 PM PST 24
Peak memory 202616 kb
Host smart-fd7ddfa4-ba17-451a-9f83-8e19dcc3ddc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32375
60098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3237560098
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.116131003
Short name T104
Test name
Test status
Simulation time 8376865684 ps
CPU time 7.3 seconds
Started Mar 03 02:23:16 PM PST 24
Finished Mar 03 02:23:23 PM PST 24
Peak memory 202524 kb
Host smart-ecf56df0-b646-4783-a6c6-0220b997218a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11613
1003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.116131003
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1815248030
Short name T40
Test name
Test status
Simulation time 188210893 ps
CPU time 1.09 seconds
Started Mar 03 02:23:10 PM PST 24
Finished Mar 03 02:23:11 PM PST 24
Peak memory 217252 kb
Host smart-e3347dab-8f79-41dd-915b-7b7de8167d94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1815248030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1815248030
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_smoke.981677658
Short name T374
Test name
Test status
Simulation time 8371516572 ps
CPU time 7.23 seconds
Started Mar 03 02:23:03 PM PST 24
Finished Mar 03 02:23:10 PM PST 24
Peak memory 202536 kb
Host smart-f6d730f4-3091-4671-afb6-6af46284868b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98167
7658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.981677658
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.in_trans.1077409928
Short name T355
Test name
Test status
Simulation time 8405550494 ps
CPU time 7.84 seconds
Started Mar 03 02:23:56 PM PST 24
Finished Mar 03 02:24:09 PM PST 24
Peak memory 202532 kb
Host smart-76f2afdd-f9f3-41dc-acfd-1ba85ac1e018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10774
09928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.in_trans.1077409928
Directory /workspace/20.in_trans/latest

Test location /workspace/coverage/default/20.setup_trans_ignored.1724506156
Short name T193
Test name
Test status
Simulation time 8354547719 ps
CPU time 7.28 seconds
Started Mar 03 02:23:58 PM PST 24
Finished Mar 03 02:24:05 PM PST 24
Peak memory 202640 kb
Host smart-cfa36b08-492a-4f96-b476-295c3b6d3763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
06156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.setup_trans_ignored.1724506156
Directory /workspace/20.setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2778684135
Short name T187
Test name
Test status
Simulation time 8370282151 ps
CPU time 8.75 seconds
Started Mar 03 02:23:55 PM PST 24
Finished Mar 03 02:24:05 PM PST 24
Peak memory 202600 kb
Host smart-1b8803b4-216b-41a1-a93b-9c5304b03ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
84135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2778684135
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2854025769
Short name T346
Test name
Test status
Simulation time 41599113 ps
CPU time 1.13 seconds
Started Mar 03 02:23:57 PM PST 24
Finished Mar 03 02:23:59 PM PST 24
Peak memory 202712 kb
Host smart-edb7a798-2b28-4246-b01c-204fdbc51175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28540
25769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2854025769
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2518174361
Short name T228
Test name
Test status
Simulation time 8393085130 ps
CPU time 7.84 seconds
Started Mar 03 02:24:02 PM PST 24
Finished Mar 03 02:24:10 PM PST 24
Peak memory 202612 kb
Host smart-0a47816d-8b16-4693-b0ed-caaa1a715b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25181
74361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2518174361
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1746647875
Short name T249
Test name
Test status
Simulation time 8374284166 ps
CPU time 7.25 seconds
Started Mar 03 02:23:58 PM PST 24
Finished Mar 03 02:24:05 PM PST 24
Peak memory 202596 kb
Host smart-5e0544df-fb62-4832-9e42-1a88da78c6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17466
47875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1746647875
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.setup_trans_ignored.421092
Short name T326
Test name
Test status
Simulation time 8361216086 ps
CPU time 8.78 seconds
Started Mar 03 02:23:50 PM PST 24
Finished Mar 03 02:23:59 PM PST 24
Peak memory 202644 kb
Host smart-f6da9883-8e8c-4450-9ba7-8f054b3d6c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
2 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.setup_trans_ignored.421092
Directory /workspace/21.setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2124709406
Short name T285
Test name
Test status
Simulation time 8371942024 ps
CPU time 8.5 seconds
Started Mar 03 02:23:50 PM PST 24
Finished Mar 03 02:23:59 PM PST 24
Peak memory 202544 kb
Host smart-4623bd7e-440c-4e91-9513-9a803996a4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21247
09406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2124709406
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1000255411
Short name T154
Test name
Test status
Simulation time 40741075 ps
CPU time 1.08 seconds
Started Mar 03 02:23:51 PM PST 24
Finished Mar 03 02:23:52 PM PST 24
Peak memory 202800 kb
Host smart-c8b8f38b-7675-4fe2-953e-ee2b1700ef49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10002
55411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1000255411
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3063938978
Short name T296
Test name
Test status
Simulation time 8401903828 ps
CPU time 7.28 seconds
Started Mar 03 02:23:59 PM PST 24
Finished Mar 03 02:24:07 PM PST 24
Peak memory 202600 kb
Host smart-16200974-fc73-46be-9898-a42616e35e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30639
38978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3063938978
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3293657816
Short name T115
Test name
Test status
Simulation time 8431926507 ps
CPU time 8.5 seconds
Started Mar 03 02:24:00 PM PST 24
Finished Mar 03 02:24:08 PM PST 24
Peak memory 202604 kb
Host smart-1ac7348a-4ac0-49f6-a47b-2f9ec81dfaa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
57816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3293657816
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3634123593
Short name T9
Test name
Test status
Simulation time 8368107660 ps
CPU time 7.18 seconds
Started Mar 03 02:23:59 PM PST 24
Finished Mar 03 02:24:06 PM PST 24
Peak memory 202652 kb
Host smart-e524a234-0d2a-4f51-bfe0-f0cfe0453d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36341
23593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3634123593
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.in_trans.3910247364
Short name T110
Test name
Test status
Simulation time 8504676428 ps
CPU time 9.15 seconds
Started Mar 03 02:23:58 PM PST 24
Finished Mar 03 02:24:07 PM PST 24
Peak memory 202628 kb
Host smart-685a0b30-1fb9-424c-a502-dac153699937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39102
47364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.in_trans.3910247364
Directory /workspace/22.in_trans/latest

Test location /workspace/coverage/default/22.setup_trans_ignored.280438838
Short name T365
Test name
Test status
Simulation time 8372638987 ps
CPU time 8.91 seconds
Started Mar 03 02:24:04 PM PST 24
Finished Mar 03 02:24:13 PM PST 24
Peak memory 202648 kb
Host smart-525f609e-7302-4bbc-b428-1f9cac96dcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28043
8838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.setup_trans_ignored.280438838
Directory /workspace/22.setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2206397838
Short name T165
Test name
Test status
Simulation time 8389506528 ps
CPU time 7.4 seconds
Started Mar 03 02:23:58 PM PST 24
Finished Mar 03 02:24:05 PM PST 24
Peak memory 202656 kb
Host smart-76f37af6-a2ec-4d89-83dc-6e3936b7fea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22063
97838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2206397838
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.4072807602
Short name T164
Test name
Test status
Simulation time 174747873 ps
CPU time 1.58 seconds
Started Mar 03 02:24:02 PM PST 24
Finished Mar 03 02:24:03 PM PST 24
Peak memory 202644 kb
Host smart-d7e6d378-f324-4b8a-adc2-5c0b2d900676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40728
07602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.4072807602
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2714253662
Short name T351
Test name
Test status
Simulation time 8368016539 ps
CPU time 7.26 seconds
Started Mar 03 02:23:58 PM PST 24
Finished Mar 03 02:24:06 PM PST 24
Peak memory 202568 kb
Host smart-4a8ddf19-3edf-4a12-b7b4-16f7890665f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27142
53662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2714253662
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/23.setup_trans_ignored.732809307
Short name T24
Test name
Test status
Simulation time 8358373016 ps
CPU time 8.35 seconds
Started Mar 03 02:24:06 PM PST 24
Finished Mar 03 02:24:15 PM PST 24
Peak memory 202652 kb
Host smart-36fcd942-b126-4b7f-9375-6f174625b537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73280
9307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.setup_trans_ignored.732809307
Directory /workspace/23.setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2942354357
Short name T32
Test name
Test status
Simulation time 8373340902 ps
CPU time 7.15 seconds
Started Mar 03 02:24:07 PM PST 24
Finished Mar 03 02:24:15 PM PST 24
Peak memory 202604 kb
Host smart-e69b9b34-e87d-4e13-b95f-20f7893642b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29423
54357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2942354357
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3864970944
Short name T70
Test name
Test status
Simulation time 8412870547 ps
CPU time 7.86 seconds
Started Mar 03 02:24:00 PM PST 24
Finished Mar 03 02:24:08 PM PST 24
Peak memory 202604 kb
Host smart-6b0ce701-6d19-4ae4-a33b-4a1d3a1c5523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649
70944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3864970944
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.456186864
Short name T248
Test name
Test status
Simulation time 8438829526 ps
CPU time 8.76 seconds
Started Mar 03 02:24:08 PM PST 24
Finished Mar 03 02:24:17 PM PST 24
Peak memory 202572 kb
Host smart-885f4f17-1041-4d56-9060-1d34935600bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45618
6864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.456186864
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3956268018
Short name T314
Test name
Test status
Simulation time 8415460049 ps
CPU time 8.89 seconds
Started Mar 03 02:24:06 PM PST 24
Finished Mar 03 02:24:15 PM PST 24
Peak memory 202612 kb
Host smart-dfa8eb61-d79d-4b04-bf4e-fb98a30c1bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39562
68018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3956268018
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.setup_trans_ignored.2763612816
Short name T53
Test name
Test status
Simulation time 8362359632 ps
CPU time 9.36 seconds
Started Mar 03 02:24:03 PM PST 24
Finished Mar 03 02:24:13 PM PST 24
Peak memory 202640 kb
Host smart-3a6bd976-5885-472d-aeca-ffb00df1a6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
12816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.setup_trans_ignored.2763612816
Directory /workspace/24.setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1993845323
Short name T231
Test name
Test status
Simulation time 8377624904 ps
CPU time 7.66 seconds
Started Mar 03 02:24:15 PM PST 24
Finished Mar 03 02:24:23 PM PST 24
Peak memory 202652 kb
Host smart-9f2bead7-6ef1-4630-b3c7-2060b46fe4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19938
45323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1993845323
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2329087991
Short name T179
Test name
Test status
Simulation time 114432626 ps
CPU time 1.41 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:25 PM PST 24
Peak memory 202744 kb
Host smart-f26e24b2-231a-4a0a-9654-a4961c855bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23290
87991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2329087991
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1335749651
Short name T94
Test name
Test status
Simulation time 8441904636 ps
CPU time 8.37 seconds
Started Mar 03 02:24:09 PM PST 24
Finished Mar 03 02:24:18 PM PST 24
Peak memory 202604 kb
Host smart-5eb0088a-5314-40c7-83e5-24d7023e29ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13357
49651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1335749651
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.4218815904
Short name T123
Test name
Test status
Simulation time 8443918872 ps
CPU time 7.47 seconds
Started Mar 03 02:24:09 PM PST 24
Finished Mar 03 02:24:16 PM PST 24
Peak memory 202608 kb
Host smart-ab63f92c-c6be-423e-a0c7-a43575613baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42188
15904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.4218815904
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_smoke.4272395225
Short name T57
Test name
Test status
Simulation time 8370042837 ps
CPU time 7.65 seconds
Started Mar 03 02:24:19 PM PST 24
Finished Mar 03 02:24:27 PM PST 24
Peak memory 202604 kb
Host smart-d15b2305-28b0-41dd-9b47-0375050733c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723
95225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.4272395225
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.in_trans.6190180
Short name T190
Test name
Test status
Simulation time 8380817750 ps
CPU time 10.04 seconds
Started Mar 03 02:24:18 PM PST 24
Finished Mar 03 02:24:29 PM PST 24
Peak memory 202576 kb
Host smart-77a060ec-5a8d-4143-a003-86754bba3f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61901
80 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.in_trans.6190180
Directory /workspace/25.in_trans/latest

Test location /workspace/coverage/default/25.setup_trans_ignored.2775492348
Short name T203
Test name
Test status
Simulation time 8360127960 ps
CPU time 8.7 seconds
Started Mar 03 02:24:08 PM PST 24
Finished Mar 03 02:24:17 PM PST 24
Peak memory 202652 kb
Host smart-8a019f3d-12c8-4385-8363-509fbbd10961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27754
92348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.setup_trans_ignored.2775492348
Directory /workspace/25.setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1971516176
Short name T306
Test name
Test status
Simulation time 8367186648 ps
CPU time 8.69 seconds
Started Mar 03 02:24:23 PM PST 24
Finished Mar 03 02:24:33 PM PST 24
Peak memory 202548 kb
Host smart-76c98cf1-6d7f-4865-a836-aca6ad159290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
16176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1971516176
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1147428127
Short name T283
Test name
Test status
Simulation time 162689222 ps
CPU time 1.91 seconds
Started Mar 03 02:24:15 PM PST 24
Finished Mar 03 02:24:18 PM PST 24
Peak memory 202684 kb
Host smart-cc61d906-0ab8-45d6-a019-00c87b9a7056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11474
28127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1147428127
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2339571959
Short name T73
Test name
Test status
Simulation time 8415063389 ps
CPU time 7.5 seconds
Started Mar 03 02:24:15 PM PST 24
Finished Mar 03 02:24:23 PM PST 24
Peak memory 202600 kb
Host smart-20b1f78d-6f01-4342-a0d2-5680875b929f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23395
71959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2339571959
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.169414338
Short name T108
Test name
Test status
Simulation time 8380708924 ps
CPU time 7.3 seconds
Started Mar 03 02:24:11 PM PST 24
Finished Mar 03 02:24:18 PM PST 24
Peak memory 202636 kb
Host smart-0b1fd684-5e14-4bc5-9b60-0114b9eeeed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16941
4338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.169414338
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2174874476
Short name T279
Test name
Test status
Simulation time 8364920895 ps
CPU time 7.24 seconds
Started Mar 03 02:24:17 PM PST 24
Finished Mar 03 02:24:25 PM PST 24
Peak memory 202616 kb
Host smart-2ae45994-c43d-4b07-b51e-a970e03451bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
74476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2174874476
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.in_trans.3336262966
Short name T357
Test name
Test status
Simulation time 8420355406 ps
CPU time 7.06 seconds
Started Mar 03 02:24:12 PM PST 24
Finished Mar 03 02:24:19 PM PST 24
Peak memory 202596 kb
Host smart-d4c2b865-7492-4882-a4bc-6cd368e88e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33362
62966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.in_trans.3336262966
Directory /workspace/26.in_trans/latest

Test location /workspace/coverage/default/26.setup_trans_ignored.2556994675
Short name T182
Test name
Test status
Simulation time 8433490337 ps
CPU time 7.27 seconds
Started Mar 03 02:24:11 PM PST 24
Finished Mar 03 02:24:19 PM PST 24
Peak memory 202660 kb
Host smart-76effcfd-c4db-4fd4-8ac8-87c037a9dfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25569
94675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.setup_trans_ignored.2556994675
Directory /workspace/26.setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3565930419
Short name T209
Test name
Test status
Simulation time 8373491845 ps
CPU time 8.21 seconds
Started Mar 03 02:24:14 PM PST 24
Finished Mar 03 02:24:22 PM PST 24
Peak memory 202616 kb
Host smart-87636b32-41d0-490f-b7d2-61df91ddc353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
30419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3565930419
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1435091070
Short name T261
Test name
Test status
Simulation time 279428420 ps
CPU time 2.16 seconds
Started Mar 03 02:24:09 PM PST 24
Finished Mar 03 02:24:11 PM PST 24
Peak memory 202688 kb
Host smart-0ab598eb-77dc-4b28-9961-49e6e02373d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14350
91070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1435091070
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2287170417
Short name T87
Test name
Test status
Simulation time 8429283786 ps
CPU time 7.99 seconds
Started Mar 03 02:24:16 PM PST 24
Finished Mar 03 02:24:24 PM PST 24
Peak memory 202588 kb
Host smart-c62052dd-bae0-4609-b91e-870e46b88ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22871
70417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2287170417
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1910684972
Short name T330
Test name
Test status
Simulation time 8418772781 ps
CPU time 8.31 seconds
Started Mar 03 02:24:06 PM PST 24
Finished Mar 03 02:24:14 PM PST 24
Peak memory 202572 kb
Host smart-b409146d-a6d8-4c7d-9a41-f933835af3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19106
84972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1910684972
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1886003071
Short name T195
Test name
Test status
Simulation time 8365985101 ps
CPU time 9.59 seconds
Started Mar 03 02:24:18 PM PST 24
Finished Mar 03 02:24:28 PM PST 24
Peak memory 202608 kb
Host smart-cd2a214c-fa57-479c-9068-7a88f39af5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18860
03071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1886003071
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.in_trans.1977472081
Short name T213
Test name
Test status
Simulation time 8384256849 ps
CPU time 8.07 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202620 kb
Host smart-700e3bc5-9869-44e9-a9d2-c3bcf18dbdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19774
72081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.in_trans.1977472081
Directory /workspace/27.in_trans/latest

Test location /workspace/coverage/default/27.setup_trans_ignored.2709563795
Short name T337
Test name
Test status
Simulation time 8363545192 ps
CPU time 7.35 seconds
Started Mar 03 02:24:11 PM PST 24
Finished Mar 03 02:24:19 PM PST 24
Peak memory 202848 kb
Host smart-0d08828e-1bf4-47d0-b714-2e1dbc55d2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27095
63795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.setup_trans_ignored.2709563795
Directory /workspace/27.setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2636226802
Short name T286
Test name
Test status
Simulation time 8374179754 ps
CPU time 7.84 seconds
Started Mar 03 02:24:14 PM PST 24
Finished Mar 03 02:24:22 PM PST 24
Peak memory 202800 kb
Host smart-299a4ec8-c89d-4d3c-987e-ceb44d16d2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26362
26802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2636226802
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1519867593
Short name T211
Test name
Test status
Simulation time 61983626 ps
CPU time 1.77 seconds
Started Mar 03 02:24:15 PM PST 24
Finished Mar 03 02:24:17 PM PST 24
Peak memory 202740 kb
Host smart-494080ae-0413-4e49-81d2-4e2bef63e66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15198
67593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1519867593
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2658124201
Short name T363
Test name
Test status
Simulation time 8375885341 ps
CPU time 10.01 seconds
Started Mar 03 02:24:19 PM PST 24
Finished Mar 03 02:24:29 PM PST 24
Peak memory 202556 kb
Host smart-35714a40-90a7-4e89-9e46-3de4451a765f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26581
24201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2658124201
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_smoke.4202048290
Short name T60
Test name
Test status
Simulation time 8375485505 ps
CPU time 7.46 seconds
Started Mar 03 02:24:05 PM PST 24
Finished Mar 03 02:24:13 PM PST 24
Peak memory 202652 kb
Host smart-fc1f96b9-df49-4017-bd8f-cfede4dd178d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020
48290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.4202048290
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.in_trans.1066692092
Short name T246
Test name
Test status
Simulation time 8491449638 ps
CPU time 8.18 seconds
Started Mar 03 02:24:13 PM PST 24
Finished Mar 03 02:24:22 PM PST 24
Peak memory 202528 kb
Host smart-5bb8d666-709e-4487-95eb-28c7d08929b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10666
92092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.in_trans.1066692092
Directory /workspace/28.in_trans/latest

Test location /workspace/coverage/default/28.setup_trans_ignored.904057894
Short name T341
Test name
Test status
Simulation time 8361616255 ps
CPU time 8.3 seconds
Started Mar 03 02:24:20 PM PST 24
Finished Mar 03 02:24:29 PM PST 24
Peak memory 202628 kb
Host smart-e18a418b-a2f8-43ed-a325-2e4a2fc406a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90405
7894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.setup_trans_ignored.904057894
Directory /workspace/28.setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2883071327
Short name T272
Test name
Test status
Simulation time 213910349 ps
CPU time 1.68 seconds
Started Mar 03 02:24:15 PM PST 24
Finished Mar 03 02:24:17 PM PST 24
Peak memory 202740 kb
Host smart-1b2d093d-b871-4262-aae5-e8b040ebbdf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28830
71327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2883071327
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.574969596
Short name T78
Test name
Test status
Simulation time 8418527563 ps
CPU time 9.6 seconds
Started Mar 03 02:24:12 PM PST 24
Finished Mar 03 02:24:21 PM PST 24
Peak memory 202648 kb
Host smart-3031a350-4f9e-4d2c-afac-c526b8ec7548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57496
9596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.574969596
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2039248260
Short name T98
Test name
Test status
Simulation time 8405375855 ps
CPU time 7.43 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:30 PM PST 24
Peak memory 202608 kb
Host smart-eee25f95-e8c6-496d-bf8d-9436e7e39977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20392
48260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2039248260
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3699405854
Short name T58
Test name
Test status
Simulation time 8370367374 ps
CPU time 8.08 seconds
Started Mar 03 02:24:15 PM PST 24
Finished Mar 03 02:24:24 PM PST 24
Peak memory 202656 kb
Host smart-0055409f-a414-445e-9943-b0da84445ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36994
05854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3699405854
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.in_trans.2940793628
Short name T364
Test name
Test status
Simulation time 8385015157 ps
CPU time 7.41 seconds
Started Mar 03 02:24:18 PM PST 24
Finished Mar 03 02:24:26 PM PST 24
Peak memory 202644 kb
Host smart-39fdad4f-df16-4624-81f6-53ead2b7ac15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29407
93628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.in_trans.2940793628
Directory /workspace/29.in_trans/latest

Test location /workspace/coverage/default/29.setup_trans_ignored.113780344
Short name T237
Test name
Test status
Simulation time 8367234721 ps
CPU time 7.67 seconds
Started Mar 03 02:24:20 PM PST 24
Finished Mar 03 02:24:28 PM PST 24
Peak memory 202616 kb
Host smart-ca0b6d17-7b69-48e4-9c51-9ad2b8c64eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11378
0344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.setup_trans_ignored.113780344
Directory /workspace/29.setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3420270445
Short name T224
Test name
Test status
Simulation time 8447122670 ps
CPU time 7.91 seconds
Started Mar 03 02:24:06 PM PST 24
Finished Mar 03 02:24:15 PM PST 24
Peak memory 202604 kb
Host smart-6bb24ad8-c805-4aa1-96f3-160d89a49da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34202
70445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3420270445
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.4060886503
Short name T244
Test name
Test status
Simulation time 209723647 ps
CPU time 2.31 seconds
Started Mar 03 02:24:16 PM PST 24
Finished Mar 03 02:24:18 PM PST 24
Peak memory 202796 kb
Host smart-13dcf8a1-3838-45b0-a094-78e807ef3f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40608
86503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.4060886503
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.4019709462
Short name T331
Test name
Test status
Simulation time 8434007081 ps
CPU time 8.57 seconds
Started Mar 03 02:24:20 PM PST 24
Finished Mar 03 02:24:29 PM PST 24
Peak memory 202624 kb
Host smart-b0579de6-4884-454e-8e5c-cfd437b9a1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40197
09462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.4019709462
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3583662606
Short name T376
Test name
Test status
Simulation time 8402604952 ps
CPU time 7.46 seconds
Started Mar 03 02:24:10 PM PST 24
Finished Mar 03 02:24:17 PM PST 24
Peak memory 202644 kb
Host smart-8d6ff5d1-6132-4ce8-bf7c-4151dae7e356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35836
62606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3583662606
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.in_trans.3002554157
Short name T49
Test name
Test status
Simulation time 8421212565 ps
CPU time 7.86 seconds
Started Mar 03 02:23:12 PM PST 24
Finished Mar 03 02:23:20 PM PST 24
Peak memory 202584 kb
Host smart-dcfe5adc-035a-4e97-8e38-bd2771c79b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30025
54157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.in_trans.3002554157
Directory /workspace/3.in_trans/latest

Test location /workspace/coverage/default/3.setup_trans_ignored.3151340952
Short name T194
Test name
Test status
Simulation time 8360709487 ps
CPU time 8.67 seconds
Started Mar 03 02:23:16 PM PST 24
Finished Mar 03 02:23:24 PM PST 24
Peak memory 202584 kb
Host smart-88eae2c9-901e-467a-81a3-ac62f046be38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31513
40952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.setup_trans_ignored.3151340952
Directory /workspace/3.setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3233242409
Short name T150
Test name
Test status
Simulation time 232303558 ps
CPU time 2.08 seconds
Started Mar 03 02:23:12 PM PST 24
Finished Mar 03 02:23:15 PM PST 24
Peak memory 202724 kb
Host smart-40b8bbce-8bb7-48c2-a5b4-de7a28316e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32332
42409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3233242409
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.379433902
Short name T95
Test name
Test status
Simulation time 8400385077 ps
CPU time 8.24 seconds
Started Mar 03 02:23:16 PM PST 24
Finished Mar 03 02:23:24 PM PST 24
Peak memory 202528 kb
Host smart-0e1fc155-d231-4b35-8d81-aabd5f14fc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37943
3902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.379433902
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2859909719
Short name T362
Test name
Test status
Simulation time 8449937024 ps
CPU time 7.86 seconds
Started Mar 03 02:23:11 PM PST 24
Finished Mar 03 02:23:19 PM PST 24
Peak memory 202620 kb
Host smart-cf1ea151-0e4e-4489-85b1-cfc935693af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28599
09719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2859909719
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1200819181
Short name T267
Test name
Test status
Simulation time 8370342208 ps
CPU time 7.79 seconds
Started Mar 03 02:23:09 PM PST 24
Finished Mar 03 02:23:17 PM PST 24
Peak memory 202600 kb
Host smart-7e19ff16-055e-4930-b57b-26ad71f7e2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12008
19181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1200819181
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.in_trans.1489467957
Short name T348
Test name
Test status
Simulation time 8418359123 ps
CPU time 8.17 seconds
Started Mar 03 02:24:17 PM PST 24
Finished Mar 03 02:24:26 PM PST 24
Peak memory 202592 kb
Host smart-d89d7911-b2a5-40b2-ab18-9365b67152e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14894
67957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.in_trans.1489467957
Directory /workspace/30.in_trans/latest

Test location /workspace/coverage/default/30.setup_trans_ignored.1527609484
Short name T308
Test name
Test status
Simulation time 8361788881 ps
CPU time 8.21 seconds
Started Mar 03 02:24:17 PM PST 24
Finished Mar 03 02:24:26 PM PST 24
Peak memory 202652 kb
Host smart-6b194bfc-d4d0-4d88-9c32-fad296bba268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
09484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.setup_trans_ignored.1527609484
Directory /workspace/30.setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2681784557
Short name T277
Test name
Test status
Simulation time 274918765 ps
CPU time 2.11 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:24 PM PST 24
Peak memory 202812 kb
Host smart-5fd7be2c-d103-459d-ad7b-29605c683502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26817
84557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2681784557
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2845157885
Short name T83
Test name
Test status
Simulation time 8440256856 ps
CPU time 9.55 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:33 PM PST 24
Peak memory 202604 kb
Host smart-e3cd0bc3-e13c-4b1e-a3fd-d1be10ac756b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28451
57885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2845157885
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2742187284
Short name T366
Test name
Test status
Simulation time 8370534701 ps
CPU time 7.41 seconds
Started Mar 03 02:24:18 PM PST 24
Finished Mar 03 02:24:26 PM PST 24
Peak memory 202536 kb
Host smart-30fc261a-dcd7-402e-940d-1bd1b27c254c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27421
87284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2742187284
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.in_trans.4209609362
Short name T359
Test name
Test status
Simulation time 8454459833 ps
CPU time 7.51 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202656 kb
Host smart-73eba1eb-0fdb-4529-b841-b1a63b901788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
09362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.in_trans.4209609362
Directory /workspace/31.in_trans/latest

Test location /workspace/coverage/default/31.setup_trans_ignored.1716319770
Short name T197
Test name
Test status
Simulation time 8357345372 ps
CPU time 7.51 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202076 kb
Host smart-87b5d609-817c-43a9-93c2-65f3683438c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17163
19770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.setup_trans_ignored.1716319770
Directory /workspace/31.setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2471813136
Short name T186
Test name
Test status
Simulation time 8466188668 ps
CPU time 7.5 seconds
Started Mar 03 02:24:23 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202540 kb
Host smart-047c5789-6364-45a5-8105-3532c7c81ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24718
13136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2471813136
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2905974922
Short name T20
Test name
Test status
Simulation time 267025586 ps
CPU time 2.12 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:25 PM PST 24
Peak memory 202728 kb
Host smart-f10c6158-532d-41cb-aeda-9b65d14a9265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29059
74922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2905974922
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2125213952
Short name T280
Test name
Test status
Simulation time 8399478753 ps
CPU time 7.5 seconds
Started Mar 03 02:24:15 PM PST 24
Finished Mar 03 02:24:23 PM PST 24
Peak memory 202644 kb
Host smart-b36e4fc2-ef09-477d-86b0-7a0fcae6ce8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21252
13952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2125213952
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3448974393
Short name T292
Test name
Test status
Simulation time 8390438914 ps
CPU time 9.52 seconds
Started Mar 03 02:24:23 PM PST 24
Finished Mar 03 02:24:33 PM PST 24
Peak memory 202632 kb
Host smart-42b65ec3-cb72-4d7e-9d10-6e77f145c4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34489
74393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3448974393
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_smoke.620727715
Short name T335
Test name
Test status
Simulation time 8394802278 ps
CPU time 8.9 seconds
Started Mar 03 02:24:24 PM PST 24
Finished Mar 03 02:24:34 PM PST 24
Peak memory 202652 kb
Host smart-1f435139-988f-412a-abfe-a079a9b60060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62072
7715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.620727715
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.in_trans.2120198086
Short name T284
Test name
Test status
Simulation time 8383411081 ps
CPU time 7.44 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202608 kb
Host smart-595d8f63-59e3-42f1-b8c7-0642e4180083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21201
98086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.in_trans.2120198086
Directory /workspace/32.in_trans/latest

Test location /workspace/coverage/default/32.setup_trans_ignored.986328908
Short name T270
Test name
Test status
Simulation time 8365503705 ps
CPU time 9.39 seconds
Started Mar 03 02:24:21 PM PST 24
Finished Mar 03 02:24:30 PM PST 24
Peak memory 202596 kb
Host smart-460665b1-1701-494d-899e-0d51f9b9ad71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98632
8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.setup_trans_ignored.986328908
Directory /workspace/32.setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2699440592
Short name T312
Test name
Test status
Simulation time 8375542710 ps
CPU time 7.98 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202452 kb
Host smart-0e0ec80f-fa2f-4f1f-92ac-9379ae25ef7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26994
40592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2699440592
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3684467695
Short name T157
Test name
Test status
Simulation time 161851884 ps
CPU time 1.71 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:25 PM PST 24
Peak memory 202956 kb
Host smart-d669acce-5f38-479f-a36f-9874c4b7bb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36844
67695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3684467695
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3232042097
Short name T12
Test name
Test status
Simulation time 8447942904 ps
CPU time 9.41 seconds
Started Mar 03 02:24:26 PM PST 24
Finished Mar 03 02:24:36 PM PST 24
Peak memory 202604 kb
Host smart-f57a0209-9993-4c02-b197-096c674cb34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
42097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3232042097
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2034432617
Short name T67
Test name
Test status
Simulation time 8389847198 ps
CPU time 8.28 seconds
Started Mar 03 02:24:17 PM PST 24
Finished Mar 03 02:24:26 PM PST 24
Peak memory 202648 kb
Host smart-1182a94a-08f6-4150-b161-dc5ea9061557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20344
32617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2034432617
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_smoke.815775662
Short name T200
Test name
Test status
Simulation time 8365925691 ps
CPU time 7.82 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202244 kb
Host smart-da32f315-6a96-4b94-a1e0-63ac4fdc9258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81577
5662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.815775662
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.in_trans.64403573
Short name T100
Test name
Test status
Simulation time 8422796086 ps
CPU time 8.11 seconds
Started Mar 03 02:24:20 PM PST 24
Finished Mar 03 02:24:28 PM PST 24
Peak memory 202596 kb
Host smart-9e4a98ec-0d51-4bf1-8d70-362db5e45be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64403
573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.in_trans.64403573
Directory /workspace/33.in_trans/latest

Test location /workspace/coverage/default/33.setup_trans_ignored.60998578
Short name T336
Test name
Test status
Simulation time 8362209053 ps
CPU time 6.98 seconds
Started Mar 03 02:24:21 PM PST 24
Finished Mar 03 02:24:28 PM PST 24
Peak memory 202652 kb
Host smart-d60e6c89-68f6-4125-bf8b-fc4e5da2c4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60998
578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.setup_trans_ignored.60998578
Directory /workspace/33.setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3435852934
Short name T276
Test name
Test status
Simulation time 8389895177 ps
CPU time 6.96 seconds
Started Mar 03 02:24:16 PM PST 24
Finished Mar 03 02:24:23 PM PST 24
Peak memory 202572 kb
Host smart-5c0d04b3-0dab-4bad-b584-9bf596e8e675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34358
52934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3435852934
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.4030705777
Short name T219
Test name
Test status
Simulation time 45437443 ps
CPU time 1.06 seconds
Started Mar 03 02:24:21 PM PST 24
Finished Mar 03 02:24:22 PM PST 24
Peak memory 202028 kb
Host smart-f263571f-0257-4e61-ba55-7d8a02bcfcd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40307
05777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.4030705777
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3894605395
Short name T16
Test name
Test status
Simulation time 8426701590 ps
CPU time 8.43 seconds
Started Mar 03 02:24:18 PM PST 24
Finished Mar 03 02:24:27 PM PST 24
Peak memory 202600 kb
Host smart-9e69a3cc-f663-42df-8855-b9ff2e08abf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38946
05395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3894605395
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1339801258
Short name T97
Test name
Test status
Simulation time 8480259871 ps
CPU time 8.8 seconds
Started Mar 03 02:24:18 PM PST 24
Finished Mar 03 02:24:28 PM PST 24
Peak memory 202572 kb
Host smart-1191a4ae-cb42-4c89-8748-630bc51f764d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13398
01258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1339801258
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.setup_trans_ignored.1030615430
Short name T343
Test name
Test status
Simulation time 8366113862 ps
CPU time 7.65 seconds
Started Mar 03 02:24:25 PM PST 24
Finished Mar 03 02:24:33 PM PST 24
Peak memory 202572 kb
Host smart-64c7bb89-240a-42e8-b00b-5e626a1d4881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10306
15430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.setup_trans_ignored.1030615430
Directory /workspace/34.setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1292499032
Short name T241
Test name
Test status
Simulation time 8368989971 ps
CPU time 9.67 seconds
Started Mar 03 02:24:24 PM PST 24
Finished Mar 03 02:24:34 PM PST 24
Peak memory 202600 kb
Host smart-fb821423-7caf-4130-8564-36947881a82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12924
99032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1292499032
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.959223756
Short name T333
Test name
Test status
Simulation time 8450094164 ps
CPU time 7.37 seconds
Started Mar 03 02:24:23 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202656 kb
Host smart-5910b12a-b479-4e0e-9316-636ed2643bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95922
3756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.959223756
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1296965124
Short name T370
Test name
Test status
Simulation time 8370617927 ps
CPU time 8.6 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:32 PM PST 24
Peak memory 202660 kb
Host smart-f057fad9-e6db-4b0f-b3f4-3146e3b9203c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12969
65124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1296965124
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.setup_trans_ignored.2397535267
Short name T263
Test name
Test status
Simulation time 8361232242 ps
CPU time 7.61 seconds
Started Mar 03 02:24:19 PM PST 24
Finished Mar 03 02:24:27 PM PST 24
Peak memory 202644 kb
Host smart-24803403-dd5a-49a6-b8fa-0ed45a34f2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23975
35267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.setup_trans_ignored.2397535267
Directory /workspace/35.setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3363482169
Short name T332
Test name
Test status
Simulation time 8370398864 ps
CPU time 9.78 seconds
Started Mar 03 02:24:22 PM PST 24
Finished Mar 03 02:24:33 PM PST 24
Peak memory 202584 kb
Host smart-1d30e56a-4fea-4d8d-8f16-60c8cb94cfb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33634
82169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3363482169
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2265758506
Short name T202
Test name
Test status
Simulation time 52111379 ps
CPU time 1.38 seconds
Started Mar 03 02:24:31 PM PST 24
Finished Mar 03 02:24:33 PM PST 24
Peak memory 202736 kb
Host smart-960b1996-6672-428f-b983-3ca976a5b0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22657
58506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2265758506
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.475501159
Short name T120
Test name
Test status
Simulation time 8425062937 ps
CPU time 8.9 seconds
Started Mar 03 02:24:21 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202612 kb
Host smart-51e14e83-dc40-4bc3-aa03-6b758d108041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47550
1159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.475501159
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1744134523
Short name T350
Test name
Test status
Simulation time 8371724696 ps
CPU time 8.12 seconds
Started Mar 03 02:24:19 PM PST 24
Finished Mar 03 02:24:28 PM PST 24
Peak memory 202604 kb
Host smart-e195ae84-d143-4ea3-82db-34118c09da90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17441
34523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1744134523
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.setup_trans_ignored.802490430
Short name T155
Test name
Test status
Simulation time 8358118923 ps
CPU time 7.38 seconds
Started Mar 03 02:24:20 PM PST 24
Finished Mar 03 02:24:28 PM PST 24
Peak memory 202648 kb
Host smart-99a4912e-e413-45fb-a156-20e9c9fb46c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80249
0430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.setup_trans_ignored.802490430
Directory /workspace/36.setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1499021988
Short name T2
Test name
Test status
Simulation time 8376564291 ps
CPU time 7.32 seconds
Started Mar 03 02:24:23 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202544 kb
Host smart-4b2d910d-d237-4ca9-a956-5d7c0c4d0739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
21988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1499021988
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3077394640
Short name T295
Test name
Test status
Simulation time 130862868 ps
CPU time 1.27 seconds
Started Mar 03 02:24:24 PM PST 24
Finished Mar 03 02:24:25 PM PST 24
Peak memory 202652 kb
Host smart-6d05cf29-1dc0-4b09-8f90-e802a16103fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773
94640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3077394640
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.4009410586
Short name T88
Test name
Test status
Simulation time 8418793914 ps
CPU time 7.52 seconds
Started Mar 03 02:24:27 PM PST 24
Finished Mar 03 02:24:35 PM PST 24
Peak memory 202640 kb
Host smart-ef432dd4-eef7-408a-b739-3a29bdc9cfdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40094
10586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.4009410586
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2660292389
Short name T358
Test name
Test status
Simulation time 8398687500 ps
CPU time 8.13 seconds
Started Mar 03 02:24:25 PM PST 24
Finished Mar 03 02:24:34 PM PST 24
Peak memory 202660 kb
Host smart-db60c339-901e-411a-9bb7-b37490fc629a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26602
92389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2660292389
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_smoke.763294205
Short name T7
Test name
Test status
Simulation time 8373984152 ps
CPU time 9.64 seconds
Started Mar 03 02:24:24 PM PST 24
Finished Mar 03 02:24:35 PM PST 24
Peak memory 202560 kb
Host smart-df9c00d5-f934-48a6-824a-d242f9d2cd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76329
4205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.763294205
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.in_trans.28484612
Short name T101
Test name
Test status
Simulation time 8435384934 ps
CPU time 7.51 seconds
Started Mar 03 02:24:35 PM PST 24
Finished Mar 03 02:24:43 PM PST 24
Peak memory 202600 kb
Host smart-fe6cafaf-a6a8-42cf-a97c-7e392a2f0401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28484
612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.in_trans.28484612
Directory /workspace/37.in_trans/latest

Test location /workspace/coverage/default/37.setup_trans_ignored.2626342654
Short name T282
Test name
Test status
Simulation time 8360559413 ps
CPU time 7.67 seconds
Started Mar 03 02:24:45 PM PST 24
Finished Mar 03 02:24:53 PM PST 24
Peak memory 202640 kb
Host smart-97831963-910c-4225-b679-b09cbdde34b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26263
42654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.setup_trans_ignored.2626342654
Directory /workspace/37.setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2895510911
Short name T369
Test name
Test status
Simulation time 8372257826 ps
CPU time 7.97 seconds
Started Mar 03 02:24:26 PM PST 24
Finished Mar 03 02:24:34 PM PST 24
Peak memory 202568 kb
Host smart-6ba22a9f-e280-4281-80e5-10ec932435bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28955
10911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2895510911
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1073598290
Short name T373
Test name
Test status
Simulation time 200085517 ps
CPU time 2.11 seconds
Started Mar 03 02:24:43 PM PST 24
Finished Mar 03 02:24:45 PM PST 24
Peak memory 202704 kb
Host smart-b43ce0eb-97cf-4aa1-b08a-4b1ef65a61cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10735
98290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1073598290
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3939389439
Short name T90
Test name
Test status
Simulation time 8430176415 ps
CPU time 7.5 seconds
Started Mar 03 02:24:23 PM PST 24
Finished Mar 03 02:24:31 PM PST 24
Peak memory 202652 kb
Host smart-921ff013-4165-4685-91b2-e0733896efe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39393
89439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3939389439
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.833032671
Short name T99
Test name
Test status
Simulation time 8437834021 ps
CPU time 7.87 seconds
Started Mar 03 02:24:43 PM PST 24
Finished Mar 03 02:24:51 PM PST 24
Peak memory 202600 kb
Host smart-526a2a7e-ec74-4b1a-90dc-0a1473371539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83303
2671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.833032671
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3132866165
Short name T262
Test name
Test status
Simulation time 8374060356 ps
CPU time 8.92 seconds
Started Mar 03 02:24:32 PM PST 24
Finished Mar 03 02:24:41 PM PST 24
Peak memory 202588 kb
Host smart-34eab5dd-d497-4c31-b3ca-d362e0b2bbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31328
66165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3132866165
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.in_trans.3122882502
Short name T360
Test name
Test status
Simulation time 8409123667 ps
CPU time 7.36 seconds
Started Mar 03 02:24:32 PM PST 24
Finished Mar 03 02:24:39 PM PST 24
Peak memory 202648 kb
Host smart-1b8d8baa-0b3a-4de1-85f0-530b58adbc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31228
82502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.in_trans.3122882502
Directory /workspace/38.in_trans/latest

Test location /workspace/coverage/default/38.setup_trans_ignored.2469390938
Short name T54
Test name
Test status
Simulation time 8358245225 ps
CPU time 9.64 seconds
Started Mar 03 02:24:29 PM PST 24
Finished Mar 03 02:24:39 PM PST 24
Peak memory 202628 kb
Host smart-c5fccce0-043a-455c-aca8-df010d124e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24693
90938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.setup_trans_ignored.2469390938
Directory /workspace/38.setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1081193259
Short name T148
Test name
Test status
Simulation time 8373866950 ps
CPU time 8.52 seconds
Started Mar 03 02:24:28 PM PST 24
Finished Mar 03 02:24:37 PM PST 24
Peak memory 202660 kb
Host smart-c69b5f37-6d37-40af-a9a5-a17759c18000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
93259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1081193259
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.36598552
Short name T176
Test name
Test status
Simulation time 60999158 ps
CPU time 1.67 seconds
Started Mar 03 02:24:29 PM PST 24
Finished Mar 03 02:24:30 PM PST 24
Peak memory 202780 kb
Host smart-931ad757-f559-41d0-9078-59492e1f8d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36598
552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.36598552
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2352509868
Short name T71
Test name
Test status
Simulation time 8428618292 ps
CPU time 8.49 seconds
Started Mar 03 02:24:44 PM PST 24
Finished Mar 03 02:24:52 PM PST 24
Peak memory 202596 kb
Host smart-4d573a01-1563-494c-9b1c-b1e26078e140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23525
09868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2352509868
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3335116911
Short name T316
Test name
Test status
Simulation time 8414470734 ps
CPU time 7.43 seconds
Started Mar 03 02:24:29 PM PST 24
Finished Mar 03 02:24:36 PM PST 24
Peak memory 202648 kb
Host smart-44cb814b-32fd-46a3-ad43-0c6eaffc7363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33351
16911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3335116911
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_smoke.4074623872
Short name T178
Test name
Test status
Simulation time 8369511051 ps
CPU time 8.17 seconds
Started Mar 03 02:24:34 PM PST 24
Finished Mar 03 02:24:43 PM PST 24
Peak memory 202608 kb
Host smart-73bc7e81-6ad2-4b16-a2e9-a88629cc6965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40746
23872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.4074623872
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.in_trans.49296791
Short name T66
Test name
Test status
Simulation time 8431404773 ps
CPU time 7.62 seconds
Started Mar 03 02:24:42 PM PST 24
Finished Mar 03 02:24:50 PM PST 24
Peak memory 202576 kb
Host smart-257151e7-6986-4a48-a9bb-5547f9fe5788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49296
791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.in_trans.49296791
Directory /workspace/39.in_trans/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3169746397
Short name T222
Test name
Test status
Simulation time 8461685341 ps
CPU time 9.02 seconds
Started Mar 03 02:24:33 PM PST 24
Finished Mar 03 02:24:47 PM PST 24
Peak memory 202616 kb
Host smart-6cebbe9c-5043-4ee3-800b-701267f629f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31697
46397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3169746397
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3776856643
Short name T245
Test name
Test status
Simulation time 53739459 ps
CPU time 1 seconds
Started Mar 03 02:24:33 PM PST 24
Finished Mar 03 02:24:34 PM PST 24
Peak memory 202712 kb
Host smart-e72ee884-b9b9-4352-9024-ae1a9612b04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37768
56643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3776856643
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2359678676
Short name T89
Test name
Test status
Simulation time 8436367719 ps
CPU time 7.88 seconds
Started Mar 03 02:24:26 PM PST 24
Finished Mar 03 02:24:34 PM PST 24
Peak memory 202548 kb
Host smart-61031817-887f-492a-a271-f3c3ce499d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23596
78676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2359678676
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2086556854
Short name T116
Test name
Test status
Simulation time 8407637846 ps
CPU time 9.12 seconds
Started Mar 03 02:24:30 PM PST 24
Finished Mar 03 02:24:39 PM PST 24
Peak memory 202572 kb
Host smart-ce02bae8-893a-4ce3-8aab-f68d0aff56ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20865
56854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2086556854
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2275416143
Short name T269
Test name
Test status
Simulation time 8381442854 ps
CPU time 7.22 seconds
Started Mar 03 02:24:30 PM PST 24
Finished Mar 03 02:24:37 PM PST 24
Peak memory 202536 kb
Host smart-37ace8f2-a531-4c26-9d0c-46677b216a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22754
16143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2275416143
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.in_trans.2841534814
Short name T161
Test name
Test status
Simulation time 8409056585 ps
CPU time 8.28 seconds
Started Mar 03 02:23:16 PM PST 24
Finished Mar 03 02:23:24 PM PST 24
Peak memory 202644 kb
Host smart-330803cc-56ba-49b2-88ca-ab364ca56e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28415
34814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.in_trans.2841534814
Directory /workspace/4.in_trans/latest

Test location /workspace/coverage/default/4.setup_trans_ignored.151359180
Short name T377
Test name
Test status
Simulation time 8356263237 ps
CPU time 7.35 seconds
Started Mar 03 02:23:12 PM PST 24
Finished Mar 03 02:23:19 PM PST 24
Peak memory 202660 kb
Host smart-13f72f18-476b-439b-b0a7-8acf5055e4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15135
9180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.setup_trans_ignored.151359180
Directory /workspace/4.setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.193523917
Short name T147
Test name
Test status
Simulation time 8388042858 ps
CPU time 9.26 seconds
Started Mar 03 02:23:09 PM PST 24
Finished Mar 03 02:23:18 PM PST 24
Peak memory 202616 kb
Host smart-32472863-2f3a-40b8-95d1-87dbe26c1eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19352
3917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.193523917
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2252218841
Short name T329
Test name
Test status
Simulation time 60940998 ps
CPU time 1.48 seconds
Started Mar 03 02:23:15 PM PST 24
Finished Mar 03 02:23:17 PM PST 24
Peak memory 202692 kb
Host smart-a228fcd1-2c55-4881-b83c-ce17c6a20ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22522
18841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2252218841
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3585513618
Short name T74
Test name
Test status
Simulation time 8408034718 ps
CPU time 7.22 seconds
Started Mar 03 02:23:10 PM PST 24
Finished Mar 03 02:23:18 PM PST 24
Peak memory 202588 kb
Host smart-d8e42d8b-4060-4851-9999-f21e83a33511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35855
13618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3585513618
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3612545429
Short name T322
Test name
Test status
Simulation time 8403360723 ps
CPU time 8.8 seconds
Started Mar 03 02:23:16 PM PST 24
Finished Mar 03 02:23:25 PM PST 24
Peak memory 202524 kb
Host smart-e4314da9-f7fe-49f4-b591-7b0a0f8f80f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36125
45429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3612545429
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3902846489
Short name T217
Test name
Test status
Simulation time 8375863907 ps
CPU time 7.29 seconds
Started Mar 03 02:23:11 PM PST 24
Finished Mar 03 02:23:19 PM PST 24
Peak memory 202608 kb
Host smart-230347e8-b8c3-4d0e-a255-0f54f9ccff07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39028
46489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3902846489
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.in_trans.780260718
Short name T252
Test name
Test status
Simulation time 8451791419 ps
CPU time 8.94 seconds
Started Mar 03 02:24:32 PM PST 24
Finished Mar 03 02:24:41 PM PST 24
Peak memory 202588 kb
Host smart-38f973b5-178f-4f4a-870f-26daace9a2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78026
0718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.in_trans.780260718
Directory /workspace/40.in_trans/latest

Test location /workspace/coverage/default/40.setup_trans_ignored.4060010463
Short name T278
Test name
Test status
Simulation time 8362875834 ps
CPU time 7.18 seconds
Started Mar 03 02:24:32 PM PST 24
Finished Mar 03 02:24:39 PM PST 24
Peak memory 202584 kb
Host smart-88b29482-35ba-4020-8cd9-113ff203e86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40600
10463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.setup_trans_ignored.4060010463
Directory /workspace/40.setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2211148491
Short name T201
Test name
Test status
Simulation time 8374753756 ps
CPU time 9.68 seconds
Started Mar 03 02:24:34 PM PST 24
Finished Mar 03 02:24:44 PM PST 24
Peak memory 202676 kb
Host smart-e90f9f6c-7b72-4ae6-b4a2-22414c56a339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
48491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2211148491
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1242431918
Short name T192
Test name
Test status
Simulation time 137245526 ps
CPU time 1.61 seconds
Started Mar 03 02:24:34 PM PST 24
Finished Mar 03 02:24:35 PM PST 24
Peak memory 202728 kb
Host smart-6a4bb527-7a34-4d19-b6ab-f89c5ca543d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12424
31918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1242431918
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3737748154
Short name T17
Test name
Test status
Simulation time 8422059392 ps
CPU time 7.46 seconds
Started Mar 03 02:24:38 PM PST 24
Finished Mar 03 02:24:46 PM PST 24
Peak memory 202596 kb
Host smart-685aa5bf-b367-4609-aafc-7452385b4275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37377
48154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3737748154
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3952451759
Short name T223
Test name
Test status
Simulation time 8449229738 ps
CPU time 7.16 seconds
Started Mar 03 02:24:33 PM PST 24
Finished Mar 03 02:24:40 PM PST 24
Peak memory 202648 kb
Host smart-956fc046-4d86-4077-b14b-45aa25a112ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39524
51759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3952451759
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1488575500
Short name T183
Test name
Test status
Simulation time 8380143083 ps
CPU time 9.09 seconds
Started Mar 03 02:24:41 PM PST 24
Finished Mar 03 02:24:50 PM PST 24
Peak memory 202532 kb
Host smart-6bc13e1e-ba18-4c67-93d1-a856832e2276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885
75500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1488575500
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.setup_trans_ignored.1254154925
Short name T315
Test name
Test status
Simulation time 8397705000 ps
CPU time 7.09 seconds
Started Mar 03 02:24:45 PM PST 24
Finished Mar 03 02:24:52 PM PST 24
Peak memory 202568 kb
Host smart-98e8f14d-82e9-4e91-bc7a-121076e625ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12541
54925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.setup_trans_ignored.1254154925
Directory /workspace/41.setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.4019966188
Short name T177
Test name
Test status
Simulation time 54780679 ps
CPU time 1.51 seconds
Started Mar 03 02:25:03 PM PST 24
Finished Mar 03 02:25:04 PM PST 24
Peak memory 202732 kb
Host smart-1981a552-7f32-4141-acf0-da4ec64cde10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40199
66188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.4019966188
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.149975004
Short name T293
Test name
Test status
Simulation time 8406128016 ps
CPU time 7.43 seconds
Started Mar 03 02:24:41 PM PST 24
Finished Mar 03 02:24:48 PM PST 24
Peak memory 202592 kb
Host smart-68bdaea3-689c-4b49-8b19-a447e28095b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14997
5004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.149975004
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_smoke.83374648
Short name T232
Test name
Test status
Simulation time 8377770021 ps
CPU time 7.23 seconds
Started Mar 03 02:24:32 PM PST 24
Finished Mar 03 02:24:40 PM PST 24
Peak memory 202656 kb
Host smart-96b1939d-66f4-4159-89da-1f92e9103230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83374
648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.83374648
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.in_trans.2846959600
Short name T300
Test name
Test status
Simulation time 8388426385 ps
CPU time 7.87 seconds
Started Mar 03 02:24:43 PM PST 24
Finished Mar 03 02:24:51 PM PST 24
Peak memory 202532 kb
Host smart-4b9b2f70-26f9-48b3-b5f2-9e7754abfd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28469
59600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.in_trans.2846959600
Directory /workspace/42.in_trans/latest

Test location /workspace/coverage/default/42.setup_trans_ignored.1764519637
Short name T347
Test name
Test status
Simulation time 8361326890 ps
CPU time 7.85 seconds
Started Mar 03 02:24:45 PM PST 24
Finished Mar 03 02:24:53 PM PST 24
Peak memory 202596 kb
Host smart-fd5bc523-38a5-4902-82ce-98a36774b6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17645
19637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.setup_trans_ignored.1764519637
Directory /workspace/42.setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3351277299
Short name T325
Test name
Test status
Simulation time 8372781617 ps
CPU time 7.26 seconds
Started Mar 03 02:24:51 PM PST 24
Finished Mar 03 02:24:59 PM PST 24
Peak memory 202556 kb
Host smart-ebe6c714-777d-4686-8f8f-a3793d15c0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33512
77299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3351277299
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2965130135
Short name T156
Test name
Test status
Simulation time 245158033 ps
CPU time 2.1 seconds
Started Mar 03 02:24:46 PM PST 24
Finished Mar 03 02:24:48 PM PST 24
Peak memory 202728 kb
Host smart-31fe2730-ff4e-4592-b4a7-9eff51317dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29651
30135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2965130135
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.349586789
Short name T307
Test name
Test status
Simulation time 8438037482 ps
CPU time 8.44 seconds
Started Mar 03 02:25:00 PM PST 24
Finished Mar 03 02:25:08 PM PST 24
Peak memory 202652 kb
Host smart-da23bda4-701a-4f86-9460-e88e068ba39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958
6789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.349586789
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2639867081
Short name T288
Test name
Test status
Simulation time 8423883559 ps
CPU time 7.68 seconds
Started Mar 03 02:24:38 PM PST 24
Finished Mar 03 02:24:46 PM PST 24
Peak memory 202660 kb
Host smart-094ba7af-b628-470d-b95c-0fe7f00162b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26398
67081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2639867081
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1483615733
Short name T253
Test name
Test status
Simulation time 8369331272 ps
CPU time 8.41 seconds
Started Mar 03 02:24:59 PM PST 24
Finished Mar 03 02:25:08 PM PST 24
Peak memory 202560 kb
Host smart-6e84fe78-628a-43ac-b8df-7a7b65265201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14836
15733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1483615733
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.in_trans.1259439458
Short name T298
Test name
Test status
Simulation time 8405932441 ps
CPU time 7.96 seconds
Started Mar 03 02:25:02 PM PST 24
Finished Mar 03 02:25:10 PM PST 24
Peak memory 202588 kb
Host smart-97b0d851-768c-4bca-87b0-50af1561ba6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12594
39458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.in_trans.1259439458
Directory /workspace/43.in_trans/latest

Test location /workspace/coverage/default/43.setup_trans_ignored.1322207179
Short name T23
Test name
Test status
Simulation time 8355774217 ps
CPU time 7.68 seconds
Started Mar 03 02:24:55 PM PST 24
Finished Mar 03 02:25:04 PM PST 24
Peak memory 202648 kb
Host smart-acf7d1d4-09e6-4e98-bc39-a70a9cfc51fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13222
07179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.setup_trans_ignored.1322207179
Directory /workspace/43.setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1781968671
Short name T304
Test name
Test status
Simulation time 8375551866 ps
CPU time 7.67 seconds
Started Mar 03 02:24:38 PM PST 24
Finished Mar 03 02:24:46 PM PST 24
Peak memory 202588 kb
Host smart-74763d53-8e34-4ad0-ac9d-4a31ef787c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
68671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1781968671
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1874863785
Short name T151
Test name
Test status
Simulation time 192068563 ps
CPU time 2.04 seconds
Started Mar 03 02:25:06 PM PST 24
Finished Mar 03 02:25:09 PM PST 24
Peak memory 202672 kb
Host smart-5b4ec3a7-91a5-4b03-8938-e1066a0c5a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18748
63785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1874863785
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.352601943
Short name T91
Test name
Test status
Simulation time 8423730021 ps
CPU time 7.88 seconds
Started Mar 03 02:24:34 PM PST 24
Finished Mar 03 02:24:42 PM PST 24
Peak memory 202592 kb
Host smart-9f7a7472-1206-4d51-b6b0-9c5d61e032a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35260
1943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.352601943
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.614657814
Short name T111
Test name
Test status
Simulation time 8513348016 ps
CPU time 7.89 seconds
Started Mar 03 02:24:49 PM PST 24
Finished Mar 03 02:24:57 PM PST 24
Peak memory 202580 kb
Host smart-cc63aab2-e7c5-4123-b17a-1472b1a96449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61465
7814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.614657814
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_smoke.360983583
Short name T191
Test name
Test status
Simulation time 8365711040 ps
CPU time 7.96 seconds
Started Mar 03 02:24:44 PM PST 24
Finished Mar 03 02:24:52 PM PST 24
Peak memory 202584 kb
Host smart-742be14b-f0df-4eb4-b20c-04a12a36e88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
3583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.360983583
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.in_trans.3891825231
Short name T317
Test name
Test status
Simulation time 8431415437 ps
CPU time 7.62 seconds
Started Mar 03 02:24:53 PM PST 24
Finished Mar 03 02:25:01 PM PST 24
Peak memory 202660 kb
Host smart-8a0ec156-16b3-471f-8c57-62c44f5f833c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38918
25231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.in_trans.3891825231
Directory /workspace/44.in_trans/latest

Test location /workspace/coverage/default/44.setup_trans_ignored.4106618746
Short name T205
Test name
Test status
Simulation time 8363117553 ps
CPU time 8.29 seconds
Started Mar 03 02:24:56 PM PST 24
Finished Mar 03 02:25:05 PM PST 24
Peak memory 202632 kb
Host smart-289616a2-b955-4782-a043-cca25f217366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41066
18746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.setup_trans_ignored.4106618746
Directory /workspace/44.setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.220112854
Short name T34
Test name
Test status
Simulation time 8368274668 ps
CPU time 7.87 seconds
Started Mar 03 02:25:03 PM PST 24
Finished Mar 03 02:25:11 PM PST 24
Peak memory 202616 kb
Host smart-92425b95-f429-44af-844c-8bffc4bbd9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22011
2854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.220112854
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4258600309
Short name T297
Test name
Test status
Simulation time 200067483 ps
CPU time 2.15 seconds
Started Mar 03 02:24:47 PM PST 24
Finished Mar 03 02:24:49 PM PST 24
Peak memory 202728 kb
Host smart-1de6ab30-0268-4dd1-9c70-fc0d527bd7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42586
00309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4258600309
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3234567243
Short name T319
Test name
Test status
Simulation time 8505584558 ps
CPU time 8.33 seconds
Started Mar 03 02:25:01 PM PST 24
Finished Mar 03 02:25:09 PM PST 24
Peak memory 202600 kb
Host smart-02e4a1cd-fdd8-436d-8658-f221ffd5ca4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32345
67243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3234567243
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1052476884
Short name T26
Test name
Test status
Simulation time 8400523081 ps
CPU time 7.38 seconds
Started Mar 03 02:25:03 PM PST 24
Finished Mar 03 02:25:11 PM PST 24
Peak memory 202656 kb
Host smart-7c059937-00ad-4fd7-ad66-1669ce756873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10524
76884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1052476884
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2988142364
Short name T227
Test name
Test status
Simulation time 8371124957 ps
CPU time 7.85 seconds
Started Mar 03 02:25:03 PM PST 24
Finished Mar 03 02:25:12 PM PST 24
Peak memory 202588 kb
Host smart-0e1e9fc1-8988-4c46-b955-2699bcfe8408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
42364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2988142364
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.setup_trans_ignored.2027844328
Short name T184
Test name
Test status
Simulation time 8365637641 ps
CPU time 8.69 seconds
Started Mar 03 02:24:51 PM PST 24
Finished Mar 03 02:25:00 PM PST 24
Peak memory 202652 kb
Host smart-71e3b8af-0c15-44da-ae36-4ab607003583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20278
44328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.setup_trans_ignored.2027844328
Directory /workspace/45.setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.903943550
Short name T299
Test name
Test status
Simulation time 8379503103 ps
CPU time 8.81 seconds
Started Mar 03 02:24:57 PM PST 24
Finished Mar 03 02:25:06 PM PST 24
Peak memory 202616 kb
Host smart-5e81fd31-b2d1-40c4-a770-5e0d7478eba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90394
3550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.903943550
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3769575835
Short name T162
Test name
Test status
Simulation time 258525820 ps
CPU time 2.22 seconds
Started Mar 03 02:24:59 PM PST 24
Finished Mar 03 02:25:02 PM PST 24
Peak memory 202624 kb
Host smart-e0e79c4a-5f4f-4dc7-825a-a073390ba449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37695
75835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3769575835
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2294010333
Short name T81
Test name
Test status
Simulation time 8426717261 ps
CPU time 7.59 seconds
Started Mar 03 02:24:57 PM PST 24
Finished Mar 03 02:25:05 PM PST 24
Peak memory 202604 kb
Host smart-78788b98-8350-4b10-bbb3-549285587a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22940
10333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2294010333
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3829309618
Short name T242
Test name
Test status
Simulation time 8380875385 ps
CPU time 9.2 seconds
Started Mar 03 02:25:04 PM PST 24
Finished Mar 03 02:25:14 PM PST 24
Peak memory 202660 kb
Host smart-bb478a22-1ddd-4c9f-819c-3cfd1b8aad8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38293
09618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3829309618
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.in_trans.543469003
Short name T229
Test name
Test status
Simulation time 8398653018 ps
CPU time 7.7 seconds
Started Mar 03 02:25:15 PM PST 24
Finished Mar 03 02:25:23 PM PST 24
Peak memory 202604 kb
Host smart-b253ddcd-cf9d-4c8c-b12a-8b4e33214e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54346
9003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.in_trans.543469003
Directory /workspace/46.in_trans/latest

Test location /workspace/coverage/default/46.setup_trans_ignored.830945268
Short name T323
Test name
Test status
Simulation time 8379169324 ps
CPU time 7.25 seconds
Started Mar 03 02:24:55 PM PST 24
Finished Mar 03 02:25:03 PM PST 24
Peak memory 202636 kb
Host smart-4bde7851-39a2-4d0b-aa9b-9c7b18adbc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83094
5268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.setup_trans_ignored.830945268
Directory /workspace/46.setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.841773294
Short name T230
Test name
Test status
Simulation time 8368167879 ps
CPU time 10 seconds
Started Mar 03 02:24:53 PM PST 24
Finished Mar 03 02:25:03 PM PST 24
Peak memory 202600 kb
Host smart-44d5ec53-eb55-4325-b17c-38265f8117d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84177
3294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.841773294
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.904231148
Short name T250
Test name
Test status
Simulation time 89224081 ps
CPU time 1.18 seconds
Started Mar 03 02:25:09 PM PST 24
Finished Mar 03 02:25:11 PM PST 24
Peak memory 202724 kb
Host smart-a85aa3ca-4bb1-474a-b537-89beacd71449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90423
1148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.904231148
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.866138960
Short name T264
Test name
Test status
Simulation time 8452556171 ps
CPU time 9.73 seconds
Started Mar 03 02:24:59 PM PST 24
Finished Mar 03 02:25:09 PM PST 24
Peak memory 202584 kb
Host smart-097542e5-e9dc-47da-9374-5e809a1a99fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86613
8960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.866138960
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3252194972
Short name T321
Test name
Test status
Simulation time 8369409259 ps
CPU time 7.52 seconds
Started Mar 03 02:24:46 PM PST 24
Finished Mar 03 02:24:54 PM PST 24
Peak memory 202564 kb
Host smart-c0670666-016f-4cda-8339-0edb465c477d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32521
94972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3252194972
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.in_trans.2237667276
Short name T287
Test name
Test status
Simulation time 8440678801 ps
CPU time 7.62 seconds
Started Mar 03 02:25:12 PM PST 24
Finished Mar 03 02:25:20 PM PST 24
Peak memory 202620 kb
Host smart-cd147652-64f5-4d56-b958-98ad07967de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22376
67276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.in_trans.2237667276
Directory /workspace/47.in_trans/latest

Test location /workspace/coverage/default/47.setup_trans_ignored.3236602553
Short name T375
Test name
Test status
Simulation time 8359741152 ps
CPU time 7.4 seconds
Started Mar 03 02:24:58 PM PST 24
Finished Mar 03 02:25:06 PM PST 24
Peak memory 202640 kb
Host smart-b474d281-574c-4901-8b4a-55af052da886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32366
02553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.setup_trans_ignored.3236602553
Directory /workspace/47.setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3479196249
Short name T320
Test name
Test status
Simulation time 8373256155 ps
CPU time 7.26 seconds
Started Mar 03 02:24:57 PM PST 24
Finished Mar 03 02:25:05 PM PST 24
Peak memory 202640 kb
Host smart-850b8a2b-2b75-472f-95c5-13a4a7288fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34791
96249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3479196249
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.313052154
Short name T55
Test name
Test status
Simulation time 64607501 ps
CPU time 1.3 seconds
Started Mar 03 02:25:09 PM PST 24
Finished Mar 03 02:25:11 PM PST 24
Peak memory 202736 kb
Host smart-2f6f0d74-2dba-4c4e-8b87-6d2e3cc9af9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31305
2154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.313052154
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2016705222
Short name T117
Test name
Test status
Simulation time 8402972310 ps
CPU time 9.53 seconds
Started Mar 03 02:25:03 PM PST 24
Finished Mar 03 02:25:13 PM PST 24
Peak memory 202604 kb
Host smart-53c3a1d2-c6e0-4ef3-9199-7129661f9ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20167
05222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2016705222
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3423383549
Short name T327
Test name
Test status
Simulation time 8373991474 ps
CPU time 7.48 seconds
Started Mar 03 02:25:12 PM PST 24
Finished Mar 03 02:25:20 PM PST 24
Peak memory 202652 kb
Host smart-0d67ae5a-394f-44cb-9f3d-4a7401b7dc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34233
83549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3423383549
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.setup_trans_ignored.3198279874
Short name T281
Test name
Test status
Simulation time 8364205216 ps
CPU time 9.81 seconds
Started Mar 03 02:24:57 PM PST 24
Finished Mar 03 02:25:07 PM PST 24
Peak memory 202652 kb
Host smart-f31c44a0-bfe9-4826-bccf-1d37a1163634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31982
79874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.setup_trans_ignored.3198279874
Directory /workspace/48.setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2850209551
Short name T5
Test name
Test status
Simulation time 8365922858 ps
CPU time 7.46 seconds
Started Mar 03 02:24:59 PM PST 24
Finished Mar 03 02:25:07 PM PST 24
Peak memory 202612 kb
Host smart-3d60095f-5ab2-4e2d-a5df-f54e35267bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28502
09551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2850209551
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.594980698
Short name T1
Test name
Test status
Simulation time 151369527 ps
CPU time 1.75 seconds
Started Mar 03 02:25:23 PM PST 24
Finished Mar 03 02:25:25 PM PST 24
Peak memory 202792 kb
Host smart-ed27d154-1286-4944-8e79-2f6448bfcce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59498
0698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.594980698
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3796224242
Short name T160
Test name
Test status
Simulation time 8417994281 ps
CPU time 8.09 seconds
Started Mar 03 02:25:10 PM PST 24
Finished Mar 03 02:25:18 PM PST 24
Peak memory 202648 kb
Host smart-ab65b764-6e72-4e7a-b4ee-680f625a53c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37962
24242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3796224242
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1484329601
Short name T189
Test name
Test status
Simulation time 8401923285 ps
CPU time 7.79 seconds
Started Mar 03 02:25:06 PM PST 24
Finished Mar 03 02:25:14 PM PST 24
Peak memory 202612 kb
Host smart-da4e389f-2a62-4fee-83e6-4ff3a8c3d1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14843
29601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1484329601
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3448383670
Short name T338
Test name
Test status
Simulation time 8368654240 ps
CPU time 9.74 seconds
Started Mar 03 02:24:51 PM PST 24
Finished Mar 03 02:25:01 PM PST 24
Peak memory 202588 kb
Host smart-0d6da59c-977b-4587-b82b-80665cff6958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34483
83670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3448383670
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.in_trans.2708940369
Short name T354
Test name
Test status
Simulation time 8378527267 ps
CPU time 7.24 seconds
Started Mar 03 02:25:12 PM PST 24
Finished Mar 03 02:25:19 PM PST 24
Peak memory 202596 kb
Host smart-23abb93d-0816-4652-80b2-b1782ace7112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27089
40369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.in_trans.2708940369
Directory /workspace/49.in_trans/latest

Test location /workspace/coverage/default/49.setup_trans_ignored.2717150710
Short name T208
Test name
Test status
Simulation time 8372442896 ps
CPU time 7.36 seconds
Started Mar 03 02:25:13 PM PST 24
Finished Mar 03 02:25:20 PM PST 24
Peak memory 202660 kb
Host smart-c804227f-3482-4473-acce-479dbccbf065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27171
50710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.setup_trans_ignored.2717150710
Directory /workspace/49.setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.426784642
Short name T372
Test name
Test status
Simulation time 8373482147 ps
CPU time 8.81 seconds
Started Mar 03 02:25:13 PM PST 24
Finished Mar 03 02:25:22 PM PST 24
Peak memory 202548 kb
Host smart-e3c37302-f178-40dd-88e0-c1bd0786140f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42678
4642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.426784642
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.4278060410
Short name T59
Test name
Test status
Simulation time 41559300 ps
CPU time 1.05 seconds
Started Mar 03 02:25:06 PM PST 24
Finished Mar 03 02:25:08 PM PST 24
Peak memory 202720 kb
Host smart-e4569ea7-e1a0-47d8-852d-ee5b7442a029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42780
60410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4278060410
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.241887270
Short name T80
Test name
Test status
Simulation time 8433603017 ps
CPU time 7.59 seconds
Started Mar 03 02:25:16 PM PST 24
Finished Mar 03 02:25:25 PM PST 24
Peak memory 202640 kb
Host smart-b3a3c4ae-a3db-47f5-8d11-0e2503e429ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24188
7270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.241887270
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1279328739
Short name T51
Test name
Test status
Simulation time 8388461683 ps
CPU time 7.11 seconds
Started Mar 03 02:25:11 PM PST 24
Finished Mar 03 02:25:18 PM PST 24
Peak memory 202524 kb
Host smart-41967d17-19c8-499e-9213-e175d0f4169b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
28739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1279328739
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3858829677
Short name T235
Test name
Test status
Simulation time 8364913598 ps
CPU time 7.07 seconds
Started Mar 03 02:25:13 PM PST 24
Finished Mar 03 02:25:20 PM PST 24
Peak memory 202572 kb
Host smart-4a50edca-d6b3-4b24-9c55-83b92535a708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
29677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3858829677
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.setup_trans_ignored.3734197841
Short name T18
Test name
Test status
Simulation time 8358414736 ps
CPU time 7.39 seconds
Started Mar 03 02:23:20 PM PST 24
Finished Mar 03 02:23:28 PM PST 24
Peak memory 202556 kb
Host smart-ec53548f-7cce-475d-9cd4-a7ddf2bebaeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37341
97841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.setup_trans_ignored.3734197841
Directory /workspace/5.setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3738808993
Short name T29
Test name
Test status
Simulation time 8369123966 ps
CPU time 7.51 seconds
Started Mar 03 02:23:20 PM PST 24
Finished Mar 03 02:23:27 PM PST 24
Peak memory 202492 kb
Host smart-1b61625b-3672-485f-bc65-d41c828c6f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37388
08993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3738808993
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1538712074
Short name T290
Test name
Test status
Simulation time 160737878 ps
CPU time 1.8 seconds
Started Mar 03 02:23:18 PM PST 24
Finished Mar 03 02:23:20 PM PST 24
Peak memory 202748 kb
Host smart-31d33b3b-5edc-492f-a3d6-98bf64c5cbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387
12074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1538712074
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2167021988
Short name T11
Test name
Test status
Simulation time 8387629390 ps
CPU time 7.32 seconds
Started Mar 03 02:23:18 PM PST 24
Finished Mar 03 02:23:25 PM PST 24
Peak memory 202492 kb
Host smart-9ba52a4e-ca8d-4c43-b892-0f96242b9cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670
21988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2167021988
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.626467153
Short name T301
Test name
Test status
Simulation time 8431680889 ps
CPU time 7.7 seconds
Started Mar 03 02:23:18 PM PST 24
Finished Mar 03 02:23:26 PM PST 24
Peak memory 202584 kb
Host smart-1b2e3fb7-e3ca-49cb-a82d-a2cc455611da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62646
7153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.626467153
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2100262466
Short name T318
Test name
Test status
Simulation time 8370617820 ps
CPU time 7.2 seconds
Started Mar 03 02:23:16 PM PST 24
Finished Mar 03 02:23:23 PM PST 24
Peak memory 202636 kb
Host smart-725925c3-4995-46d9-8db3-8ee4de4a967d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21002
62466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2100262466
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.in_trans.677968537
Short name T103
Test name
Test status
Simulation time 8435436069 ps
CPU time 7.63 seconds
Started Mar 03 02:23:20 PM PST 24
Finished Mar 03 02:23:27 PM PST 24
Peak memory 202592 kb
Host smart-86bc7e7f-e257-4504-9634-0f595a1f9eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67796
8537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.in_trans.677968537
Directory /workspace/6.in_trans/latest

Test location /workspace/coverage/default/6.setup_trans_ignored.864323923
Short name T50
Test name
Test status
Simulation time 8369492386 ps
CPU time 7.7 seconds
Started Mar 03 02:23:20 PM PST 24
Finished Mar 03 02:23:28 PM PST 24
Peak memory 202632 kb
Host smart-a0b2f36b-a3aa-4d98-9a35-710103d8fcbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86432
3923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.setup_trans_ignored.864323923
Directory /workspace/6.setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2849519610
Short name T33
Test name
Test status
Simulation time 8383098624 ps
CPU time 7.47 seconds
Started Mar 03 02:23:17 PM PST 24
Finished Mar 03 02:23:25 PM PST 24
Peak memory 202544 kb
Host smart-c8300a6e-c2be-4966-b86a-7f0ff8c09577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28495
19610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2849519610
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2447405429
Short name T313
Test name
Test status
Simulation time 68660063 ps
CPU time 1.52 seconds
Started Mar 03 02:23:19 PM PST 24
Finished Mar 03 02:23:20 PM PST 24
Peak memory 202732 kb
Host smart-cee86958-ab33-424d-9097-9c95df51d904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24474
05429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2447405429
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1390299346
Short name T84
Test name
Test status
Simulation time 8433866188 ps
CPU time 7.69 seconds
Started Mar 03 02:23:20 PM PST 24
Finished Mar 03 02:23:27 PM PST 24
Peak memory 202592 kb
Host smart-85ae5b6c-71d9-4cc2-ac42-1cdf2b292e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13902
99346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1390299346
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3317762267
Short name T339
Test name
Test status
Simulation time 8523601612 ps
CPU time 8.58 seconds
Started Mar 03 02:23:18 PM PST 24
Finished Mar 03 02:23:27 PM PST 24
Peak memory 202596 kb
Host smart-2c050e1a-de17-4ce1-82f9-1c28b8cfae38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33177
62267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3317762267
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1237611315
Short name T260
Test name
Test status
Simulation time 8366448093 ps
CPU time 8.74 seconds
Started Mar 03 02:23:19 PM PST 24
Finished Mar 03 02:23:27 PM PST 24
Peak memory 202612 kb
Host smart-ca5055e3-fed1-4496-bf6d-3579abd0b48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12376
11315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1237611315
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.in_trans.3779645754
Short name T258
Test name
Test status
Simulation time 8413972823 ps
CPU time 9.43 seconds
Started Mar 03 02:23:21 PM PST 24
Finished Mar 03 02:23:30 PM PST 24
Peak memory 202584 kb
Host smart-ff37012f-46cd-453d-85e0-a1cf3dca81f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37796
45754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.in_trans.3779645754
Directory /workspace/7.in_trans/latest

Test location /workspace/coverage/default/7.setup_trans_ignored.2622133589
Short name T199
Test name
Test status
Simulation time 8356406511 ps
CPU time 8.88 seconds
Started Mar 03 02:23:20 PM PST 24
Finished Mar 03 02:23:29 PM PST 24
Peak memory 202652 kb
Host smart-2b64a29c-0c82-43eb-9dea-a33392fb41db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26221
33589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.setup_trans_ignored.2622133589
Directory /workspace/7.setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2230344091
Short name T207
Test name
Test status
Simulation time 8367776420 ps
CPU time 9.16 seconds
Started Mar 03 02:23:19 PM PST 24
Finished Mar 03 02:23:29 PM PST 24
Peak memory 202620 kb
Host smart-c79a2b76-779c-40b3-8c51-02433635e390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22303
44091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2230344091
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3782313276
Short name T220
Test name
Test status
Simulation time 153908408 ps
CPU time 1.81 seconds
Started Mar 03 02:23:22 PM PST 24
Finished Mar 03 02:23:24 PM PST 24
Peak memory 202680 kb
Host smart-c6171d69-b949-44f5-a6a6-7aa7384f4be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37823
13276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3782313276
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3456901129
Short name T93
Test name
Test status
Simulation time 8424179157 ps
CPU time 7.43 seconds
Started Mar 03 02:23:19 PM PST 24
Finished Mar 03 02:23:27 PM PST 24
Peak memory 202604 kb
Host smart-b77b2a1a-f04b-4f2f-b1a8-32023ccff38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569
01129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3456901129
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4168766229
Short name T324
Test name
Test status
Simulation time 8408250493 ps
CPU time 7.7 seconds
Started Mar 03 02:23:20 PM PST 24
Finished Mar 03 02:23:27 PM PST 24
Peak memory 202208 kb
Host smart-d9794c40-aa26-4317-a2c4-8cedc28a48bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41687
66229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4168766229
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2664525438
Short name T367
Test name
Test status
Simulation time 8372696099 ps
CPU time 8.06 seconds
Started Mar 03 02:23:21 PM PST 24
Finished Mar 03 02:23:29 PM PST 24
Peak memory 202664 kb
Host smart-ce1406b3-aa84-4a1d-b2d6-5bf9ce8a28df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26645
25438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2664525438
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.in_trans.443723123
Short name T291
Test name
Test status
Simulation time 8465172923 ps
CPU time 7.73 seconds
Started Mar 03 02:23:23 PM PST 24
Finished Mar 03 02:23:30 PM PST 24
Peak memory 202600 kb
Host smart-c01dc8c1-82ef-4ff1-b12d-061d2f6a501e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44372
3123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.in_trans.443723123
Directory /workspace/8.in_trans/latest

Test location /workspace/coverage/default/8.setup_trans_ignored.2981495748
Short name T185
Test name
Test status
Simulation time 8361795688 ps
CPU time 7.86 seconds
Started Mar 03 02:23:23 PM PST 24
Finished Mar 03 02:23:31 PM PST 24
Peak memory 202632 kb
Host smart-93f71fae-f81b-4771-a84c-a57b766d522b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
95748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.setup_trans_ignored.2981495748
Directory /workspace/8.setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2277975369
Short name T233
Test name
Test status
Simulation time 8370486826 ps
CPU time 7.28 seconds
Started Mar 03 02:23:22 PM PST 24
Finished Mar 03 02:23:29 PM PST 24
Peak memory 202616 kb
Host smart-e96414e2-1af1-4839-b112-adfbabaa7435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22779
75369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2277975369
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2370641251
Short name T340
Test name
Test status
Simulation time 172321736 ps
CPU time 1.94 seconds
Started Mar 03 02:23:25 PM PST 24
Finished Mar 03 02:23:27 PM PST 24
Peak memory 202748 kb
Host smart-37532de3-908e-4021-b3ec-2bdd7e29b7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23706
41251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2370641251
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3754925736
Short name T257
Test name
Test status
Simulation time 8437315727 ps
CPU time 8.97 seconds
Started Mar 03 02:23:23 PM PST 24
Finished Mar 03 02:23:32 PM PST 24
Peak memory 202584 kb
Host smart-c2fd12ea-ddf5-47a1-b60e-5d870ef06216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
25736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3754925736
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3477721429
Short name T234
Test name
Test status
Simulation time 8365771811 ps
CPU time 7.8 seconds
Started Mar 03 02:23:28 PM PST 24
Finished Mar 03 02:23:36 PM PST 24
Peak memory 202656 kb
Host smart-bc9cf40f-533e-4b40-bed7-27551bc0598e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34777
21429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3477721429
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.in_trans.135459355
Short name T159
Test name
Test status
Simulation time 8437989807 ps
CPU time 8.04 seconds
Started Mar 03 02:23:23 PM PST 24
Finished Mar 03 02:23:31 PM PST 24
Peak memory 202572 kb
Host smart-b80772c3-a464-4d12-8091-b2f34d4f76ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13545
9355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.in_trans.135459355
Directory /workspace/9.in_trans/latest

Test location /workspace/coverage/default/9.setup_trans_ignored.714421177
Short name T256
Test name
Test status
Simulation time 8358821967 ps
CPU time 7.1 seconds
Started Mar 03 02:23:24 PM PST 24
Finished Mar 03 02:23:31 PM PST 24
Peak memory 202644 kb
Host smart-1670f572-e5d4-4c78-8a1f-40a22d517861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71442
1177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.setup_trans_ignored.714421177
Directory /workspace/9.setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1627274279
Short name T21
Test name
Test status
Simulation time 67788933 ps
CPU time 1.91 seconds
Started Mar 03 02:23:26 PM PST 24
Finished Mar 03 02:23:28 PM PST 24
Peak memory 202796 kb
Host smart-594ac1ac-25b8-430a-9114-e225095d5165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16272
74279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1627274279
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3115165832
Short name T75
Test name
Test status
Simulation time 8440163752 ps
CPU time 7.5 seconds
Started Mar 03 02:23:26 PM PST 24
Finished Mar 03 02:23:34 PM PST 24
Peak memory 202668 kb
Host smart-d1a1936f-1c08-46b5-9754-0cac57bf00ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31151
65832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3115165832
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.970148661
Short name T10
Test name
Test status
Simulation time 8378487281 ps
CPU time 7.67 seconds
Started Mar 03 02:23:22 PM PST 24
Finished Mar 03 02:23:30 PM PST 24
Peak memory 202480 kb
Host smart-64ef13a6-f86d-46b0-bd8e-b0017388d2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97014
8661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.970148661
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2761041888
Short name T56
Test name
Test status
Simulation time 8370217013 ps
CPU time 7.81 seconds
Started Mar 03 02:23:22 PM PST 24
Finished Mar 03 02:23:29 PM PST 24
Peak memory 202608 kb
Host smart-8b35fe13-1dde-4bae-b750-95d8f23170e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27610
41888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2761041888
Directory /workspace/9.usbdev_smoke/latest
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