Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2040	1		T1	4		T2	2		T3	2
all_values[1]	2040	1		T1	4		T2	2		T3	2
all_values[2]	2040	1		T1	4		T2	2		T3	2
all_values[3]	2040	1		T1	4		T2	2		T3	2
all_values[4]	2040	1		T1	4		T2	2		T3	2
all_values[5]	2040	1		T1	4		T2	2		T3	2
all_values[6]	2040	1		T1	4		T2	2		T3	2
all_values[7]	2040	1		T1	4		T2	2		T3	2
all_values[8]	2040	1		T1	4		T2	2		T3	2
all_values[9]	2040	1		T1	4		T2	2		T3	2
all_values[10]	2040	1		T1	4		T2	2		T3	2
all_values[11]	2040	1		T1	4		T2	2		T3	2
all_values[12]	2040	1		T1	4		T2	2		T3	2
all_values[13]	2040	1		T1	4		T2	2		T3	2
all_values[14]	2040	1		T1	4		T2	2		T3	2
all_values[15]	2040	1		T1	4		T2	2		T3	2
all_values[16]	2040	1		T1	4		T2	2		T3	2
all_values[17]	2040	1		T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33866	1		T1	72		T2	36		T3	36
auto[1]	2854	1		T6	2		T22	3		T12	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32690	1		T1	72		T2	36		T3	36
auto[1]	4030	1		T57	62		T58	77		T59	116

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1600	1		T1	4		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	110	1		T58	2		T59	2		T61	5
all_values[0]	auto[1]	auto[0]	231	1		T22	3		T23	1		T24	1
all_values[0]	auto[1]	auto[1]	99	1		T57	3		T58	3		T59	6
all_values[1]	auto[0]	auto[0]	1552	1		T1	4		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	105	1		T58	3		T59	5		T60	2
all_values[1]	auto[1]	auto[0]	269	1		T6	2		T12	3		T14	3
all_values[1]	auto[1]	auto[1]	114	1		T57	4		T58	1		T59	3
all_values[2]	auto[0]	auto[0]	1799	1		T1	4		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	114	1		T58	4		T59	6		T60	2
all_values[2]	auto[1]	auto[0]	11	1		T215	2		T216	1		T217	1
all_values[2]	auto[1]	auto[1]	116	1		T58	1		T59	2		T60	5
all_values[3]	auto[0]	auto[0]	1792	1		T1	4		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	120	1		T57	1		T58	1		T59	1
all_values[3]	auto[1]	auto[0]	22	1		T60	1		T210	1		T218	1
all_values[3]	auto[1]	auto[1]	106	1		T57	4		T58	3		T59	7
all_values[4]	auto[0]	auto[0]	1799	1		T1	4		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	89	1		T57	4		T60	6		T211	6
all_values[4]	auto[1]	auto[0]	37	1		T57	1		T59	5		T60	1
all_values[4]	auto[1]	auto[1]	115	1		T58	4		T60	1		T61	5
all_values[5]	auto[0]	auto[0]	1792	1		T1	4		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	113	1		T57	4		T60	3		T61	1
all_values[5]	auto[1]	auto[0]	39	1		T58	1		T59	4		T61	1
all_values[5]	auto[1]	auto[1]	96	1		T58	4		T60	5		T61	3
all_values[6]	auto[0]	auto[0]	1790	1		T1	4		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	98	1		T60	4		T211	6		T219	6
all_values[6]	auto[1]	auto[0]	29	1		T57	1		T59	3		T60	1
all_values[6]	auto[1]	auto[1]	123	1		T57	4		T58	3		T59	4
all_values[7]	auto[0]	auto[0]	1791	1		T1	4		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	120	1		T57	1		T58	3		T59	3
all_values[7]	auto[1]	auto[0]	19	1		T61	1		T210	1		T218	1
all_values[7]	auto[1]	auto[1]	110	1		T57	4		T58	2		T59	5
all_values[8]	auto[0]	auto[0]	1796	1		T1	4		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	122	1		T57	3		T58	1		T59	6
all_values[8]	auto[1]	auto[0]	17	1		T218	2		T220	1		T216	3
all_values[8]	auto[1]	auto[1]	105	1		T57	2		T58	4		T59	2
all_values[9]	auto[0]	auto[0]	1787	1		T1	4		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	102	1		T58	3		T59	1		T60	5
all_values[9]	auto[1]	auto[0]	18	1		T59	1		T218	1		T221	1
all_values[9]	auto[1]	auto[1]	133	1		T57	5		T58	1		T59	5
all_values[10]	auto[0]	auto[0]	1804	1		T1	4		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	123	1		T58	3		T59	5		T60	4
all_values[10]	auto[1]	auto[0]	22	1		T59	1		T60	1		T221	1
all_values[10]	auto[1]	auto[1]	91	1		T57	5		T59	2		T60	1
all_values[11]	auto[0]	auto[0]	1785	1		T1	4		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	147	1		T57	2		T58	4		T59	4
all_values[11]	auto[1]	auto[0]	18	1		T61	4		T210	4		T222	4
all_values[11]	auto[1]	auto[1]	90	1		T57	3		T58	1		T59	4
all_values[12]	auto[0]	auto[0]	1793	1		T1	4		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	119	1		T58	3		T60	2		T210	5
all_values[12]	auto[1]	auto[0]	21	1		T57	3		T60	1		T211	1
all_values[12]	auto[1]	auto[1]	107	1		T58	2		T59	8		T60	4
all_values[13]	auto[0]	auto[0]	1796	1		T1	4		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	101	1		T58	3		T59	4		T60	2
all_values[13]	auto[1]	auto[0]	28	1		T57	3		T58	1		T60	1
all_values[13]	auto[1]	auto[1]	115	1		T59	3		T60	4		T61	3
all_values[14]	auto[0]	auto[0]	1790	1		T1	4		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	90	1		T59	3		T211	4		T219	3
all_values[14]	auto[1]	auto[0]	25	1		T57	1		T58	1		T60	2
all_values[14]	auto[1]	auto[1]	135	1		T57	3		T58	4		T59	4
all_values[15]	auto[0]	auto[0]	1784	1		T1	4		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	117	1		T57	4		T59	5		T60	6
all_values[15]	auto[1]	auto[0]	12	1		T58	1		T210	1		T211	1
all_values[15]	auto[1]	auto[1]	127	1		T57	1		T58	4		T59	3
all_values[16]	auto[0]	auto[0]	1795	1		T1	4		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	119	1		T57	4		T58	4		T59	1
all_values[16]	auto[1]	auto[0]	15	1		T59	1		T219	1		T222	1
all_values[16]	auto[1]	auto[1]	111	1		T57	1		T58	1		T59	6
all_values[17]	auto[0]	auto[0]	1797	1		T1	4		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	115	1		T58	2		T59	5		T60	1
all_values[17]	auto[1]	auto[0]	15	1		T57	3		T61	1		T210	2
all_values[17]	auto[1]	auto[1]	113	1		T58	3		T59	1		T60	6