Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2040	1		T1	4		T2	2		T3	2
all_pins[1]	2040	1		T1	4		T2	2		T3	2
all_pins[2]	2040	1		T1	4		T2	2		T3	2
all_pins[3]	2040	1		T1	4		T2	2		T3	2
all_pins[4]	2040	1		T1	4		T2	2		T3	2
all_pins[5]	2040	1		T1	4		T2	2		T3	2
all_pins[6]	2040	1		T1	4		T2	2		T3	2
all_pins[7]	2040	1		T1	4		T2	2		T3	2
all_pins[8]	2040	1		T1	4		T2	2		T3	2
all_pins[9]	2040	1		T1	4		T2	2		T3	2
all_pins[10]	2040	1		T1	4		T2	2		T3	2
all_pins[11]	2040	1		T1	4		T2	2		T3	2
all_pins[12]	2040	1		T1	4		T2	2		T3	2
all_pins[13]	2040	1		T1	4		T2	2		T3	2
all_pins[14]	2040	1		T1	4		T2	2		T3	2
all_pins[15]	2040	1		T1	4		T2	2		T3	2
all_pins[16]	2040	1		T1	4		T2	2		T3	2
all_pins[17]	2040	1		T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	35674	1		T1	72		T2	36		T3	36
values[0x1]	1046	1		T6	1		T12	1		T14	1
transitions[0x0=>0x1]	823	1		T6	1		T12	1		T14	1
transitions[0x1=>0x0]	835	1		T6	1		T12	1		T14	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1998	1		T1	4		T2	2		T3	2
all_pins[0]	values[0x1]	42	1		T57	1		T59	2		T60	2
all_pins[0]	transitions[0x0=>0x1]	30	1		T57	1		T59	1		T60	2
all_pins[0]	transitions[0x1=>0x0]	127	1		T6	1		T12	1		T14	1
all_pins[1]	values[0x0]	1901	1		T1	4		T2	2		T3	2
all_pins[1]	values[0x1]	139	1		T6	1		T12	1		T14	1
all_pins[1]	transitions[0x0=>0x1]	129	1		T6	1		T12	1		T14	1
all_pins[1]	transitions[0x1=>0x0]	52	1		T58	1		T60	3		T61	2
all_pins[2]	values[0x0]	1978	1		T1	4		T2	2		T3	2
all_pins[2]	values[0x1]	62	1		T58	1		T60	3		T61	2
all_pins[2]	transitions[0x0=>0x1]	44	1		T58	1		T60	1		T61	2
all_pins[2]	transitions[0x1=>0x0]	43	1		T57	3		T58	2		T59	6
all_pins[3]	values[0x0]	1979	1		T1	4		T2	2		T3	2
all_pins[3]	values[0x1]	61	1		T57	3		T58	2		T59	6
all_pins[3]	transitions[0x0=>0x1]	50	1		T57	3		T59	6		T60	3
all_pins[3]	transitions[0x1=>0x0]	37	1		T58	1		T60	1		T210	1
all_pins[4]	values[0x0]	1992	1		T1	4		T2	2		T3	2
all_pins[4]	values[0x1]	48	1		T58	3		T60	1		T210	1
all_pins[4]	transitions[0x0=>0x1]	43	1		T58	3		T60	1		T210	1
all_pins[4]	transitions[0x1=>0x0]	43	1		T60	2		T61	2		T210	2
all_pins[5]	values[0x0]	1992	1		T1	4		T2	2		T3	2
all_pins[5]	values[0x1]	48	1		T60	2		T61	2		T210	2
all_pins[5]	transitions[0x0=>0x1]	37	1		T60	1		T61	2		T210	2
all_pins[5]	transitions[0x1=>0x0]	52	1		T57	2		T59	3		T60	1
all_pins[6]	values[0x0]	1977	1		T1	4		T2	2		T3	2
all_pins[6]	values[0x1]	63	1		T57	2		T59	3		T60	2
all_pins[6]	transitions[0x0=>0x1]	54	1		T57	2		T59	2		T60	2
all_pins[6]	transitions[0x1=>0x0]	36	1		T57	1		T58	1		T59	1
all_pins[7]	values[0x0]	1995	1		T1	4		T2	2		T3	2
all_pins[7]	values[0x1]	45	1		T57	1		T58	1		T59	2
all_pins[7]	transitions[0x0=>0x1]	32	1		T58	1		T59	2		T60	2
all_pins[7]	transitions[0x1=>0x0]	28	1		T57	1		T58	1		T59	1
all_pins[8]	values[0x0]	1999	1		T1	4		T2	2		T3	2
all_pins[8]	values[0x1]	41	1		T57	2		T58	1		T59	1
all_pins[8]	transitions[0x0=>0x1]	30	1		T59	1		T60	2		T210	1
all_pins[8]	transitions[0x1=>0x0]	65	1		T59	2		T60	1		T210	1
all_pins[9]	values[0x0]	1964	1		T1	4		T2	2		T3	2
all_pins[9]	values[0x1]	76	1		T57	2		T58	1		T59	2
all_pins[9]	transitions[0x0=>0x1]	60	1		T57	2		T58	1		T59	2
all_pins[9]	transitions[0x1=>0x0]	32	1		T59	1		T60	1		T61	2
all_pins[10]	values[0x0]	1992	1		T1	4		T2	2		T3	2
all_pins[10]	values[0x1]	48	1		T59	1		T60	1		T61	3
all_pins[10]	transitions[0x0=>0x1]	38	1		T60	1		T61	3		T210	2
all_pins[10]	transitions[0x1=>0x0]	36	1		T57	2		T58	1		T59	2
all_pins[11]	values[0x0]	1994	1		T1	4		T2	2		T3	2
all_pins[11]	values[0x1]	46	1		T57	2		T58	1		T59	3
all_pins[11]	transitions[0x0=>0x1]	32	1		T57	2		T211	2		T219	2
all_pins[11]	transitions[0x1=>0x0]	39	1		T59	2		T60	1		T211	1
all_pins[12]	values[0x0]	1987	1		T1	4		T2	2		T3	2
all_pins[12]	values[0x1]	53	1		T58	1		T59	5		T60	3
all_pins[12]	transitions[0x0=>0x1]	46	1		T58	1		T59	4		T60	2
all_pins[12]	transitions[0x1=>0x0]	39	1		T59	1		T211	4		T223	2
all_pins[13]	values[0x0]	1994	1		T1	4		T2	2		T3	2
all_pins[13]	values[0x1]	46	1		T59	2		T60	1		T211	4
all_pins[13]	transitions[0x0=>0x1]	32	1		T59	1		T211	3		T223	1
all_pins[13]	transitions[0x1=>0x0]	46	1		T58	2		T59	2		T60	3
all_pins[14]	values[0x0]	1980	1		T1	4		T2	2		T3	2
all_pins[14]	values[0x1]	60	1		T58	2		T59	3		T60	4
all_pins[14]	transitions[0x0=>0x1]	43	1		T59	2		T60	3		T61	1
all_pins[14]	transitions[0x1=>0x0]	52	1		T59	1		T210	1		T211	3
all_pins[15]	values[0x0]	1971	1		T1	4		T2	2		T3	2
all_pins[15]	values[0x1]	69	1		T58	2		T59	2		T60	1
all_pins[15]	transitions[0x0=>0x1]	51	1		T58	2		T60	1		T61	2
all_pins[15]	transitions[0x1=>0x0]	29	1		T58	1		T59	1		T60	3
all_pins[16]	values[0x0]	1993	1		T1	4		T2	2		T3	2
all_pins[16]	values[0x1]	47	1		T58	1		T59	3		T60	3
all_pins[16]	transitions[0x0=>0x1]	41	1		T58	1		T59	3		T60	3
all_pins[16]	transitions[0x1=>0x0]	46	1		T58	1		T60	3		T61	1
all_pins[17]	values[0x0]	1988	1		T1	4		T2	2		T3	2
all_pins[17]	values[0x1]	52	1		T58	1		T60	3		T61	1
all_pins[17]	transitions[0x0=>0x1]	31	1		T58	1		T60	3		T61	1
all_pins[17]	transitions[0x1=>0x0]	33	1		T57	1		T59	2		T60	2