Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	227	1		T57	4		T58	4		T59	7
all_values[1]	227	1		T57	4		T58	4		T59	7
all_values[2]	227	1		T57	4		T58	4		T59	7
all_values[3]	227	1		T57	4		T58	4		T59	7
all_values[4]	227	1		T57	4		T58	4		T59	7
all_values[5]	227	1		T57	4		T58	4		T59	7
all_values[6]	227	1		T57	4		T58	4		T59	7
all_values[7]	227	1		T57	4		T58	4		T59	7
all_values[8]	227	1		T57	4		T58	4		T59	7
all_values[9]	227	1		T57	4		T58	4		T59	7
all_values[10]	227	1		T57	4		T58	4		T59	7
all_values[11]	227	1		T57	4		T58	4		T59	7
all_values[12]	227	1		T57	4		T58	4		T59	7
all_values[13]	227	1		T57	4		T58	4		T59	7
all_values[14]	227	1		T57	4		T58	4		T59	7
all_values[15]	227	1		T57	4		T58	4		T59	7
all_values[16]	227	1		T57	4		T58	4		T59	7
all_values[17]	227	1		T57	4		T58	4		T59	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2262	1		T57	43		T58	45		T59	68
auto[1]	1824	1		T57	29		T58	27		T59	58

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	746	1		T57	24		T58	13		T59	26
auto[1]	3340	1		T57	48		T58	59		T59	100

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2405	1		T57	45		T58	39		T59	78
auto[1]	1681	1		T57	27		T58	33		T59	48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	24	1		T57	1		T60	2		T223	2
all_values[0]	auto[0]	auto[0]	auto[1]	40	1		T59	1		T61	1		T211	3
all_values[0]	auto[0]	auto[1]	auto[0]	30	1		T57	1		T60	2		T210	1
all_values[0]	auto[0]	auto[1]	auto[1]	45	1		T57	1		T58	2		T59	3
all_values[0]	auto[1]	auto[0]	auto[1]	51	1		T58	2		T59	1		T61	3
all_values[0]	auto[1]	auto[1]	auto[1]	37	1		T57	1		T59	2		T60	2
all_values[1]	auto[0]	auto[0]	auto[0]	29	1		T57	1		T58	1		T218	1
all_values[1]	auto[0]	auto[0]	auto[1]	42	1		T58	1		T59	2		T60	1
all_values[1]	auto[0]	auto[1]	auto[0]	17	1		T218	1		T223	2		T224	4
all_values[1]	auto[0]	auto[1]	auto[1]	50	1		T57	2		T59	2		T60	4
all_values[1]	auto[1]	auto[0]	auto[1]	54	1		T57	1		T58	2		T59	2
all_values[1]	auto[1]	auto[1]	auto[1]	35	1		T59	1		T210	1		T219	1
all_values[2]	auto[0]	auto[0]	auto[0]	28	1		T57	4		T60	1		T61	1
all_values[2]	auto[0]	auto[0]	auto[1]	48	1		T58	1		T59	5		T210	1
all_values[2]	auto[0]	auto[1]	auto[0]	8	1		T215	2		T216	1		T224	2
all_values[2]	auto[0]	auto[1]	auto[1]	53	1		T58	1		T59	1		T60	3
all_values[2]	auto[1]	auto[0]	auto[1]	57	1		T58	2		T59	1		T60	2
all_values[2]	auto[1]	auto[1]	auto[1]	33	1		T60	1		T61	1		T219	1
all_values[3]	auto[0]	auto[0]	auto[0]	30	1		T58	1		T61	1		T210	2
all_values[3]	auto[0]	auto[0]	auto[1]	53	1		T60	1		T61	1		T211	2
all_values[3]	auto[0]	auto[1]	auto[0]	11	1		T60	1		T220	1		T225	1
all_values[3]	auto[0]	auto[1]	auto[1]	41	1		T57	1		T58	1		T59	2
all_values[3]	auto[1]	auto[0]	auto[1]	48	1		T57	2		T58	1		T59	2
all_values[3]	auto[1]	auto[1]	auto[1]	44	1		T57	1		T58	1		T59	3
all_values[4]	auto[0]	auto[0]	auto[0]	27	1		T57	1		T58	1		T59	3
all_values[4]	auto[0]	auto[0]	auto[1]	38	1		T57	1		T60	3		T211	1
all_values[4]	auto[0]	auto[1]	auto[0]	32	1		T59	4		T60	1		T221	1
all_values[4]	auto[0]	auto[1]	auto[1]	44	1		T58	1		T61	1		T210	2
all_values[4]	auto[1]	auto[0]	auto[1]	44	1		T57	1		T58	1		T60	1
all_values[4]	auto[1]	auto[1]	auto[1]	42	1		T57	1		T58	1		T60	2
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T57	1		T58	1		T59	4
all_values[5]	auto[0]	auto[0]	auto[1]	43	1		T57	2		T211	3		T219	4
all_values[5]	auto[0]	auto[1]	auto[0]	23	1		T59	3		T61	1		T210	1
all_values[5]	auto[0]	auto[1]	auto[1]	42	1		T58	2		T60	2		T61	1
all_values[5]	auto[1]	auto[0]	auto[1]	51	1		T57	1		T60	4		T61	1
all_values[5]	auto[1]	auto[1]	auto[1]	37	1		T58	1		T60	1		T61	1
all_values[6]	auto[0]	auto[0]	auto[0]	23	1		T57	1		T58	2		T59	1
all_values[6]	auto[0]	auto[0]	auto[1]	38	1		T60	2		T211	2		T219	2
all_values[6]	auto[0]	auto[1]	auto[0]	22	1		T59	3		T210	4		T219	1
all_values[6]	auto[0]	auto[1]	auto[1]	50	1		T57	1		T58	1		T59	2
all_values[6]	auto[1]	auto[0]	auto[1]	49	1		T59	1		T60	1		T211	3
all_values[6]	auto[1]	auto[1]	auto[1]	45	1		T57	2		T58	1		T60	1
all_values[7]	auto[0]	auto[0]	auto[0]	21	1		T218	1		T223	1		T216	1
all_values[7]	auto[0]	auto[0]	auto[1]	53	1		T57	1		T58	1		T59	2
all_values[7]	auto[0]	auto[1]	auto[0]	15	1		T61	1		T210	1		T216	3
all_values[7]	auto[0]	auto[1]	auto[1]	46	1		T57	2		T58	1		T59	3
all_values[7]	auto[1]	auto[0]	auto[1]	57	1		T57	1		T58	2		T59	2
all_values[7]	auto[1]	auto[1]	auto[1]	35	1		T60	3		T61	2		T210	1
all_values[8]	auto[0]	auto[0]	auto[0]	28	1		T60	1		T219	1		T218	1
all_values[8]	auto[0]	auto[0]	auto[1]	49	1		T57	1		T59	3		T61	1
all_values[8]	auto[0]	auto[1]	auto[0]	12	1		T218	1		T220	1		T216	1
all_values[8]	auto[0]	auto[1]	auto[1]	38	1		T58	2		T59	1		T60	2
all_values[8]	auto[1]	auto[0]	auto[1]	68	1		T57	1		T58	2		T59	3
all_values[8]	auto[1]	auto[1]	auto[1]	32	1		T57	2		T60	2		T61	1
all_values[9]	auto[0]	auto[0]	auto[0]	22	1		T58	1		T59	1		T210	1
all_values[9]	auto[0]	auto[0]	auto[1]	35	1		T58	1		T60	1		T61	1
all_values[9]	auto[0]	auto[1]	auto[0]	9	1		T59	1		T226	1		T227	1
all_values[9]	auto[0]	auto[1]	auto[1]	46	1		T57	2		T59	2		T60	2
all_values[9]	auto[1]	auto[0]	auto[1]	53	1		T57	1		T58	2		T59	2
all_values[9]	auto[1]	auto[1]	auto[1]	62	1		T57	1		T59	1		T60	2
all_values[10]	auto[0]	auto[0]	auto[0]	38	1		T58	2		T59	1		T60	1
all_values[10]	auto[0]	auto[0]	auto[1]	57	1		T58	1		T59	1		T60	2
all_values[10]	auto[0]	auto[1]	auto[0]	14	1		T60	2		T221	1		T216	1
all_values[10]	auto[0]	auto[1]	auto[1]	38	1		T57	2		T59	2		T60	1
all_values[10]	auto[1]	auto[0]	auto[1]	47	1		T57	1		T58	1		T59	2
all_values[10]	auto[1]	auto[1]	auto[1]	33	1		T57	1		T59	1		T61	1
all_values[11]	auto[0]	auto[0]	auto[0]	13	1		T61	1		T210	2		T216	1
all_values[11]	auto[0]	auto[0]	auto[1]	62	1		T58	2		T59	2		T60	4
all_values[11]	auto[0]	auto[1]	auto[0]	15	1		T61	3		T210	2		T222	4
all_values[11]	auto[0]	auto[1]	auto[1]	41	1		T57	1		T59	1		T60	1
all_values[11]	auto[1]	auto[0]	auto[1]	60	1		T57	3		T58	1		T59	1
all_values[11]	auto[1]	auto[1]	auto[1]	36	1		T58	1		T59	3		T60	1
all_values[12]	auto[0]	auto[0]	auto[0]	26	1		T57	3		T61	2		T211	1
all_values[12]	auto[0]	auto[0]	auto[1]	55	1		T58	2		T60	1		T210	3
all_values[12]	auto[0]	auto[1]	auto[0]	14	1		T57	1		T60	2		T211	1
all_values[12]	auto[0]	auto[1]	auto[1]	44	1		T59	1		T60	1		T61	1
all_values[12]	auto[1]	auto[0]	auto[1]	46	1		T58	1		T59	1		T60	1
all_values[12]	auto[1]	auto[1]	auto[1]	42	1		T58	1		T59	5		T60	2
all_values[13]	auto[0]	auto[0]	auto[0]	30	1		T57	3		T58	1		T59	1
all_values[13]	auto[0]	auto[0]	auto[1]	36	1		T58	1		T59	2		T60	1
all_values[13]	auto[0]	auto[1]	auto[0]	17	1		T57	1		T58	1		T61	1
all_values[13]	auto[0]	auto[1]	auto[1]	52	1		T59	1		T60	2		T61	1
all_values[13]	auto[1]	auto[0]	auto[1]	63	1		T58	1		T59	2		T60	1
all_values[13]	auto[1]	auto[1]	auto[1]	29	1		T59	1		T60	1		T61	1
all_values[14]	auto[0]	auto[0]	auto[0]	25	1		T57	2		T58	1		T59	1
all_values[14]	auto[0]	auto[0]	auto[1]	44	1		T59	1		T211	1		T219	1
all_values[14]	auto[0]	auto[1]	auto[0]	15	1		T60	3		T222	1		T216	1
all_values[14]	auto[0]	auto[1]	auto[1]	51	1		T57	1		T58	1		T59	2
all_values[14]	auto[1]	auto[0]	auto[1]	47	1		T59	3		T61	1		T210	1
all_values[14]	auto[1]	auto[1]	auto[1]	45	1		T57	1		T58	2		T60	3
all_values[15]	auto[0]	auto[0]	auto[0]	14	1		T58	1		T61	1		T211	2
all_values[15]	auto[0]	auto[0]	auto[1]	48	1		T57	1		T59	2		T60	2
all_values[15]	auto[0]	auto[1]	auto[0]	9	1		T210	1		T222	2		T223	1
all_values[15]	auto[0]	auto[1]	auto[1]	52	1		T58	1		T59	1		T60	1
all_values[15]	auto[1]	auto[0]	auto[1]	53	1		T57	2		T59	3		T60	3
all_values[15]	auto[1]	auto[1]	auto[1]	51	1		T57	1		T58	2		T59	1
all_values[16]	auto[0]	auto[0]	auto[0]	21	1		T59	1		T223	3		T220	2
all_values[16]	auto[0]	auto[0]	auto[1]	52	1		T57	2		T58	2		T59	1
all_values[16]	auto[0]	auto[1]	auto[0]	14	1		T219	1		T222	1		T223	1
all_values[16]	auto[0]	auto[1]	auto[1]	47	1		T59	3		T60	2		T61	1
all_values[16]	auto[1]	auto[0]	auto[1]	58	1		T57	1		T58	1		T60	2
all_values[16]	auto[1]	auto[1]	auto[1]	35	1		T57	1		T58	1		T59	2
all_values[17]	auto[0]	auto[0]	auto[0]	30	1		T57	3		T59	2		T60	1
all_values[17]	auto[0]	auto[0]	auto[1]	45	1		T59	3		T60	1		T211	2
all_values[17]	auto[0]	auto[1]	auto[0]	9	1		T57	1		T61	1		T210	2
all_values[17]	auto[0]	auto[1]	auto[1]	41	1		T58	1		T60	2		T61	1
all_values[17]	auto[1]	auto[0]	auto[1]	58	1		T58	2		T59	2		T60	1
all_values[17]	auto[1]	auto[1]	auto[1]	44	1		T58	1		T60	2		T61	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal