Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.60 95.96 87.25 96.95 45.31 93.96 97.36 96.40


Total test records in report: 727
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html
T589 /workspace/coverage/default/14.usbdev_random_length_out_trans.745700266 Mar 05 01:06:28 PM PST 24 Mar 05 01:06:36 PM PST 24 8369547375 ps
T590 /workspace/coverage/default/27.usbdev_in_trans.3176046499 Mar 05 01:07:22 PM PST 24 Mar 05 01:07:30 PM PST 24 8446626892 ps
T591 /workspace/coverage/default/34.usbdev_max_length_out_transaction.2125127836 Mar 05 01:07:34 PM PST 24 Mar 05 01:07:44 PM PST 24 8407820975 ps
T592 /workspace/coverage/default/45.usbdev_pkt_sent.1473577002 Mar 05 01:08:02 PM PST 24 Mar 05 01:08:10 PM PST 24 8423158207 ps
T593 /workspace/coverage/default/41.usbdev_pkt_sent.3034826942 Mar 05 01:07:47 PM PST 24 Mar 05 01:07:54 PM PST 24 8377052645 ps
T594 /workspace/coverage/default/11.usbdev_in_trans.3180538132 Mar 05 01:06:25 PM PST 24 Mar 05 01:06:33 PM PST 24 8448678706 ps
T595 /workspace/coverage/default/42.usbdev_random_length_out_trans.844232429 Mar 05 01:07:55 PM PST 24 Mar 05 01:08:03 PM PST 24 8388328664 ps
T177 /workspace/coverage/default/4.usbdev_fifo_rst.1868557655 Mar 05 01:05:58 PM PST 24 Mar 05 01:06:00 PM PST 24 61440018 ps
T596 /workspace/coverage/default/1.usbdev_smoke.547600730 Mar 05 01:05:47 PM PST 24 Mar 05 01:05:57 PM PST 24 8371502604 ps
T101 /workspace/coverage/default/5.usbdev_nak_trans.3823727226 Mar 05 01:05:53 PM PST 24 Mar 05 01:06:02 PM PST 24 8430918117 ps
T181 /workspace/coverage/default/34.usbdev_fifo_rst.2245841816 Mar 05 01:07:37 PM PST 24 Mar 05 01:07:39 PM PST 24 73841997 ps
T597 /workspace/coverage/default/15.usbdev_pkt_sent.3029086079 Mar 05 01:06:40 PM PST 24 Mar 05 01:06:48 PM PST 24 8387045738 ps
T598 /workspace/coverage/default/7.usbdev_random_length_out_trans.2560270249 Mar 05 01:06:04 PM PST 24 Mar 05 01:06:13 PM PST 24 8385298056 ps
T599 /workspace/coverage/default/10.usbdev_av_buffer.1727584446 Mar 05 01:06:14 PM PST 24 Mar 05 01:06:23 PM PST 24 8367868125 ps
T600 /workspace/coverage/default/4.usbdev_in_trans.3090410450 Mar 05 01:05:53 PM PST 24 Mar 05 01:06:01 PM PST 24 8417984944 ps
T601 /workspace/coverage/default/31.usbdev_fifo_rst.703348282 Mar 05 01:07:23 PM PST 24 Mar 05 01:07:25 PM PST 24 226393919 ps
T602 /workspace/coverage/default/31.usbdev_out_stall.1794750463 Mar 05 01:07:22 PM PST 24 Mar 05 01:07:30 PM PST 24 8427382163 ps
T603 /workspace/coverage/default/8.usbdev_out_trans_nak.3686349050 Mar 05 01:06:14 PM PST 24 Mar 05 01:06:22 PM PST 24 8386979609 ps
T604 /workspace/coverage/default/32.usbdev_setup_trans_ignored.2261509809 Mar 05 01:07:30 PM PST 24 Mar 05 01:07:39 PM PST 24 8362503676 ps
T605 /workspace/coverage/default/15.usbdev_av_buffer.2355769691 Mar 05 01:06:34 PM PST 24 Mar 05 01:06:42 PM PST 24 8371336502 ps
T606 /workspace/coverage/default/17.usbdev_fifo_rst.1052848438 Mar 05 01:06:45 PM PST 24 Mar 05 01:06:47 PM PST 24 73509570 ps
T607 /workspace/coverage/default/48.usbdev_out_stall.529679150 Mar 05 01:08:16 PM PST 24 Mar 05 01:08:24 PM PST 24 8444746478 ps
T608 /workspace/coverage/default/36.usbdev_fifo_rst.2425162264 Mar 05 01:07:34 PM PST 24 Mar 05 01:07:36 PM PST 24 126829503 ps
T609 /workspace/coverage/default/17.usbdev_smoke.1150053407 Mar 05 01:06:35 PM PST 24 Mar 05 01:06:44 PM PST 24 8374378553 ps
T610 /workspace/coverage/default/23.usbdev_min_length_out_transaction.2931986350 Mar 05 01:06:57 PM PST 24 Mar 05 01:07:04 PM PST 24 8359929214 ps
T611 /workspace/coverage/default/11.usbdev_nak_trans.1471399352 Mar 05 01:06:29 PM PST 24 Mar 05 01:06:38 PM PST 24 8500737104 ps
T612 /workspace/coverage/default/49.usbdev_setup_trans_ignored.2662936291 Mar 05 01:08:18 PM PST 24 Mar 05 01:08:26 PM PST 24 8362283553 ps
T613 /workspace/coverage/default/5.usbdev_setup_trans_ignored.1175346885 Mar 05 01:05:53 PM PST 24 Mar 05 01:06:02 PM PST 24 8378377999 ps
T614 /workspace/coverage/default/10.usbdev_random_length_out_trans.3814934620 Mar 05 01:06:16 PM PST 24 Mar 05 01:06:24 PM PST 24 8390228945 ps
T615 /workspace/coverage/default/46.usbdev_out_stall.637714074 Mar 05 01:08:07 PM PST 24 Mar 05 01:08:18 PM PST 24 8399453261 ps
T616 /workspace/coverage/default/32.usbdev_in_trans.2453015778 Mar 05 01:07:25 PM PST 24 Mar 05 01:07:35 PM PST 24 8398650709 ps
T617 /workspace/coverage/default/42.usbdev_out_stall.418214766 Mar 05 01:07:57 PM PST 24 Mar 05 01:08:05 PM PST 24 8381951846 ps
T618 /workspace/coverage/default/39.usbdev_in_trans.595658152 Mar 05 01:07:43 PM PST 24 Mar 05 01:07:50 PM PST 24 8451800919 ps
T619 /workspace/coverage/default/48.usbdev_nak_trans.1629517909 Mar 05 01:08:09 PM PST 24 Mar 05 01:08:17 PM PST 24 8440847874 ps
T620 /workspace/coverage/default/40.usbdev_max_length_out_transaction.882068165 Mar 05 01:07:45 PM PST 24 Mar 05 01:07:53 PM PST 24 8413439279 ps
T621 /workspace/coverage/default/49.usbdev_in_trans.3555304693 Mar 05 01:08:20 PM PST 24 Mar 05 01:08:29 PM PST 24 8401254913 ps
T622 /workspace/coverage/default/10.usbdev_min_length_out_transaction.600472616 Mar 05 01:06:29 PM PST 24 Mar 05 01:06:38 PM PST 24 8366390870 ps
T623 /workspace/coverage/default/11.usbdev_max_length_out_transaction.3941264790 Mar 05 01:06:24 PM PST 24 Mar 05 01:06:32 PM PST 24 8408356422 ps
T624 /workspace/coverage/default/3.usbdev_in_trans.539829736 Mar 05 01:05:54 PM PST 24 Mar 05 01:06:02 PM PST 24 8452624096 ps
T625 /workspace/coverage/default/42.usbdev_max_length_out_transaction.2897892295 Mar 05 01:07:52 PM PST 24 Mar 05 01:08:00 PM PST 24 8406521020 ps
T626 /workspace/coverage/default/24.usbdev_min_length_out_transaction.517184209 Mar 05 01:07:00 PM PST 24 Mar 05 01:07:08 PM PST 24 8372373565 ps
T627 /workspace/coverage/default/45.usbdev_smoke.2575536397 Mar 05 01:07:56 PM PST 24 Mar 05 01:08:04 PM PST 24 8368490304 ps
T628 /workspace/coverage/default/32.usbdev_min_length_out_transaction.301340690 Mar 05 01:07:28 PM PST 24 Mar 05 01:07:36 PM PST 24 8365440832 ps
T192 /workspace/coverage/default/15.usbdev_fifo_rst.3999675247 Mar 05 01:06:36 PM PST 24 Mar 05 01:06:38 PM PST 24 80102096 ps
T629 /workspace/coverage/default/38.usbdev_max_length_out_transaction.1718702477 Mar 05 01:07:43 PM PST 24 Mar 05 01:07:52 PM PST 24 8407323908 ps
T630 /workspace/coverage/default/30.usbdev_out_trans_nak.1928809315 Mar 05 01:07:28 PM PST 24 Mar 05 01:07:38 PM PST 24 8418522549 ps
T631 /workspace/coverage/default/38.usbdev_nak_trans.2432164354 Mar 05 01:07:40 PM PST 24 Mar 05 01:07:47 PM PST 24 8430911804 ps
T632 /workspace/coverage/default/28.usbdev_min_length_out_transaction.2706788243 Mar 05 01:07:28 PM PST 24 Mar 05 01:07:37 PM PST 24 8361991996 ps
T633 /workspace/coverage/default/35.usbdev_out_trans_nak.123230610 Mar 05 01:07:44 PM PST 24 Mar 05 01:07:55 PM PST 24 8383124260 ps
T634 /workspace/coverage/default/43.usbdev_setup_trans_ignored.295510915 Mar 05 01:08:00 PM PST 24 Mar 05 01:08:08 PM PST 24 8361022841 ps
T635 /workspace/coverage/default/34.usbdev_min_length_out_transaction.4178158499 Mar 05 01:07:30 PM PST 24 Mar 05 01:07:39 PM PST 24 8362686295 ps
T636 /workspace/coverage/default/13.usbdev_max_length_out_transaction.2416301278 Mar 05 01:06:25 PM PST 24 Mar 05 01:06:33 PM PST 24 8418006701 ps
T637 /workspace/coverage/default/31.usbdev_setup_trans_ignored.3384604714 Mar 05 01:07:24 PM PST 24 Mar 05 01:07:32 PM PST 24 8359547797 ps
T638 /workspace/coverage/default/20.usbdev_min_length_out_transaction.3709523352 Mar 05 01:06:51 PM PST 24 Mar 05 01:07:00 PM PST 24 8368607404 ps
T639 /workspace/coverage/default/22.usbdev_min_length_out_transaction.1905315733 Mar 05 01:07:00 PM PST 24 Mar 05 01:07:08 PM PST 24 8366037433 ps
T640 /workspace/coverage/default/20.usbdev_max_length_out_transaction.1158190332 Mar 05 01:06:53 PM PST 24 Mar 05 01:07:04 PM PST 24 8408459106 ps
T62 /workspace/coverage/default/4.usbdev_sec_cm.293992875 Mar 05 01:06:01 PM PST 24 Mar 05 01:06:02 PM PST 24 89175987 ps
T641 /workspace/coverage/default/36.usbdev_av_buffer.3149521366 Mar 05 01:07:39 PM PST 24 Mar 05 01:07:47 PM PST 24 8463183548 ps
T642 /workspace/coverage/default/0.usbdev_setup_trans_ignored.3202355011 Mar 05 01:05:38 PM PST 24 Mar 05 01:05:47 PM PST 24 8365193739 ps
T643 /workspace/coverage/default/22.usbdev_out_trans_nak.4111404391 Mar 05 01:07:02 PM PST 24 Mar 05 01:07:10 PM PST 24 8362990728 ps
T644 /workspace/coverage/default/46.usbdev_smoke.4240060025 Mar 05 01:08:06 PM PST 24 Mar 05 01:08:13 PM PST 24 8363702883 ps
T645 /workspace/coverage/default/14.usbdev_fifo_rst.2555799701 Mar 05 01:06:39 PM PST 24 Mar 05 01:06:41 PM PST 24 132638699 ps
T646 /workspace/coverage/default/7.usbdev_av_buffer.2827156993 Mar 05 01:06:02 PM PST 24 Mar 05 01:06:09 PM PST 24 8373212722 ps
T647 /workspace/coverage/default/8.usbdev_fifo_rst.395817625 Mar 05 01:06:15 PM PST 24 Mar 05 01:06:17 PM PST 24 198650868 ps
T648 /workspace/coverage/default/4.usbdev_out_stall.1296038510 Mar 05 01:05:57 PM PST 24 Mar 05 01:06:06 PM PST 24 8375855980 ps
T649 /workspace/coverage/default/23.usbdev_out_trans_nak.2210165296 Mar 05 01:06:59 PM PST 24 Mar 05 01:07:08 PM PST 24 8394324430 ps
T650 /workspace/coverage/default/8.usbdev_nak_trans.2702564156 Mar 05 01:06:04 PM PST 24 Mar 05 01:06:12 PM PST 24 8389382402 ps
T651 /workspace/coverage/default/12.usbdev_nak_trans.2815243338 Mar 05 01:06:26 PM PST 24 Mar 05 01:06:34 PM PST 24 8414510447 ps
T63 /workspace/coverage/default/1.usbdev_sec_cm.657733324 Mar 05 01:05:45 PM PST 24 Mar 05 01:05:46 PM PST 24 312519858 ps
T652 /workspace/coverage/default/45.usbdev_av_buffer.4184072595 Mar 05 01:08:02 PM PST 24 Mar 05 01:08:09 PM PST 24 8368330002 ps
T653 /workspace/coverage/default/48.usbdev_pkt_sent.3035936006 Mar 05 01:08:09 PM PST 24 Mar 05 01:08:17 PM PST 24 8404678133 ps
T654 /workspace/coverage/default/6.usbdev_setup_trans_ignored.2659546731 Mar 05 01:06:03 PM PST 24 Mar 05 01:06:10 PM PST 24 8360740007 ps
T655 /workspace/coverage/default/44.usbdev_max_length_out_transaction.1143420316 Mar 05 01:07:58 PM PST 24 Mar 05 01:08:05 PM PST 24 8415879957 ps
T656 /workspace/coverage/default/35.usbdev_pkt_sent.3091796609 Mar 05 01:07:37 PM PST 24 Mar 05 01:07:45 PM PST 24 8385454605 ps
T657 /workspace/coverage/default/14.usbdev_nak_trans.3860646187 Mar 05 01:06:29 PM PST 24 Mar 05 01:06:37 PM PST 24 8378820195 ps
T658 /workspace/coverage/default/43.usbdev_min_length_out_transaction.1794138036 Mar 05 01:07:59 PM PST 24 Mar 05 01:08:08 PM PST 24 8363862581 ps
T659 /workspace/coverage/default/5.usbdev_pkt_sent.2152941896 Mar 05 01:05:53 PM PST 24 Mar 05 01:06:02 PM PST 24 8445369929 ps
T660 /workspace/coverage/default/29.usbdev_in_trans.1772673657 Mar 05 01:07:31 PM PST 24 Mar 05 01:07:39 PM PST 24 8450104430 ps
T661 /workspace/coverage/default/10.usbdev_max_length_out_transaction.500633821 Mar 05 01:06:13 PM PST 24 Mar 05 01:06:21 PM PST 24 8409257570 ps
T662 /workspace/coverage/default/43.usbdev_av_buffer.560001680 Mar 05 01:08:01 PM PST 24 Mar 05 01:08:08 PM PST 24 8369392808 ps
T663 /workspace/coverage/default/2.usbdev_setup_trans_ignored.715326789 Mar 05 01:05:45 PM PST 24 Mar 05 01:05:55 PM PST 24 8441759809 ps
T45 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3213161452 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:35 PM PST 24 121296572 ps
T46 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.994213801 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:30 PM PST 24 74796505 ps
T57 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2268735772 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:39 PM PST 24 26343760 ps
T47 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3172355630 Mar 05 12:39:43 PM PST 24 Mar 05 12:39:44 PM PST 24 82733812 ps
T58 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3616634513 Mar 05 12:40:03 PM PST 24 Mar 05 12:40:04 PM PST 24 66092392 ps
T137 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2764072911 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:31 PM PST 24 112002196 ps
T51 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3948380088 Mar 05 12:39:42 PM PST 24 Mar 05 12:39:45 PM PST 24 68899432 ps
T138 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2777138348 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:48 PM PST 24 273528021 ps
T52 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1824978196 Mar 05 12:39:42 PM PST 24 Mar 05 12:39:44 PM PST 24 170305795 ps
T59 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2595439138 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:30 PM PST 24 32905260 ps
T60 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2747374102 Mar 05 12:39:47 PM PST 24 Mar 05 12:39:48 PM PST 24 31475400 ps
T53 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3277039364 Mar 05 12:39:14 PM PST 24 Mar 05 12:39:15 PM PST 24 104913168 ps
T77 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2796339184 Mar 05 12:39:35 PM PST 24 Mar 05 12:39:36 PM PST 24 35926014 ps
T61 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.349002299 Mar 05 12:39:49 PM PST 24 Mar 05 12:39:55 PM PST 24 35830713 ps
T664 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3039546164 Mar 05 12:39:28 PM PST 24 Mar 05 12:39:30 PM PST 24 250290881 ps
T210 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.197168163 Mar 05 12:39:50 PM PST 24 Mar 05 12:39:51 PM PST 24 26233162 ps
T211 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3821090751 Mar 05 12:39:28 PM PST 24 Mar 05 12:39:29 PM PST 24 30535505 ps
T219 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2488432630 Mar 05 12:39:45 PM PST 24 Mar 05 12:39:46 PM PST 24 26360687 ps
T78 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1788132427 Mar 05 12:39:35 PM PST 24 Mar 05 12:39:41 PM PST 24 70419478 ps
T79 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3388043058 Mar 05 12:39:44 PM PST 24 Mar 05 12:39:46 PM PST 24 124729296 ps
T80 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4036388817 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:18 PM PST 24 35172662 ps
T218 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2532486509 Mar 05 12:39:45 PM PST 24 Mar 05 12:39:46 PM PST 24 25985574 ps
T81 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3143386491 Mar 05 12:39:14 PM PST 24 Mar 05 12:39:17 PM PST 24 128780222 ps
T160 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1844150104 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:32 PM PST 24 36828675 ps
T161 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4038669129 Mar 05 12:39:43 PM PST 24 Mar 05 12:39:44 PM PST 24 159174192 ps
T142 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1669602564 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:41 PM PST 24 133935244 ps
T139 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1171494321 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:41 PM PST 24 125311731 ps
T54 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4010252149 Mar 05 12:40:57 PM PST 24 Mar 05 12:40:58 PM PST 24 285553554 ps
T143 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2523350961 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:42 PM PST 24 188539563 ps
T141 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1472991036 Mar 05 12:39:37 PM PST 24 Mar 05 12:39:40 PM PST 24 327016733 ps
T162 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1487594295 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:34 PM PST 24 77398503 ps
T140 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3329722592 Mar 05 12:39:52 PM PST 24 Mar 05 12:39:53 PM PST 24 81103640 ps
T221 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1894008995 Mar 05 12:39:45 PM PST 24 Mar 05 12:39:46 PM PST 24 24266970 ps
T198 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3805076676 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:20 PM PST 24 69994733 ps
T222 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3927146781 Mar 05 12:39:37 PM PST 24 Mar 05 12:39:38 PM PST 24 28532229 ps
T228 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.983569566 Mar 05 12:39:21 PM PST 24 Mar 05 12:39:24 PM PST 24 131863557 ps
T144 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3272482051 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:40 PM PST 24 75474253 ps
T223 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3595122017 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:39 PM PST 24 20131024 ps
T194 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4079548424 Mar 05 12:39:46 PM PST 24 Mar 05 12:39:47 PM PST 24 113184388 ps
T220 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.71543629 Mar 05 12:39:47 PM PST 24 Mar 05 12:39:48 PM PST 24 23492268 ps
T55 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.304727240 Mar 05 12:39:27 PM PST 24 Mar 05 12:39:28 PM PST 24 31687879 ps
T145 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2864308631 Mar 05 12:39:32 PM PST 24 Mar 05 12:39:33 PM PST 24 50752949 ps
T215 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3965262785 Mar 05 12:39:34 PM PST 24 Mar 05 12:39:35 PM PST 24 26318354 ps
T146 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.963016084 Mar 05 12:39:28 PM PST 24 Mar 05 12:39:29 PM PST 24 55846518 ps
T147 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4242047787 Mar 05 12:39:30 PM PST 24 Mar 05 12:39:32 PM PST 24 73078553 ps
T216 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3958956246 Mar 05 12:39:42 PM PST 24 Mar 05 12:39:43 PM PST 24 23349448 ps
T665 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1268737866 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:42 PM PST 24 151028533 ps
T205 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4207086355 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:31 PM PST 24 45516688 ps
T666 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1791404393 Mar 05 12:40:01 PM PST 24 Mar 05 12:40:01 PM PST 24 19682671 ps
T148 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4080583003 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:39 PM PST 24 80948776 ps
T206 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1576468757 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:32 PM PST 24 94211000 ps
T195 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1846864148 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:34 PM PST 24 48818324 ps
T197 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1135545569 Mar 05 12:39:35 PM PST 24 Mar 05 12:39:38 PM PST 24 86463408 ps
T667 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3735921503 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:42 PM PST 24 56758095 ps
T668 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.395048706 Mar 05 12:39:47 PM PST 24 Mar 05 12:39:48 PM PST 24 24564783 ps
T669 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3534041216 Mar 05 12:39:36 PM PST 24 Mar 05 12:39:41 PM PST 24 465953346 ps
T149 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4246125659 Mar 05 12:42:53 PM PST 24 Mar 05 12:42:56 PM PST 24 89476818 ps
T204 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3550465047 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:39 PM PST 24 28164504 ps
T213 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4275103898 Mar 05 12:39:27 PM PST 24 Mar 05 12:39:31 PM PST 24 453895294 ps
T209 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2595903358 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:34 PM PST 24 81451689 ps
T670 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.661069847 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:23 PM PST 24 41207510 ps
T217 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2504729472 Mar 05 12:39:25 PM PST 24 Mar 05 12:39:27 PM PST 24 37224613 ps
T150 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2776297154 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:31 PM PST 24 153788767 ps
T151 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.972282375 Mar 05 12:39:34 PM PST 24 Mar 05 12:39:35 PM PST 24 47359888 ps
T203 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2411533733 Mar 05 12:39:36 PM PST 24 Mar 05 12:39:37 PM PST 24 48206939 ps
T196 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.430315397 Mar 05 12:39:16 PM PST 24 Mar 05 12:39:17 PM PST 24 55082567 ps
T199 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1825925202 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:34 PM PST 24 87820587 ps
T671 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3783231288 Mar 05 12:39:27 PM PST 24 Mar 05 12:39:29 PM PST 24 42592512 ps
T200 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3723949617 Mar 05 12:39:32 PM PST 24 Mar 05 12:39:35 PM PST 24 84618555 ps
T672 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.8408972 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:31 PM PST 24 54805466 ps
T673 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2265577386 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:40 PM PST 24 22217377 ps
T674 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3003908075 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:40 PM PST 24 121584367 ps
T675 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3803847002 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:41 PM PST 24 22724968 ps
T676 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.281305053 Mar 05 12:39:25 PM PST 24 Mar 05 12:39:26 PM PST 24 25349395 ps
T201 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2541355562 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:40 PM PST 24 81598470 ps
T224 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2196909681 Mar 05 12:39:47 PM PST 24 Mar 05 12:39:48 PM PST 24 53000025 ps
T677 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1680785990 Mar 05 12:39:21 PM PST 24 Mar 05 12:39:23 PM PST 24 69050332 ps
T678 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.947620961 Mar 05 12:39:24 PM PST 24 Mar 05 12:39:25 PM PST 24 31111581 ps
T202 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3701477593 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:40 PM PST 24 63206616 ps
T679 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3330058771 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:39 PM PST 24 69235399 ps
T152 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.887529913 Mar 05 12:40:25 PM PST 24 Mar 05 12:40:28 PM PST 24 158050887 ps
T207 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1658222596 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:33 PM PST 24 131590813 ps
T208 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3357100742 Mar 05 12:39:44 PM PST 24 Mar 05 12:39:46 PM PST 24 145824588 ps
T680 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.444837151 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:40 PM PST 24 54276632 ps
T153 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.81256358 Mar 05 12:39:36 PM PST 24 Mar 05 12:39:37 PM PST 24 31500746 ps
T681 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3854388572 Mar 05 12:39:57 PM PST 24 Mar 05 12:39:58 PM PST 24 29484888 ps
T154 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2450063096 Mar 05 12:39:23 PM PST 24 Mar 05 12:39:24 PM PST 24 39128459 ps
T682 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1102079418 Mar 05 12:39:23 PM PST 24 Mar 05 12:39:25 PM PST 24 107464760 ps
T683 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3377758117 Mar 05 12:39:34 PM PST 24 Mar 05 12:39:36 PM PST 24 130965158 ps
T684 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3132773652 Mar 05 12:39:28 PM PST 24 Mar 05 12:39:29 PM PST 24 25710425 ps
T685 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.415148748 Mar 05 12:39:32 PM PST 24 Mar 05 12:39:33 PM PST 24 58036363 ps
T686 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1969484825 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:33 PM PST 24 70931455 ps
T155 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3115456548 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:30 PM PST 24 72408409 ps
T226 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.645197890 Mar 05 12:39:43 PM PST 24 Mar 05 12:39:44 PM PST 24 21671455 ps
T156 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2505727543 Mar 05 12:39:24 PM PST 24 Mar 05 12:39:27 PM PST 24 209984412 ps
T225 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1031944903 Mar 05 12:39:59 PM PST 24 Mar 05 12:40:00 PM PST 24 22234920 ps
T687 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1805806994 Mar 05 12:39:20 PM PST 24 Mar 05 12:39:21 PM PST 24 127318502 ps
T688 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1946137136 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:41 PM PST 24 87196518 ps
T689 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3629095186 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:33 PM PST 24 153898947 ps
T690 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2949687024 Mar 05 12:39:28 PM PST 24 Mar 05 12:39:29 PM PST 24 117350136 ps
T691 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.253297195 Mar 05 12:39:17 PM PST 24 Mar 05 12:39:18 PM PST 24 42644014 ps
T692 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.174991118 Mar 05 12:39:42 PM PST 24 Mar 05 12:39:43 PM PST 24 28537015 ps
T693 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2305888334 Mar 05 12:40:00 PM PST 24 Mar 05 12:40:01 PM PST 24 33666229 ps
T212 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1038410745 Mar 05 12:39:24 PM PST 24 Mar 05 12:39:26 PM PST 24 134324160 ps
T694 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2701932145 Mar 05 12:39:43 PM PST 24 Mar 05 12:39:44 PM PST 24 32727280 ps
T695 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3885315804 Mar 05 12:39:40 PM PST 24 Mar 05 12:39:41 PM PST 24 130146604 ps
T696 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1477276909 Mar 05 12:40:07 PM PST 24 Mar 05 12:40:08 PM PST 24 34564792 ps
T697 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2157182421 Mar 05 12:39:35 PM PST 24 Mar 05 12:39:39 PM PST 24 46408591 ps
T698 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.435172474 Mar 05 12:39:51 PM PST 24 Mar 05 12:39:53 PM PST 24 84472208 ps
T699 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1304230687 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:32 PM PST 24 25600338 ps
T157 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2150834814 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:39 PM PST 24 160104343 ps
T700 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2910273338 Mar 05 12:39:36 PM PST 24 Mar 05 12:39:37 PM PST 24 42454737 ps
T227 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1486650957 Mar 05 12:39:52 PM PST 24 Mar 05 12:39:53 PM PST 24 38045792 ps
T701 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3165543429 Mar 05 12:39:27 PM PST 24 Mar 05 12:39:29 PM PST 24 163442789 ps
T56 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.523620166 Mar 05 12:39:32 PM PST 24 Mar 05 12:39:33 PM PST 24 49678136 ps
T702 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1844201743 Mar 05 12:39:19 PM PST 24 Mar 05 12:39:21 PM PST 24 76369256 ps
T703 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.301052776 Mar 05 12:39:37 PM PST 24 Mar 05 12:39:40 PM PST 24 95418632 ps
T214 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.689140171 Mar 05 12:39:22 PM PST 24 Mar 05 12:39:25 PM PST 24 269549293 ps
T704 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1498442300 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:40 PM PST 24 52846322 ps
T158 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1039317600 Mar 05 12:39:28 PM PST 24 Mar 05 12:39:29 PM PST 24 33249567 ps
T705 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.407431700 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:35 PM PST 24 189046165 ps
T706 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4158243865 Mar 05 12:39:25 PM PST 24 Mar 05 12:39:27 PM PST 24 143240956 ps
T707 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1559518710 Mar 05 12:39:43 PM PST 24 Mar 05 12:39:44 PM PST 24 20382407 ps
T159 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4171106426 Mar 05 12:39:39 PM PST 24 Mar 05 12:39:40 PM PST 24 31150554 ps
T708 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2327688302 Mar 05 12:39:29 PM PST 24 Mar 05 12:39:30 PM PST 24 144363965 ps
T709 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2988724389 Mar 05 12:43:23 PM PST 24 Mar 05 12:43:25 PM PST 24 151838069 ps
T710 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2288861793 Mar 05 12:39:34 PM PST 24 Mar 05 12:39:35 PM PST 24 22305375 ps
T711 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2682886942 Mar 05 12:39:11 PM PST 24 Mar 05 12:39:14 PM PST 24 130753018 ps
T712 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2967503858 Mar 05 12:39:47 PM PST 24 Mar 05 12:39:48 PM PST 24 24011724 ps
T713 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3363102099 Mar 05 12:39:47 PM PST 24 Mar 05 12:39:48 PM PST 24 24800217 ps
T714 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.679773435 Mar 05 12:39:21 PM PST 24 Mar 05 12:39:23 PM PST 24 22400755 ps
T715 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1925098713 Mar 05 12:39:47 PM PST 24 Mar 05 12:39:48 PM PST 24 78427938 ps
T229 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4225189791 Mar 05 12:39:30 PM PST 24 Mar 05 12:39:33 PM PST 24 274638952 ps
T716 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2205381636 Mar 05 12:39:12 PM PST 24 Mar 05 12:39:15 PM PST 24 89560034 ps
T717 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.596812976 Mar 05 12:39:50 PM PST 24 Mar 05 12:39:51 PM PST 24 35883180 ps
T718 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1840595005 Mar 05 12:39:50 PM PST 24 Mar 05 12:39:50 PM PST 24 28387113 ps
T230 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1784175371 Mar 05 12:39:34 PM PST 24 Mar 05 12:39:37 PM PST 24 372612917 ps
T719 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2226993912 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:09 PM PST 24 67091103 ps
T720 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1802728562 Mar 05 12:39:18 PM PST 24 Mar 05 12:39:19 PM PST 24 41861905 ps
T721 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1682174604 Mar 05 12:39:48 PM PST 24 Mar 05 12:39:48 PM PST 24 20818664 ps
T722 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2584624794 Mar 05 12:39:26 PM PST 24 Mar 05 12:39:27 PM PST 24 76762434 ps
T723 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4164312512 Mar 05 12:39:36 PM PST 24 Mar 05 12:39:37 PM PST 24 60193488 ps
T724 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1740349930 Mar 05 12:39:36 PM PST 24 Mar 05 12:39:39 PM PST 24 273000484 ps
T725 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.566489389 Mar 05 12:39:42 PM PST 24 Mar 05 12:39:42 PM PST 24 28875812 ps
T726 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2731169111 Mar 05 12:39:30 PM PST 24 Mar 05 12:39:34 PM PST 24 118484782 ps
T727 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3616853396 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:09 PM PST 24 273718463 ps

Test location /workspace/coverage/default/1.usbdev_in_trans.2493099694
Short name T6
Test name
Test status
Simulation time 8407152405 ps
CPU time 7.79 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:50 PM PST 24
Peak memory 202404 kb
Host smart-ded6f27e-e7c7-4ef3-9f3e-83599e6d5539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24930
99694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2493099694
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2747374102
Short name T60
Test name
Test status
Simulation time 31475400 ps
CPU time 0.66 seconds
Started Mar 05 12:39:47 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 202200 kb
Host smart-58ef22f4-490e-4f68-92cf-5861a4634a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2747374102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2747374102
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3213161452
Short name T45
Test name
Test status
Simulation time 121296572 ps
CPU time 1.74 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 211084 kb
Host smart-179919ec-773a-45ab-b870-0e7a6ecc791e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213161452 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.3213161452
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2357227077
Short name T240
Test name
Test status
Simulation time 247325276 ps
CPU time 2.05 seconds
Started Mar 05 01:07:01 PM PST 24
Finished Mar 05 01:07:04 PM PST 24
Peak memory 202304 kb
Host smart-0b179682-5acc-4c57-a8e6-be9fff3d8778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23572
27077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2357227077
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.131650645
Short name T4
Test name
Test status
Simulation time 8383271675 ps
CPU time 9.01 seconds
Started Mar 05 01:07:13 PM PST 24
Finished Mar 05 01:07:22 PM PST 24
Peak memory 202436 kb
Host smart-25150266-b74a-4beb-8b38-b120712143fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13165
0645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.131650645
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3927281082
Short name T49
Test name
Test status
Simulation time 378644600 ps
CPU time 1.21 seconds
Started Mar 05 01:05:32 PM PST 24
Finished Mar 05 01:05:33 PM PST 24
Peak memory 218352 kb
Host smart-fac39623-3547-4a79-bb77-60644bd12cb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3927281082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3927281082
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/18.usbdev_smoke.438954431
Short name T23
Test name
Test status
Simulation time 8370836668 ps
CPU time 7.94 seconds
Started Mar 05 01:06:44 PM PST 24
Finished Mar 05 01:06:52 PM PST 24
Peak memory 202312 kb
Host smart-bf46739d-8438-485c-ba91-85cc9c0774c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43895
4431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.438954431
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.856086296
Short name T84
Test name
Test status
Simulation time 8392684769 ps
CPU time 6.97 seconds
Started Mar 05 01:07:38 PM PST 24
Finished Mar 05 01:07:45 PM PST 24
Peak memory 202476 kb
Host smart-013c1087-6a83-4037-bb81-5776e9c2ee46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85608
6296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.856086296
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3965262785
Short name T215
Test name
Test status
Simulation time 26318354 ps
CPU time 0.65 seconds
Started Mar 05 12:39:34 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 202036 kb
Host smart-d19cce6c-6fa4-41c0-8390-9c08cbf8ef08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3965262785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3965262785
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3624919791
Short name T11
Test name
Test status
Simulation time 8380085401 ps
CPU time 7.39 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:51 PM PST 24
Peak memory 202476 kb
Host smart-06145213-cce2-4d79-ad09-c82f5673a0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36249
19791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3624919791
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1669602564
Short name T142
Test name
Test status
Simulation time 133935244 ps
CPU time 2.29 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 202884 kb
Host smart-da3c2ecb-9036-4367-9096-05bddd8d0c0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1669602564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1669602564
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2864308631
Short name T145
Test name
Test status
Simulation time 50752949 ps
CPU time 0.85 seconds
Started Mar 05 12:39:32 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 202632 kb
Host smart-a1b2faa6-6697-4ac5-afca-c83db9ad2da5
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864308631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2864308631
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.197168163
Short name T210
Test name
Test status
Simulation time 26233162 ps
CPU time 0.67 seconds
Started Mar 05 12:39:50 PM PST 24
Finished Mar 05 12:39:51 PM PST 24
Peak memory 201956 kb
Host smart-e2592cf8-9e59-4514-ae07-a0adcadda08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=197168163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.197168163
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2917291826
Short name T169
Test name
Test status
Simulation time 152776534 ps
CPU time 1.4 seconds
Started Mar 05 01:07:24 PM PST 24
Finished Mar 05 01:07:26 PM PST 24
Peak memory 202500 kb
Host smart-4e5984ad-7488-4a85-9e5e-8e22cee5d10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29172
91826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2917291826
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.71543629
Short name T220
Test name
Test status
Simulation time 23492268 ps
CPU time 0.63 seconds
Started Mar 05 12:39:47 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 202032 kb
Host smart-ae34fdeb-ac4b-460e-8664-3cab84d9d249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=71543629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.71543629
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2777138348
Short name T138
Test name
Test status
Simulation time 273528021 ps
CPU time 2.84 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 202864 kb
Host smart-dd47b80b-8823-4702-b399-7f4a067c6bfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2777138348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2777138348
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1208286624
Short name T254
Test name
Test status
Simulation time 8389341887 ps
CPU time 7.25 seconds
Started Mar 05 01:06:44 PM PST 24
Finished Mar 05 01:06:51 PM PST 24
Peak memory 202324 kb
Host smart-d0e02dae-a186-4a3e-b065-8e4cc1b9cc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12082
86624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1208286624
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1904611439
Short name T82
Test name
Test status
Simulation time 8448740594 ps
CPU time 7.43 seconds
Started Mar 05 01:06:36 PM PST 24
Finished Mar 05 01:06:43 PM PST 24
Peak memory 202484 kb
Host smart-1ce8666d-30ba-42e2-8ca2-eb4c9dd80186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19046
11439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1904611439
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4275103898
Short name T213
Test name
Test status
Simulation time 453895294 ps
CPU time 4.4 seconds
Started Mar 05 12:39:27 PM PST 24
Finished Mar 05 12:39:31 PM PST 24
Peak memory 202852 kb
Host smart-a608eaf7-87b2-4439-a731-24e6e852c43a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4275103898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.4275103898
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3131677788
Short name T178
Test name
Test status
Simulation time 222765314 ps
CPU time 1.91 seconds
Started Mar 05 01:08:27 PM PST 24
Finished Mar 05 01:08:30 PM PST 24
Peak memory 202320 kb
Host smart-8ad10bd0-8270-485b-ad9f-9ac7d96bb44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31316
77788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3131677788
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1847543395
Short name T3
Test name
Test status
Simulation time 235529693 ps
CPU time 2.09 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:44 PM PST 24
Peak memory 202488 kb
Host smart-fd6755ff-09f8-4224-993b-2e701f4ed34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18475
43395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1847543395
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2532486509
Short name T218
Test name
Test status
Simulation time 25985574 ps
CPU time 0.63 seconds
Started Mar 05 12:39:45 PM PST 24
Finished Mar 05 12:39:46 PM PST 24
Peak memory 201964 kb
Host smart-135a0b4b-c117-4dbe-bbfa-408bc041e417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2532486509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2532486509
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4010252149
Short name T54
Test name
Test status
Simulation time 285553554 ps
CPU time 0.98 seconds
Started Mar 05 12:40:57 PM PST 24
Finished Mar 05 12:40:58 PM PST 24
Peak memory 202528 kb
Host smart-8f9e0d98-df1a-4906-a2f7-a1e20d687452
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010252149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4010252149
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2929200042
Short name T166
Test name
Test status
Simulation time 55439745 ps
CPU time 1.01 seconds
Started Mar 05 01:07:47 PM PST 24
Finished Mar 05 01:07:49 PM PST 24
Peak memory 202500 kb
Host smart-614b484f-d68d-4ab8-b90e-0ece83790ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
00042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2929200042
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.983569566
Short name T228
Test name
Test status
Simulation time 131863557 ps
CPU time 2.36 seconds
Started Mar 05 12:39:21 PM PST 24
Finished Mar 05 12:39:24 PM PST 24
Peak memory 202852 kb
Host smart-b29b7027-9887-44cd-87ab-8186af2b2b31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=983569566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.983569566
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.947620961
Short name T678
Test name
Test status
Simulation time 31111581 ps
CPU time 0.65 seconds
Started Mar 05 12:39:24 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 201936 kb
Host smart-7456c052-bda7-4aed-ac6e-4b60959b0dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=947620961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.947620961
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2595439138
Short name T59
Test name
Test status
Simulation time 32905260 ps
CPU time 0.68 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 202036 kb
Host smart-f0e1b0cd-b5c6-4f85-8404-3a66bcc2f42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2595439138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2595439138
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1472991036
Short name T141
Test name
Test status
Simulation time 327016733 ps
CPU time 2.66 seconds
Started Mar 05 12:39:37 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 202904 kb
Host smart-55014f37-e030-41da-bb56-f1f09e2efcff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1472991036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1472991036
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.689140171
Short name T214
Test name
Test status
Simulation time 269549293 ps
CPU time 2.74 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 202848 kb
Host smart-a50e034f-388f-489f-8855-1bca0b071745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=689140171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.689140171
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1443356105
Short name T26
Test name
Test status
Simulation time 8460283680 ps
CPU time 7.68 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:52 PM PST 24
Peak memory 202404 kb
Host smart-d1e980e8-fd20-4545-bda0-144b66e70147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14433
56105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1443356105
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1487594295
Short name T162
Test name
Test status
Simulation time 77398503 ps
CPU time 1.13 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 202880 kb
Host smart-2b966c8b-c508-4fbc-aae9-ae947828ccd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487594295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.1487594295
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.664230942
Short name T123
Test name
Test status
Simulation time 8443105749 ps
CPU time 7.65 seconds
Started Mar 05 01:06:28 PM PST 24
Finished Mar 05 01:06:36 PM PST 24
Peak memory 202476 kb
Host smart-b782ef7a-af44-4935-b95d-13434c484ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66423
0942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.664230942
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.4073462911
Short name T131
Test name
Test status
Simulation time 8445897456 ps
CPU time 7.75 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 202412 kb
Host smart-f341d0ef-3766-41bc-b060-8e9035f4888e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40734
62911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.4073462911
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2265227658
Short name T506
Test name
Test status
Simulation time 8426370697 ps
CPU time 7.12 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:37 PM PST 24
Peak memory 202328 kb
Host smart-773c2d92-0848-4b61-95cb-87b1376277b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22652
27658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2265227658
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.4011180450
Short name T116
Test name
Test status
Simulation time 8425871106 ps
CPU time 7.51 seconds
Started Mar 05 01:06:25 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202428 kb
Host smart-72ba1566-ad91-40ae-96c8-21aefcbbea64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40111
80450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.4011180450
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.368472491
Short name T450
Test name
Test status
Simulation time 8420629061 ps
CPU time 7.25 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 202360 kb
Host smart-775475e7-58cb-4f4d-9077-a35a1624e0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36847
2491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.368472491
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1937405475
Short name T133
Test name
Test status
Simulation time 8424236489 ps
CPU time 8.31 seconds
Started Mar 05 01:06:39 PM PST 24
Finished Mar 05 01:06:47 PM PST 24
Peak memory 202484 kb
Host smart-d1372c2c-50d3-438b-9412-161178f7ac3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19374
05475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1937405475
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3797613805
Short name T134
Test name
Test status
Simulation time 8398169334 ps
CPU time 7.58 seconds
Started Mar 05 01:07:01 PM PST 24
Finished Mar 05 01:07:09 PM PST 24
Peak memory 202352 kb
Host smart-5d515701-b3a3-4336-84d6-3e6df5018276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37976
13805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3797613805
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1008783311
Short name T557
Test name
Test status
Simulation time 8427162044 ps
CPU time 7.67 seconds
Started Mar 05 01:07:12 PM PST 24
Finished Mar 05 01:07:20 PM PST 24
Peak memory 202372 kb
Host smart-94264660-8d17-4c54-8eff-6d3b9ff7f286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
83311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1008783311
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1740349930
Short name T724
Test name
Test status
Simulation time 273000484 ps
CPU time 2.86 seconds
Started Mar 05 12:39:36 PM PST 24
Finished Mar 05 12:39:39 PM PST 24
Peak memory 202816 kb
Host smart-0f9697cf-15f7-4ad0-93c6-2b7eade6485b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1740349930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1740349930
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3279282814
Short name T270
Test name
Test status
Simulation time 8431413427 ps
CPU time 7.13 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:50 PM PST 24
Peak memory 202356 kb
Host smart-6d872c97-259c-45e5-892d-7032deaf4176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32792
82814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3279282814
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3388043058
Short name T79
Test name
Test status
Simulation time 124729296 ps
CPU time 2.37 seconds
Started Mar 05 12:39:44 PM PST 24
Finished Mar 05 12:39:46 PM PST 24
Peak memory 202920 kb
Host smart-1878cdb8-750a-4783-b64f-5dd1f6de21f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3388043058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3388043058
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.872581514
Short name T85
Test name
Test status
Simulation time 8402272227 ps
CPU time 7.13 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:50 PM PST 24
Peak memory 202312 kb
Host smart-37513b7e-5364-473b-93ad-1b1ce64a2db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87258
1514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.872581514
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.194250446
Short name T97
Test name
Test status
Simulation time 8439647655 ps
CPU time 7.55 seconds
Started Mar 05 01:06:16 PM PST 24
Finished Mar 05 01:06:24 PM PST 24
Peak memory 202476 kb
Host smart-7b93fd08-25a6-4cda-97c1-149dc20f6693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19425
0446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.194250446
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1471399352
Short name T611
Test name
Test status
Simulation time 8500737104 ps
CPU time 7.86 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:38 PM PST 24
Peak memory 202424 kb
Host smart-c96a88c6-d5ac-46cc-9747-62ed692ba2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
99352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1471399352
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3413512248
Short name T258
Test name
Test status
Simulation time 8359666439 ps
CPU time 7.41 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202472 kb
Host smart-af463291-211d-446e-aef0-0526e748a302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34135
12248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3413512248
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2815243338
Short name T651
Test name
Test status
Simulation time 8414510447 ps
CPU time 7.36 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 202400 kb
Host smart-7fd539e7-e972-4aca-8301-d83f9d4804c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28152
43338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2815243338
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.263071355
Short name T100
Test name
Test status
Simulation time 8397115392 ps
CPU time 7.68 seconds
Started Mar 05 01:06:25 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202424 kb
Host smart-efe3d7fe-4305-454b-8050-9bdaa98bfa0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26307
1355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.263071355
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.688344746
Short name T401
Test name
Test status
Simulation time 8372955518 ps
CPU time 7.34 seconds
Started Mar 05 01:06:28 PM PST 24
Finished Mar 05 01:06:36 PM PST 24
Peak memory 202460 kb
Host smart-7051bb13-b5c4-4c50-ad73-115d3e317bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68834
4746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.688344746
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3534514648
Short name T38
Test name
Test status
Simulation time 8368307840 ps
CPU time 7.3 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:42 PM PST 24
Peak memory 202552 kb
Host smart-70ef5a77-e669-4528-8476-84a46c534dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35345
14648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3534514648
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4205985225
Short name T5
Test name
Test status
Simulation time 8392829147 ps
CPU time 7.69 seconds
Started Mar 05 01:06:39 PM PST 24
Finished Mar 05 01:06:47 PM PST 24
Peak memory 202424 kb
Host smart-941b3a88-eabf-4670-ab01-bf29ed3d8fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42059
85225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4205985225
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2766352053
Short name T112
Test name
Test status
Simulation time 8428171562 ps
CPU time 7.56 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:49 PM PST 24
Peak memory 202428 kb
Host smart-6da2ff9b-aaf1-4f8a-b727-86ab314a6e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27663
52053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2766352053
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.525736955
Short name T71
Test name
Test status
Simulation time 8420314265 ps
CPU time 8.97 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:07:00 PM PST 24
Peak memory 202448 kb
Host smart-ecec2a2c-955e-4a3f-beea-ba40ac822784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52573
6955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.525736955
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.386271273
Short name T107
Test name
Test status
Simulation time 8390408068 ps
CPU time 9.47 seconds
Started Mar 05 01:07:15 PM PST 24
Finished Mar 05 01:07:24 PM PST 24
Peak memory 202424 kb
Host smart-0c7f5d72-af79-49d8-abdc-526b58fa7195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38627
1273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.386271273
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.964776067
Short name T87
Test name
Test status
Simulation time 8399474738 ps
CPU time 7.28 seconds
Started Mar 05 01:07:24 PM PST 24
Finished Mar 05 01:07:31 PM PST 24
Peak memory 202420 kb
Host smart-b2e30f86-ef6e-40c2-8821-6a44352df636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96477
6067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.964776067
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.691270307
Short name T92
Test name
Test status
Simulation time 8421312461 ps
CPU time 7.61 seconds
Started Mar 05 01:06:02 PM PST 24
Finished Mar 05 01:06:10 PM PST 24
Peak memory 202472 kb
Host smart-cec9338a-3dbd-4e13-ba4e-7ff352f32557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69127
0307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.691270307
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2505727543
Short name T156
Test name
Test status
Simulation time 209984412 ps
CPU time 2.26 seconds
Started Mar 05 12:39:24 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 202692 kb
Host smart-68f7e183-781e-4f63-abea-6aae7dd534af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505727543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2505727543
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3550465047
Short name T204
Test name
Test status
Simulation time 28164504 ps
CPU time 0.71 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:39 PM PST 24
Peak memory 202600 kb
Host smart-94a4a8be-1ecf-42cd-acae-5e70c2d7f6f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550465047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3550465047
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2450063096
Short name T154
Test name
Test status
Simulation time 39128459 ps
CPU time 0.8 seconds
Started Mar 05 12:39:23 PM PST 24
Finished Mar 05 12:39:24 PM PST 24
Peak memory 202636 kb
Host smart-39477f4c-4271-441a-86a6-97c1fa9f995b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450063096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2450063096
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4246125659
Short name T149
Test name
Test status
Simulation time 89476818 ps
CPU time 2.08 seconds
Started Mar 05 12:42:53 PM PST 24
Finished Mar 05 12:42:56 PM PST 24
Peak memory 201912 kb
Host smart-52812ae4-ed5c-421b-8821-facbed506c71
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4246125659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.4246125659
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1802728562
Short name T720
Test name
Test status
Simulation time 41861905 ps
CPU time 1.03 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:19 PM PST 24
Peak memory 202860 kb
Host smart-db35f55c-97fc-4144-abcf-123378d773a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802728562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.1802728562
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.407431700
Short name T705
Test name
Test status
Simulation time 189046165 ps
CPU time 2.13 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 202844 kb
Host smart-18ead19b-a018-4ec1-b407-4b9fe32624e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=407431700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.407431700
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2226993912
Short name T719
Test name
Test status
Simulation time 67091103 ps
CPU time 2 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:09 PM PST 24
Peak memory 202756 kb
Host smart-7252a638-4f4c-434b-bbd1-cf37c97ec8ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226993912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2226993912
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1171494321
Short name T139
Test name
Test status
Simulation time 125311731 ps
CPU time 1.51 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 211088 kb
Host smart-9bd27837-16c7-4bb8-8a04-a2094b8adfb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171494321 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.1171494321
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1844150104
Short name T160
Test name
Test status
Simulation time 36828675 ps
CPU time 0.77 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:32 PM PST 24
Peak memory 202636 kb
Host smart-b8a614f4-57a2-4b49-bd2f-0b912cf2c0b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844150104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1844150104
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2523350961
Short name T143
Test name
Test status
Simulation time 188539563 ps
CPU time 2.22 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:42 PM PST 24
Peak memory 202764 kb
Host smart-ffefb799-97ed-4a9b-b658-ade7ee2627c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2523350961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2523350961
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3534041216
Short name T669
Test name
Test status
Simulation time 465953346 ps
CPU time 4.11 seconds
Started Mar 05 12:39:36 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 202688 kb
Host smart-e61a8937-9bc4-4ac7-95f6-85f207299924
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3534041216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3534041216
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3165543429
Short name T701
Test name
Test status
Simulation time 163442789 ps
CPU time 1.63 seconds
Started Mar 05 12:39:27 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 202908 kb
Host smart-fdac82f9-6160-47c1-b5c0-284e69d780e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165543429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.3165543429
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.430315397
Short name T196
Test name
Test status
Simulation time 55082567 ps
CPU time 1.56 seconds
Started Mar 05 12:39:16 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 202812 kb
Host smart-71e60b32-927a-4a2f-a5a4-23df523cc493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=430315397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.430315397
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.415148748
Short name T685
Test name
Test status
Simulation time 58036363 ps
CPU time 1.62 seconds
Started Mar 05 12:39:32 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 211248 kb
Host smart-9b75187d-278d-4504-9fd4-2f9fc494cd15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415148748 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.415148748
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1825925202
Short name T199
Test name
Test status
Simulation time 87820587 ps
CPU time 2.63 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 202792 kb
Host smart-7b52b624-d25b-4e39-9aa2-05a5b33b6dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1825925202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1825925202
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3805076676
Short name T198
Test name
Test status
Simulation time 69994733 ps
CPU time 2.03 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:20 PM PST 24
Peak memory 219196 kb
Host smart-10ed4f68-e3d2-4687-a5ed-95ba6ba453a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805076676 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3805076676
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.4036388817
Short name T80
Test name
Test status
Simulation time 35172662 ps
CPU time 0.79 seconds
Started Mar 05 12:39:18 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 202516 kb
Host smart-33d3420f-4625-43b4-a0c6-67c163f9a44a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036388817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.4036388817
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4242047787
Short name T147
Test name
Test status
Simulation time 73078553 ps
CPU time 1.4 seconds
Started Mar 05 12:39:30 PM PST 24
Finished Mar 05 12:39:32 PM PST 24
Peak memory 202832 kb
Host smart-cc179f0c-2e30-4850-ac74-17780019ba40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242047787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.4242047787
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4158243865
Short name T706
Test name
Test status
Simulation time 143240956 ps
CPU time 1.99 seconds
Started Mar 05 12:39:25 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 211092 kb
Host smart-c6ed432e-3015-476e-8365-2145e535ce31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158243865 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.4158243865
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.972282375
Short name T151
Test name
Test status
Simulation time 47359888 ps
CPU time 0.79 seconds
Started Mar 05 12:39:34 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 202644 kb
Host smart-26f294d4-06c2-4c75-8a30-2f9a727570e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972282375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.972282375
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1477276909
Short name T696
Test name
Test status
Simulation time 34564792 ps
CPU time 0.68 seconds
Started Mar 05 12:40:07 PM PST 24
Finished Mar 05 12:40:08 PM PST 24
Peak memory 201872 kb
Host smart-01d472cc-3bf3-4b2a-b940-96025c322e43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1477276909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1477276909
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3885315804
Short name T695
Test name
Test status
Simulation time 130146604 ps
CPU time 1.49 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 202884 kb
Host smart-fcee88bb-b050-48f9-ba97-d97784e8aef9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885315804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.3885315804
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1824978196
Short name T52
Test name
Test status
Simulation time 170305795 ps
CPU time 1.89 seconds
Started Mar 05 12:39:42 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 213452 kb
Host smart-122478ee-8c22-4f7e-94b2-940a89f089fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824978196 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.1824978196
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.253297195
Short name T691
Test name
Test status
Simulation time 42644014 ps
CPU time 0.78 seconds
Started Mar 05 12:39:17 PM PST 24
Finished Mar 05 12:39:18 PM PST 24
Peak memory 202628 kb
Host smart-2ca4fa70-8775-477a-a08a-869fade8cb14
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253297195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.253297195
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3272482051
Short name T144
Test name
Test status
Simulation time 75474253 ps
CPU time 1.49 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 202884 kb
Host smart-520a140a-8011-4062-9b63-dd98db0fb330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272482051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.3272482051
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3172355630
Short name T47
Test name
Test status
Simulation time 82733812 ps
CPU time 1.27 seconds
Started Mar 05 12:39:43 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 202812 kb
Host smart-57663a19-5afd-4285-95e6-efc72524d987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3172355630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3172355630
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1788132427
Short name T78
Test name
Test status
Simulation time 70419478 ps
CPU time 2.28 seconds
Started Mar 05 12:39:35 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 211036 kb
Host smart-14e21224-5695-47fb-803b-97c735cb5f85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788132427 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.1788132427
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.81256358
Short name T153
Test name
Test status
Simulation time 31500746 ps
CPU time 0.76 seconds
Started Mar 05 12:39:36 PM PST 24
Finished Mar 05 12:39:37 PM PST 24
Peak memory 202520 kb
Host smart-65ef1bd8-6490-493c-aa0a-ca96a3165775
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81256358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.81256358
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3927146781
Short name T222
Test name
Test status
Simulation time 28532229 ps
CPU time 0.66 seconds
Started Mar 05 12:39:37 PM PST 24
Finished Mar 05 12:39:38 PM PST 24
Peak memory 201996 kb
Host smart-a5e45e10-47ea-4cad-aadc-5f968614c18e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3927146781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3927146781
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3735921503
Short name T667
Test name
Test status
Simulation time 56758095 ps
CPU time 1.37 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:42 PM PST 24
Peak memory 202788 kb
Host smart-3108f153-6967-44c4-96d6-c9137cdbab8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735921503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.3735921503
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2411533733
Short name T203
Test name
Test status
Simulation time 48206939 ps
CPU time 1.32 seconds
Started Mar 05 12:39:36 PM PST 24
Finished Mar 05 12:39:37 PM PST 24
Peak memory 202752 kb
Host smart-44f5a919-2526-45af-8c12-685c017e771b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2411533733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2411533733
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1038410745
Short name T212
Test name
Test status
Simulation time 134324160 ps
CPU time 2.29 seconds
Started Mar 05 12:39:24 PM PST 24
Finished Mar 05 12:39:26 PM PST 24
Peak memory 202800 kb
Host smart-64e7b9f1-3d0b-4e67-bc39-4a83d239aafd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1038410745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1038410745
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1658222596
Short name T207
Test name
Test status
Simulation time 131590813 ps
CPU time 1.56 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 211200 kb
Host smart-f380af15-1ef2-4dce-9982-ac79979c36b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658222596 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.1658222596
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4171106426
Short name T159
Test name
Test status
Simulation time 31150554 ps
CPU time 0.89 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 202764 kb
Host smart-3f68a93e-c2e0-4ed1-8c59-a6c253be7323
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171106426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4171106426
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.435172474
Short name T698
Test name
Test status
Simulation time 84472208 ps
CPU time 1.1 seconds
Started Mar 05 12:39:51 PM PST 24
Finished Mar 05 12:39:53 PM PST 24
Peak memory 202860 kb
Host smart-4948be8b-7ee9-410c-bc18-7eff94579ebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435172474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_c
sr_outstanding.435172474
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3723949617
Short name T200
Test name
Test status
Simulation time 84618555 ps
CPU time 2.4 seconds
Started Mar 05 12:39:32 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 202816 kb
Host smart-0e7109a0-6c08-42ee-8673-d92498965f90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3723949617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3723949617
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.8408972
Short name T672
Test name
Test status
Simulation time 54805466 ps
CPU time 1.6 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:31 PM PST 24
Peak memory 211044 kb
Host smart-fee630f6-ad95-43b4-aacb-e8a72cb3e421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8408972 -assert nopostproc +UVM_TESTNAME=usbdev
_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.8408972
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2157182421
Short name T697
Test name
Test status
Simulation time 46408591 ps
CPU time 0.78 seconds
Started Mar 05 12:39:35 PM PST 24
Finished Mar 05 12:39:39 PM PST 24
Peak memory 202536 kb
Host smart-1dfd5820-a6e7-48bd-a222-28afc2f9d289
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157182421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2157182421
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1304230687
Short name T699
Test name
Test status
Simulation time 25600338 ps
CPU time 0.64 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:32 PM PST 24
Peak memory 202052 kb
Host smart-77061f8b-e906-4be8-a086-a3918ccf6972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1304230687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1304230687
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3330058771
Short name T679
Test name
Test status
Simulation time 69235399 ps
CPU time 1.42 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:39 PM PST 24
Peak memory 202920 kb
Host smart-a9021804-e5c9-45a3-9457-319d62b615c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330058771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.3330058771
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3701477593
Short name T202
Test name
Test status
Simulation time 63206616 ps
CPU time 1.87 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 202844 kb
Host smart-ae052cda-d862-49e1-b5cb-6a92c4e74136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3701477593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3701477593
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1784175371
Short name T230
Test name
Test status
Simulation time 372612917 ps
CPU time 2.83 seconds
Started Mar 05 12:39:34 PM PST 24
Finished Mar 05 12:39:37 PM PST 24
Peak memory 202836 kb
Host smart-b7407dca-03a1-461b-9a0f-7c46b669f683
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1784175371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1784175371
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.444837151
Short name T680
Test name
Test status
Simulation time 54276632 ps
CPU time 1.63 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 211144 kb
Host smart-f23b4ef6-aec3-40bb-b149-1273bf940e25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444837151 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.444837151
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2584624794
Short name T722
Test name
Test status
Simulation time 76762434 ps
CPU time 1.02 seconds
Started Mar 05 12:39:26 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 202800 kb
Host smart-9f758b11-80c0-4b13-a7ba-193721b87e5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584624794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2584624794
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3595122017
Short name T223
Test name
Test status
Simulation time 20131024 ps
CPU time 0.63 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:39 PM PST 24
Peak memory 201992 kb
Host smart-d347d56a-d672-40f4-88ff-5d90cd9251a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3595122017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3595122017
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.661069847
Short name T670
Test name
Test status
Simulation time 41207510 ps
CPU time 0.95 seconds
Started Mar 05 12:39:22 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 202824 kb
Host smart-887039b6-5e6a-407a-823a-14b5a8b52701
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661069847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_c
sr_outstanding.661069847
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2764072911
Short name T137
Test name
Test status
Simulation time 112002196 ps
CPU time 1.48 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:31 PM PST 24
Peak memory 202860 kb
Host smart-6c295b30-a4c9-4ada-9ebc-0c5380fb5254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2764072911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2764072911
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3948380088
Short name T51
Test name
Test status
Simulation time 68899432 ps
CPU time 2.07 seconds
Started Mar 05 12:39:42 PM PST 24
Finished Mar 05 12:39:45 PM PST 24
Peak memory 211140 kb
Host smart-54da0583-72ad-4575-87ec-e5a88fc631b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948380088 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.3948380088
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2305888334
Short name T693
Test name
Test status
Simulation time 33666229 ps
CPU time 0.96 seconds
Started Mar 05 12:40:00 PM PST 24
Finished Mar 05 12:40:01 PM PST 24
Peak memory 202824 kb
Host smart-d9674557-8840-4072-b726-366ba22f0363
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305888334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2305888334
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4038669129
Short name T161
Test name
Test status
Simulation time 159174192 ps
CPU time 1.61 seconds
Started Mar 05 12:39:43 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 202888 kb
Host smart-a008a7c5-e5df-4169-a27e-40a71920875d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038669129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.4038669129
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1135545569
Short name T197
Test name
Test status
Simulation time 86463408 ps
CPU time 2.46 seconds
Started Mar 05 12:39:35 PM PST 24
Finished Mar 05 12:39:38 PM PST 24
Peak memory 202856 kb
Host smart-119fe5d0-8cd2-496c-ab66-3832047534c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1135545569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1135545569
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3329722592
Short name T140
Test name
Test status
Simulation time 81103640 ps
CPU time 1.23 seconds
Started Mar 05 12:39:52 PM PST 24
Finished Mar 05 12:39:53 PM PST 24
Peak memory 211152 kb
Host smart-01c4a5d1-6364-4536-98d3-d38a735a93c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329722592 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3329722592
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2796339184
Short name T77
Test name
Test status
Simulation time 35926014 ps
CPU time 0.96 seconds
Started Mar 05 12:39:35 PM PST 24
Finished Mar 05 12:39:36 PM PST 24
Peak memory 202892 kb
Host smart-db5e59c7-d64f-47b2-bb95-0a460e950261
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796339184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2796339184
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1925098713
Short name T715
Test name
Test status
Simulation time 78427938 ps
CPU time 1.05 seconds
Started Mar 05 12:39:47 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 202840 kb
Host smart-7ad624d5-15c7-4cd2-b078-b0def4329426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925098713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.1925098713
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4079548424
Short name T194
Test name
Test status
Simulation time 113184388 ps
CPU time 1.6 seconds
Started Mar 05 12:39:46 PM PST 24
Finished Mar 05 12:39:47 PM PST 24
Peak memory 202752 kb
Host smart-cd71b09a-5917-40f9-a0c5-c8b933bdcc24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4079548424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4079548424
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.887529913
Short name T152
Test name
Test status
Simulation time 158050887 ps
CPU time 2.01 seconds
Started Mar 05 12:40:25 PM PST 24
Finished Mar 05 12:40:28 PM PST 24
Peak memory 202792 kb
Host smart-46a1ad10-de5a-49af-9df6-f70f7b289d46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887529913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.887529913
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.304727240
Short name T55
Test name
Test status
Simulation time 31687879 ps
CPU time 0.72 seconds
Started Mar 05 12:39:27 PM PST 24
Finished Mar 05 12:39:28 PM PST 24
Peak memory 202544 kb
Host smart-6d0b22aa-396b-4d2a-ba8f-1d6187cb617a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304727240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.304727240
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1844201743
Short name T702
Test name
Test status
Simulation time 76369256 ps
CPU time 1.31 seconds
Started Mar 05 12:39:19 PM PST 24
Finished Mar 05 12:39:21 PM PST 24
Peak memory 211144 kb
Host smart-d157cec9-c901-4726-9a7b-3be73620d16e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844201743 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.1844201743
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3821090751
Short name T211
Test name
Test status
Simulation time 30535505 ps
CPU time 0.66 seconds
Started Mar 05 12:39:28 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 202016 kb
Host smart-53abaed1-3e26-43ba-bb00-85c88cbf9081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3821090751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3821090751
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2776297154
Short name T150
Test name
Test status
Simulation time 153788767 ps
CPU time 1.49 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:31 PM PST 24
Peak memory 202760 kb
Host smart-71e8848f-49eb-4361-885b-b7b3e4cecce5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2776297154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2776297154
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3629095186
Short name T689
Test name
Test status
Simulation time 153898947 ps
CPU time 3.93 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 202684 kb
Host smart-9af89f72-7bcf-473f-bf89-02d18290f0f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3629095186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3629095186
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3003908075
Short name T674
Test name
Test status
Simulation time 121584367 ps
CPU time 1.43 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 202808 kb
Host smart-5036c3df-4742-4309-92f0-506b6ec30850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003908075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.3003908075
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3616853396
Short name T727
Test name
Test status
Simulation time 273718463 ps
CPU time 2.82 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:09 PM PST 24
Peak memory 202784 kb
Host smart-6ededf4a-9818-4e1b-8eb9-565b6480f521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3616853396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3616853396
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4225189791
Short name T229
Test name
Test status
Simulation time 274638952 ps
CPU time 2.89 seconds
Started Mar 05 12:39:30 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 202852 kb
Host smart-0698c076-5061-4f34-903e-edbb459b512f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4225189791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4225189791
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1894008995
Short name T221
Test name
Test status
Simulation time 24266970 ps
CPU time 0.64 seconds
Started Mar 05 12:39:45 PM PST 24
Finished Mar 05 12:39:46 PM PST 24
Peak memory 202024 kb
Host smart-de5fabb8-7467-438d-bf74-974c8c0bd24a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1894008995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1894008995
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2967503858
Short name T712
Test name
Test status
Simulation time 24011724 ps
CPU time 0.64 seconds
Started Mar 05 12:39:47 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 201976 kb
Host smart-07c783bd-64e3-43e0-8a3b-025c8a30e979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2967503858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2967503858
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.645197890
Short name T226
Test name
Test status
Simulation time 21671455 ps
CPU time 0.63 seconds
Started Mar 05 12:39:43 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 201984 kb
Host smart-7a9e6ac5-9352-41cc-93f4-7a79b0cf09fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=645197890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.645197890
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1791404393
Short name T666
Test name
Test status
Simulation time 19682671 ps
CPU time 0.64 seconds
Started Mar 05 12:40:01 PM PST 24
Finished Mar 05 12:40:01 PM PST 24
Peak memory 202040 kb
Host smart-f8b8ddc6-7965-4bae-90dc-de0abf121de0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1791404393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1791404393
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2265577386
Short name T673
Test name
Test status
Simulation time 22217377 ps
CPU time 0.65 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 202020 kb
Host smart-7c54d1b7-dc69-4a91-acb3-2b3c759e2964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2265577386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2265577386
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2701932145
Short name T694
Test name
Test status
Simulation time 32727280 ps
CPU time 0.7 seconds
Started Mar 05 12:39:43 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 202000 kb
Host smart-be521a32-5852-497a-8b98-f70ecea31af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2701932145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2701932145
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1559518710
Short name T707
Test name
Test status
Simulation time 20382407 ps
CPU time 0.61 seconds
Started Mar 05 12:39:43 PM PST 24
Finished Mar 05 12:39:44 PM PST 24
Peak memory 201976 kb
Host smart-38226537-912f-4d91-8382-19415c95631d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1559518710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1559518710
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2288861793
Short name T710
Test name
Test status
Simulation time 22305375 ps
CPU time 0.63 seconds
Started Mar 05 12:39:34 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 201936 kb
Host smart-181d7430-b6f8-4262-ae39-b5cdebfdad6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2288861793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2288861793
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2682886942
Short name T711
Test name
Test status
Simulation time 130753018 ps
CPU time 3.44 seconds
Started Mar 05 12:39:11 PM PST 24
Finished Mar 05 12:39:14 PM PST 24
Peak memory 202680 kb
Host smart-0c4bbf59-4dda-424e-a612-042568463500
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682886942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2682886942
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.523620166
Short name T56
Test name
Test status
Simulation time 49678136 ps
CPU time 0.83 seconds
Started Mar 05 12:39:32 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 202616 kb
Host smart-79130e39-7504-4495-bb45-97114aa4f8cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523620166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.523620166
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2327688302
Short name T708
Test name
Test status
Simulation time 144363965 ps
CPU time 1.74 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 211088 kb
Host smart-d78d2541-7485-406b-ac2f-2ab350fe115f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327688302 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2327688302
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1039317600
Short name T158
Test name
Test status
Simulation time 33249567 ps
CPU time 0.79 seconds
Started Mar 05 12:39:28 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 202460 kb
Host smart-d9109e4f-80f4-450c-89a5-898aa71efc7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039317600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1039317600
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1682174604
Short name T721
Test name
Test status
Simulation time 20818664 ps
CPU time 0.68 seconds
Started Mar 05 12:39:48 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 201980 kb
Host smart-97e13208-a8d8-47e4-885d-8521dc3ea0cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1682174604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1682174604
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2988724389
Short name T709
Test name
Test status
Simulation time 151838069 ps
CPU time 2.22 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:25 PM PST 24
Peak memory 202708 kb
Host smart-c6bd1310-0e57-47be-b886-4a7f49e2f66a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2988724389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2988724389
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1268737866
Short name T665
Test name
Test status
Simulation time 151028533 ps
CPU time 3.61 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:42 PM PST 24
Peak memory 202632 kb
Host smart-9455ec83-019e-4a19-bac2-ea9cf0ca4936
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1268737866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1268737866
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2949687024
Short name T690
Test name
Test status
Simulation time 117350136 ps
CPU time 1.51 seconds
Started Mar 05 12:39:28 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 202896 kb
Host smart-ec76fab5-0fea-4f62-be90-caab4be1c391
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949687024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.2949687024
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1969484825
Short name T686
Test name
Test status
Simulation time 70931455 ps
CPU time 2.13 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:33 PM PST 24
Peak memory 202804 kb
Host smart-0895673e-7b85-4b7f-9749-8c829d2d3489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1969484825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1969484825
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.174991118
Short name T692
Test name
Test status
Simulation time 28537015 ps
CPU time 0.63 seconds
Started Mar 05 12:39:42 PM PST 24
Finished Mar 05 12:39:43 PM PST 24
Peak memory 201860 kb
Host smart-b052a799-71fe-4f94-9864-605ecf30ab29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=174991118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.174991118
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.395048706
Short name T668
Test name
Test status
Simulation time 24564783 ps
CPU time 0.65 seconds
Started Mar 05 12:39:47 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 201984 kb
Host smart-67b4d9e1-ca45-4073-a740-4da86f1745bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=395048706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.395048706
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.566489389
Short name T725
Test name
Test status
Simulation time 28875812 ps
CPU time 0.68 seconds
Started Mar 05 12:39:42 PM PST 24
Finished Mar 05 12:39:42 PM PST 24
Peak memory 202036 kb
Host smart-a5cea30c-6be7-48db-9d5b-39b4fe0429c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=566489389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.566489389
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3803847002
Short name T675
Test name
Test status
Simulation time 22724968 ps
CPU time 0.69 seconds
Started Mar 05 12:39:40 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 202044 kb
Host smart-13320e1b-4eb6-4e32-aa0d-a0bda1b59045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3803847002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3803847002
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3854388572
Short name T681
Test name
Test status
Simulation time 29484888 ps
CPU time 0.65 seconds
Started Mar 05 12:39:57 PM PST 24
Finished Mar 05 12:39:58 PM PST 24
Peak memory 201988 kb
Host smart-2385ed29-70bf-4036-aec3-89ad9c6a05ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3854388572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3854388572
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3363102099
Short name T713
Test name
Test status
Simulation time 24800217 ps
CPU time 0.68 seconds
Started Mar 05 12:39:47 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 202016 kb
Host smart-627b2b19-644c-4d16-b6d1-9faf45fcbf3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363102099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3363102099
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.349002299
Short name T61
Test name
Test status
Simulation time 35830713 ps
CPU time 0.66 seconds
Started Mar 05 12:39:49 PM PST 24
Finished Mar 05 12:39:55 PM PST 24
Peak memory 201988 kb
Host smart-e975b98d-abf8-477d-bfd1-58cab2f3e992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=349002299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.349002299
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3143386491
Short name T81
Test name
Test status
Simulation time 128780222 ps
CPU time 3.19 seconds
Started Mar 05 12:39:14 PM PST 24
Finished Mar 05 12:39:17 PM PST 24
Peak memory 202760 kb
Host smart-8ae57151-d022-4bb6-88c2-9ab5ce8b6eb5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143386491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3143386491
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4207086355
Short name T205
Test name
Test status
Simulation time 45516688 ps
CPU time 1.16 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:31 PM PST 24
Peak memory 211068 kb
Host smart-7f1f5838-f43d-4e53-b921-bcc84e7849d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207086355 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.4207086355
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.963016084
Short name T146
Test name
Test status
Simulation time 55846518 ps
CPU time 1.02 seconds
Started Mar 05 12:39:28 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 202868 kb
Host smart-77fde124-f884-434d-94ba-9bad1b654096
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963016084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.963016084
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2504729472
Short name T217
Test name
Test status
Simulation time 37224613 ps
CPU time 0.68 seconds
Started Mar 05 12:39:25 PM PST 24
Finished Mar 05 12:39:27 PM PST 24
Peak memory 201092 kb
Host smart-ce70385d-674a-4671-9b21-2f2dfbd129e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2504729472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2504729472
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2150834814
Short name T157
Test name
Test status
Simulation time 160104343 ps
CPU time 1.4 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:39 PM PST 24
Peak memory 202712 kb
Host smart-1585edee-406b-4363-80ff-cf45c375823e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2150834814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2150834814
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3039546164
Short name T664
Test name
Test status
Simulation time 250290881 ps
CPU time 2.38 seconds
Started Mar 05 12:39:28 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 202664 kb
Host smart-51a3f0e2-ad08-42a2-b868-3dc437bf0c80
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3039546164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3039546164
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4080583003
Short name T148
Test name
Test status
Simulation time 80948776 ps
CPU time 0.98 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:39 PM PST 24
Peak memory 202780 kb
Host smart-38794031-e7fc-4deb-988f-2c32c78b21d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080583003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.4080583003
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.301052776
Short name T703
Test name
Test status
Simulation time 95418632 ps
CPU time 2.61 seconds
Started Mar 05 12:39:37 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 202804 kb
Host smart-50fc85aa-7f88-420a-a3c2-a98946b9b4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=301052776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.301052776
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.596812976
Short name T717
Test name
Test status
Simulation time 35883180 ps
CPU time 0.65 seconds
Started Mar 05 12:39:50 PM PST 24
Finished Mar 05 12:39:51 PM PST 24
Peak memory 202004 kb
Host smart-7fa0d003-7fef-4137-be02-6f2c42a22e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=596812976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.596812976
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2268735772
Short name T57
Test name
Test status
Simulation time 26343760 ps
CPU time 0.62 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:39 PM PST 24
Peak memory 201960 kb
Host smart-0eb0a888-11c5-42c8-90c3-4cf8bce6e7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2268735772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2268735772
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1840595005
Short name T718
Test name
Test status
Simulation time 28387113 ps
CPU time 0.63 seconds
Started Mar 05 12:39:50 PM PST 24
Finished Mar 05 12:39:50 PM PST 24
Peak memory 202004 kb
Host smart-a8a22bbf-d48d-4588-ad43-91dd8c652bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1840595005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1840595005
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1031944903
Short name T225
Test name
Test status
Simulation time 22234920 ps
CPU time 0.64 seconds
Started Mar 05 12:39:59 PM PST 24
Finished Mar 05 12:40:00 PM PST 24
Peak memory 201948 kb
Host smart-1623426b-869a-4331-8032-6e186101041e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1031944903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1031944903
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3132773652
Short name T684
Test name
Test status
Simulation time 25710425 ps
CPU time 0.66 seconds
Started Mar 05 12:39:28 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 202040 kb
Host smart-5fd8c530-5c2c-4d53-8e50-1df1c64632f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3132773652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3132773652
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2488432630
Short name T219
Test name
Test status
Simulation time 26360687 ps
CPU time 0.67 seconds
Started Mar 05 12:39:45 PM PST 24
Finished Mar 05 12:39:46 PM PST 24
Peak memory 201940 kb
Host smart-47069d6c-fda1-4462-94a2-e0c894f543d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2488432630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2488432630
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1486650957
Short name T227
Test name
Test status
Simulation time 38045792 ps
CPU time 0.68 seconds
Started Mar 05 12:39:52 PM PST 24
Finished Mar 05 12:39:53 PM PST 24
Peak memory 202040 kb
Host smart-d18bbb20-19cd-459e-baf6-a25c0c180d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1486650957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1486650957
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3616634513
Short name T58
Test name
Test status
Simulation time 66092392 ps
CPU time 0.68 seconds
Started Mar 05 12:40:03 PM PST 24
Finished Mar 05 12:40:04 PM PST 24
Peak memory 202028 kb
Host smart-aa82cad7-b843-4d56-90fd-704777e1cdb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3616634513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3616634513
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3958956246
Short name T216
Test name
Test status
Simulation time 23349448 ps
CPU time 0.64 seconds
Started Mar 05 12:39:42 PM PST 24
Finished Mar 05 12:39:43 PM PST 24
Peak memory 202036 kb
Host smart-951e7040-bf92-494e-90af-749c299d99b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3958956246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3958956246
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2196909681
Short name T224
Test name
Test status
Simulation time 53000025 ps
CPU time 0.67 seconds
Started Mar 05 12:39:47 PM PST 24
Finished Mar 05 12:39:48 PM PST 24
Peak memory 201972 kb
Host smart-9e372e7c-9607-4f3f-9e0d-4d9e632c7323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2196909681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2196909681
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1946137136
Short name T688
Test name
Test status
Simulation time 87196518 ps
CPU time 2.18 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 211024 kb
Host smart-381c5f07-ce87-43b2-8adc-1fe65b2979bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946137136 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1946137136
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.281305053
Short name T676
Test name
Test status
Simulation time 25349395 ps
CPU time 0.78 seconds
Started Mar 05 12:39:25 PM PST 24
Finished Mar 05 12:39:26 PM PST 24
Peak memory 202460 kb
Host smart-135711ae-4173-40a3-aadf-c73951eb8951
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281305053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.281305053
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2595903358
Short name T209
Test name
Test status
Simulation time 81451689 ps
CPU time 1.11 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 202916 kb
Host smart-403e9acc-27fe-4874-8033-2bdb0d22afbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595903358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.2595903358
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2731169111
Short name T726
Test name
Test status
Simulation time 118484782 ps
CPU time 3.6 seconds
Started Mar 05 12:39:30 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 202820 kb
Host smart-dbb8f4f2-0d55-44b5-96ef-37fc6854a223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2731169111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2731169111
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3783231288
Short name T671
Test name
Test status
Simulation time 42592512 ps
CPU time 1.44 seconds
Started Mar 05 12:39:27 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 211084 kb
Host smart-a0be62bc-4900-43a0-9ee8-ba7c20a0ae27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783231288 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3783231288
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4164312512
Short name T723
Test name
Test status
Simulation time 60193488 ps
CPU time 1.02 seconds
Started Mar 05 12:39:36 PM PST 24
Finished Mar 05 12:39:37 PM PST 24
Peak memory 202740 kb
Host smart-14c9f98e-0136-4fef-a3ac-bd9338721817
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164312512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4164312512
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1805806994
Short name T687
Test name
Test status
Simulation time 127318502 ps
CPU time 0.7 seconds
Started Mar 05 12:39:20 PM PST 24
Finished Mar 05 12:39:21 PM PST 24
Peak memory 201912 kb
Host smart-075cefb6-aaca-49f2-8c00-b7b1b869cf49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1805806994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1805806994
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1576468757
Short name T206
Test name
Test status
Simulation time 94211000 ps
CPU time 1.06 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:32 PM PST 24
Peak memory 202836 kb
Host smart-0f8b48a2-6220-4e97-995e-b534e2e396ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576468757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.1576468757
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2205381636
Short name T716
Test name
Test status
Simulation time 89560034 ps
CPU time 2.58 seconds
Started Mar 05 12:39:12 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 202412 kb
Host smart-56027cb2-ff86-4131-a3b2-66f146417e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2205381636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2205381636
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3377758117
Short name T683
Test name
Test status
Simulation time 130965158 ps
CPU time 1.78 seconds
Started Mar 05 12:39:34 PM PST 24
Finished Mar 05 12:39:36 PM PST 24
Peak memory 211100 kb
Host smart-ff7396a5-2f5e-47af-81dc-ec56b5e74f71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377758117 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.3377758117
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.679773435
Short name T714
Test name
Test status
Simulation time 22400755 ps
CPU time 0.71 seconds
Started Mar 05 12:39:21 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 202604 kb
Host smart-012f6b84-71fa-4f74-86a3-6893d57e520e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=679773435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.679773435
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3277039364
Short name T53
Test name
Test status
Simulation time 104913168 ps
CPU time 1.2 seconds
Started Mar 05 12:39:14 PM PST 24
Finished Mar 05 12:39:15 PM PST 24
Peak memory 202860 kb
Host smart-8de7a265-d828-4344-b554-b2968df87a3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277039364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.3277039364
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1102079418
Short name T682
Test name
Test status
Simulation time 107464760 ps
CPU time 1.6 seconds
Started Mar 05 12:39:23 PM PST 24
Finished Mar 05 12:39:25 PM PST 24
Peak memory 202820 kb
Host smart-191d1f1b-b1d5-4624-b934-451f2730d241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1102079418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1102079418
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1498442300
Short name T704
Test name
Test status
Simulation time 52846322 ps
CPU time 1.13 seconds
Started Mar 05 12:39:39 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 212112 kb
Host smart-55bbe33f-7830-476d-83e1-e87ced40e83e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498442300 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.1498442300
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3115456548
Short name T155
Test name
Test status
Simulation time 72408409 ps
CPU time 1.02 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 202700 kb
Host smart-b2854433-a488-4bd1-b79c-f6c8c81b4b6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115456548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3115456548
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1680785990
Short name T677
Test name
Test status
Simulation time 69050332 ps
CPU time 1.04 seconds
Started Mar 05 12:39:21 PM PST 24
Finished Mar 05 12:39:23 PM PST 24
Peak memory 202916 kb
Host smart-938c1e6a-75f9-4c0a-9572-1f8f95130034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680785990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.1680785990
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2541355562
Short name T201
Test name
Test status
Simulation time 81598470 ps
CPU time 2.4 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:40 PM PST 24
Peak memory 202840 kb
Host smart-5f8d660e-bccd-4993-842a-5d5869765c35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541355562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2541355562
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.994213801
Short name T46
Test name
Test status
Simulation time 74796505 ps
CPU time 1.2 seconds
Started Mar 05 12:39:29 PM PST 24
Finished Mar 05 12:39:30 PM PST 24
Peak memory 211056 kb
Host smart-e7e0e55c-bc15-426b-ac71-87b97a62f9e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994213801 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.994213801
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2910273338
Short name T700
Test name
Test status
Simulation time 42454737 ps
CPU time 0.8 seconds
Started Mar 05 12:39:36 PM PST 24
Finished Mar 05 12:39:37 PM PST 24
Peak memory 202560 kb
Host smart-5f27b093-d0c0-4df5-a330-885ef1964bb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910273338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2910273338
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3357100742
Short name T208
Test name
Test status
Simulation time 145824588 ps
CPU time 1.56 seconds
Started Mar 05 12:39:44 PM PST 24
Finished Mar 05 12:39:46 PM PST 24
Peak memory 202860 kb
Host smart-52f9456f-4747-4d68-b4b9-645ffce6c72e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357100742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.3357100742
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1846864148
Short name T195
Test name
Test status
Simulation time 48818324 ps
CPU time 1.43 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 202844 kb
Host smart-440a0ea7-d26a-4c4a-952b-32108b8a7e46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1846864148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1846864148
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1817581750
Short name T398
Test name
Test status
Simulation time 8429040688 ps
CPU time 7.87 seconds
Started Mar 05 01:05:38 PM PST 24
Finished Mar 05 01:05:47 PM PST 24
Peak memory 202412 kb
Host smart-b7ce3018-5227-4211-a377-0afeb70580ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18175
81750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1817581750
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.453321363
Short name T272
Test name
Test status
Simulation time 187652218 ps
CPU time 2.03 seconds
Started Mar 05 01:05:37 PM PST 24
Finished Mar 05 01:05:41 PM PST 24
Peak memory 202424 kb
Host smart-7b736b6f-8456-4e00-8436-04738c6ed4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45332
1363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.453321363
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2898584202
Short name T466
Test name
Test status
Simulation time 8395000135 ps
CPU time 8.96 seconds
Started Mar 05 01:05:37 PM PST 24
Finished Mar 05 01:05:48 PM PST 24
Peak memory 202392 kb
Host smart-79697e87-c63b-4508-adc0-925ffa73e6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28985
84202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2898584202
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.373585410
Short name T381
Test name
Test status
Simulation time 8409332706 ps
CPU time 8.16 seconds
Started Mar 05 01:05:39 PM PST 24
Finished Mar 05 01:05:47 PM PST 24
Peak memory 202368 kb
Host smart-82043537-e01c-4a27-8c69-2acaaccf7a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37358
5410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.373585410
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.174964178
Short name T10
Test name
Test status
Simulation time 8362760509 ps
CPU time 7.88 seconds
Started Mar 05 01:05:37 PM PST 24
Finished Mar 05 01:05:46 PM PST 24
Peak memory 202464 kb
Host smart-62a6022f-dcdb-49d8-9cdd-8d59284cb5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
4178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.174964178
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2450022240
Short name T490
Test name
Test status
Simulation time 8400539263 ps
CPU time 7.75 seconds
Started Mar 05 01:05:38 PM PST 24
Finished Mar 05 01:05:47 PM PST 24
Peak memory 202400 kb
Host smart-b657c6d3-2f57-4054-9072-d76fefb4e4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24500
22240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2450022240
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2192472566
Short name T241
Test name
Test status
Simulation time 8391154114 ps
CPU time 7.16 seconds
Started Mar 05 01:05:33 PM PST 24
Finished Mar 05 01:05:40 PM PST 24
Peak memory 202324 kb
Host smart-77506f6b-568e-42c8-bbbe-df1377328975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21924
72566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2192472566
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1975301454
Short name T332
Test name
Test status
Simulation time 8403939430 ps
CPU time 7.38 seconds
Started Mar 05 01:05:39 PM PST 24
Finished Mar 05 01:05:47 PM PST 24
Peak memory 202324 kb
Host smart-e7e5e92c-d496-459c-8371-646fbbeeb0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19753
01454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1975301454
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2176919128
Short name T121
Test name
Test status
Simulation time 8434451904 ps
CPU time 7.5 seconds
Started Mar 05 01:05:39 PM PST 24
Finished Mar 05 01:05:47 PM PST 24
Peak memory 202448 kb
Host smart-3c229be1-8542-4c49-a9a0-1ff021a84a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21769
19128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2176919128
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.715100287
Short name T487
Test name
Test status
Simulation time 8396310381 ps
CPU time 7.32 seconds
Started Mar 05 01:05:38 PM PST 24
Finished Mar 05 01:05:46 PM PST 24
Peak memory 202452 kb
Host smart-9caf7b6f-7fef-45b1-b990-70a1714ec52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71510
0287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.715100287
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3202355011
Short name T642
Test name
Test status
Simulation time 8365193739 ps
CPU time 8.42 seconds
Started Mar 05 01:05:38 PM PST 24
Finished Mar 05 01:05:47 PM PST 24
Peak memory 202468 kb
Host smart-6a65b79a-4973-4e2e-9ac3-a40a5960eb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32023
55011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3202355011
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.4031626217
Short name T264
Test name
Test status
Simulation time 8368234009 ps
CPU time 8.78 seconds
Started Mar 05 01:05:32 PM PST 24
Finished Mar 05 01:05:41 PM PST 24
Peak memory 202404 kb
Host smart-d1feb9b2-ef86-40fd-b04f-e24168c4a1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316
26217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.4031626217
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3622413227
Short name T298
Test name
Test status
Simulation time 8373442197 ps
CPU time 7.17 seconds
Started Mar 05 01:05:41 PM PST 24
Finished Mar 05 01:05:48 PM PST 24
Peak memory 202360 kb
Host smart-de3f3c21-a3af-43dc-b29b-3c4c37cacef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36224
13227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3622413227
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3864549474
Short name T65
Test name
Test status
Simulation time 38122353 ps
CPU time 1.21 seconds
Started Mar 05 01:05:43 PM PST 24
Finished Mar 05 01:05:44 PM PST 24
Peak memory 202420 kb
Host smart-3b804e02-8a8b-4f72-8182-935829cb0614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38645
49474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3864549474
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3789638393
Short name T352
Test name
Test status
Simulation time 8402878454 ps
CPU time 7.5 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:49 PM PST 24
Peak memory 202464 kb
Host smart-c3d54ac5-77cd-4564-92f5-4dbbb5d70e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37896
38393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3789638393
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.631067740
Short name T474
Test name
Test status
Simulation time 8362251595 ps
CPU time 8.12 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:51 PM PST 24
Peak memory 202424 kb
Host smart-70603231-6481-481a-aacf-43296c8b1ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63106
7740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.631067740
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2450126954
Short name T20
Test name
Test status
Simulation time 8372745151 ps
CPU time 7.23 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:50 PM PST 24
Peak memory 202368 kb
Host smart-6cf7ed44-cfb8-401b-b2b1-ce3564c3e874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24501
26954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2450126954
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2042623898
Short name T128
Test name
Test status
Simulation time 8397417465 ps
CPU time 8.52 seconds
Started Mar 05 01:05:41 PM PST 24
Finished Mar 05 01:05:50 PM PST 24
Peak memory 202472 kb
Host smart-26eaebb1-0bf6-4f08-8e42-44febc8f4c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20426
23898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2042623898
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1162656725
Short name T567
Test name
Test status
Simulation time 8383122928 ps
CPU time 9.85 seconds
Started Mar 05 01:05:41 PM PST 24
Finished Mar 05 01:05:51 PM PST 24
Peak memory 202460 kb
Host smart-7fa11a66-7394-42d8-bfb0-5f645624a730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11626
56725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1162656725
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.657733324
Short name T63
Test name
Test status
Simulation time 312519858 ps
CPU time 1.16 seconds
Started Mar 05 01:05:45 PM PST 24
Finished Mar 05 01:05:46 PM PST 24
Peak memory 217208 kb
Host smart-efd2edd4-9616-472b-8f38-0288c8c60d22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=657733324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.657733324
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3276205446
Short name T446
Test name
Test status
Simulation time 8364342084 ps
CPU time 7.61 seconds
Started Mar 05 01:05:40 PM PST 24
Finished Mar 05 01:05:48 PM PST 24
Peak memory 202416 kb
Host smart-8d8a2196-9f3c-4b41-b3d8-9049a95e107e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32762
05446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3276205446
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.547600730
Short name T596
Test name
Test status
Simulation time 8371502604 ps
CPU time 9.13 seconds
Started Mar 05 01:05:47 PM PST 24
Finished Mar 05 01:05:57 PM PST 24
Peak memory 202400 kb
Host smart-a6a379ae-7077-49c4-bd61-a8124e6a8ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54760
0730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.547600730
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1727584446
Short name T599
Test name
Test status
Simulation time 8367868125 ps
CPU time 8.96 seconds
Started Mar 05 01:06:14 PM PST 24
Finished Mar 05 01:06:23 PM PST 24
Peak memory 202572 kb
Host smart-6c9a82a8-d523-4fcc-9d41-0e26af4bf0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17275
84446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1727584446
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.932879547
Short name T486
Test name
Test status
Simulation time 72163640 ps
CPU time 2.01 seconds
Started Mar 05 01:06:30 PM PST 24
Finished Mar 05 01:06:32 PM PST 24
Peak memory 202392 kb
Host smart-bec610d8-f6ee-4e8c-a801-cb7de2e4827d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93287
9547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.932879547
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.500633821
Short name T661
Test name
Test status
Simulation time 8409257570 ps
CPU time 7.9 seconds
Started Mar 05 01:06:13 PM PST 24
Finished Mar 05 01:06:21 PM PST 24
Peak memory 202408 kb
Host smart-39657bf8-97ce-4972-8116-7af7b51ff1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50063
3821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.500633821
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.600472616
Short name T622
Test name
Test status
Simulation time 8366390870 ps
CPU time 8.31 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:38 PM PST 24
Peak memory 202420 kb
Host smart-b72c2871-aed4-4a82-9254-fee741f6c7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60047
2616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.600472616
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.992814689
Short name T579
Test name
Test status
Simulation time 8408135851 ps
CPU time 8.01 seconds
Started Mar 05 01:06:13 PM PST 24
Finished Mar 05 01:06:21 PM PST 24
Peak memory 202308 kb
Host smart-3500f5c7-bfae-4dac-a8a6-51a435854e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99281
4689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.992814689
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3076019296
Short name T357
Test name
Test status
Simulation time 8368542385 ps
CPU time 7.29 seconds
Started Mar 05 01:06:16 PM PST 24
Finished Mar 05 01:06:24 PM PST 24
Peak memory 202420 kb
Host smart-628b4050-ee53-4102-a778-d1548b3e2e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760
19296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3076019296
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.624723565
Short name T14
Test name
Test status
Simulation time 8377762548 ps
CPU time 7.35 seconds
Started Mar 05 01:06:14 PM PST 24
Finished Mar 05 01:06:22 PM PST 24
Peak memory 202428 kb
Host smart-c40597e1-6077-406c-951e-4f8880ab587f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62472
3565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.624723565
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.3814934620
Short name T614
Test name
Test status
Simulation time 8390228945 ps
CPU time 7.61 seconds
Started Mar 05 01:06:16 PM PST 24
Finished Mar 05 01:06:24 PM PST 24
Peak memory 202308 kb
Host smart-acf233f5-0422-4925-96e9-48c8cd91ff84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38149
34620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.3814934620
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1409020582
Short name T436
Test name
Test status
Simulation time 8420740323 ps
CPU time 7.02 seconds
Started Mar 05 01:06:20 PM PST 24
Finished Mar 05 01:06:27 PM PST 24
Peak memory 202404 kb
Host smart-9218d0d9-e9fb-46c6-a0d4-9a0f8aacfb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14090
20582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1409020582
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1549533871
Short name T404
Test name
Test status
Simulation time 8374527921 ps
CPU time 8.57 seconds
Started Mar 05 01:06:19 PM PST 24
Finished Mar 05 01:06:28 PM PST 24
Peak memory 202412 kb
Host smart-f37eddf6-7bd5-43e0-a169-f00acc50681a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15495
33871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1549533871
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1240064076
Short name T42
Test name
Test status
Simulation time 8374790153 ps
CPU time 9.26 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:39 PM PST 24
Peak memory 202412 kb
Host smart-4af852c3-ebcc-45a0-86f2-47770adf0d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12400
64076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1240064076
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1346467977
Short name T353
Test name
Test status
Simulation time 42950410 ps
CPU time 1.16 seconds
Started Mar 05 01:06:27 PM PST 24
Finished Mar 05 01:06:28 PM PST 24
Peak memory 202436 kb
Host smart-a7c7f97c-4cb3-4d25-bd34-bb8cf4ee5abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13464
67977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1346467977
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3180538132
Short name T594
Test name
Test status
Simulation time 8448678706 ps
CPU time 7.98 seconds
Started Mar 05 01:06:25 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202408 kb
Host smart-d023090c-d225-41d6-8754-4ca07bec6334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31805
38132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3180538132
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3941264790
Short name T623
Test name
Test status
Simulation time 8408356422 ps
CPU time 8.33 seconds
Started Mar 05 01:06:24 PM PST 24
Finished Mar 05 01:06:32 PM PST 24
Peak memory 202456 kb
Host smart-327c4ea0-92f3-420e-aec6-55a4ace7a6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39412
64790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3941264790
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1879885523
Short name T301
Test name
Test status
Simulation time 8389300112 ps
CPU time 7.89 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 202432 kb
Host smart-d120852d-45af-452d-97ed-1b9bee4c17cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798
85523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1879885523
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.977832769
Short name T431
Test name
Test status
Simulation time 8397758782 ps
CPU time 9.32 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:39 PM PST 24
Peak memory 202412 kb
Host smart-465f9163-75cf-4dab-b6b1-597cdb9661a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97783
2769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.977832769
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.264674157
Short name T411
Test name
Test status
Simulation time 8383889382 ps
CPU time 7.44 seconds
Started Mar 05 01:06:27 PM PST 24
Finished Mar 05 01:06:35 PM PST 24
Peak memory 202420 kb
Host smart-ea75d974-0e8b-4cd9-9893-638149f5d898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26467
4157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.264674157
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3183855322
Short name T479
Test name
Test status
Simulation time 8400658264 ps
CPU time 7.51 seconds
Started Mar 05 01:06:23 PM PST 24
Finished Mar 05 01:06:30 PM PST 24
Peak memory 202404 kb
Host smart-ebf58408-f275-4bcf-9d34-c8add92f627d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31838
55322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3183855322
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3966141493
Short name T549
Test name
Test status
Simulation time 8365443968 ps
CPU time 7.58 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:37 PM PST 24
Peak memory 202372 kb
Host smart-b7975d56-dba6-46c9-8c7a-52650d0f5898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39661
41493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3966141493
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1052817853
Short name T37
Test name
Test status
Simulation time 8374251112 ps
CPU time 8.45 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:35 PM PST 24
Peak memory 202264 kb
Host smart-c2bd3c75-3171-40a1-a633-0646397b2d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10528
17853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1052817853
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2269574714
Short name T581
Test name
Test status
Simulation time 144669149 ps
CPU time 1.64 seconds
Started Mar 05 01:06:27 PM PST 24
Finished Mar 05 01:06:29 PM PST 24
Peak memory 202628 kb
Host smart-66ef840c-b2b3-40c2-bd47-084ba31205c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22695
74714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2269574714
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1803904912
Short name T293
Test name
Test status
Simulation time 8406917951 ps
CPU time 8.76 seconds
Started Mar 05 01:06:24 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202428 kb
Host smart-d8a7ecaa-60de-4b11-a858-bf3ac20029ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18039
04912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1803904912
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2416230081
Short name T323
Test name
Test status
Simulation time 8366794104 ps
CPU time 7.37 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 202484 kb
Host smart-6b3169c6-5aa5-49b2-839e-e69be94e1095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24162
30081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2416230081
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3646632060
Short name T439
Test name
Test status
Simulation time 8421835727 ps
CPU time 7.33 seconds
Started Mar 05 01:06:27 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 202428 kb
Host smart-37967d82-dc81-445f-a14c-879b33fd007a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36466
32060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3646632060
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2108157420
Short name T447
Test name
Test status
Simulation time 8401689215 ps
CPU time 7.42 seconds
Started Mar 05 01:06:23 PM PST 24
Finished Mar 05 01:06:31 PM PST 24
Peak memory 202416 kb
Host smart-03eebc88-e804-4482-85b5-3885949d3cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21081
57420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2108157420
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2299221340
Short name T455
Test name
Test status
Simulation time 8381510862 ps
CPU time 7.57 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202416 kb
Host smart-6ce231b2-7fb9-49ee-9546-161cec2c856e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22992
21340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2299221340
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3233270509
Short name T263
Test name
Test status
Simulation time 8363896087 ps
CPU time 7.44 seconds
Started Mar 05 01:06:27 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 202476 kb
Host smart-4209158d-e7f6-4035-a479-efe5309c2d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32332
70509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3233270509
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1461681054
Short name T346
Test name
Test status
Simulation time 8368930533 ps
CPU time 7.63 seconds
Started Mar 05 01:06:25 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202428 kb
Host smart-4db93f43-a4e2-48eb-a2bb-67d69901d46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14616
81054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1461681054
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.877225710
Short name T187
Test name
Test status
Simulation time 8366427861 ps
CPU time 8.57 seconds
Started Mar 05 01:06:28 PM PST 24
Finished Mar 05 01:06:37 PM PST 24
Peak memory 202376 kb
Host smart-63d727dd-b3ac-4ee4-a1b5-cd30ec2ddc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87722
5710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.877225710
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.4100442615
Short name T72
Test name
Test status
Simulation time 156786995 ps
CPU time 1.71 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:28 PM PST 24
Peak memory 202476 kb
Host smart-2c419b00-8975-460b-8d7b-068a4c972172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41004
42615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.4100442615
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2416301278
Short name T636
Test name
Test status
Simulation time 8418006701 ps
CPU time 7.42 seconds
Started Mar 05 01:06:25 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202428 kb
Host smart-0fbf09a1-71d4-48ef-b14e-355c94e18960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163
01278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2416301278
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.480624800
Short name T244
Test name
Test status
Simulation time 8365554772 ps
CPU time 7.72 seconds
Started Mar 05 01:06:25 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202404 kb
Host smart-692d2454-c418-492e-9a3b-ce5c1b5b67c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48062
4800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.480624800
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3667686099
Short name T243
Test name
Test status
Simulation time 8393265966 ps
CPU time 7.94 seconds
Started Mar 05 01:06:27 PM PST 24
Finished Mar 05 01:06:35 PM PST 24
Peak memory 202416 kb
Host smart-42cfd30b-f50e-4c57-93bd-44dbe06902a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36676
86099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3667686099
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3757105988
Short name T473
Test name
Test status
Simulation time 8401993031 ps
CPU time 8.51 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:38 PM PST 24
Peak memory 202472 kb
Host smart-6ec3289d-a9f3-4eb5-950d-588ca28a0711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571
05988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3757105988
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.849716694
Short name T559
Test name
Test status
Simulation time 8370027237 ps
CPU time 7.52 seconds
Started Mar 05 01:06:25 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202476 kb
Host smart-0edef5b9-268e-4018-be33-49ba7ed53752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84971
6694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.849716694
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.2591325723
Short name T425
Test name
Test status
Simulation time 8388124939 ps
CPU time 9.94 seconds
Started Mar 05 01:06:27 PM PST 24
Finished Mar 05 01:06:37 PM PST 24
Peak memory 202420 kb
Host smart-23b6acee-3b3e-4bfa-8c37-92c3af232a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25913
25723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.2591325723
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.916696473
Short name T278
Test name
Test status
Simulation time 8363799234 ps
CPU time 8.15 seconds
Started Mar 05 01:06:24 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202472 kb
Host smart-7f2995b1-69b3-470d-aa3a-5265aa9d1d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91669
6473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.916696473
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1174400120
Short name T456
Test name
Test status
Simulation time 8372671420 ps
CPU time 7.3 seconds
Started Mar 05 01:06:25 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202476 kb
Host smart-d391255a-a4aa-4f8f-92c0-3213d8992970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11744
00120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1174400120
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2555799701
Short name T645
Test name
Test status
Simulation time 132638699 ps
CPU time 1.62 seconds
Started Mar 05 01:06:39 PM PST 24
Finished Mar 05 01:06:41 PM PST 24
Peak memory 202328 kb
Host smart-c0d2798a-500d-4426-9148-7541bf68e87c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25557
99701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2555799701
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3635310496
Short name T432
Test name
Test status
Simulation time 8364350025 ps
CPU time 7.92 seconds
Started Mar 05 01:06:36 PM PST 24
Finished Mar 05 01:06:44 PM PST 24
Peak memory 202428 kb
Host smart-f426d249-3292-48e8-9d6a-9eb986773106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36353
10496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3635310496
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3860646187
Short name T657
Test name
Test status
Simulation time 8378820195 ps
CPU time 7.53 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:37 PM PST 24
Peak memory 202400 kb
Host smart-c5239290-464e-434f-8eeb-a527356de8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38606
46187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3860646187
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2653088488
Short name T388
Test name
Test status
Simulation time 8383574691 ps
CPU time 7.19 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:42 PM PST 24
Peak memory 202368 kb
Host smart-477d1466-286f-4ef5-a301-6640a6d3b9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530
88488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2653088488
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2369414403
Short name T475
Test name
Test status
Simulation time 8385822636 ps
CPU time 7.35 seconds
Started Mar 05 01:06:40 PM PST 24
Finished Mar 05 01:06:48 PM PST 24
Peak memory 202320 kb
Host smart-9b25c45f-c454-45d1-8d96-bde396da0b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23694
14403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2369414403
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.745700266
Short name T589
Test name
Test status
Simulation time 8369547375 ps
CPU time 7.48 seconds
Started Mar 05 01:06:28 PM PST 24
Finished Mar 05 01:06:36 PM PST 24
Peak memory 202404 kb
Host smart-bfba35c8-465f-4b07-b5e5-1f5371aaf9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74570
0266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.745700266
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.763134227
Short name T532
Test name
Test status
Simulation time 8365919822 ps
CPU time 7.56 seconds
Started Mar 05 01:06:31 PM PST 24
Finished Mar 05 01:06:39 PM PST 24
Peak memory 202456 kb
Host smart-221a494f-e7c2-4cdd-81df-578bd807c078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76313
4227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.763134227
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1248952741
Short name T318
Test name
Test status
Simulation time 8377793417 ps
CPU time 7.33 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:33 PM PST 24
Peak memory 202424 kb
Host smart-672f68f9-b9ed-428f-a51d-e72a8a765fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12489
52741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1248952741
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2355769691
Short name T605
Test name
Test status
Simulation time 8371336502 ps
CPU time 7.49 seconds
Started Mar 05 01:06:34 PM PST 24
Finished Mar 05 01:06:42 PM PST 24
Peak memory 202484 kb
Host smart-9bc71440-2c0e-47ae-9f99-2f0d0370b32a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
69691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2355769691
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3999675247
Short name T192
Test name
Test status
Simulation time 80102096 ps
CPU time 2 seconds
Started Mar 05 01:06:36 PM PST 24
Finished Mar 05 01:06:38 PM PST 24
Peak memory 202444 kb
Host smart-c50192d3-0471-4686-ba5b-5f4ad6e61453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39996
75247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3999675247
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3605137433
Short name T568
Test name
Test status
Simulation time 8403934134 ps
CPU time 8.51 seconds
Started Mar 05 01:06:43 PM PST 24
Finished Mar 05 01:06:52 PM PST 24
Peak memory 202312 kb
Host smart-d8a75f0a-8feb-47fd-8312-0675e15e55ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36051
37433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3605137433
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3748929476
Short name T184
Test name
Test status
Simulation time 8364175113 ps
CPU time 7.55 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:42 PM PST 24
Peak memory 202428 kb
Host smart-9f4b1c72-c945-416a-9d34-13884a0a92e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37489
29476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3748929476
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1322252651
Short name T93
Test name
Test status
Simulation time 8412719207 ps
CPU time 7.5 seconds
Started Mar 05 01:06:37 PM PST 24
Finished Mar 05 01:06:45 PM PST 24
Peak memory 202364 kb
Host smart-87cb0f16-5d2b-4561-816f-d4b8f26b1e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13222
52651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1322252651
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1575919256
Short name T462
Test name
Test status
Simulation time 8371325311 ps
CPU time 7.39 seconds
Started Mar 05 01:06:37 PM PST 24
Finished Mar 05 01:06:45 PM PST 24
Peak memory 202424 kb
Host smart-1a98eb4b-929c-4acc-97e4-9823f6845d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15759
19256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1575919256
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.990056769
Short name T9
Test name
Test status
Simulation time 8484596621 ps
CPU time 7.32 seconds
Started Mar 05 01:06:34 PM PST 24
Finished Mar 05 01:06:42 PM PST 24
Peak memory 202448 kb
Host smart-141383f5-6401-4586-8543-646d084d80ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99005
6769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.990056769
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3029086079
Short name T597
Test name
Test status
Simulation time 8387045738 ps
CPU time 8.18 seconds
Started Mar 05 01:06:40 PM PST 24
Finished Mar 05 01:06:48 PM PST 24
Peak memory 202372 kb
Host smart-7600c089-540f-4b98-9918-356c56019eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30290
86079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3029086079
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.2029730268
Short name T421
Test name
Test status
Simulation time 8397986559 ps
CPU time 8.69 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:44 PM PST 24
Peak memory 202420 kb
Host smart-bbed920f-d1d6-454c-9f1a-d4bf8e89088e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20297
30268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.2029730268
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1043476428
Short name T309
Test name
Test status
Simulation time 8358220885 ps
CPU time 7.68 seconds
Started Mar 05 01:06:39 PM PST 24
Finished Mar 05 01:06:47 PM PST 24
Peak memory 202352 kb
Host smart-8f2acb2e-c9b8-4b89-8359-5f4098564b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10434
76428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1043476428
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.307752855
Short name T565
Test name
Test status
Simulation time 8371023050 ps
CPU time 6.93 seconds
Started Mar 05 01:06:37 PM PST 24
Finished Mar 05 01:06:44 PM PST 24
Peak memory 202368 kb
Host smart-c00e3636-5826-4322-a843-940d2d8a9cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
2855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.307752855
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3184643036
Short name T334
Test name
Test status
Simulation time 8372772865 ps
CPU time 7.19 seconds
Started Mar 05 01:06:40 PM PST 24
Finished Mar 05 01:06:47 PM PST 24
Peak memory 202320 kb
Host smart-ce42c101-e066-4229-8c68-139842641839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31846
43036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3184643036
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3723046015
Short name T176
Test name
Test status
Simulation time 183222366 ps
CPU time 1.78 seconds
Started Mar 05 01:06:36 PM PST 24
Finished Mar 05 01:06:38 PM PST 24
Peak memory 202444 kb
Host smart-ff435a94-5547-44f7-ab8f-3fad726c8cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37230
46015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3723046015
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2968353779
Short name T494
Test name
Test status
Simulation time 8404013173 ps
CPU time 7.23 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:43 PM PST 24
Peak memory 202308 kb
Host smart-509e15ea-e177-4081-94f3-5e3bddc65ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29683
53779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2968353779
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2917631939
Short name T236
Test name
Test status
Simulation time 8371990589 ps
CPU time 8.94 seconds
Started Mar 05 01:06:40 PM PST 24
Finished Mar 05 01:06:49 PM PST 24
Peak memory 202324 kb
Host smart-74b3828e-16f4-4aec-89e5-ed6ee373b02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29176
31939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2917631939
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.849288646
Short name T86
Test name
Test status
Simulation time 8429372284 ps
CPU time 7.28 seconds
Started Mar 05 01:06:40 PM PST 24
Finished Mar 05 01:06:47 PM PST 24
Peak memory 202424 kb
Host smart-7ffde954-8c5a-43fa-b87e-9511c94c25c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84928
8646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.849288646
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3222877571
Short name T459
Test name
Test status
Simulation time 8366130462 ps
CPU time 8.08 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:43 PM PST 24
Peak memory 202424 kb
Host smart-af92c99c-8562-4590-ad6b-9480e77465f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32228
77571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3222877571
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3086746239
Short name T253
Test name
Test status
Simulation time 8403065209 ps
CPU time 6.79 seconds
Started Mar 05 01:06:34 PM PST 24
Finished Mar 05 01:06:41 PM PST 24
Peak memory 202304 kb
Host smart-82e87bf9-2e6d-439f-bc60-4df1fae5e260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30867
46239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3086746239
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.322613382
Short name T390
Test name
Test status
Simulation time 8447576020 ps
CPU time 7.75 seconds
Started Mar 05 01:06:44 PM PST 24
Finished Mar 05 01:06:52 PM PST 24
Peak memory 202364 kb
Host smart-90d7530e-f08e-43ff-9b86-55a2f313f694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32261
3382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.322613382
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.872936963
Short name T321
Test name
Test status
Simulation time 8390497417 ps
CPU time 6.9 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:42 PM PST 24
Peak memory 202576 kb
Host smart-201c4006-3038-40d3-86a1-e94256c6fa9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87293
6963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.872936963
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1759477631
Short name T387
Test name
Test status
Simulation time 8381581070 ps
CPU time 7.32 seconds
Started Mar 05 01:06:36 PM PST 24
Finished Mar 05 01:06:44 PM PST 24
Peak memory 202484 kb
Host smart-13cb6bb8-6790-4538-86a8-e943c599334c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17594
77631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1759477631
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2254131480
Short name T75
Test name
Test status
Simulation time 8368286790 ps
CPU time 8.78 seconds
Started Mar 05 01:06:37 PM PST 24
Finished Mar 05 01:06:46 PM PST 24
Peak memory 202480 kb
Host smart-3d6de0f6-3ec0-497c-b3b2-fb017e66cc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22541
31480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2254131480
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1052848438
Short name T606
Test name
Test status
Simulation time 73509570 ps
CPU time 0.99 seconds
Started Mar 05 01:06:45 PM PST 24
Finished Mar 05 01:06:47 PM PST 24
Peak memory 202376 kb
Host smart-be441656-6d8a-4713-a4cd-ffdcb46c4d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10528
48438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1052848438
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.191139650
Short name T528
Test name
Test status
Simulation time 8417463233 ps
CPU time 7.82 seconds
Started Mar 05 01:06:40 PM PST 24
Finished Mar 05 01:06:48 PM PST 24
Peak memory 202428 kb
Host smart-a58c01c3-0db0-4b10-8a57-871f966e032a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19113
9650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.191139650
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.665352610
Short name T275
Test name
Test status
Simulation time 8408357525 ps
CPU time 7.11 seconds
Started Mar 05 01:06:41 PM PST 24
Finished Mar 05 01:06:48 PM PST 24
Peak memory 202284 kb
Host smart-b74f9d5d-806b-4c46-a0dd-80f89691e1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66535
2610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.665352610
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.913212582
Short name T584
Test name
Test status
Simulation time 8375335528 ps
CPU time 7.1 seconds
Started Mar 05 01:06:46 PM PST 24
Finished Mar 05 01:06:53 PM PST 24
Peak memory 202400 kb
Host smart-78399f35-971f-45e4-8cde-50cfacc08b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91321
2582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.913212582
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3759645135
Short name T399
Test name
Test status
Simulation time 8377575602 ps
CPU time 7.11 seconds
Started Mar 05 01:06:39 PM PST 24
Finished Mar 05 01:06:46 PM PST 24
Peak memory 202472 kb
Host smart-ee0ec5e2-3671-46b1-9187-461b0951124b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37596
45135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3759645135
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.437256408
Short name T415
Test name
Test status
Simulation time 8409369269 ps
CPU time 8.32 seconds
Started Mar 05 01:06:36 PM PST 24
Finished Mar 05 01:06:44 PM PST 24
Peak memory 202420 kb
Host smart-a1038800-eb56-49bf-a23b-9944a8cae335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43725
6408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.437256408
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.752932733
Short name T189
Test name
Test status
Simulation time 8388137804 ps
CPU time 7.84 seconds
Started Mar 05 01:06:40 PM PST 24
Finished Mar 05 01:06:48 PM PST 24
Peak memory 202408 kb
Host smart-1219f1dd-66ab-4346-842b-f07ef22b3145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75293
2733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.752932733
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.452419552
Short name T402
Test name
Test status
Simulation time 8370489528 ps
CPU time 7.08 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:42 PM PST 24
Peak memory 202416 kb
Host smart-7c776c17-bcd0-43ec-88ce-4074bba889ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45241
9552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.452419552
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1150053407
Short name T609
Test name
Test status
Simulation time 8374378553 ps
CPU time 8.09 seconds
Started Mar 05 01:06:35 PM PST 24
Finished Mar 05 01:06:44 PM PST 24
Peak memory 202428 kb
Host smart-14127eeb-a18b-4876-a9c2-e566f7e24544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11500
53407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1150053407
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3279398297
Short name T493
Test name
Test status
Simulation time 8377545510 ps
CPU time 7.34 seconds
Started Mar 05 01:06:40 PM PST 24
Finished Mar 05 01:06:47 PM PST 24
Peak memory 202436 kb
Host smart-492c02bd-0777-48d5-85f3-01f6dee36a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32793
98297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3279398297
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3074686688
Short name T167
Test name
Test status
Simulation time 46521929 ps
CPU time 1.3 seconds
Started Mar 05 01:06:45 PM PST 24
Finished Mar 05 01:06:47 PM PST 24
Peak memory 202400 kb
Host smart-a683dcdd-bfa5-42d7-bb4d-e75eb944ce13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746
86688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3074686688
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1819818630
Short name T576
Test name
Test status
Simulation time 8417094053 ps
CPU time 9.18 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:59 PM PST 24
Peak memory 202376 kb
Host smart-e33f50b3-71b1-4871-9289-b1a26498d024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18198
18630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1819818630
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1154781756
Short name T577
Test name
Test status
Simulation time 8409345723 ps
CPU time 8.37 seconds
Started Mar 05 01:06:44 PM PST 24
Finished Mar 05 01:06:53 PM PST 24
Peak memory 202508 kb
Host smart-a9653a1a-d0f6-4a29-a1b1-a97d0431122f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11547
81756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1154781756
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.311057283
Short name T338
Test name
Test status
Simulation time 8363689690 ps
CPU time 7.27 seconds
Started Mar 05 01:06:46 PM PST 24
Finished Mar 05 01:06:53 PM PST 24
Peak memory 202464 kb
Host smart-40625b0c-67cc-4981-83d8-76e70b9e15aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31105
7283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.311057283
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2672403874
Short name T440
Test name
Test status
Simulation time 8422961081 ps
CPU time 7.22 seconds
Started Mar 05 01:06:44 PM PST 24
Finished Mar 05 01:06:51 PM PST 24
Peak memory 202416 kb
Host smart-5732b5bb-35fc-44fb-9fe3-9c6a1a09190b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26724
03874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2672403874
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4139547828
Short name T509
Test name
Test status
Simulation time 8472701379 ps
CPU time 7.88 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:57 PM PST 24
Peak memory 202552 kb
Host smart-85f6338f-b5e4-4039-ac75-75db0f24688a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41395
47828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4139547828
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1221738065
Short name T251
Test name
Test status
Simulation time 8381520956 ps
CPU time 7.32 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:57 PM PST 24
Peak memory 202396 kb
Host smart-b16de192-110c-4930-8cdc-da2df3770ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12217
38065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1221738065
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.2477657395
Short name T172
Test name
Test status
Simulation time 8403184259 ps
CPU time 7.41 seconds
Started Mar 05 01:06:45 PM PST 24
Finished Mar 05 01:06:53 PM PST 24
Peak memory 202480 kb
Host smart-640df73d-3d20-435d-8bd4-80b65b29198a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24776
57395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.2477657395
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1646377956
Short name T457
Test name
Test status
Simulation time 8360964422 ps
CPU time 7.36 seconds
Started Mar 05 01:06:36 PM PST 24
Finished Mar 05 01:06:43 PM PST 24
Peak memory 202472 kb
Host smart-00f2f97f-a21e-43d0-9f53-97cd593b914b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16463
77956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1646377956
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.764602363
Short name T365
Test name
Test status
Simulation time 8374671476 ps
CPU time 9.04 seconds
Started Mar 05 01:06:45 PM PST 24
Finished Mar 05 01:06:55 PM PST 24
Peak memory 202484 kb
Host smart-6194e376-34c2-40d6-9a92-0ccf4265ffc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76460
2363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.764602363
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2090079918
Short name T44
Test name
Test status
Simulation time 229299122 ps
CPU time 1.62 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:52 PM PST 24
Peak memory 202504 kb
Host smart-69c83d55-a0f4-4ef5-97ac-6f32fdfc636a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20900
79918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2090079918
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2783513900
Short name T514
Test name
Test status
Simulation time 8418677888 ps
CPU time 7.76 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:58 PM PST 24
Peak memory 202464 kb
Host smart-6e5c6bb8-4c7e-48c1-979f-6690f72cdd2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27835
13900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2783513900
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3524823944
Short name T328
Test name
Test status
Simulation time 8406482536 ps
CPU time 8.09 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:58 PM PST 24
Peak memory 202320 kb
Host smart-636d0ae0-b023-4afd-834e-75c05c37444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35248
23944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3524823944
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2575053906
Short name T287
Test name
Test status
Simulation time 8365446056 ps
CPU time 7.78 seconds
Started Mar 05 01:06:45 PM PST 24
Finished Mar 05 01:06:54 PM PST 24
Peak memory 202424 kb
Host smart-fa1a1ca7-901b-46a3-880f-d9f96482413e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25750
53906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2575053906
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2666585412
Short name T96
Test name
Test status
Simulation time 8426201058 ps
CPU time 7.67 seconds
Started Mar 05 01:06:48 PM PST 24
Finished Mar 05 01:06:56 PM PST 24
Peak memory 202476 kb
Host smart-6e7f142f-1bed-4fcb-9299-7dfda28079e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26665
85412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2666585412
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2880674136
Short name T417
Test name
Test status
Simulation time 8365972088 ps
CPU time 7.28 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:56 PM PST 24
Peak memory 202476 kb
Host smart-b2b1f3eb-5598-4777-8b28-eea5303b1852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28806
74136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2880674136
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2606459758
Short name T322
Test name
Test status
Simulation time 8376540036 ps
CPU time 7.07 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:58 PM PST 24
Peak memory 202416 kb
Host smart-75af6dcd-350b-4f92-b988-5c2c7d7a4804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26064
59758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2606459758
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3769117933
Short name T114
Test name
Test status
Simulation time 8425630529 ps
CPU time 7.46 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:58 PM PST 24
Peak memory 202436 kb
Host smart-3513d5e4-6c35-4556-affe-41d71213d0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691
17933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3769117933
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.2958713671
Short name T347
Test name
Test status
Simulation time 8387909357 ps
CPU time 7.25 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:56 PM PST 24
Peak memory 202440 kb
Host smart-3fc9d741-d4d5-499e-9f5e-2bd01df48f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29587
13671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.2958713671
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.368883354
Short name T345
Test name
Test status
Simulation time 8358159646 ps
CPU time 9.7 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:07:00 PM PST 24
Peak memory 202408 kb
Host smart-13210295-7b08-4319-9ee0-d6fdd95bbb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36888
3354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.368883354
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2233991629
Short name T555
Test name
Test status
Simulation time 8373194035 ps
CPU time 8.68 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:59 PM PST 24
Peak memory 202368 kb
Host smart-435001b6-62fa-4407-aebc-bfd7feadb29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22339
91629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2233991629
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.3909813829
Short name T374
Test name
Test status
Simulation time 8366835333 ps
CPU time 7.13 seconds
Started Mar 05 01:05:48 PM PST 24
Finished Mar 05 01:05:56 PM PST 24
Peak memory 202224 kb
Host smart-ab5e563d-237a-46b2-a353-c747b799507b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
13829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.3909813829
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3862758899
Short name T547
Test name
Test status
Simulation time 8405919321 ps
CPU time 7.34 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:50 PM PST 24
Peak memory 202300 kb
Host smart-0c507639-363c-4a4c-8c5f-c21234be89cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38627
58899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3862758899
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.233309308
Short name T163
Test name
Test status
Simulation time 8407390047 ps
CPU time 7.73 seconds
Started Mar 05 01:05:47 PM PST 24
Finished Mar 05 01:05:55 PM PST 24
Peak memory 202360 kb
Host smart-5df6cd86-3cd2-4ae8-b2e4-8ca343c3c19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23330
9308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.233309308
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2558317602
Short name T452
Test name
Test status
Simulation time 8364890940 ps
CPU time 9.25 seconds
Started Mar 05 01:05:41 PM PST 24
Finished Mar 05 01:05:50 PM PST 24
Peak memory 202352 kb
Host smart-fe13e051-1295-4e45-b7f5-dbcff072d31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25583
17602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2558317602
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1400701855
Short name T268
Test name
Test status
Simulation time 8380117476 ps
CPU time 7.52 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:49 PM PST 24
Peak memory 202428 kb
Host smart-5e838dc1-ada3-4351-bc2a-11160650088b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14007
01855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1400701855
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.559843426
Short name T231
Test name
Test status
Simulation time 8365706216 ps
CPU time 7.6 seconds
Started Mar 05 01:05:48 PM PST 24
Finished Mar 05 01:05:57 PM PST 24
Peak memory 202216 kb
Host smart-6c018707-2649-410f-8688-f469f0cde92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55984
3426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.559843426
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2149389087
Short name T124
Test name
Test status
Simulation time 8375669601 ps
CPU time 7.87 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:50 PM PST 24
Peak memory 202384 kb
Host smart-d3aa32f1-b696-41da-8a08-fbe9b31dccb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21493
89087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2149389087
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2410708841
Short name T50
Test name
Test status
Simulation time 97329806 ps
CPU time 0.89 seconds
Started Mar 05 01:05:54 PM PST 24
Finished Mar 05 01:05:55 PM PST 24
Peak memory 217188 kb
Host smart-16b85eb3-58df-45f7-817a-3d586681fb6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2410708841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2410708841
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.715326789
Short name T663
Test name
Test status
Simulation time 8441759809 ps
CPU time 9.13 seconds
Started Mar 05 01:05:45 PM PST 24
Finished Mar 05 01:05:55 PM PST 24
Peak memory 202464 kb
Host smart-0aa0a9ea-6eb7-4abf-8d14-5d0a4afbe9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71532
6789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.715326789
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4143965919
Short name T483
Test name
Test status
Simulation time 8401412107 ps
CPU time 8.68 seconds
Started Mar 05 01:05:42 PM PST 24
Finished Mar 05 01:05:51 PM PST 24
Peak memory 202428 kb
Host smart-fff9b76c-46d4-4593-9ae1-043553d6e793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41439
65919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4143965919
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2176198853
Short name T295
Test name
Test status
Simulation time 8371430189 ps
CPU time 7.1 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:56 PM PST 24
Peak memory 202448 kb
Host smart-423ca48f-1955-410b-9a4b-3e16f5ba459f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21761
98853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2176198853
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.4062841233
Short name T369
Test name
Test status
Simulation time 33530517 ps
CPU time 1.02 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:51 PM PST 24
Peak memory 202508 kb
Host smart-c068498c-5d04-4965-96b7-72e07a530053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40628
41233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.4062841233
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3407349000
Short name T319
Test name
Test status
Simulation time 8379768800 ps
CPU time 8.15 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:58 PM PST 24
Peak memory 202484 kb
Host smart-fdfc66c3-d4af-4a0d-8c58-a4426508bfc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34073
49000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3407349000
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1158190332
Short name T640
Test name
Test status
Simulation time 8408459106 ps
CPU time 10.38 seconds
Started Mar 05 01:06:53 PM PST 24
Finished Mar 05 01:07:04 PM PST 24
Peak memory 202368 kb
Host smart-8f8147cc-01f6-4f19-bff9-f841fee5bdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11581
90332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1158190332
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3709523352
Short name T638
Test name
Test status
Simulation time 8368607404 ps
CPU time 8.23 seconds
Started Mar 05 01:06:51 PM PST 24
Finished Mar 05 01:07:00 PM PST 24
Peak memory 202484 kb
Host smart-7c8c8f08-ba5f-4547-94e4-6fe733e37a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37095
23352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3709523352
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.131071463
Short name T378
Test name
Test status
Simulation time 8404710896 ps
CPU time 7.34 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:57 PM PST 24
Peak memory 202404 kb
Host smart-9bbfa505-9b43-4d0d-9f6b-c624e273c30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13107
1463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.131071463
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4246031186
Short name T266
Test name
Test status
Simulation time 8369473941 ps
CPU time 7.65 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:58 PM PST 24
Peak memory 202364 kb
Host smart-e4ffa511-4ec2-45de-928f-b605518a6816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42460
31186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4246031186
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3118176072
Short name T173
Test name
Test status
Simulation time 8365961677 ps
CPU time 8.56 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:57 PM PST 24
Peak memory 202472 kb
Host smart-c00db262-003e-499a-b8fd-dd0643a77f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31181
76072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3118176072
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.641416301
Short name T465
Test name
Test status
Simulation time 8422622105 ps
CPU time 7.27 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:56 PM PST 24
Peak memory 202476 kb
Host smart-258e8d4a-e785-4c18-a305-8674cc840578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64141
6301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.641416301
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.2493926460
Short name T297
Test name
Test status
Simulation time 8405882832 ps
CPU time 8.39 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:58 PM PST 24
Peak memory 202348 kb
Host smart-72fdc31c-fc0f-40bb-9de7-fa57969b9e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24939
26460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.2493926460
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2328699790
Short name T386
Test name
Test status
Simulation time 8364136988 ps
CPU time 8.81 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:59 PM PST 24
Peak memory 202456 kb
Host smart-dbeca497-ecfa-40e4-96ae-93b5dae04d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
99790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2328699790
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.376071495
Short name T291
Test name
Test status
Simulation time 8369464820 ps
CPU time 8.3 seconds
Started Mar 05 01:06:49 PM PST 24
Finished Mar 05 01:06:57 PM PST 24
Peak memory 202424 kb
Host smart-3eaedbac-93b4-456c-bb60-14b14fadb3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37607
1495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.376071495
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3159701720
Short name T188
Test name
Test status
Simulation time 8402081891 ps
CPU time 6.93 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:57 PM PST 24
Peak memory 202484 kb
Host smart-5deb1d64-d20e-4c35-858d-ba0201e13560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31597
01720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3159701720
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2372751148
Short name T392
Test name
Test status
Simulation time 68343006 ps
CPU time 1.78 seconds
Started Mar 05 01:07:02 PM PST 24
Finished Mar 05 01:07:04 PM PST 24
Peak memory 202628 kb
Host smart-9803ce44-be7a-4d4e-83d5-2c773222823f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23727
51148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2372751148
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3053282969
Short name T585
Test name
Test status
Simulation time 8491762302 ps
CPU time 7.51 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:57 PM PST 24
Peak memory 202424 kb
Host smart-65655746-e0e8-477c-b2b8-904b41b17e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
82969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3053282969
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2774351358
Short name T288
Test name
Test status
Simulation time 8425063099 ps
CPU time 7.08 seconds
Started Mar 05 01:06:58 PM PST 24
Finished Mar 05 01:07:05 PM PST 24
Peak memory 202364 kb
Host smart-bdbb77fd-0061-464d-af65-a1609ad25a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27743
51358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2774351358
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.4186948125
Short name T424
Test name
Test status
Simulation time 8363877896 ps
CPU time 8.2 seconds
Started Mar 05 01:06:51 PM PST 24
Finished Mar 05 01:07:00 PM PST 24
Peak memory 202484 kb
Host smart-91528fec-c148-43fe-b525-9d6a1ebab294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41869
48125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.4186948125
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3534407624
Short name T343
Test name
Test status
Simulation time 8399215151 ps
CPU time 7.12 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:07 PM PST 24
Peak memory 202476 kb
Host smart-ab5014c7-bff0-466d-8cbe-7e51559d3254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344
07624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3534407624
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3332624922
Short name T453
Test name
Test status
Simulation time 8391549921 ps
CPU time 7.5 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:07 PM PST 24
Peak memory 202248 kb
Host smart-0232a58c-ec94-4ea8-b499-43255625906e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33326
24922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3332624922
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2220127584
Short name T122
Test name
Test status
Simulation time 8404125166 ps
CPU time 7.84 seconds
Started Mar 05 01:06:48 PM PST 24
Finished Mar 05 01:06:56 PM PST 24
Peak memory 202440 kb
Host smart-dc23b3b6-4dfe-4efe-98fb-d2526c9c595a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201
27584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2220127584
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.771944385
Short name T525
Test name
Test status
Simulation time 8393902051 ps
CPU time 8.02 seconds
Started Mar 05 01:06:50 PM PST 24
Finished Mar 05 01:06:58 PM PST 24
Peak memory 202464 kb
Host smart-f1ab563c-7f00-4bd1-86c9-f833c4e1fdf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77194
4385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.771944385
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3974694129
Short name T505
Test name
Test status
Simulation time 8363212657 ps
CPU time 8.79 seconds
Started Mar 05 01:06:51 PM PST 24
Finished Mar 05 01:07:00 PM PST 24
Peak memory 202440 kb
Host smart-89ae10c2-fd67-4db3-bd74-ae9c70fa5a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39746
94129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3974694129
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.271173229
Short name T292
Test name
Test status
Simulation time 8368568075 ps
CPU time 7.52 seconds
Started Mar 05 01:06:52 PM PST 24
Finished Mar 05 01:06:59 PM PST 24
Peak memory 202320 kb
Host smart-2658815e-2b92-456a-82cc-2e7a1fbc1d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27117
3229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.271173229
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2713249527
Short name T470
Test name
Test status
Simulation time 8378193614 ps
CPU time 9.37 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:10 PM PST 24
Peak memory 202436 kb
Host smart-6a921be9-00fa-4f2b-ade0-ecc6f4043d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27132
49527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2713249527
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1750462534
Short name T573
Test name
Test status
Simulation time 8438227814 ps
CPU time 7.6 seconds
Started Mar 05 01:06:58 PM PST 24
Finished Mar 05 01:07:07 PM PST 24
Peak memory 202428 kb
Host smart-dae79c4a-1d89-4aba-90a3-3b9b6e36bd11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17504
62534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1750462534
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2640437747
Short name T476
Test name
Test status
Simulation time 8412503327 ps
CPU time 9.29 seconds
Started Mar 05 01:07:03 PM PST 24
Finished Mar 05 01:07:12 PM PST 24
Peak memory 202428 kb
Host smart-945f02e6-c399-4341-97d1-8c8871a29324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404
37747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2640437747
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1905315733
Short name T639
Test name
Test status
Simulation time 8366037433 ps
CPU time 7.31 seconds
Started Mar 05 01:07:00 PM PST 24
Finished Mar 05 01:07:08 PM PST 24
Peak memory 202484 kb
Host smart-3b7f03be-6512-468a-abb3-891018ea843c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19053
15733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1905315733
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.4179862154
Short name T95
Test name
Test status
Simulation time 8416065178 ps
CPU time 8.71 seconds
Started Mar 05 01:06:58 PM PST 24
Finished Mar 05 01:07:07 PM PST 24
Peak memory 202424 kb
Host smart-b0c3425f-e0a0-481d-b798-707633029b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41798
62154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.4179862154
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3139499387
Short name T463
Test name
Test status
Simulation time 8388939402 ps
CPU time 6.98 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:07 PM PST 24
Peak memory 202124 kb
Host smart-322496fe-d27e-4fe3-81c2-95d7e58d94cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31394
99387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3139499387
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.4111404391
Short name T643
Test name
Test status
Simulation time 8362990728 ps
CPU time 7.54 seconds
Started Mar 05 01:07:02 PM PST 24
Finished Mar 05 01:07:10 PM PST 24
Peak memory 202420 kb
Host smart-fc1de4d5-fb0c-4516-a9a5-020c3a4dc84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41114
04391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.4111404391
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3284330494
Short name T115
Test name
Test status
Simulation time 8408038499 ps
CPU time 8 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:08 PM PST 24
Peak memory 202380 kb
Host smart-5b23deeb-4f84-4830-8e10-b5900867b336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32843
30494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3284330494
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3531686968
Short name T434
Test name
Test status
Simulation time 8371704608 ps
CPU time 8.36 seconds
Started Mar 05 01:07:07 PM PST 24
Finished Mar 05 01:07:16 PM PST 24
Peak memory 202480 kb
Host smart-f63c429e-ad9c-4c09-adf3-f72e1edd45a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35316
86968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3531686968
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3446237066
Short name T66
Test name
Test status
Simulation time 8360942341 ps
CPU time 9.46 seconds
Started Mar 05 01:06:57 PM PST 24
Finished Mar 05 01:07:06 PM PST 24
Peak memory 202476 kb
Host smart-48d10f2a-1a12-4522-9849-ba5682c302d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34462
37066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3446237066
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.4265925069
Short name T403
Test name
Test status
Simulation time 8367613246 ps
CPU time 7.24 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:07 PM PST 24
Peak memory 202372 kb
Host smart-a04508c3-72cc-49db-8a01-6eb2f1c62276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42659
25069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.4265925069
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2940153437
Short name T311
Test name
Test status
Simulation time 8374810926 ps
CPU time 7.18 seconds
Started Mar 05 01:07:00 PM PST 24
Finished Mar 05 01:07:08 PM PST 24
Peak memory 202360 kb
Host smart-3734d163-ba9e-4c84-91c6-c0968dee24f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29401
53437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2940153437
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.207201932
Short name T575
Test name
Test status
Simulation time 83103532 ps
CPU time 1.23 seconds
Started Mar 05 01:07:03 PM PST 24
Finished Mar 05 01:07:05 PM PST 24
Peak memory 202492 kb
Host smart-4d4cd0cd-7f40-4047-966d-e1ae78b03f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20720
1932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.207201932
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3769133981
Short name T232
Test name
Test status
Simulation time 8417955782 ps
CPU time 8.13 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:08 PM PST 24
Peak memory 202252 kb
Host smart-77b3a2ff-3ea8-4ab7-a39d-ae07b0026b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691
33981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3769133981
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2931986350
Short name T610
Test name
Test status
Simulation time 8359929214 ps
CPU time 7.37 seconds
Started Mar 05 01:06:57 PM PST 24
Finished Mar 05 01:07:04 PM PST 24
Peak memory 202600 kb
Host smart-fa306872-57ea-4e68-8262-5f6f3869da61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29319
86350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2931986350
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1604219079
Short name T103
Test name
Test status
Simulation time 8451586158 ps
CPU time 8.68 seconds
Started Mar 05 01:07:01 PM PST 24
Finished Mar 05 01:07:10 PM PST 24
Peak memory 202424 kb
Host smart-dc5a5de0-462f-4312-a011-7a897a7d0b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16042
19079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1604219079
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3641439349
Short name T526
Test name
Test status
Simulation time 8390832462 ps
CPU time 8.81 seconds
Started Mar 05 01:07:03 PM PST 24
Finished Mar 05 01:07:12 PM PST 24
Peak memory 202428 kb
Host smart-c0c3caa2-9ed1-4893-9262-6b96816a2386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36414
39349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3641439349
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2210165296
Short name T649
Test name
Test status
Simulation time 8394324430 ps
CPU time 7.67 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:08 PM PST 24
Peak memory 202184 kb
Host smart-5b70e10c-3b69-4a34-b83f-3969b031af51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22101
65296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2210165296
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.2266398762
Short name T64
Test name
Test status
Simulation time 8393881673 ps
CPU time 7.5 seconds
Started Mar 05 01:06:58 PM PST 24
Finished Mar 05 01:07:07 PM PST 24
Peak memory 202364 kb
Host smart-3abb549a-9e53-4f8e-a376-52fd7e602db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22663
98762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.2266398762
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2579215579
Short name T545
Test name
Test status
Simulation time 8359169052 ps
CPU time 7.55 seconds
Started Mar 05 01:07:00 PM PST 24
Finished Mar 05 01:07:09 PM PST 24
Peak memory 202356 kb
Host smart-64e6e5d0-974b-43d3-984b-db9c2ca0096f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25792
15579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2579215579
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3678439109
Short name T423
Test name
Test status
Simulation time 8368052529 ps
CPU time 7.29 seconds
Started Mar 05 01:07:03 PM PST 24
Finished Mar 05 01:07:11 PM PST 24
Peak memory 202480 kb
Host smart-26f8b179-2c5a-44dd-aaf3-a372e1c9be35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36784
39109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3678439109
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1737399692
Short name T400
Test name
Test status
Simulation time 8372502016 ps
CPU time 9.32 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:10 PM PST 24
Peak memory 202328 kb
Host smart-1c9de308-f94f-481a-96d9-53eab5bea606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17373
99692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1737399692
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3476432366
Short name T165
Test name
Test status
Simulation time 169630889 ps
CPU time 1.73 seconds
Started Mar 05 01:07:07 PM PST 24
Finished Mar 05 01:07:10 PM PST 24
Peak memory 202424 kb
Host smart-e8c847f8-1ead-4e08-9f8b-471598c55f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34764
32366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3476432366
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1279933876
Short name T373
Test name
Test status
Simulation time 8410023153 ps
CPU time 8.15 seconds
Started Mar 05 01:07:03 PM PST 24
Finished Mar 05 01:07:12 PM PST 24
Peak memory 202436 kb
Host smart-27c35cc6-001f-49bf-b1d7-8029adee35f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12799
33876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1279933876
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1731538161
Short name T359
Test name
Test status
Simulation time 8404350580 ps
CPU time 9.38 seconds
Started Mar 05 01:07:00 PM PST 24
Finished Mar 05 01:07:10 PM PST 24
Peak memory 202408 kb
Host smart-32d639ce-18ad-4bb4-85b7-a8943224c37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17315
38161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1731538161
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.517184209
Short name T626
Test name
Test status
Simulation time 8372373565 ps
CPU time 7.26 seconds
Started Mar 05 01:07:00 PM PST 24
Finished Mar 05 01:07:08 PM PST 24
Peak memory 202460 kb
Host smart-e60c4db1-2213-4916-a9c4-711a90f8c5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51718
4209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.517184209
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3930610169
Short name T110
Test name
Test status
Simulation time 8444562225 ps
CPU time 7.06 seconds
Started Mar 05 01:07:02 PM PST 24
Finished Mar 05 01:07:10 PM PST 24
Peak memory 202424 kb
Host smart-76665cc9-2c29-4845-8157-d0847ddedb9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39306
10169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3930610169
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1258826779
Short name T529
Test name
Test status
Simulation time 8396102250 ps
CPU time 9.22 seconds
Started Mar 05 01:07:03 PM PST 24
Finished Mar 05 01:07:12 PM PST 24
Peak memory 202428 kb
Host smart-d11cface-7b4b-4e02-88fc-aed7413d3e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12588
26779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1258826779
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3750887809
Short name T554
Test name
Test status
Simulation time 8384116270 ps
CPU time 7.53 seconds
Started Mar 05 01:06:59 PM PST 24
Finished Mar 05 01:07:07 PM PST 24
Peak memory 202304 kb
Host smart-8ee799b7-6783-450f-b2e0-b5678b8e522b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37508
87809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3750887809
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2004395187
Short name T135
Test name
Test status
Simulation time 8457316409 ps
CPU time 9.31 seconds
Started Mar 05 01:07:00 PM PST 24
Finished Mar 05 01:07:10 PM PST 24
Peak memory 202320 kb
Host smart-ed216ea6-36f7-420b-9cbf-8c3e03c5f40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20043
95187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2004395187
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1410555876
Short name T340
Test name
Test status
Simulation time 8374497363 ps
CPU time 9.39 seconds
Started Mar 05 01:06:57 PM PST 24
Finished Mar 05 01:07:08 PM PST 24
Peak memory 202424 kb
Host smart-3b63fce5-110e-4302-b905-c722f5124115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14105
55876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1410555876
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1387260152
Short name T22
Test name
Test status
Simulation time 8431582559 ps
CPU time 7.99 seconds
Started Mar 05 01:06:57 PM PST 24
Finished Mar 05 01:07:06 PM PST 24
Peak memory 202408 kb
Host smart-130e5b47-4384-47ef-b382-91329d1f6b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13872
60152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1387260152
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.370210459
Short name T307
Test name
Test status
Simulation time 8366006766 ps
CPU time 7.54 seconds
Started Mar 05 01:07:07 PM PST 24
Finished Mar 05 01:07:16 PM PST 24
Peak memory 202424 kb
Host smart-7a709111-a59b-41f0-84c9-ca6b893a2c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37021
0459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.370210459
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1854969502
Short name T562
Test name
Test status
Simulation time 8382840072 ps
CPU time 8.02 seconds
Started Mar 05 01:06:56 PM PST 24
Finished Mar 05 01:07:04 PM PST 24
Peak memory 202484 kb
Host smart-e5544154-2115-4937-a353-eb1d608d5a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18549
69502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1854969502
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.137329276
Short name T552
Test name
Test status
Simulation time 165902719 ps
CPU time 1.93 seconds
Started Mar 05 01:07:15 PM PST 24
Finished Mar 05 01:07:17 PM PST 24
Peak memory 202436 kb
Host smart-17140646-9bb5-4d0e-89eb-a89ac6910044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13732
9276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.137329276
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1130298980
Short name T17
Test name
Test status
Simulation time 8456414613 ps
CPU time 7.43 seconds
Started Mar 05 01:07:15 PM PST 24
Finished Mar 05 01:07:22 PM PST 24
Peak memory 202380 kb
Host smart-298bd4bc-5e06-4227-9750-a3d8e38e86a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11302
98980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1130298980
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1807623691
Short name T355
Test name
Test status
Simulation time 8364789108 ps
CPU time 8.58 seconds
Started Mar 05 01:07:14 PM PST 24
Finished Mar 05 01:07:23 PM PST 24
Peak memory 202376 kb
Host smart-34403d51-cb7c-4c9a-a7cf-892c04cea547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18076
23691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1807623691
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3975187072
Short name T104
Test name
Test status
Simulation time 8404804984 ps
CPU time 7.86 seconds
Started Mar 05 01:07:15 PM PST 24
Finished Mar 05 01:07:23 PM PST 24
Peak memory 202320 kb
Host smart-00700e0b-7fd8-490e-a041-88a4256da6ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751
87072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3975187072
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.4078408949
Short name T235
Test name
Test status
Simulation time 8373322379 ps
CPU time 7.25 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:30 PM PST 24
Peak memory 202368 kb
Host smart-f4806dd9-9d51-417f-8f8d-ef1c8518a65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40784
08949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.4078408949
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1265231814
Short name T348
Test name
Test status
Simulation time 8386801506 ps
CPU time 7.78 seconds
Started Mar 05 01:07:10 PM PST 24
Finished Mar 05 01:07:18 PM PST 24
Peak memory 202372 kb
Host smart-f1415238-d7dd-4e85-abcb-f7fe887deb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12652
31814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1265231814
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.953057971
Short name T33
Test name
Test status
Simulation time 8445505127 ps
CPU time 9.01 seconds
Started Mar 05 01:07:07 PM PST 24
Finished Mar 05 01:07:17 PM PST 24
Peak memory 202448 kb
Host smart-cc8d68fb-129a-40da-9c88-8fa7e45f923e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95305
7971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.953057971
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.2053022957
Short name T256
Test name
Test status
Simulation time 8473552203 ps
CPU time 7.05 seconds
Started Mar 05 01:07:12 PM PST 24
Finished Mar 05 01:07:19 PM PST 24
Peak memory 202600 kb
Host smart-97a954d2-9e4b-4ddc-91e3-0445fe2b1c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20530
22957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.2053022957
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2739016619
Short name T502
Test name
Test status
Simulation time 8369850002 ps
CPU time 8 seconds
Started Mar 05 01:07:00 PM PST 24
Finished Mar 05 01:07:08 PM PST 24
Peak memory 202256 kb
Host smart-2fa22359-d01f-4665-a7ec-7a9223a7c596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27390
16619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2739016619
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1042766927
Short name T422
Test name
Test status
Simulation time 8371495710 ps
CPU time 8.19 seconds
Started Mar 05 01:07:12 PM PST 24
Finished Mar 05 01:07:21 PM PST 24
Peak memory 202380 kb
Host smart-74e8399d-6706-4f5a-9884-3c0458491d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10427
66927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1042766927
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2858627968
Short name T435
Test name
Test status
Simulation time 73588802 ps
CPU time 2.03 seconds
Started Mar 05 01:07:18 PM PST 24
Finished Mar 05 01:07:22 PM PST 24
Peak memory 202436 kb
Host smart-9adef412-b82d-474c-b218-276970b3dad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28586
27968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2858627968
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.4217292507
Short name T517
Test name
Test status
Simulation time 8418722830 ps
CPU time 9.49 seconds
Started Mar 05 01:07:11 PM PST 24
Finished Mar 05 01:07:21 PM PST 24
Peak memory 202472 kb
Host smart-c0e463d8-807d-4419-85c4-97e4b92d2a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42172
92507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.4217292507
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3771534463
Short name T530
Test name
Test status
Simulation time 8411416067 ps
CPU time 7.91 seconds
Started Mar 05 01:07:13 PM PST 24
Finished Mar 05 01:07:21 PM PST 24
Peak memory 202484 kb
Host smart-b858ac1d-010f-4a3f-bbf9-b7a80704d48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37715
34463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3771534463
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3364051007
Short name T90
Test name
Test status
Simulation time 8385982208 ps
CPU time 9.02 seconds
Started Mar 05 01:07:16 PM PST 24
Finished Mar 05 01:07:26 PM PST 24
Peak memory 202456 kb
Host smart-6c21919d-56c6-4c42-ad48-92402f80bb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33640
51007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3364051007
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1319116120
Short name T191
Test name
Test status
Simulation time 8366413606 ps
CPU time 8.37 seconds
Started Mar 05 01:07:10 PM PST 24
Finished Mar 05 01:07:18 PM PST 24
Peak memory 202408 kb
Host smart-e39702b7-0458-4c9c-947d-00b405cc0901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13191
16120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1319116120
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2022456154
Short name T428
Test name
Test status
Simulation time 8393845388 ps
CPU time 8.86 seconds
Started Mar 05 01:07:14 PM PST 24
Finished Mar 05 01:07:23 PM PST 24
Peak memory 202460 kb
Host smart-88492f10-c9cc-4fe2-b5f6-063badbab6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20224
56154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2022456154
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1252298676
Short name T337
Test name
Test status
Simulation time 8414413335 ps
CPU time 7.09 seconds
Started Mar 05 01:07:17 PM PST 24
Finished Mar 05 01:07:25 PM PST 24
Peak memory 202436 kb
Host smart-332efaac-aa63-4749-b6b3-ff15c19c9110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12522
98676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1252298676
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.2793237772
Short name T341
Test name
Test status
Simulation time 8383396945 ps
CPU time 9.51 seconds
Started Mar 05 01:07:14 PM PST 24
Finished Mar 05 01:07:24 PM PST 24
Peak memory 202404 kb
Host smart-e15f09c4-9a0e-4c76-aaef-c3ba20bead59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27932
37772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.2793237772
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.4141416472
Short name T368
Test name
Test status
Simulation time 8367797926 ps
CPU time 9.83 seconds
Started Mar 05 01:07:16 PM PST 24
Finished Mar 05 01:07:26 PM PST 24
Peak memory 202484 kb
Host smart-8bcffc11-aebe-4beb-9302-6b344acfa845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41414
16472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.4141416472
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2910769846
Short name T522
Test name
Test status
Simulation time 8368647924 ps
CPU time 7.95 seconds
Started Mar 05 01:07:11 PM PST 24
Finished Mar 05 01:07:19 PM PST 24
Peak memory 202372 kb
Host smart-e2a37112-bb7e-46f8-82be-7d209f8e95a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29107
69846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2910769846
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.555737642
Short name T491
Test name
Test status
Simulation time 8371477300 ps
CPU time 7.86 seconds
Started Mar 05 01:07:12 PM PST 24
Finished Mar 05 01:07:20 PM PST 24
Peak memory 202436 kb
Host smart-ef44300e-3110-4aae-b437-3f4fbdea2849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55573
7642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.555737642
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1582087936
Short name T233
Test name
Test status
Simulation time 100732779 ps
CPU time 1.73 seconds
Started Mar 05 01:07:14 PM PST 24
Finished Mar 05 01:07:16 PM PST 24
Peak memory 202424 kb
Host smart-7b13f117-971c-4944-884e-8ec53ccf8fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15820
87936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1582087936
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3176046499
Short name T590
Test name
Test status
Simulation time 8446626892 ps
CPU time 7.35 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:30 PM PST 24
Peak memory 202432 kb
Host smart-4194e380-3a09-42bc-b400-1c7605b66dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
46499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3176046499
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.829989029
Short name T427
Test name
Test status
Simulation time 8423318554 ps
CPU time 7.69 seconds
Started Mar 05 01:07:10 PM PST 24
Finished Mar 05 01:07:18 PM PST 24
Peak memory 202404 kb
Host smart-c85ea0d2-b3b6-4f59-b6f3-5e01d0a55330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82998
9029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.829989029
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.979486409
Short name T252
Test name
Test status
Simulation time 8378636943 ps
CPU time 7.56 seconds
Started Mar 05 01:07:15 PM PST 24
Finished Mar 05 01:07:23 PM PST 24
Peak memory 202508 kb
Host smart-8ee2191c-eae6-498d-8731-551d2f701ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97948
6409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.979486409
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2987868577
Short name T351
Test name
Test status
Simulation time 8380332324 ps
CPU time 7.65 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:30 PM PST 24
Peak memory 202024 kb
Host smart-0e6ed76e-7942-4dce-a542-1dfac08b050c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878
68577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2987868577
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3158671069
Short name T333
Test name
Test status
Simulation time 8399118573 ps
CPU time 8.61 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:31 PM PST 24
Peak memory 201892 kb
Host smart-9d934bbd-4249-424d-9e27-7e91849c1e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31586
71069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3158671069
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.735493075
Short name T125
Test name
Test status
Simulation time 8480732070 ps
CPU time 7.17 seconds
Started Mar 05 01:07:20 PM PST 24
Finished Mar 05 01:07:27 PM PST 24
Peak memory 202356 kb
Host smart-139ccf32-1742-44d9-87bf-a229182554ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73549
3075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.735493075
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3537518015
Short name T325
Test name
Test status
Simulation time 8368689887 ps
CPU time 7 seconds
Started Mar 05 01:07:21 PM PST 24
Finished Mar 05 01:07:28 PM PST 24
Peak memory 202376 kb
Host smart-53880db7-5ab5-44cd-bb88-3d88c69f28b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
18015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3537518015
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1969200090
Short name T296
Test name
Test status
Simulation time 8421499303 ps
CPU time 8.35 seconds
Started Mar 05 01:07:13 PM PST 24
Finished Mar 05 01:07:22 PM PST 24
Peak memory 202480 kb
Host smart-cb79a9f7-2b98-45b1-9a27-422dc8af051c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19692
00090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1969200090
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.610925981
Short name T237
Test name
Test status
Simulation time 43896616 ps
CPU time 1.26 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:32 PM PST 24
Peak memory 202428 kb
Host smart-80f77df5-bf21-46aa-992d-8db825fd72fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61092
5981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.610925981
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3860888757
Short name T260
Test name
Test status
Simulation time 8406447648 ps
CPU time 7.24 seconds
Started Mar 05 01:07:24 PM PST 24
Finished Mar 05 01:07:31 PM PST 24
Peak memory 202484 kb
Host smart-be6f58b2-1f83-4a22-8077-e85da2a009d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38608
88757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3860888757
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2706788243
Short name T632
Test name
Test status
Simulation time 8361991996 ps
CPU time 9.16 seconds
Started Mar 05 01:07:28 PM PST 24
Finished Mar 05 01:07:37 PM PST 24
Peak memory 202372 kb
Host smart-ecb89f20-491a-4909-bbef-efb560c5740e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27067
88243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2706788243
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2986024687
Short name T111
Test name
Test status
Simulation time 8429393044 ps
CPU time 8.2 seconds
Started Mar 05 01:07:15 PM PST 24
Finished Mar 05 01:07:23 PM PST 24
Peak memory 202476 kb
Host smart-99e9a7e9-41c6-44ed-b796-54275811f457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860
24687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2986024687
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1984538723
Short name T461
Test name
Test status
Simulation time 8390828700 ps
CPU time 7.11 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202308 kb
Host smart-6c448a53-0194-49df-8c68-33b750466193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
38723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1984538723
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1076973879
Short name T242
Test name
Test status
Simulation time 8369244084 ps
CPU time 9.12 seconds
Started Mar 05 01:07:25 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202420 kb
Host smart-86d40e82-605e-449a-8ab1-3a7cd064870b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10769
73879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1076973879
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1891756730
Short name T130
Test name
Test status
Simulation time 8447718160 ps
CPU time 8.08 seconds
Started Mar 05 01:07:14 PM PST 24
Finished Mar 05 01:07:23 PM PST 24
Peak memory 202328 kb
Host smart-7ca8bce3-a93e-40fe-a3e0-440bddfcf938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18917
56730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1891756730
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.4163426312
Short name T518
Test name
Test status
Simulation time 8380206731 ps
CPU time 7.57 seconds
Started Mar 05 01:07:17 PM PST 24
Finished Mar 05 01:07:25 PM PST 24
Peak memory 202420 kb
Host smart-1b54c6e8-a0c4-450f-9983-55a436d1367b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41634
26312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.4163426312
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.894220916
Short name T327
Test name
Test status
Simulation time 8365543900 ps
CPU time 7.79 seconds
Started Mar 05 01:07:18 PM PST 24
Finished Mar 05 01:07:28 PM PST 24
Peak memory 202464 kb
Host smart-83f9a5bb-e267-4341-9e98-d2cc98f1098b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89422
0916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.894220916
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.6491060
Short name T414
Test name
Test status
Simulation time 8367778700 ps
CPU time 7.31 seconds
Started Mar 05 01:07:10 PM PST 24
Finished Mar 05 01:07:18 PM PST 24
Peak memory 202468 kb
Host smart-c49c5e20-1eff-4a2c-96d2-6ee240c1e804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64910
60 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.6491060
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3719394691
Short name T2
Test name
Test status
Simulation time 8370997846 ps
CPU time 7.24 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:29 PM PST 24
Peak memory 202484 kb
Host smart-10747cda-5d35-4042-9a05-292fba7a1427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37193
94691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3719394691
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.4293897874
Short name T170
Test name
Test status
Simulation time 114775808 ps
CPU time 1.46 seconds
Started Mar 05 01:07:23 PM PST 24
Finished Mar 05 01:07:25 PM PST 24
Peak memory 202388 kb
Host smart-e5edcd8d-072b-4960-95d8-c2d1895f2f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938
97874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.4293897874
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1772673657
Short name T660
Test name
Test status
Simulation time 8450104430 ps
CPU time 7.45 seconds
Started Mar 05 01:07:31 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 202428 kb
Host smart-59f0e50f-1448-43fb-baa9-5b2a6aa33ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17726
73657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1772673657
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.541465714
Short name T31
Test name
Test status
Simulation time 8413494412 ps
CPU time 9.55 seconds
Started Mar 05 01:07:23 PM PST 24
Finished Mar 05 01:07:33 PM PST 24
Peak memory 202404 kb
Host smart-14c2f101-8d7b-4688-bbf9-7929f4e8a529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54146
5714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.541465714
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.314002211
Short name T335
Test name
Test status
Simulation time 8368406761 ps
CPU time 7.36 seconds
Started Mar 05 01:07:28 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202348 kb
Host smart-8edf1c70-06c4-461b-a855-79520f3f5c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31400
2211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.314002211
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.764507347
Short name T535
Test name
Test status
Simulation time 8446390483 ps
CPU time 7.28 seconds
Started Mar 05 01:07:23 PM PST 24
Finished Mar 05 01:07:31 PM PST 24
Peak memory 202424 kb
Host smart-7b687592-310d-4bc9-b3be-5c291b3e1202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76450
7347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.764507347
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3392485138
Short name T317
Test name
Test status
Simulation time 8403538667 ps
CPU time 10.19 seconds
Started Mar 05 01:07:25 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202348 kb
Host smart-91796afa-8d44-41ef-9aea-7edf53926b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33924
85138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3392485138
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2685541751
Short name T294
Test name
Test status
Simulation time 8378037068 ps
CPU time 9.5 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202308 kb
Host smart-26113cd7-d450-4572-8cdb-a7cb6b31548b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26855
41751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2685541751
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.796045752
Short name T331
Test name
Test status
Simulation time 8461227765 ps
CPU time 6.99 seconds
Started Mar 05 01:07:43 PM PST 24
Finished Mar 05 01:07:50 PM PST 24
Peak memory 202300 kb
Host smart-4528a069-24d6-4d56-8956-72a2a0edcdea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79604
5752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.796045752
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.3925782683
Short name T433
Test name
Test status
Simulation time 8387670383 ps
CPU time 7.5 seconds
Started Mar 05 01:07:23 PM PST 24
Finished Mar 05 01:07:31 PM PST 24
Peak memory 202448 kb
Host smart-efc6e639-1cb5-4f68-9e1a-15551134eb33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39257
82683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.3925782683
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3010453008
Short name T523
Test name
Test status
Simulation time 8363273004 ps
CPU time 7.59 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:30 PM PST 24
Peak memory 202588 kb
Host smart-d3b07dc5-96cd-407b-9326-75ca73f5ffd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30104
53008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3010453008
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.796514431
Short name T289
Test name
Test status
Simulation time 8371987388 ps
CPU time 6.93 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:29 PM PST 24
Peak memory 202456 kb
Host smart-ba223385-e39b-40af-ba93-5c8d4d4b2ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79651
4431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.796514431
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.4251502800
Short name T580
Test name
Test status
Simulation time 8371365731 ps
CPU time 9.59 seconds
Started Mar 05 01:05:52 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 202448 kb
Host smart-67c4a549-4602-4f10-a4a8-17c425b9da89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42515
02800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.4251502800
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2540357337
Short name T412
Test name
Test status
Simulation time 258039748 ps
CPU time 1.95 seconds
Started Mar 05 01:05:54 PM PST 24
Finished Mar 05 01:05:56 PM PST 24
Peak memory 202376 kb
Host smart-b6834101-67da-4db9-83c5-02b7a4861f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25403
57337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2540357337
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.539829736
Short name T624
Test name
Test status
Simulation time 8452624096 ps
CPU time 7.35 seconds
Started Mar 05 01:05:54 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 202416 kb
Host smart-5f98c79c-9274-4427-95f8-446941a6daf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53982
9736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.539829736
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.594200971
Short name T326
Test name
Test status
Simulation time 8407808986 ps
CPU time 7.44 seconds
Started Mar 05 01:05:55 PM PST 24
Finished Mar 05 01:06:03 PM PST 24
Peak memory 202380 kb
Host smart-0ce61e8a-2643-4394-91cf-3729d72a8d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59420
0971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.594200971
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1181974197
Short name T393
Test name
Test status
Simulation time 8369263524 ps
CPU time 9.67 seconds
Started Mar 05 01:05:53 PM PST 24
Finished Mar 05 01:06:04 PM PST 24
Peak memory 202408 kb
Host smart-b0be1d4f-5e62-46a6-82a3-b41e039bd4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11819
74197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1181974197
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2726519805
Short name T531
Test name
Test status
Simulation time 8412822398 ps
CPU time 7.42 seconds
Started Mar 05 01:06:01 PM PST 24
Finished Mar 05 01:06:08 PM PST 24
Peak memory 202436 kb
Host smart-0a08c095-2862-4ddd-bfff-2df5a9129bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27265
19805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2726519805
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.230444690
Short name T312
Test name
Test status
Simulation time 8397538009 ps
CPU time 7.38 seconds
Started Mar 05 01:05:58 PM PST 24
Finished Mar 05 01:06:06 PM PST 24
Peak memory 202420 kb
Host smart-b9241269-ba96-4144-8f18-ba3650ca97e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23044
4690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.230444690
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3370290224
Short name T443
Test name
Test status
Simulation time 8404802942 ps
CPU time 7.84 seconds
Started Mar 05 01:05:59 PM PST 24
Finished Mar 05 01:06:07 PM PST 24
Peak memory 202424 kb
Host smart-489c9d4e-cfa0-4f4a-8cc4-0d8ead46bffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33702
90224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3370290224
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.787947069
Short name T454
Test name
Test status
Simulation time 8408723608 ps
CPU time 7.65 seconds
Started Mar 05 01:05:56 PM PST 24
Finished Mar 05 01:06:04 PM PST 24
Peak memory 202252 kb
Host smart-3eab32ab-d335-4855-b447-89bde5a465e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78794
7069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.787947069
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.2090372174
Short name T489
Test name
Test status
Simulation time 8407541750 ps
CPU time 8.84 seconds
Started Mar 05 01:05:54 PM PST 24
Finished Mar 05 01:06:03 PM PST 24
Peak memory 202404 kb
Host smart-531e25c3-ebdc-4231-95e6-d1d2d7c4761e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903
72174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.2090372174
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2868485045
Short name T48
Test name
Test status
Simulation time 276775388 ps
CPU time 1.05 seconds
Started Mar 05 01:05:52 PM PST 24
Finished Mar 05 01:05:53 PM PST 24
Peak memory 217092 kb
Host smart-8408a17c-9a9b-4760-a98a-85ae0eb85b37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2868485045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2868485045
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_smoke.878600409
Short name T384
Test name
Test status
Simulation time 8368563309 ps
CPU time 8.39 seconds
Started Mar 05 01:05:55 PM PST 24
Finished Mar 05 01:06:03 PM PST 24
Peak memory 202396 kb
Host smart-7e778908-2dd1-4bd2-9ab0-2611c55acb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87860
0409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.878600409
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2402111262
Short name T451
Test name
Test status
Simulation time 8367763059 ps
CPU time 7.86 seconds
Started Mar 05 01:07:23 PM PST 24
Finished Mar 05 01:07:32 PM PST 24
Peak memory 202440 kb
Host smart-d969b656-85da-458f-8dce-e545c257d5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24021
11262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2402111262
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.4278331450
Short name T136
Test name
Test status
Simulation time 8374022698 ps
CPU time 7.69 seconds
Started Mar 05 01:07:25 PM PST 24
Finished Mar 05 01:07:34 PM PST 24
Peak memory 202456 kb
Host smart-6aa55041-fd67-4dde-9efc-73b9a1abec58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42783
31450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.4278331450
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1945476052
Short name T587
Test name
Test status
Simulation time 8411476412 ps
CPU time 9.88 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:32 PM PST 24
Peak memory 202372 kb
Host smart-9889597a-5e51-4f43-9783-e297767e42d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454
76052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1945476052
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1666900342
Short name T304
Test name
Test status
Simulation time 8362556090 ps
CPU time 7.51 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202428 kb
Host smart-ba246671-1f3c-47c8-91fe-bb9a9a355f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16669
00342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1666900342
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3204679329
Short name T99
Test name
Test status
Simulation time 8387669811 ps
CPU time 7.05 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:34 PM PST 24
Peak memory 202348 kb
Host smart-d2d51af9-6108-4744-8da5-a3d650093181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32046
79329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3204679329
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3357029863
Short name T382
Test name
Test status
Simulation time 8411725102 ps
CPU time 6.99 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:40 PM PST 24
Peak memory 202428 kb
Host smart-e62052eb-59ff-4be6-a00c-e8c04721ee86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33570
29863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3357029863
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1928809315
Short name T630
Test name
Test status
Simulation time 8418522549 ps
CPU time 8.71 seconds
Started Mar 05 01:07:28 PM PST 24
Finished Mar 05 01:07:38 PM PST 24
Peak memory 202316 kb
Host smart-d24b341b-56c4-45ea-b7ab-16b7bd2580ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19288
09315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1928809315
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.4160380713
Short name T281
Test name
Test status
Simulation time 8417558065 ps
CPU time 7.68 seconds
Started Mar 05 01:07:24 PM PST 24
Finished Mar 05 01:07:32 PM PST 24
Peak memory 202436 kb
Host smart-713045d2-fe48-4ee4-ad15-20d9af19999e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41603
80713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.4160380713
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3648877063
Short name T180
Test name
Test status
Simulation time 8387871041 ps
CPU time 7.51 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202480 kb
Host smart-5904f65d-a3d6-4a8d-9a23-d6efd1c6f02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36488
77063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3648877063
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.530118751
Short name T492
Test name
Test status
Simulation time 8362077413 ps
CPU time 7.49 seconds
Started Mar 05 01:07:34 PM PST 24
Finished Mar 05 01:07:42 PM PST 24
Peak memory 202292 kb
Host smart-a82ac2aa-b05e-429f-b0f3-33892226d9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53011
8751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.530118751
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2328914099
Short name T303
Test name
Test status
Simulation time 8370458705 ps
CPU time 9.72 seconds
Started Mar 05 01:07:23 PM PST 24
Finished Mar 05 01:07:33 PM PST 24
Peak memory 202432 kb
Host smart-4d2d500b-3ac0-4a06-ac7c-79d6dab27474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23289
14099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2328914099
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3077782928
Short name T560
Test name
Test status
Simulation time 8371489077 ps
CPU time 7.92 seconds
Started Mar 05 01:07:29 PM PST 24
Finished Mar 05 01:07:38 PM PST 24
Peak memory 202380 kb
Host smart-8d9e5fa9-2d76-48a6-babb-038dfc4e3d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30777
82928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3077782928
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.703348282
Short name T601
Test name
Test status
Simulation time 226393919 ps
CPU time 1.84 seconds
Started Mar 05 01:07:23 PM PST 24
Finished Mar 05 01:07:25 PM PST 24
Peak memory 202400 kb
Host smart-9f1f2fc6-82f0-4bce-91d6-60690736f3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70334
8282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.703348282
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1372363709
Short name T19
Test name
Test status
Simulation time 8521512526 ps
CPU time 7.43 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202412 kb
Host smart-6b160a18-f0f5-4a80-b76e-7ffcf71be3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13723
63709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1372363709
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1903671210
Short name T330
Test name
Test status
Simulation time 8405545960 ps
CPU time 7.64 seconds
Started Mar 05 01:07:27 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202468 kb
Host smart-180488fe-6fa2-47bf-ae17-263c06585680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19036
71210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1903671210
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4292724060
Short name T472
Test name
Test status
Simulation time 8366558424 ps
CPU time 8.46 seconds
Started Mar 05 01:07:34 PM PST 24
Finished Mar 05 01:07:42 PM PST 24
Peak memory 202312 kb
Host smart-bb48f604-2a6a-4a24-ac6a-1eff91c7393e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42927
24060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4292724060
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1794750463
Short name T602
Test name
Test status
Simulation time 8427382163 ps
CPU time 7.35 seconds
Started Mar 05 01:07:22 PM PST 24
Finished Mar 05 01:07:30 PM PST 24
Peak memory 202372 kb
Host smart-43b88275-5485-4318-ac3e-5bfeee91d3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17947
50463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1794750463
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.4120512472
Short name T305
Test name
Test status
Simulation time 8392453801 ps
CPU time 7.24 seconds
Started Mar 05 01:07:23 PM PST 24
Finished Mar 05 01:07:31 PM PST 24
Peak memory 202404 kb
Host smart-13badb6c-d29f-4cdf-81e5-4f8892d02055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41205
12472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.4120512472
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.859969857
Short name T193
Test name
Test status
Simulation time 8416650793 ps
CPU time 7.72 seconds
Started Mar 05 01:07:25 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202460 kb
Host smart-8bfb47e2-7938-45dc-ab64-88df96ffa3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85996
9857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.859969857
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3524999206
Short name T245
Test name
Test status
Simulation time 8390334811 ps
CPU time 8.91 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:40 PM PST 24
Peak memory 202416 kb
Host smart-3442dd69-a6be-4627-8f29-a0d766a9dab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35249
99206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3524999206
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3384604714
Short name T637
Test name
Test status
Simulation time 8359547797 ps
CPU time 7.77 seconds
Started Mar 05 01:07:24 PM PST 24
Finished Mar 05 01:07:32 PM PST 24
Peak memory 202472 kb
Host smart-58ca63eb-b448-4776-8694-2bd6bcbbe01f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33846
04714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3384604714
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1363319779
Short name T314
Test name
Test status
Simulation time 8372896053 ps
CPU time 8.08 seconds
Started Mar 05 01:07:25 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202480 kb
Host smart-cadb740d-8ca5-460b-9e7b-e7f94680412a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13633
19779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1363319779
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.611243329
Short name T306
Test name
Test status
Simulation time 8368946432 ps
CPU time 7.19 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:38 PM PST 24
Peak memory 202380 kb
Host smart-31755468-0eec-4089-87bd-af88270c07b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61124
3329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.611243329
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3736810435
Short name T185
Test name
Test status
Simulation time 179862745 ps
CPU time 1.66 seconds
Started Mar 05 01:07:32 PM PST 24
Finished Mar 05 01:07:34 PM PST 24
Peak memory 202412 kb
Host smart-311d535c-880b-4880-97a3-7684936d062b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37368
10435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3736810435
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2453015778
Short name T616
Test name
Test status
Simulation time 8398650709 ps
CPU time 7.74 seconds
Started Mar 05 01:07:25 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202396 kb
Host smart-13a02d39-2f7c-4efd-b83c-edd1c429507a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24530
15778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2453015778
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1937388569
Short name T336
Test name
Test status
Simulation time 8418898362 ps
CPU time 7.56 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202428 kb
Host smart-b454dd9e-915d-46d4-bffc-d6386c43e8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19373
88569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1937388569
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.301340690
Short name T628
Test name
Test status
Simulation time 8365440832 ps
CPU time 7.61 seconds
Started Mar 05 01:07:28 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202304 kb
Host smart-22ded525-1ad2-4f04-8f24-ee20733a3999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30134
0690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.301340690
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.3074512957
Short name T108
Test name
Test status
Simulation time 8411295693 ps
CPU time 7.99 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:41 PM PST 24
Peak memory 202468 kb
Host smart-806d03f4-2bee-4677-a101-cdf69502f989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30745
12957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3074512957
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.382976994
Short name T410
Test name
Test status
Simulation time 8380769966 ps
CPU time 7.94 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:41 PM PST 24
Peak memory 202416 kb
Host smart-bf2bf8ca-e812-421f-ac0e-1e7760566a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38297
6994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.382976994
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3592566568
Short name T468
Test name
Test status
Simulation time 8433612118 ps
CPU time 7.79 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 202428 kb
Host smart-f5641bba-addb-48c7-9829-c69cca1813e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35925
66568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3592566568
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3021794893
Short name T571
Test name
Test status
Simulation time 8384054012 ps
CPU time 7.32 seconds
Started Mar 05 01:07:25 PM PST 24
Finished Mar 05 01:07:33 PM PST 24
Peak memory 202552 kb
Host smart-a17d2abb-30ef-4db7-86d2-b00c6a7eb093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30217
94893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3021794893
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2261509809
Short name T604
Test name
Test status
Simulation time 8362503676 ps
CPU time 7.99 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 202456 kb
Host smart-9469b308-1161-41ba-aa84-e72aad1e1716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22615
09809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2261509809
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2206173967
Short name T429
Test name
Test status
Simulation time 8373694957 ps
CPU time 7.86 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 202428 kb
Host smart-f0a20fd7-4f43-4f4e-a112-bfae71b2c89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22061
73967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2206173967
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.323970002
Short name T379
Test name
Test status
Simulation time 8371539790 ps
CPU time 9.55 seconds
Started Mar 05 01:07:29 PM PST 24
Finished Mar 05 01:07:40 PM PST 24
Peak memory 202412 kb
Host smart-129b8747-5021-4859-88ee-ddf01458b2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32397
0002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.323970002
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.547920999
Short name T420
Test name
Test status
Simulation time 83970377 ps
CPU time 1.08 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:34 PM PST 24
Peak memory 202492 kb
Host smart-84dafd44-fd29-4f23-8ce0-e4d1c05a37cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54792
0999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.547920999
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.197836144
Short name T360
Test name
Test status
Simulation time 8449160154 ps
CPU time 7.34 seconds
Started Mar 05 01:07:28 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202452 kb
Host smart-667fbdd1-e7e6-42eb-9233-a9c36d22a4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19783
6144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.197836144
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3276036627
Short name T389
Test name
Test status
Simulation time 8418327215 ps
CPU time 6.99 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:40 PM PST 24
Peak memory 202420 kb
Host smart-a2b296f0-8ccb-45be-9802-f5fe485464cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32760
36627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3276036627
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2584380749
Short name T310
Test name
Test status
Simulation time 8364638874 ps
CPU time 8.01 seconds
Started Mar 05 01:07:32 PM PST 24
Finished Mar 05 01:07:41 PM PST 24
Peak memory 202428 kb
Host smart-64fd7bba-f3af-4b86-8345-16a1994be355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25843
80749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2584380749
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.267586170
Short name T105
Test name
Test status
Simulation time 8417015234 ps
CPU time 8.53 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:42 PM PST 24
Peak memory 202416 kb
Host smart-47308904-2a96-4936-82b1-a532fdfff8df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26758
6170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.267586170
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2181195072
Short name T362
Test name
Test status
Simulation time 8376974743 ps
CPU time 7.67 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:41 PM PST 24
Peak memory 202428 kb
Host smart-be2f4735-e45d-4a3d-a472-7211e6a7397a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21811
95072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2181195072
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2388254576
Short name T504
Test name
Test status
Simulation time 8403187851 ps
CPU time 7.15 seconds
Started Mar 05 01:07:34 PM PST 24
Finished Mar 05 01:07:42 PM PST 24
Peak memory 202308 kb
Host smart-4af3b709-570d-45c8-87a6-e07eebe6425a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23882
54576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2388254576
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3674076269
Short name T119
Test name
Test status
Simulation time 8422591974 ps
CPU time 7.61 seconds
Started Mar 05 01:07:32 PM PST 24
Finished Mar 05 01:07:40 PM PST 24
Peak memory 202436 kb
Host smart-730a1a44-fc72-46cd-bef8-9e4c500c5bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
76269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3674076269
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.924049828
Short name T542
Test name
Test status
Simulation time 8416617279 ps
CPU time 7.85 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202464 kb
Host smart-346473b0-2d6c-4294-b583-e46c8e94eae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92404
9828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.924049828
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2827597187
Short name T29
Test name
Test status
Simulation time 8363772061 ps
CPU time 7.64 seconds
Started Mar 05 01:07:32 PM PST 24
Finished Mar 05 01:07:40 PM PST 24
Peak memory 202384 kb
Host smart-664532ba-576a-4d71-ad8c-be517bb96376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28275
97187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2827597187
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.44659419
Short name T28
Test name
Test status
Simulation time 8372834896 ps
CPU time 7.86 seconds
Started Mar 05 01:07:29 PM PST 24
Finished Mar 05 01:07:38 PM PST 24
Peak memory 202404 kb
Host smart-386de9a5-d8ef-4d14-a917-87325993b2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44659
419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.44659419
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3331426142
Short name T279
Test name
Test status
Simulation time 8373552545 ps
CPU time 7.3 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202484 kb
Host smart-8436fde9-3b8c-4e37-80f5-7901f2629f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33314
26142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3331426142
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2245841816
Short name T181
Test name
Test status
Simulation time 73841997 ps
CPU time 1.82 seconds
Started Mar 05 01:07:37 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 202256 kb
Host smart-80cb5d83-6b32-4085-aff2-4ff03af4654b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22458
41816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2245841816
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1691237629
Short name T485
Test name
Test status
Simulation time 8431513672 ps
CPU time 7.93 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:38 PM PST 24
Peak memory 202324 kb
Host smart-46aec370-b61b-430a-bad9-02b9b0740653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16912
37629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1691237629
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2125127836
Short name T591
Test name
Test status
Simulation time 8407820975 ps
CPU time 9.24 seconds
Started Mar 05 01:07:34 PM PST 24
Finished Mar 05 01:07:44 PM PST 24
Peak memory 202480 kb
Host smart-4e8c0ee2-3b22-463a-80f9-c250214615e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21251
27836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2125127836
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4178158499
Short name T635
Test name
Test status
Simulation time 8362686295 ps
CPU time 7.53 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 201900 kb
Host smart-4b406479-486e-4a21-88ae-00cda358c829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41781
58499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4178158499
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1512447623
Short name T94
Test name
Test status
Simulation time 8378241393 ps
CPU time 9.03 seconds
Started Mar 05 01:07:32 PM PST 24
Finished Mar 05 01:07:41 PM PST 24
Peak memory 202272 kb
Host smart-ba200233-7197-4687-a873-6b9b13a8a3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15124
47623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1512447623
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3930340127
Short name T442
Test name
Test status
Simulation time 8400516443 ps
CPU time 7.45 seconds
Started Mar 05 01:07:36 PM PST 24
Finished Mar 05 01:07:44 PM PST 24
Peak memory 202260 kb
Host smart-26cafdfe-a92b-4837-b4f7-8e372a9516ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39303
40127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3930340127
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1291603963
Short name T558
Test name
Test status
Simulation time 8396291705 ps
CPU time 8.02 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:41 PM PST 24
Peak memory 202420 kb
Host smart-cda4e14f-f8a8-4e51-816f-79377b820ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12916
03963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1291603963
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4155391582
Short name T586
Test name
Test status
Simulation time 8378226777 ps
CPU time 8.6 seconds
Started Mar 05 01:07:26 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202484 kb
Host smart-2a911eb8-1094-405c-93e5-6a5a7c59e3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553
91582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4155391582
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.358016521
Short name T247
Test name
Test status
Simulation time 8409675019 ps
CPU time 8.36 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 202300 kb
Host smart-c8e6c2f4-173a-4b0a-97a8-e89da28d7e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35801
6521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.358016521
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3223068315
Short name T503
Test name
Test status
Simulation time 8377316729 ps
CPU time 7.07 seconds
Started Mar 05 01:07:27 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202308 kb
Host smart-0d274c40-dc3b-4b9e-84a5-69120c868b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32230
68315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3223068315
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1705737833
Short name T299
Test name
Test status
Simulation time 8367074488 ps
CPU time 7.78 seconds
Started Mar 05 01:07:30 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 202324 kb
Host smart-2468608f-dc1b-49e6-b07d-ae2cc697ba9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17057
37833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1705737833
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.717110148
Short name T413
Test name
Test status
Simulation time 8374956064 ps
CPU time 9.88 seconds
Started Mar 05 01:07:36 PM PST 24
Finished Mar 05 01:07:46 PM PST 24
Peak memory 202320 kb
Host smart-f834f811-6000-4971-adc0-5fa30020e611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71711
0148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.717110148
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1848093641
Short name T276
Test name
Test status
Simulation time 310983237 ps
CPU time 2.23 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:35 PM PST 24
Peak memory 202404 kb
Host smart-10f1663e-e85b-4faf-906c-85fb4dd8943e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18480
93641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1848093641
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3072734921
Short name T127
Test name
Test status
Simulation time 8399717250 ps
CPU time 8.6 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:42 PM PST 24
Peak memory 202484 kb
Host smart-f04d6cee-75a2-4126-a423-941be85280a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30727
34921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3072734921
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2770648271
Short name T574
Test name
Test status
Simulation time 8409472240 ps
CPU time 7.29 seconds
Started Mar 05 01:07:36 PM PST 24
Finished Mar 05 01:07:44 PM PST 24
Peak memory 202252 kb
Host smart-0a2b687c-75ee-49e9-bfa7-e0555f872cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
48271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2770648271
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.398585766
Short name T437
Test name
Test status
Simulation time 8450862578 ps
CPU time 7.26 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:53 PM PST 24
Peak memory 202068 kb
Host smart-de682e42-6a10-462f-a79a-4e2fcae9c9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39858
5766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.398585766
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.378313425
Short name T406
Test name
Test status
Simulation time 8382987630 ps
CPU time 7.59 seconds
Started Mar 05 01:07:40 PM PST 24
Finished Mar 05 01:07:48 PM PST 24
Peak memory 202316 kb
Host smart-c46bac96-f56e-41d9-b2c8-5c2a87670d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37831
3425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.378313425
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.123230610
Short name T633
Test name
Test status
Simulation time 8383124260 ps
CPU time 9.12 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:55 PM PST 24
Peak memory 202412 kb
Host smart-a34bab1b-f959-4068-836d-fc8a82052c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
0610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.123230610
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3091796609
Short name T656
Test name
Test status
Simulation time 8385454605 ps
CPU time 7.67 seconds
Started Mar 05 01:07:37 PM PST 24
Finished Mar 05 01:07:45 PM PST 24
Peak memory 202428 kb
Host smart-35cc0dba-728c-44dc-b6e8-268bc937f335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30917
96609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3091796609
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.1665209355
Short name T363
Test name
Test status
Simulation time 8379342808 ps
CPU time 7.03 seconds
Started Mar 05 01:07:32 PM PST 24
Finished Mar 05 01:07:39 PM PST 24
Peak memory 202520 kb
Host smart-7ee75aa7-3836-40b4-beca-951f9b1207b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16652
09355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.1665209355
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3515594577
Short name T550
Test name
Test status
Simulation time 8361286166 ps
CPU time 8.36 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202284 kb
Host smart-45b83493-19b8-4ccb-a32c-b3549ef3a8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35155
94577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3515594577
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3702599200
Short name T495
Test name
Test status
Simulation time 8372537010 ps
CPU time 7.69 seconds
Started Mar 05 01:07:35 PM PST 24
Finished Mar 05 01:07:43 PM PST 24
Peak memory 202444 kb
Host smart-ad82da89-4147-4078-9bf8-19fe480bc6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37025
99200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3702599200
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3149521366
Short name T641
Test name
Test status
Simulation time 8463183548 ps
CPU time 8.54 seconds
Started Mar 05 01:07:39 PM PST 24
Finished Mar 05 01:07:47 PM PST 24
Peak memory 202436 kb
Host smart-dc180907-3736-4d20-9ab4-d95556ed3661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31495
21366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3149521366
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2425162264
Short name T608
Test name
Test status
Simulation time 126829503 ps
CPU time 1.58 seconds
Started Mar 05 01:07:34 PM PST 24
Finished Mar 05 01:07:36 PM PST 24
Peak memory 202436 kb
Host smart-11b2f3f1-513b-42d1-aa3a-6f9c344f5d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24251
62264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2425162264
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2554109944
Short name T405
Test name
Test status
Simulation time 8416846588 ps
CPU time 8.46 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:41 PM PST 24
Peak memory 202484 kb
Host smart-8f5ab9eb-3131-4863-a5e0-a9838086e330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25541
09944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2554109944
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1186763696
Short name T358
Test name
Test status
Simulation time 8367507060 ps
CPU time 8.47 seconds
Started Mar 05 01:07:43 PM PST 24
Finished Mar 05 01:07:52 PM PST 24
Peak memory 202412 kb
Host smart-08a908b4-7b8c-4730-8155-1321e9a47391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11867
63696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1186763696
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.385689661
Short name T109
Test name
Test status
Simulation time 8428020874 ps
CPU time 7.08 seconds
Started Mar 05 01:07:33 PM PST 24
Finished Mar 05 01:07:40 PM PST 24
Peak memory 202424 kb
Host smart-81bbdf04-6e77-471f-9c3b-8593a5b3a32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38568
9661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.385689661
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2378285900
Short name T460
Test name
Test status
Simulation time 8375581574 ps
CPU time 7.45 seconds
Started Mar 05 01:07:38 PM PST 24
Finished Mar 05 01:07:46 PM PST 24
Peak memory 202420 kb
Host smart-909a4f55-f029-4990-96d0-503012cf8f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23782
85900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2378285900
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1731849461
Short name T449
Test name
Test status
Simulation time 8434431411 ps
CPU time 7.41 seconds
Started Mar 05 01:07:34 PM PST 24
Finished Mar 05 01:07:41 PM PST 24
Peak memory 202428 kb
Host smart-f8b8c9f4-87d5-4a1b-93ad-305cb0927e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17318
49461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1731849461
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1425874888
Short name T246
Test name
Test status
Simulation time 8406523780 ps
CPU time 7.54 seconds
Started Mar 05 01:07:38 PM PST 24
Finished Mar 05 01:07:45 PM PST 24
Peak memory 202480 kb
Host smart-7e017704-52dc-4f9b-987c-cb67d84edc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14258
74888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1425874888
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1078013073
Short name T539
Test name
Test status
Simulation time 8359247705 ps
CPU time 7.52 seconds
Started Mar 05 01:07:34 PM PST 24
Finished Mar 05 01:07:42 PM PST 24
Peak memory 202460 kb
Host smart-8da504fb-6074-4a3d-8870-9516a28792e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10780
13073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1078013073
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2937766445
Short name T315
Test name
Test status
Simulation time 8371882640 ps
CPU time 8.38 seconds
Started Mar 05 01:07:35 PM PST 24
Finished Mar 05 01:07:43 PM PST 24
Peak memory 202396 kb
Host smart-6a2bb898-9484-4364-b3c3-9fcfbd373011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29377
66445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2937766445
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2082119220
Short name T300
Test name
Test status
Simulation time 8367760463 ps
CPU time 9.5 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202412 kb
Host smart-57488e3e-1545-4f2f-87ca-39fac6928763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20821
19220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2082119220
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2997693742
Short name T537
Test name
Test status
Simulation time 215430245 ps
CPU time 2.03 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:48 PM PST 24
Peak memory 202412 kb
Host smart-2891d477-6167-41c0-a523-6d124b185feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29976
93742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2997693742
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.4255323707
Short name T129
Test name
Test status
Simulation time 8436321952 ps
CPU time 7.69 seconds
Started Mar 05 01:07:37 PM PST 24
Finished Mar 05 01:07:45 PM PST 24
Peak memory 202484 kb
Host smart-cd242a7c-6371-494e-8e29-e7e9cc4d1608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42553
23707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.4255323707
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2247456998
Short name T70
Test name
Test status
Simulation time 8407535382 ps
CPU time 8.58 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:55 PM PST 24
Peak memory 202272 kb
Host smart-b344155e-3e2c-4dd3-9f1c-d42c494ba734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22474
56998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2247456998
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2020336364
Short name T285
Test name
Test status
Simulation time 8365059623 ps
CPU time 8.29 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:55 PM PST 24
Peak memory 202412 kb
Host smart-3eb65247-5c54-4760-9a79-8424684210f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20203
36364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2020336364
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.4128219734
Short name T164
Test name
Test status
Simulation time 8407375191 ps
CPU time 7.48 seconds
Started Mar 05 01:07:38 PM PST 24
Finished Mar 05 01:07:45 PM PST 24
Peak memory 202476 kb
Host smart-1e127c6d-8422-4337-89de-040d1b504e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41282
19734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.4128219734
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2772242221
Short name T556
Test name
Test status
Simulation time 8402657667 ps
CPU time 7.4 seconds
Started Mar 05 01:07:38 PM PST 24
Finished Mar 05 01:07:46 PM PST 24
Peak memory 202432 kb
Host smart-e86dd7bd-b5c1-432c-afad-ef6810df0cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27722
42221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2772242221
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2016966775
Short name T120
Test name
Test status
Simulation time 8501800698 ps
CPU time 9.33 seconds
Started Mar 05 01:07:40 PM PST 24
Finished Mar 05 01:07:49 PM PST 24
Peak memory 202484 kb
Host smart-f51f8349-7b7d-4299-9037-86a77b7e7345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20169
66775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2016966775
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.201185811
Short name T471
Test name
Test status
Simulation time 8368660839 ps
CPU time 7.81 seconds
Started Mar 05 01:07:40 PM PST 24
Finished Mar 05 01:07:48 PM PST 24
Peak memory 202324 kb
Host smart-031f4503-2511-44c8-8890-1dfc20bcfe96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20118
5811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.201185811
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1305083879
Short name T564
Test name
Test status
Simulation time 8357690657 ps
CPU time 7.52 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:53 PM PST 24
Peak memory 202440 kb
Host smart-9c94e680-f2e2-4075-9c15-39d91bb6085c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13050
83879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1305083879
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.843664719
Short name T499
Test name
Test status
Simulation time 8375340615 ps
CPU time 8.68 seconds
Started Mar 05 01:07:39 PM PST 24
Finished Mar 05 01:07:48 PM PST 24
Peak memory 202312 kb
Host smart-05b0c520-29f1-49f0-acf5-c671c809acd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84366
4719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.843664719
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.740779570
Short name T36
Test name
Test status
Simulation time 8368333831 ps
CPU time 7.38 seconds
Started Mar 05 01:07:38 PM PST 24
Finished Mar 05 01:07:45 PM PST 24
Peak memory 202424 kb
Host smart-036aff9e-f099-4681-960e-5af0483fec3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74077
9570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.740779570
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3776948655
Short name T469
Test name
Test status
Simulation time 159477190 ps
CPU time 1.77 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:47 PM PST 24
Peak memory 202472 kb
Host smart-bbd11c68-0f2d-4b1a-923b-a6ebd8041682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37769
48655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3776948655
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.239158012
Short name T113
Test name
Test status
Simulation time 8444288788 ps
CPU time 7.04 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:53 PM PST 24
Peak memory 202404 kb
Host smart-cad5b9c4-e3b3-495f-a814-320c1527d257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23915
8012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.239158012
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1718702477
Short name T629
Test name
Test status
Simulation time 8407323908 ps
CPU time 8.82 seconds
Started Mar 05 01:07:43 PM PST 24
Finished Mar 05 01:07:52 PM PST 24
Peak memory 202484 kb
Host smart-e4079c2b-9489-497c-a77b-a29ce8cc5450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17187
02477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1718702477
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1144453229
Short name T467
Test name
Test status
Simulation time 8371110404 ps
CPU time 9.86 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:56 PM PST 24
Peak memory 202376 kb
Host smart-6cb93992-2c93-408d-87c0-a9c7101e1367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11444
53229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1144453229
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2432164354
Short name T631
Test name
Test status
Simulation time 8430911804 ps
CPU time 7.32 seconds
Started Mar 05 01:07:40 PM PST 24
Finished Mar 05 01:07:47 PM PST 24
Peak memory 202420 kb
Host smart-9c82dad4-732f-441f-bb09-a6805fc70433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24321
64354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2432164354
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2832563075
Short name T190
Test name
Test status
Simulation time 8380960318 ps
CPU time 7.81 seconds
Started Mar 05 01:07:43 PM PST 24
Finished Mar 05 01:07:51 PM PST 24
Peak memory 202424 kb
Host smart-728974bc-6e2b-438b-8c6f-768de75d48d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28325
63075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2832563075
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2445678918
Short name T445
Test name
Test status
Simulation time 8437200578 ps
CPU time 8.78 seconds
Started Mar 05 01:07:39 PM PST 24
Finished Mar 05 01:07:48 PM PST 24
Peak memory 202436 kb
Host smart-3b68f022-3e95-46b9-bb88-5aee6af3d275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24456
78918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2445678918
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.4151007290
Short name T511
Test name
Test status
Simulation time 8401364469 ps
CPU time 7.48 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:51 PM PST 24
Peak memory 202360 kb
Host smart-764fee36-de42-48e4-b538-2e6ea38f90eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41510
07290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.4151007290
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3701335743
Short name T186
Test name
Test status
Simulation time 8359382917 ps
CPU time 7.5 seconds
Started Mar 05 01:07:38 PM PST 24
Finished Mar 05 01:07:46 PM PST 24
Peak memory 201852 kb
Host smart-c1a57acc-e331-4158-8368-342e32a3a449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37013
35743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3701335743
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3956921566
Short name T171
Test name
Test status
Simulation time 8369945739 ps
CPU time 7.83 seconds
Started Mar 05 01:07:40 PM PST 24
Finished Mar 05 01:07:48 PM PST 24
Peak memory 202476 kb
Host smart-57a0eddf-ab1f-4303-a36b-ad5e41799dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39569
21566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3956921566
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1731208267
Short name T578
Test name
Test status
Simulation time 8369627520 ps
CPU time 7.39 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:53 PM PST 24
Peak memory 202408 kb
Host smart-ffbfd89a-16f3-41bd-94db-ed3658b6e9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17312
08267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1731208267
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.357162553
Short name T544
Test name
Test status
Simulation time 108950728 ps
CPU time 1.35 seconds
Started Mar 05 01:07:47 PM PST 24
Finished Mar 05 01:07:48 PM PST 24
Peak memory 202404 kb
Host smart-19b8798b-ddf0-4fc3-8766-5eb387f446e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35716
2553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.357162553
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.595658152
Short name T618
Test name
Test status
Simulation time 8451800919 ps
CPU time 7.2 seconds
Started Mar 05 01:07:43 PM PST 24
Finished Mar 05 01:07:50 PM PST 24
Peak memory 202420 kb
Host smart-2b0f4d6d-f913-40d4-b4e2-1c370686c529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59565
8152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.595658152
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.317217403
Short name T370
Test name
Test status
Simulation time 8414142013 ps
CPU time 7.59 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:53 PM PST 24
Peak memory 202404 kb
Host smart-174cf051-1123-4183-9df9-0be9fc331906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31721
7403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.317217403
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.68726120
Short name T238
Test name
Test status
Simulation time 8385738152 ps
CPU time 7.4 seconds
Started Mar 05 01:07:50 PM PST 24
Finished Mar 05 01:07:58 PM PST 24
Peak memory 202232 kb
Host smart-a8677280-eb30-4d61-ac71-d923e067cbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68726
120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.68726120
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2756321017
Short name T13
Test name
Test status
Simulation time 8453025226 ps
CPU time 8.01 seconds
Started Mar 05 01:07:42 PM PST 24
Finished Mar 05 01:07:50 PM PST 24
Peak memory 202420 kb
Host smart-c4e7e05d-ce68-4c7c-abc8-4a7d1ae2206c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563
21017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2756321017
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2940465061
Short name T551
Test name
Test status
Simulation time 8378879036 ps
CPU time 8.42 seconds
Started Mar 05 01:07:49 PM PST 24
Finished Mar 05 01:07:57 PM PST 24
Peak memory 202372 kb
Host smart-230857a3-c66d-4e92-94f6-10dcfb38a0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29404
65061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2940465061
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3037938808
Short name T396
Test name
Test status
Simulation time 8399012892 ps
CPU time 7.45 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:51 PM PST 24
Peak memory 202368 kb
Host smart-d2946dec-f1f1-44bd-b311-eb0ed2580b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30379
38808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3037938808
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.761467939
Short name T118
Test name
Test status
Simulation time 8377439026 ps
CPU time 8.16 seconds
Started Mar 05 01:07:49 PM PST 24
Finished Mar 05 01:07:57 PM PST 24
Peak memory 202476 kb
Host smart-b13e5753-5bb2-4762-be01-06bc3b20924e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76146
7939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.761467939
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2305996601
Short name T316
Test name
Test status
Simulation time 8378148599 ps
CPU time 7.01 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:51 PM PST 24
Peak memory 202296 kb
Host smart-732e317f-b20c-4be5-8415-d6e419e47a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23059
96601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2305996601
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2374737234
Short name T249
Test name
Test status
Simulation time 8363841908 ps
CPU time 7.75 seconds
Started Mar 05 01:07:50 PM PST 24
Finished Mar 05 01:07:58 PM PST 24
Peak memory 202232 kb
Host smart-54284d0c-0f60-4f55-bf9e-b9782cbfff43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23747
37234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2374737234
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1761896354
Short name T561
Test name
Test status
Simulation time 8439362931 ps
CPU time 7.08 seconds
Started Mar 05 01:07:47 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202424 kb
Host smart-0217d47c-870e-4870-af0b-0223aff625b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17618
96354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1761896354
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3187465404
Short name T179
Test name
Test status
Simulation time 8372647773 ps
CPU time 9.38 seconds
Started Mar 05 01:05:58 PM PST 24
Finished Mar 05 01:06:08 PM PST 24
Peak memory 202312 kb
Host smart-89571267-f8ff-4632-b305-aa9b46632d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31874
65404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3187465404
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1868557655
Short name T177
Test name
Test status
Simulation time 61440018 ps
CPU time 1.67 seconds
Started Mar 05 01:05:58 PM PST 24
Finished Mar 05 01:06:00 PM PST 24
Peak memory 202424 kb
Host smart-7eb39d33-5e3a-4f9b-803c-32de12fa61e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685
57655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1868557655
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3090410450
Short name T600
Test name
Test status
Simulation time 8417984944 ps
CPU time 7.31 seconds
Started Mar 05 01:05:53 PM PST 24
Finished Mar 05 01:06:01 PM PST 24
Peak memory 202416 kb
Host smart-b6aa54a7-894f-4c79-8f5d-751707c99df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30904
10450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3090410450
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3555099959
Short name T570
Test name
Test status
Simulation time 8406336328 ps
CPU time 7.22 seconds
Started Mar 05 01:05:54 PM PST 24
Finished Mar 05 01:06:01 PM PST 24
Peak memory 202344 kb
Host smart-5ac81c92-2f5a-4260-9176-179ee308a845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35550
99959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3555099959
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1651721244
Short name T521
Test name
Test status
Simulation time 8364088142 ps
CPU time 7.91 seconds
Started Mar 05 01:05:53 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 202332 kb
Host smart-993d18e6-5b0c-452d-8ccc-efb9a4ee4e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
21244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1651721244
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1296038510
Short name T648
Test name
Test status
Simulation time 8375855980 ps
CPU time 8.18 seconds
Started Mar 05 01:05:57 PM PST 24
Finished Mar 05 01:06:06 PM PST 24
Peak memory 202304 kb
Host smart-55998b36-3baf-45f6-96d4-cec938ce5a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12960
38510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1296038510
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1816961619
Short name T484
Test name
Test status
Simulation time 8384100271 ps
CPU time 9.22 seconds
Started Mar 05 01:05:55 PM PST 24
Finished Mar 05 01:06:05 PM PST 24
Peak memory 202448 kb
Host smart-4c217b7c-dd67-4068-8745-92c258731821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169
61619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1816961619
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.853564916
Short name T395
Test name
Test status
Simulation time 8372322654 ps
CPU time 10.09 seconds
Started Mar 05 01:05:56 PM PST 24
Finished Mar 05 01:06:06 PM PST 24
Peak memory 202252 kb
Host smart-c9802964-6fa3-4d2b-b4fd-c4a214037e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85356
4916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.853564916
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.1464358246
Short name T488
Test name
Test status
Simulation time 8459111837 ps
CPU time 9.76 seconds
Started Mar 05 01:05:55 PM PST 24
Finished Mar 05 01:06:05 PM PST 24
Peak memory 202372 kb
Host smart-32d523a3-d3ef-45bc-bf64-4fd5a0f583ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14643
58246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.1464358246
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.293992875
Short name T62
Test name
Test status
Simulation time 89175987 ps
CPU time 0.9 seconds
Started Mar 05 01:06:01 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 217268 kb
Host smart-f4ea4623-e441-4e0e-bbb5-c87aadfc80c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=293992875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.293992875
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1309934335
Short name T350
Test name
Test status
Simulation time 8389763723 ps
CPU time 6.9 seconds
Started Mar 05 01:05:52 PM PST 24
Finished Mar 05 01:05:59 PM PST 24
Peak memory 202416 kb
Host smart-81a6e664-ca49-4c36-8f0d-e3de71a75659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13099
34335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1309934335
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2403553079
Short name T507
Test name
Test status
Simulation time 8374290853 ps
CPU time 7.03 seconds
Started Mar 05 01:05:55 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 202420 kb
Host smart-5b79878b-aac5-4642-b1a8-179cec911710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24035
53079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2403553079
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1063749215
Short name T376
Test name
Test status
Simulation time 8381592326 ps
CPU time 8.32 seconds
Started Mar 05 01:07:48 PM PST 24
Finished Mar 05 01:07:57 PM PST 24
Peak memory 202436 kb
Host smart-e102ee1e-7d5c-4bcb-b94d-9047461297fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10637
49215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1063749215
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2730488568
Short name T354
Test name
Test status
Simulation time 8438733563 ps
CPU time 9.42 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202552 kb
Host smart-77d197e3-4c56-4730-a15f-90a13e901c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
88568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2730488568
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.882068165
Short name T620
Test name
Test status
Simulation time 8413439279 ps
CPU time 6.95 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:53 PM PST 24
Peak memory 202404 kb
Host smart-ef23be4c-484b-4581-a109-32f51cd10557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88206
8165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.882068165
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3122914135
Short name T444
Test name
Test status
Simulation time 8367698636 ps
CPU time 9.3 seconds
Started Mar 05 01:07:50 PM PST 24
Finished Mar 05 01:08:00 PM PST 24
Peak memory 202264 kb
Host smart-718dcb3c-37ac-4acc-9e3f-72af1e21382b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31229
14135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3122914135
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3581130753
Short name T510
Test name
Test status
Simulation time 8440379261 ps
CPU time 9.21 seconds
Started Mar 05 01:07:47 PM PST 24
Finished Mar 05 01:07:57 PM PST 24
Peak memory 202420 kb
Host smart-5a34f9b8-ee15-4a3a-a149-51db04edf37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35811
30753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3581130753
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1150561961
Short name T7
Test name
Test status
Simulation time 8378739449 ps
CPU time 8.1 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202108 kb
Host smart-50edd2b2-85c2-4109-beb7-c66d576cc85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
61961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1150561961
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2150952919
Short name T329
Test name
Test status
Simulation time 8407454955 ps
CPU time 7.18 seconds
Started Mar 05 01:07:47 PM PST 24
Finished Mar 05 01:07:55 PM PST 24
Peak memory 202472 kb
Host smart-3ac50d7e-8488-4e2b-bd00-cad157f2bce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21509
52919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2150952919
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1488637605
Short name T132
Test name
Test status
Simulation time 8433057773 ps
CPU time 7.61 seconds
Started Mar 05 01:07:47 PM PST 24
Finished Mar 05 01:07:56 PM PST 24
Peak memory 202428 kb
Host smart-6935120c-a39d-4575-9a70-75b0c635f0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14886
37605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1488637605
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3511031776
Short name T265
Test name
Test status
Simulation time 8388724329 ps
CPU time 9.57 seconds
Started Mar 05 01:07:48 PM PST 24
Finished Mar 05 01:07:58 PM PST 24
Peak memory 202416 kb
Host smart-fce73b5c-9b5e-451f-87b8-0fe0ff7780b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35110
31776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3511031776
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.581891836
Short name T520
Test name
Test status
Simulation time 8396204201 ps
CPU time 9.12 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:55 PM PST 24
Peak memory 202408 kb
Host smart-f44be164-419f-4c53-af57-2b3f94249b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58189
1836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.581891836
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2662253279
Short name T313
Test name
Test status
Simulation time 8371755100 ps
CPU time 8.06 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202352 kb
Host smart-195f6c4a-3257-4590-9d39-c3e58006cec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26622
53279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2662253279
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1929475979
Short name T533
Test name
Test status
Simulation time 8372076786 ps
CPU time 7.86 seconds
Started Mar 05 01:07:43 PM PST 24
Finished Mar 05 01:07:51 PM PST 24
Peak memory 202364 kb
Host smart-b74021a7-4ef2-4891-ac51-74e25fc09558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19294
75979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1929475979
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.110116927
Short name T349
Test name
Test status
Simulation time 301004564 ps
CPU time 2.29 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:48 PM PST 24
Peak memory 202416 kb
Host smart-14ffccc8-bc0c-43ec-a1cb-05e266a6e01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11011
6927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.110116927
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1084388242
Short name T588
Test name
Test status
Simulation time 8437146658 ps
CPU time 7.32 seconds
Started Mar 05 01:07:47 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202392 kb
Host smart-5571b702-d3b0-40a4-afdc-fc915b01efdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
88242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1084388242
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2905005031
Short name T283
Test name
Test status
Simulation time 8406704161 ps
CPU time 8.03 seconds
Started Mar 05 01:07:44 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202368 kb
Host smart-5e10bef4-0b69-481c-99ca-de86a304a238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29050
05031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2905005031
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2490644965
Short name T524
Test name
Test status
Simulation time 8367348911 ps
CPU time 7.66 seconds
Started Mar 05 01:07:48 PM PST 24
Finished Mar 05 01:07:56 PM PST 24
Peak memory 202436 kb
Host smart-35246af8-d768-4f6c-84be-d34f5a8784fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24906
44965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2490644965
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.104656707
Short name T250
Test name
Test status
Simulation time 8366687083 ps
CPU time 7.46 seconds
Started Mar 05 01:07:50 PM PST 24
Finished Mar 05 01:07:58 PM PST 24
Peak memory 202252 kb
Host smart-995745cf-1a60-4d4a-baf5-256d5002b5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
6707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.104656707
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2264667789
Short name T519
Test name
Test status
Simulation time 8379354166 ps
CPU time 7.65 seconds
Started Mar 05 01:07:48 PM PST 24
Finished Mar 05 01:07:56 PM PST 24
Peak memory 202364 kb
Host smart-76773af9-8f97-4a04-9ee5-104464652c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22646
67789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2264667789
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3034826942
Short name T593
Test name
Test status
Simulation time 8377052645 ps
CPU time 7.45 seconds
Started Mar 05 01:07:47 PM PST 24
Finished Mar 05 01:07:54 PM PST 24
Peak memory 202484 kb
Host smart-31225803-d986-4b0f-9fd1-db49bffabf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30348
26942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3034826942
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.43185078
Short name T408
Test name
Test status
Simulation time 8381336383 ps
CPU time 8.62 seconds
Started Mar 05 01:07:45 PM PST 24
Finished Mar 05 01:07:55 PM PST 24
Peak memory 202464 kb
Host smart-b7aac30a-7b0d-4c76-9bcc-8e7e16722352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43185
078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.43185078
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1035143501
Short name T416
Test name
Test status
Simulation time 8360623584 ps
CPU time 8.18 seconds
Started Mar 05 01:07:50 PM PST 24
Finished Mar 05 01:07:58 PM PST 24
Peak memory 202392 kb
Host smart-80654a45-3e01-4abe-b6a4-a39de5564ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10351
43501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1035143501
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3637372538
Short name T364
Test name
Test status
Simulation time 8367072736 ps
CPU time 7.29 seconds
Started Mar 05 01:07:49 PM PST 24
Finished Mar 05 01:07:57 PM PST 24
Peak memory 202424 kb
Host smart-cee9e302-68fe-4b5b-a9dc-34c9a090c3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36373
72538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3637372538
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3331226011
Short name T409
Test name
Test status
Simulation time 8375141475 ps
CPU time 9.74 seconds
Started Mar 05 01:07:53 PM PST 24
Finished Mar 05 01:08:03 PM PST 24
Peak memory 202484 kb
Host smart-7b5e1ff7-fe1b-4e60-a99a-0598f24f9e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33312
26011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3331226011
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1185920214
Short name T73
Test name
Test status
Simulation time 82740080 ps
CPU time 1.16 seconds
Started Mar 05 01:07:56 PM PST 24
Finished Mar 05 01:07:57 PM PST 24
Peak memory 202384 kb
Host smart-7e33291e-e1d6-4692-ae25-78409aa3a5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11859
20214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1185920214
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.339766904
Short name T498
Test name
Test status
Simulation time 8428271618 ps
CPU time 8.29 seconds
Started Mar 05 01:07:58 PM PST 24
Finished Mar 05 01:08:06 PM PST 24
Peak memory 202372 kb
Host smart-44ccf965-679d-4e0d-a178-9a19eafb4f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33976
6904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.339766904
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2897892295
Short name T625
Test name
Test status
Simulation time 8406521020 ps
CPU time 7.27 seconds
Started Mar 05 01:07:52 PM PST 24
Finished Mar 05 01:08:00 PM PST 24
Peak memory 202392 kb
Host smart-721567be-481b-4673-b5b1-8684a807d54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28978
92295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2897892295
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1946615628
Short name T255
Test name
Test status
Simulation time 8366778928 ps
CPU time 10.21 seconds
Started Mar 05 01:07:52 PM PST 24
Finished Mar 05 01:08:02 PM PST 24
Peak memory 202428 kb
Host smart-32d653f1-e97e-4efa-a925-c2d9e3869843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19466
15628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1946615628
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2475544297
Short name T91
Test name
Test status
Simulation time 8457172633 ps
CPU time 7.52 seconds
Started Mar 05 01:07:54 PM PST 24
Finished Mar 05 01:08:02 PM PST 24
Peak memory 202360 kb
Host smart-0f8741c5-bbe1-4762-89ef-e945badc4ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24755
44297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2475544297
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.418214766
Short name T617
Test name
Test status
Simulation time 8381951846 ps
CPU time 7.85 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:05 PM PST 24
Peak memory 202476 kb
Host smart-d204f887-0ffa-45e7-86a9-29118bcaeb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41821
4766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.418214766
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4040168180
Short name T407
Test name
Test status
Simulation time 8386172580 ps
CPU time 7.03 seconds
Started Mar 05 01:08:02 PM PST 24
Finished Mar 05 01:08:09 PM PST 24
Peak memory 202424 kb
Host smart-7734f7b1-f120-4ff7-a742-fc42f3752a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40401
68180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4040168180
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.232543451
Short name T536
Test name
Test status
Simulation time 8419013088 ps
CPU time 7.72 seconds
Started Mar 05 01:07:56 PM PST 24
Finished Mar 05 01:08:03 PM PST 24
Peak memory 202428 kb
Host smart-69b68c26-f87c-4cb2-8cd6-cf1e2f662c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23254
3451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.232543451
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.844232429
Short name T595
Test name
Test status
Simulation time 8388328664 ps
CPU time 8.35 seconds
Started Mar 05 01:07:55 PM PST 24
Finished Mar 05 01:08:03 PM PST 24
Peak memory 202328 kb
Host smart-2c1e4184-ed1b-498f-a61b-88e73d258fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84423
2429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.844232429
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2292860856
Short name T426
Test name
Test status
Simulation time 8368308199 ps
CPU time 7.11 seconds
Started Mar 05 01:07:55 PM PST 24
Finished Mar 05 01:08:03 PM PST 24
Peak memory 202368 kb
Host smart-5de725c6-9aa1-49e7-928a-52f860990989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928
60856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2292860856
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.560001680
Short name T662
Test name
Test status
Simulation time 8369392808 ps
CPU time 7.7 seconds
Started Mar 05 01:08:01 PM PST 24
Finished Mar 05 01:08:08 PM PST 24
Peak memory 202436 kb
Host smart-5f6fb1ed-d0e3-4175-8fe9-71ac8545f679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56000
1680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.560001680
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.2079374605
Short name T478
Test name
Test status
Simulation time 69870995 ps
CPU time 1.88 seconds
Started Mar 05 01:08:01 PM PST 24
Finished Mar 05 01:08:03 PM PST 24
Peak memory 202380 kb
Host smart-000e91ea-e64f-4415-ae86-1ab3a6378075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20793
74605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.2079374605
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1675262353
Short name T419
Test name
Test status
Simulation time 8440021779 ps
CPU time 7.68 seconds
Started Mar 05 01:07:56 PM PST 24
Finished Mar 05 01:08:04 PM PST 24
Peak memory 202428 kb
Host smart-ac395c68-9bff-4090-86ee-d3bdda8d6d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16752
62353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1675262353
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.592473010
Short name T259
Test name
Test status
Simulation time 8403768265 ps
CPU time 8.58 seconds
Started Mar 05 01:07:59 PM PST 24
Finished Mar 05 01:08:07 PM PST 24
Peak memory 202408 kb
Host smart-4686f3b4-c618-4e8f-920d-f5660fb2ef26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59247
3010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.592473010
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1794138036
Short name T658
Test name
Test status
Simulation time 8363862581 ps
CPU time 9.17 seconds
Started Mar 05 01:07:59 PM PST 24
Finished Mar 05 01:08:08 PM PST 24
Peak memory 202424 kb
Host smart-33cb24df-d855-438a-a001-b3cfa335d0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17941
38036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1794138036
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.945487357
Short name T308
Test name
Test status
Simulation time 8408557256 ps
CPU time 8.32 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:06 PM PST 24
Peak memory 202440 kb
Host smart-959bbcff-5dd9-471f-b5ed-26a8608bb7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94548
7357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.945487357
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2883110268
Short name T1
Test name
Test status
Simulation time 8392884765 ps
CPU time 7.34 seconds
Started Mar 05 01:07:58 PM PST 24
Finished Mar 05 01:08:05 PM PST 24
Peak memory 202380 kb
Host smart-c6eee081-3ea1-4ef2-89c1-11ba4711bcec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28831
10268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2883110268
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2137684418
Short name T383
Test name
Test status
Simulation time 8457756673 ps
CPU time 8.96 seconds
Started Mar 05 01:08:00 PM PST 24
Finished Mar 05 01:08:09 PM PST 24
Peak memory 202436 kb
Host smart-52613ba3-4bed-42de-9929-a6ad31e38161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
84418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2137684418
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.295510915
Short name T634
Test name
Test status
Simulation time 8361022841 ps
CPU time 7.21 seconds
Started Mar 05 01:08:00 PM PST 24
Finished Mar 05 01:08:08 PM PST 24
Peak memory 202488 kb
Host smart-ab9467f0-0cfe-404d-9edf-4f979aea151b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29551
0915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.295510915
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1012967209
Short name T183
Test name
Test status
Simulation time 8366643826 ps
CPU time 7.21 seconds
Started Mar 05 01:07:55 PM PST 24
Finished Mar 05 01:08:03 PM PST 24
Peak memory 202368 kb
Host smart-e2801587-099d-474e-9ae3-58d497281ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10129
67209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1012967209
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.495571010
Short name T320
Test name
Test status
Simulation time 8374202737 ps
CPU time 7.16 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:05 PM PST 24
Peak memory 202436 kb
Host smart-eb3e03cc-7908-42d2-9ed1-5a23fde725f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49557
1010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.495571010
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.336494655
Short name T342
Test name
Test status
Simulation time 39984938 ps
CPU time 1.03 seconds
Started Mar 05 01:08:01 PM PST 24
Finished Mar 05 01:08:02 PM PST 24
Peak memory 202324 kb
Host smart-6ff057dd-f172-4de4-a56d-9fe736bf7dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33649
4655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.336494655
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.841177215
Short name T69
Test name
Test status
Simulation time 8440115890 ps
CPU time 8.38 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:06 PM PST 24
Peak memory 202468 kb
Host smart-68841f48-b3db-4edf-b5f8-5eda33c957b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84117
7215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.841177215
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1143420316
Short name T655
Test name
Test status
Simulation time 8415879957 ps
CPU time 6.95 seconds
Started Mar 05 01:07:58 PM PST 24
Finished Mar 05 01:08:05 PM PST 24
Peak memory 202320 kb
Host smart-6a787e46-612a-4e3a-8bc5-ed56b36e201c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11434
20316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1143420316
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2949436849
Short name T441
Test name
Test status
Simulation time 8363587392 ps
CPU time 8.32 seconds
Started Mar 05 01:08:00 PM PST 24
Finished Mar 05 01:08:08 PM PST 24
Peak memory 202500 kb
Host smart-c26d5d7c-55d3-4d8c-b038-b7c325cc0046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29494
36849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2949436849
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.216780297
Short name T89
Test name
Test status
Simulation time 8433659993 ps
CPU time 9.72 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:07 PM PST 24
Peak memory 202424 kb
Host smart-55cb2ce2-56f8-43e8-bfde-bc958547ac87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21678
0297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.216780297
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.283678312
Short name T366
Test name
Test status
Simulation time 8401055594 ps
CPU time 8.15 seconds
Started Mar 05 01:08:00 PM PST 24
Finished Mar 05 01:08:08 PM PST 24
Peak memory 202396 kb
Host smart-ffffe2b6-61b1-4df2-965a-adda7ee00eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28367
8312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.283678312
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.71333916
Short name T290
Test name
Test status
Simulation time 8390804449 ps
CPU time 7.96 seconds
Started Mar 05 01:07:58 PM PST 24
Finished Mar 05 01:08:06 PM PST 24
Peak memory 202388 kb
Host smart-471ccd40-c0a4-4efd-b29d-82592ad22c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71333
916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.71333916
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1211519210
Short name T569
Test name
Test status
Simulation time 8429128012 ps
CPU time 8.14 seconds
Started Mar 05 01:08:00 PM PST 24
Finished Mar 05 01:08:09 PM PST 24
Peak memory 202460 kb
Host smart-5c5d878c-a91c-4380-b7fe-f6074cf110d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115
19210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1211519210
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3929850375
Short name T67
Test name
Test status
Simulation time 8367970157 ps
CPU time 8.23 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:06 PM PST 24
Peak memory 202420 kb
Host smart-f0077ec8-edb2-40d0-a441-1035e5d41bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39298
50375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3929850375
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2416096969
Short name T501
Test name
Test status
Simulation time 8366478446 ps
CPU time 8.24 seconds
Started Mar 05 01:07:58 PM PST 24
Finished Mar 05 01:08:07 PM PST 24
Peak memory 202472 kb
Host smart-7535b675-c489-403e-bde5-99e0e060344b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24160
96969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2416096969
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3815919513
Short name T497
Test name
Test status
Simulation time 8373114870 ps
CPU time 7.4 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:05 PM PST 24
Peak memory 202476 kb
Host smart-8f339efa-c823-4795-a2f5-089ca927ceb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38159
19513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3815919513
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.4184072595
Short name T652
Test name
Test status
Simulation time 8368330002 ps
CPU time 7.52 seconds
Started Mar 05 01:08:02 PM PST 24
Finished Mar 05 01:08:09 PM PST 24
Peak memory 202332 kb
Host smart-6ddd3d37-d16d-4cb0-8ff0-58acceb09519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41840
72595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.4184072595
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2761160180
Short name T234
Test name
Test status
Simulation time 36199221 ps
CPU time 1.01 seconds
Started Mar 05 01:07:58 PM PST 24
Finished Mar 05 01:07:59 PM PST 24
Peak memory 202480 kb
Host smart-5bcf2c38-7292-4a62-8b10-70c75777d523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27611
60180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2761160180
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2001259322
Short name T12
Test name
Test status
Simulation time 8369094486 ps
CPU time 7.64 seconds
Started Mar 05 01:07:59 PM PST 24
Finished Mar 05 01:08:07 PM PST 24
Peak memory 202396 kb
Host smart-a8440d27-1f26-4a8f-aa2b-f52e57a6accb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20012
59322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2001259322
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1895542427
Short name T372
Test name
Test status
Simulation time 8366328621 ps
CPU time 7.24 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:05 PM PST 24
Peak memory 202456 kb
Host smart-08877d0c-fddc-4729-897c-2656cc4b8120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18955
42427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1895542427
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2542037249
Short name T512
Test name
Test status
Simulation time 8380289910 ps
CPU time 7.72 seconds
Started Mar 05 01:07:58 PM PST 24
Finished Mar 05 01:08:06 PM PST 24
Peak memory 202476 kb
Host smart-58bf0082-e2e5-4f83-b0bb-e1c1ee5f228d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25420
37249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2542037249
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2209320135
Short name T257
Test name
Test status
Simulation time 8406269340 ps
CPU time 7.4 seconds
Started Mar 05 01:07:58 PM PST 24
Finished Mar 05 01:08:05 PM PST 24
Peak memory 202476 kb
Host smart-3b6b1d2a-65e1-4b75-836f-6d13de4e676c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22093
20135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2209320135
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3430921722
Short name T541
Test name
Test status
Simulation time 8393032850 ps
CPU time 9.46 seconds
Started Mar 05 01:07:59 PM PST 24
Finished Mar 05 01:08:09 PM PST 24
Peak memory 202392 kb
Host smart-d1e65330-a2c8-4aee-8d6e-00cfc80c7fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
21722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3430921722
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1473577002
Short name T592
Test name
Test status
Simulation time 8423158207 ps
CPU time 8.08 seconds
Started Mar 05 01:08:02 PM PST 24
Finished Mar 05 01:08:10 PM PST 24
Peak memory 202324 kb
Host smart-e62400aa-3869-4f11-b39c-f280ec9fa6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14735
77002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1473577002
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.40066769
Short name T391
Test name
Test status
Simulation time 8368880817 ps
CPU time 8.61 seconds
Started Mar 05 01:07:57 PM PST 24
Finished Mar 05 01:08:06 PM PST 24
Peak memory 202428 kb
Host smart-88777a46-8dc6-45e7-9acc-8c74cca6c027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066
769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.40066769
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.766847421
Short name T438
Test name
Test status
Simulation time 8360208044 ps
CPU time 6.93 seconds
Started Mar 05 01:07:54 PM PST 24
Finished Mar 05 01:08:02 PM PST 24
Peak memory 202600 kb
Host smart-cf46fb1a-3343-405b-8b4d-ec526d1ebf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76684
7421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.766847421
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2575536397
Short name T627
Test name
Test status
Simulation time 8368490304 ps
CPU time 7.83 seconds
Started Mar 05 01:07:56 PM PST 24
Finished Mar 05 01:08:04 PM PST 24
Peak memory 202420 kb
Host smart-fae2710e-2db7-49a7-8dc4-cc1602b6cf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25755
36397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2575536397
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3491570724
Short name T40
Test name
Test status
Simulation time 8368834102 ps
CPU time 7.52 seconds
Started Mar 05 01:08:06 PM PST 24
Finished Mar 05 01:08:14 PM PST 24
Peak memory 202372 kb
Host smart-a039e751-e8ec-4b8b-860d-3567d6f92247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34915
70724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3491570724
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3985634229
Short name T175
Test name
Test status
Simulation time 155729321 ps
CPU time 1.67 seconds
Started Mar 05 01:08:04 PM PST 24
Finished Mar 05 01:08:06 PM PST 24
Peak memory 202380 kb
Host smart-72bae978-1a46-442c-bb95-7359de3c7c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39856
34229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3985634229
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3784600435
Short name T516
Test name
Test status
Simulation time 8414235241 ps
CPU time 7.56 seconds
Started Mar 05 01:08:07 PM PST 24
Finished Mar 05 01:08:16 PM PST 24
Peak memory 202320 kb
Host smart-dc8bfd50-4f49-4c96-b4b7-f595d35fd129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37846
00435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3784600435
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2397441183
Short name T361
Test name
Test status
Simulation time 8487496739 ps
CPU time 6.72 seconds
Started Mar 05 01:08:02 PM PST 24
Finished Mar 05 01:08:09 PM PST 24
Peak memory 202476 kb
Host smart-995fa975-2905-4bed-a4fe-a0db2939860a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23974
41183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2397441183
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2842074492
Short name T248
Test name
Test status
Simulation time 8365350307 ps
CPU time 7.69 seconds
Started Mar 05 01:08:04 PM PST 24
Finished Mar 05 01:08:12 PM PST 24
Peak memory 202556 kb
Host smart-90ce2e32-cc70-4cc9-b949-17d53f96eff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28420
74492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2842074492
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.67184584
Short name T106
Test name
Test status
Simulation time 8423244662 ps
CPU time 8.07 seconds
Started Mar 05 01:08:09 PM PST 24
Finished Mar 05 01:08:18 PM PST 24
Peak memory 202420 kb
Host smart-3bbe41d4-ac94-4be9-817e-2df8e5576588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67184
584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.67184584
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.637714074
Short name T615
Test name
Test status
Simulation time 8399453261 ps
CPU time 8.9 seconds
Started Mar 05 01:08:07 PM PST 24
Finished Mar 05 01:08:18 PM PST 24
Peak memory 202436 kb
Host smart-ec01e784-6cef-46f4-a5ec-b5eb4e279c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63771
4074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.637714074
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3670374461
Short name T553
Test name
Test status
Simulation time 8389035137 ps
CPU time 7.88 seconds
Started Mar 05 01:08:09 PM PST 24
Finished Mar 05 01:08:18 PM PST 24
Peak memory 202504 kb
Host smart-8d371eeb-850b-4bf8-adf3-1696366012e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36703
74461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3670374461
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2658160250
Short name T515
Test name
Test status
Simulation time 8445402791 ps
CPU time 9.76 seconds
Started Mar 05 01:08:04 PM PST 24
Finished Mar 05 01:08:14 PM PST 24
Peak memory 202436 kb
Host smart-d2e7f9ed-72b3-42e7-8e61-9dc2899574b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26581
60250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2658160250
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.622564857
Short name T324
Test name
Test status
Simulation time 8376859311 ps
CPU time 8.26 seconds
Started Mar 05 01:08:07 PM PST 24
Finished Mar 05 01:08:16 PM PST 24
Peak memory 202404 kb
Host smart-00947b6e-6230-4d37-8a72-89a7daf8cec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62256
4857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.622564857
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2133035344
Short name T30
Test name
Test status
Simulation time 8361188824 ps
CPU time 7.82 seconds
Started Mar 05 01:08:05 PM PST 24
Finished Mar 05 01:08:13 PM PST 24
Peak memory 202464 kb
Host smart-09d1ee0a-d651-4de0-8d63-de1c7b859b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21330
35344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2133035344
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4240060025
Short name T644
Test name
Test status
Simulation time 8363702883 ps
CPU time 7.46 seconds
Started Mar 05 01:08:06 PM PST 24
Finished Mar 05 01:08:13 PM PST 24
Peak memory 202376 kb
Host smart-0bfeffb0-8084-4b89-b9c4-59522516b5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400
60025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4240060025
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.368640756
Short name T35
Test name
Test status
Simulation time 8368168141 ps
CPU time 8.02 seconds
Started Mar 05 01:08:02 PM PST 24
Finished Mar 05 01:08:11 PM PST 24
Peak memory 202468 kb
Host smart-5a084ade-eca2-4b80-a34e-b149241cf386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36864
0756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.368640756
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.187282597
Short name T76
Test name
Test status
Simulation time 68341980 ps
CPU time 1.76 seconds
Started Mar 05 01:08:10 PM PST 24
Finished Mar 05 01:08:12 PM PST 24
Peak memory 202428 kb
Host smart-7baee305-73d4-43b7-a782-2a10f076fa3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18728
2597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.187282597
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.162963547
Short name T117
Test name
Test status
Simulation time 8403252041 ps
CPU time 7.65 seconds
Started Mar 05 01:08:08 PM PST 24
Finished Mar 05 01:08:22 PM PST 24
Peak memory 202372 kb
Host smart-7d4e6851-67d7-427d-930d-bbc9f8d3a98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16296
3547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.162963547
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.831214814
Short name T482
Test name
Test status
Simulation time 8429130543 ps
CPU time 9.6 seconds
Started Mar 05 01:08:10 PM PST 24
Finished Mar 05 01:08:20 PM PST 24
Peak memory 202404 kb
Host smart-7c8d6523-d7de-45f4-9b31-d8b855860d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83121
4814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.831214814
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.681919207
Short name T280
Test name
Test status
Simulation time 8376392692 ps
CPU time 7.5 seconds
Started Mar 05 01:08:08 PM PST 24
Finished Mar 05 01:08:17 PM PST 24
Peak memory 202312 kb
Host smart-589adaca-e4e1-4050-8860-9216707f23e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68191
9207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.681919207
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.472578482
Short name T102
Test name
Test status
Simulation time 8429784326 ps
CPU time 8.34 seconds
Started Mar 05 01:08:07 PM PST 24
Finished Mar 05 01:08:16 PM PST 24
Peak memory 202424 kb
Host smart-71027200-8855-4fd5-aa6c-67a124b84667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47257
8482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.472578482
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3487022640
Short name T513
Test name
Test status
Simulation time 8401857762 ps
CPU time 8.22 seconds
Started Mar 05 01:08:03 PM PST 24
Finished Mar 05 01:08:11 PM PST 24
Peak memory 202368 kb
Host smart-f285de61-af84-411e-aa41-f947f8588d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34870
22640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3487022640
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3118505105
Short name T367
Test name
Test status
Simulation time 8403828158 ps
CPU time 7.06 seconds
Started Mar 05 01:08:12 PM PST 24
Finished Mar 05 01:08:19 PM PST 24
Peak memory 202444 kb
Host smart-69f5b700-87ae-4fc0-9350-5ae8148bbb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31185
05105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3118505105
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1680216789
Short name T397
Test name
Test status
Simulation time 8385492276 ps
CPU time 7.65 seconds
Started Mar 05 01:08:07 PM PST 24
Finished Mar 05 01:08:15 PM PST 24
Peak memory 202436 kb
Host smart-fe496549-453a-45b3-80fa-4424642ba0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16802
16789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1680216789
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2048895314
Short name T371
Test name
Test status
Simulation time 8364962345 ps
CPU time 7.17 seconds
Started Mar 05 01:08:04 PM PST 24
Finished Mar 05 01:08:11 PM PST 24
Peak memory 202480 kb
Host smart-1d6d9f99-29db-40d1-a50d-e942eb43db37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20488
95314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2048895314
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2305916660
Short name T284
Test name
Test status
Simulation time 8372091041 ps
CPU time 7.17 seconds
Started Mar 05 01:08:09 PM PST 24
Finished Mar 05 01:08:17 PM PST 24
Peak memory 202320 kb
Host smart-7c651f04-febc-42c6-aec6-16dcee05bf1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23059
16660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2305916660
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.70442729
Short name T21
Test name
Test status
Simulation time 8369214846 ps
CPU time 8.49 seconds
Started Mar 05 01:08:06 PM PST 24
Finished Mar 05 01:08:15 PM PST 24
Peak memory 202432 kb
Host smart-573e6baa-c292-432f-a9c3-2a5fd27771a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70442
729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.70442729
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2771976993
Short name T582
Test name
Test status
Simulation time 91742345 ps
CPU time 1.18 seconds
Started Mar 05 01:08:16 PM PST 24
Finished Mar 05 01:08:18 PM PST 24
Peak memory 202380 kb
Host smart-0041ecd0-c567-419d-aaef-7d942e13f25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27719
76993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2771976993
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1099036058
Short name T83
Test name
Test status
Simulation time 8396932044 ps
CPU time 8.66 seconds
Started Mar 05 01:08:07 PM PST 24
Finished Mar 05 01:08:16 PM PST 24
Peak memory 202460 kb
Host smart-35589390-7579-4d3a-aa24-9f5655353fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10990
36058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1099036058
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2584822204
Short name T480
Test name
Test status
Simulation time 8407781944 ps
CPU time 7.07 seconds
Started Mar 05 01:08:14 PM PST 24
Finished Mar 05 01:08:21 PM PST 24
Peak memory 202364 kb
Host smart-d7ba7b98-cd05-4231-8181-aa18c1d5887a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25848
22204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2584822204
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3390521185
Short name T543
Test name
Test status
Simulation time 8387629372 ps
CPU time 8.93 seconds
Started Mar 05 01:08:18 PM PST 24
Finished Mar 05 01:08:27 PM PST 24
Peak memory 202428 kb
Host smart-9f8b9c87-b9a7-4836-98f8-657a02f15bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33905
21185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3390521185
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1629517909
Short name T619
Test name
Test status
Simulation time 8440847874 ps
CPU time 7.7 seconds
Started Mar 05 01:08:09 PM PST 24
Finished Mar 05 01:08:17 PM PST 24
Peak memory 202396 kb
Host smart-ed8309ef-57bd-411c-9e14-daab51075f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16295
17909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1629517909
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.529679150
Short name T607
Test name
Test status
Simulation time 8444746478 ps
CPU time 7.09 seconds
Started Mar 05 01:08:16 PM PST 24
Finished Mar 05 01:08:24 PM PST 24
Peak memory 202428 kb
Host smart-f674cca2-0c4c-4999-a0b5-e463459ac513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52967
9150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.529679150
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.317703069
Short name T277
Test name
Test status
Simulation time 8373067855 ps
CPU time 7.41 seconds
Started Mar 05 01:08:16 PM PST 24
Finished Mar 05 01:08:24 PM PST 24
Peak memory 202428 kb
Host smart-7dbefc67-b0e5-43ae-b125-95507da1c96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31770
3069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.317703069
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3035936006
Short name T653
Test name
Test status
Simulation time 8404678133 ps
CPU time 7.67 seconds
Started Mar 05 01:08:09 PM PST 24
Finished Mar 05 01:08:17 PM PST 24
Peak memory 202436 kb
Host smart-b5a23152-61c7-4119-b525-5ef2dffd7d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30359
36006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3035936006
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3365904186
Short name T496
Test name
Test status
Simulation time 8365906459 ps
CPU time 8.14 seconds
Started Mar 05 01:08:19 PM PST 24
Finished Mar 05 01:08:27 PM PST 24
Peak memory 202416 kb
Host smart-76f9efc3-5d9f-493d-8f63-70892a7f2d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
04186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3365904186
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1386795333
Short name T418
Test name
Test status
Simulation time 8364120900 ps
CPU time 7.44 seconds
Started Mar 05 01:08:08 PM PST 24
Finished Mar 05 01:08:17 PM PST 24
Peak memory 202448 kb
Host smart-fb5a1ee7-b1da-4737-896f-61d6baed959c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13867
95333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1386795333
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1654199135
Short name T548
Test name
Test status
Simulation time 8371531623 ps
CPU time 7.89 seconds
Started Mar 05 01:08:03 PM PST 24
Finished Mar 05 01:08:11 PM PST 24
Peak memory 202404 kb
Host smart-55f1c012-1eb9-4082-aa2e-f3afb7d0c034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16541
99135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1654199135
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3952223316
Short name T448
Test name
Test status
Simulation time 8369060826 ps
CPU time 8.81 seconds
Started Mar 05 01:08:21 PM PST 24
Finished Mar 05 01:08:31 PM PST 24
Peak memory 202540 kb
Host smart-904f529c-73e3-4c6e-9253-39bb44b31e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39522
23316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3952223316
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3555304693
Short name T621
Test name
Test status
Simulation time 8401254913 ps
CPU time 7.48 seconds
Started Mar 05 01:08:20 PM PST 24
Finished Mar 05 01:08:29 PM PST 24
Peak memory 202452 kb
Host smart-ebf4efaf-8cd6-48bb-bf57-2cfe8678c028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35553
04693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3555304693
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2059834072
Short name T262
Test name
Test status
Simulation time 8409268821 ps
CPU time 9.42 seconds
Started Mar 05 01:08:16 PM PST 24
Finished Mar 05 01:08:26 PM PST 24
Peak memory 202372 kb
Host smart-5c286ea1-5b2d-46d0-af93-22863235c3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20598
34072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2059834072
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2832854590
Short name T546
Test name
Test status
Simulation time 8369494759 ps
CPU time 8.23 seconds
Started Mar 05 01:08:18 PM PST 24
Finished Mar 05 01:08:27 PM PST 24
Peak memory 202484 kb
Host smart-156bb1d9-9537-4955-8327-e80603b6277e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28328
54590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2832854590
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1749772009
Short name T500
Test name
Test status
Simulation time 8419975913 ps
CPU time 8.12 seconds
Started Mar 05 01:08:23 PM PST 24
Finished Mar 05 01:08:32 PM PST 24
Peak memory 202420 kb
Host smart-6e9699e1-db88-45ad-9df8-0b041a143b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17497
72009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1749772009
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.603093708
Short name T458
Test name
Test status
Simulation time 8408285597 ps
CPU time 7.38 seconds
Started Mar 05 01:08:15 PM PST 24
Finished Mar 05 01:08:23 PM PST 24
Peak memory 202368 kb
Host smart-d5a2b708-f485-4763-9724-af1a676a5c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60309
3708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.603093708
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2228673051
Short name T481
Test name
Test status
Simulation time 8407045442 ps
CPU time 7.91 seconds
Started Mar 05 01:08:21 PM PST 24
Finished Mar 05 01:08:30 PM PST 24
Peak memory 202316 kb
Host smart-ad3f3a14-b52b-4a1a-bdca-aff9213a4e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22286
73051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2228673051
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3074747592
Short name T25
Test name
Test status
Simulation time 8465062958 ps
CPU time 8.59 seconds
Started Mar 05 01:08:18 PM PST 24
Finished Mar 05 01:08:27 PM PST 24
Peak memory 202376 kb
Host smart-12f9fd16-9150-4952-adaf-3aa760eba4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30747
47592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3074747592
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.4149608997
Short name T477
Test name
Test status
Simulation time 8365131870 ps
CPU time 7.02 seconds
Started Mar 05 01:08:14 PM PST 24
Finished Mar 05 01:08:22 PM PST 24
Peak memory 202480 kb
Host smart-2a1cbe5c-7fc8-47d5-9c1b-af35396467c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41496
08997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.4149608997
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2662936291
Short name T612
Test name
Test status
Simulation time 8362283553 ps
CPU time 7.64 seconds
Started Mar 05 01:08:18 PM PST 24
Finished Mar 05 01:08:26 PM PST 24
Peak memory 202480 kb
Host smart-3422ed7d-69d8-49f6-89c6-62b32c513239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26629
36291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2662936291
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4285248196
Short name T375
Test name
Test status
Simulation time 8365920811 ps
CPU time 7.57 seconds
Started Mar 05 01:08:15 PM PST 24
Finished Mar 05 01:08:23 PM PST 24
Peak memory 202428 kb
Host smart-2ae495d8-713d-4e5a-bbec-2ac0f09c72e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42852
48196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4285248196
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3786303578
Short name T39
Test name
Test status
Simulation time 8372878191 ps
CPU time 8.5 seconds
Started Mar 05 01:05:53 PM PST 24
Finished Mar 05 01:06:03 PM PST 24
Peak memory 202360 kb
Host smart-3c1c7010-63e3-4113-9701-3ddd083aeee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
03578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3786303578
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.4049780593
Short name T273
Test name
Test status
Simulation time 8394273681 ps
CPU time 7.35 seconds
Started Mar 05 01:05:59 PM PST 24
Finished Mar 05 01:06:06 PM PST 24
Peak memory 202364 kb
Host smart-09e66ea5-b32b-460e-bcaa-4106a8dd1022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40497
80593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.4049780593
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2523469342
Short name T282
Test name
Test status
Simulation time 8422339788 ps
CPU time 7.32 seconds
Started Mar 05 01:06:02 PM PST 24
Finished Mar 05 01:06:10 PM PST 24
Peak memory 202460 kb
Host smart-15e3de75-cfbc-4cf7-9e72-a8af31bbe58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25234
69342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2523469342
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2554191246
Short name T534
Test name
Test status
Simulation time 8368346484 ps
CPU time 7.62 seconds
Started Mar 05 01:05:55 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 202352 kb
Host smart-8e30f7b4-03f7-4898-ae2e-281efef49985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25541
91246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2554191246
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3823727226
Short name T101
Test name
Test status
Simulation time 8430918117 ps
CPU time 8.08 seconds
Started Mar 05 01:05:53 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 202464 kb
Host smart-de4d255b-dec8-4495-a90b-f51635fed2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38237
27226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3823727226
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.246285711
Short name T261
Test name
Test status
Simulation time 8386581502 ps
CPU time 7.2 seconds
Started Mar 05 01:06:06 PM PST 24
Finished Mar 05 01:06:14 PM PST 24
Peak memory 202364 kb
Host smart-a8b68e69-0f9b-4877-8565-24f467a36c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24628
5711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.246285711
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.1979315294
Short name T377
Test name
Test status
Simulation time 8375088567 ps
CPU time 8.69 seconds
Started Mar 05 01:06:06 PM PST 24
Finished Mar 05 01:06:15 PM PST 24
Peak memory 202428 kb
Host smart-334e0f3c-fead-4dc4-b638-38a45484c19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19793
15294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.1979315294
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2152941896
Short name T659
Test name
Test status
Simulation time 8445369929 ps
CPU time 8.11 seconds
Started Mar 05 01:05:53 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 202128 kb
Host smart-93a64b67-2f50-415c-b891-3a49a5da2314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21529
41896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2152941896
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1547107808
Short name T344
Test name
Test status
Simulation time 8396242527 ps
CPU time 7.58 seconds
Started Mar 05 01:06:01 PM PST 24
Finished Mar 05 01:06:09 PM PST 24
Peak memory 202464 kb
Host smart-f676778b-84c6-48df-94d5-f154b56d7832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
07808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1547107808
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1175346885
Short name T613
Test name
Test status
Simulation time 8378377999 ps
CPU time 7.45 seconds
Started Mar 05 01:05:53 PM PST 24
Finished Mar 05 01:06:02 PM PST 24
Peak memory 202212 kb
Host smart-1739e089-0cd4-4f93-b69e-f5c895e924ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11753
46885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1175346885
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.522326804
Short name T41
Test name
Test status
Simulation time 8370949211 ps
CPU time 7.82 seconds
Started Mar 05 01:06:06 PM PST 24
Finished Mar 05 01:06:14 PM PST 24
Peak memory 202432 kb
Host smart-47a5093c-dcbc-4ba0-9d22-c3f1eaea0cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52232
6804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.522326804
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1679269744
Short name T74
Test name
Test status
Simulation time 168835336 ps
CPU time 1.77 seconds
Started Mar 05 01:06:06 PM PST 24
Finished Mar 05 01:06:08 PM PST 24
Peak memory 202432 kb
Host smart-0bc17bce-6ad9-4577-9904-322ca8417979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792
69744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1679269744
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1448029280
Short name T126
Test name
Test status
Simulation time 8407864362 ps
CPU time 7.93 seconds
Started Mar 05 01:06:04 PM PST 24
Finished Mar 05 01:06:12 PM PST 24
Peak memory 202416 kb
Host smart-32f56514-44c2-47e8-821b-cfb2b50bb3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14480
29280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1448029280
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2233016521
Short name T8
Test name
Test status
Simulation time 8409653435 ps
CPU time 6.84 seconds
Started Mar 05 01:06:05 PM PST 24
Finished Mar 05 01:06:13 PM PST 24
Peak memory 202364 kb
Host smart-04ae1506-5099-47e2-98d9-b9e243310d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22330
16521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2233016521
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.724165986
Short name T269
Test name
Test status
Simulation time 8371106932 ps
CPU time 9.41 seconds
Started Mar 05 01:06:04 PM PST 24
Finished Mar 05 01:06:14 PM PST 24
Peak memory 202400 kb
Host smart-30375f21-c7a1-4fbd-aff1-3daeb56cda82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72416
5986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.724165986
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.795955558
Short name T98
Test name
Test status
Simulation time 8423975702 ps
CPU time 7.47 seconds
Started Mar 05 01:06:03 PM PST 24
Finished Mar 05 01:06:11 PM PST 24
Peak memory 202364 kb
Host smart-d728fcab-e314-458e-92c5-d1779e5fedaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79595
5558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.795955558
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3308470703
Short name T32
Test name
Test status
Simulation time 8406289823 ps
CPU time 7.07 seconds
Started Mar 05 01:06:03 PM PST 24
Finished Mar 05 01:06:11 PM PST 24
Peak memory 202424 kb
Host smart-f276f18e-9f51-4151-b5bc-cce89913dc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33084
70703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3308470703
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.15111809
Short name T286
Test name
Test status
Simulation time 8377246794 ps
CPU time 8.21 seconds
Started Mar 05 01:06:04 PM PST 24
Finished Mar 05 01:06:12 PM PST 24
Peak memory 202360 kb
Host smart-05861d6f-adbe-423c-bda6-32854e90fef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15111
809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.15111809
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2601925498
Short name T15
Test name
Test status
Simulation time 8392665712 ps
CPU time 7.66 seconds
Started Mar 05 01:06:03 PM PST 24
Finished Mar 05 01:06:11 PM PST 24
Peak memory 202368 kb
Host smart-ce863139-c711-4401-80b4-6e4867552476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26019
25498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2601925498
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.4161500930
Short name T380
Test name
Test status
Simulation time 8376628095 ps
CPU time 7.4 seconds
Started Mar 05 01:06:05 PM PST 24
Finished Mar 05 01:06:14 PM PST 24
Peak memory 202380 kb
Host smart-987e8dd8-c88c-410c-8e18-e9c6b69fa241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41615
00930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.4161500930
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2659546731
Short name T654
Test name
Test status
Simulation time 8360740007 ps
CPU time 7.05 seconds
Started Mar 05 01:06:03 PM PST 24
Finished Mar 05 01:06:10 PM PST 24
Peak memory 202304 kb
Host smart-816edda4-37bb-42f4-90eb-f1161e8236f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26595
46731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2659546731
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2331806513
Short name T24
Test name
Test status
Simulation time 8368307309 ps
CPU time 7.45 seconds
Started Mar 05 01:06:09 PM PST 24
Finished Mar 05 01:06:17 PM PST 24
Peak memory 202428 kb
Host smart-80d2d239-766b-466f-8634-30e3f2ed0524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23318
06513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2331806513
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2827156993
Short name T646
Test name
Test status
Simulation time 8373212722 ps
CPU time 7.08 seconds
Started Mar 05 01:06:02 PM PST 24
Finished Mar 05 01:06:09 PM PST 24
Peak memory 202436 kb
Host smart-f7f8b6f5-7c86-4141-82bd-8864d5eb7496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28271
56993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2827156993
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2970145095
Short name T394
Test name
Test status
Simulation time 98906894 ps
CPU time 1.29 seconds
Started Mar 05 01:06:09 PM PST 24
Finished Mar 05 01:06:10 PM PST 24
Peak memory 202280 kb
Host smart-04099fef-868c-40de-94b4-618ec85dea82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29701
45095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2970145095
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3160857937
Short name T356
Test name
Test status
Simulation time 8438221070 ps
CPU time 7.5 seconds
Started Mar 05 01:06:08 PM PST 24
Finished Mar 05 01:06:15 PM PST 24
Peak memory 202416 kb
Host smart-c3741829-488a-4f0a-80a0-ca50eda3ef7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31608
57937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3160857937
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3573798123
Short name T508
Test name
Test status
Simulation time 8405316384 ps
CPU time 7.61 seconds
Started Mar 05 01:06:06 PM PST 24
Finished Mar 05 01:06:14 PM PST 24
Peak memory 202376 kb
Host smart-833e2507-0170-4608-b3ce-be032199484e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35737
98123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3573798123
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.157401073
Short name T34
Test name
Test status
Simulation time 8364494594 ps
CPU time 6.9 seconds
Started Mar 05 01:06:08 PM PST 24
Finished Mar 05 01:06:15 PM PST 24
Peak memory 202404 kb
Host smart-7c6c8945-3f82-48f8-80f2-4a65887d4209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15740
1073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.157401073
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1227318941
Short name T88
Test name
Test status
Simulation time 8424696727 ps
CPU time 8.17 seconds
Started Mar 05 01:06:05 PM PST 24
Finished Mar 05 01:06:15 PM PST 24
Peak memory 202480 kb
Host smart-2099c719-c08e-49ff-ba8a-561b48801f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12273
18941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1227318941
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1524994522
Short name T464
Test name
Test status
Simulation time 8371413501 ps
CPU time 8.38 seconds
Started Mar 05 01:06:08 PM PST 24
Finished Mar 05 01:06:16 PM PST 24
Peak memory 202424 kb
Host smart-aaf7f2e5-65b9-4a21-a8e0-a61e8ca4b582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
94522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1524994522
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3778481247
Short name T385
Test name
Test status
Simulation time 8367548641 ps
CPU time 8.78 seconds
Started Mar 05 01:06:03 PM PST 24
Finished Mar 05 01:06:12 PM PST 24
Peak memory 202424 kb
Host smart-18d3d104-94a0-4883-90d1-cd0a5fdf675b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37784
81247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3778481247
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2807273433
Short name T27
Test name
Test status
Simulation time 8454932897 ps
CPU time 10.26 seconds
Started Mar 05 01:06:05 PM PST 24
Finished Mar 05 01:06:15 PM PST 24
Peak memory 202472 kb
Host smart-8fb4b699-33ad-490f-91c2-d4a5b476258b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072
73433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2807273433
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2560270249
Short name T598
Test name
Test status
Simulation time 8385298056 ps
CPU time 9.15 seconds
Started Mar 05 01:06:04 PM PST 24
Finished Mar 05 01:06:13 PM PST 24
Peak memory 202408 kb
Host smart-621591da-0e36-4520-8543-97144f953e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25602
70249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2560270249
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2941999462
Short name T566
Test name
Test status
Simulation time 8362744027 ps
CPU time 8.25 seconds
Started Mar 05 01:06:03 PM PST 24
Finished Mar 05 01:06:12 PM PST 24
Peak memory 202348 kb
Host smart-24b62774-dcc7-455d-a17c-07b003abafad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29419
99462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2941999462
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1088168596
Short name T168
Test name
Test status
Simulation time 8374816680 ps
CPU time 7.27 seconds
Started Mar 05 01:06:03 PM PST 24
Finished Mar 05 01:06:10 PM PST 24
Peak memory 202480 kb
Host smart-b25c4931-8942-400b-adeb-0f1922b41d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10881
68596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1088168596
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3005755732
Short name T527
Test name
Test status
Simulation time 8372873990 ps
CPU time 8.44 seconds
Started Mar 05 01:06:07 PM PST 24
Finished Mar 05 01:06:16 PM PST 24
Peak memory 202408 kb
Host smart-74e8a880-69a6-4a33-a507-d066506af975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
55732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3005755732
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.395817625
Short name T647
Test name
Test status
Simulation time 198650868 ps
CPU time 1.91 seconds
Started Mar 05 01:06:15 PM PST 24
Finished Mar 05 01:06:17 PM PST 24
Peak memory 202424 kb
Host smart-d10874b5-3630-4306-bc01-cd5cdfae8449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581
7625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.395817625
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3996937367
Short name T16
Test name
Test status
Simulation time 8449666808 ps
CPU time 7.88 seconds
Started Mar 05 01:06:20 PM PST 24
Finished Mar 05 01:06:28 PM PST 24
Peak memory 202416 kb
Host smart-314db622-e58b-4fa5-b620-82a7b01350ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39969
37367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3996937367
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.893614631
Short name T339
Test name
Test status
Simulation time 8408961186 ps
CPU time 7.76 seconds
Started Mar 05 01:06:15 PM PST 24
Finished Mar 05 01:06:23 PM PST 24
Peak memory 202464 kb
Host smart-db6441ad-16d4-42c1-b1a3-b3fe26adff40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89361
4631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.893614631
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3094240379
Short name T430
Test name
Test status
Simulation time 8360930247 ps
CPU time 7.89 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:38 PM PST 24
Peak memory 202360 kb
Host smart-45afcb95-afe5-4a80-88ca-12e86998fb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30942
40379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3094240379
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2702564156
Short name T650
Test name
Test status
Simulation time 8389382402 ps
CPU time 7.47 seconds
Started Mar 05 01:06:04 PM PST 24
Finished Mar 05 01:06:12 PM PST 24
Peak memory 202392 kb
Host smart-9ef42a95-3f73-4740-9312-484b77d44c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27025
64156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2702564156
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1604483465
Short name T239
Test name
Test status
Simulation time 8377816085 ps
CPU time 7.36 seconds
Started Mar 05 01:06:14 PM PST 24
Finished Mar 05 01:06:22 PM PST 24
Peak memory 202352 kb
Host smart-84100e5f-f69b-4cf3-a4d3-32c26edaeb5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16044
83465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1604483465
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3686349050
Short name T603
Test name
Test status
Simulation time 8386979609 ps
CPU time 7.69 seconds
Started Mar 05 01:06:14 PM PST 24
Finished Mar 05 01:06:22 PM PST 24
Peak memory 202424 kb
Host smart-9286977a-6879-4377-b614-b87ea2382d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36863
49050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3686349050
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3905748567
Short name T563
Test name
Test status
Simulation time 8471213086 ps
CPU time 7.71 seconds
Started Mar 05 01:06:06 PM PST 24
Finished Mar 05 01:06:14 PM PST 24
Peak memory 202388 kb
Host smart-37ea95ca-db99-4b3b-8ec7-5c290b56ae2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39057
48567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3905748567
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3124231842
Short name T538
Test name
Test status
Simulation time 8411463552 ps
CPU time 7.35 seconds
Started Mar 05 01:06:15 PM PST 24
Finished Mar 05 01:06:23 PM PST 24
Peak memory 202316 kb
Host smart-55abddb0-7e18-4b99-8edf-21297e4a19df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31242
31842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3124231842
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2250576438
Short name T572
Test name
Test status
Simulation time 8362543709 ps
CPU time 9.74 seconds
Started Mar 05 01:06:29 PM PST 24
Finished Mar 05 01:06:38 PM PST 24
Peak memory 202468 kb
Host smart-3d47faf5-c47d-4928-861a-9a1b310d6ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22505
76438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2250576438
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.354111639
Short name T182
Test name
Test status
Simulation time 8372830292 ps
CPU time 7.89 seconds
Started Mar 05 01:06:06 PM PST 24
Finished Mar 05 01:06:14 PM PST 24
Peak memory 202476 kb
Host smart-b13a030b-c765-48ae-8389-313c118c9e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35411
1639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.354111639
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1126555727
Short name T540
Test name
Test status
Simulation time 8371511870 ps
CPU time 7.72 seconds
Started Mar 05 01:06:26 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 202436 kb
Host smart-f696a310-3b06-422a-9024-62ee39e09e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11265
55727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1126555727
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.2069869735
Short name T43
Test name
Test status
Simulation time 51731163 ps
CPU time 1.48 seconds
Started Mar 05 01:06:14 PM PST 24
Finished Mar 05 01:06:16 PM PST 24
Peak memory 202492 kb
Host smart-37a8532a-a629-4f00-98e7-ca2f6ca995e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20698
69735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2069869735
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.4134975454
Short name T271
Test name
Test status
Simulation time 8407759371 ps
CPU time 8.06 seconds
Started Mar 05 01:06:12 PM PST 24
Finished Mar 05 01:06:21 PM PST 24
Peak memory 202612 kb
Host smart-7e9a960d-cd3f-451d-80e6-da9e972278fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41349
75454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.4134975454
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3499354901
Short name T302
Test name
Test status
Simulation time 8378965732 ps
CPU time 7.55 seconds
Started Mar 05 01:06:17 PM PST 24
Finished Mar 05 01:06:25 PM PST 24
Peak memory 202308 kb
Host smart-ddca536e-2076-48ce-bd30-e21b33e06e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34993
54901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3499354901
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2228656672
Short name T267
Test name
Test status
Simulation time 8389592554 ps
CPU time 8.4 seconds
Started Mar 05 01:06:15 PM PST 24
Finished Mar 05 01:06:24 PM PST 24
Peak memory 202296 kb
Host smart-26cc5b5f-285a-49ef-93a0-8933bac25cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22286
56672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2228656672
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2659171798
Short name T68
Test name
Test status
Simulation time 8393818379 ps
CPU time 7.67 seconds
Started Mar 05 01:06:15 PM PST 24
Finished Mar 05 01:06:23 PM PST 24
Peak memory 202428 kb
Host smart-3d448d24-ef35-4fe3-92f9-fad4716110c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
71798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2659171798
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.589536535
Short name T18
Test name
Test status
Simulation time 8466963752 ps
CPU time 7.08 seconds
Started Mar 05 01:06:14 PM PST 24
Finished Mar 05 01:06:21 PM PST 24
Peak memory 202360 kb
Host smart-7352e995-61bb-4856-a280-77aa7065028b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58953
6535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.589536535
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.2489130067
Short name T174
Test name
Test status
Simulation time 8412206363 ps
CPU time 8.65 seconds
Started Mar 05 01:06:17 PM PST 24
Finished Mar 05 01:06:26 PM PST 24
Peak memory 202456 kb
Host smart-6ec0ff39-fe6c-4580-9a3e-a2d313b74fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24891
30067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.2489130067
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4234669262
Short name T274
Test name
Test status
Simulation time 8374715101 ps
CPU time 7.44 seconds
Started Mar 05 01:06:14 PM PST 24
Finished Mar 05 01:06:21 PM PST 24
Peak memory 202460 kb
Host smart-397aa688-184f-46cf-ba2f-134f510fcefb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42346
69262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4234669262
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.649086435
Short name T583
Test name
Test status
Simulation time 8370440654 ps
CPU time 7.58 seconds
Started Mar 05 01:06:16 PM PST 24
Finished Mar 05 01:06:24 PM PST 24
Peak memory 202476 kb
Host smart-4eaf88dd-0f21-4685-8c60-aa97f2d8b363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64908
6435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.649086435
Directory /workspace/9.usbdev_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%