Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2005	1		T1	3		T2	5		T3	4
all_values[1]	2005	1		T1	3		T2	5		T3	4
all_values[2]	2005	1		T1	3		T2	5		T3	4
all_values[3]	2005	1		T1	3		T2	5		T3	4
all_values[4]	2005	1		T1	3		T2	5		T3	4
all_values[5]	2005	1		T1	3		T2	5		T3	4
all_values[6]	2005	1		T1	3		T2	5		T3	4
all_values[7]	2005	1		T1	3		T2	5		T3	4
all_values[8]	2005	1		T1	3		T2	5		T3	4
all_values[9]	2005	1		T1	3		T2	5		T3	4
all_values[10]	2005	1		T1	3		T2	5		T3	4
all_values[11]	2005	1		T1	3		T2	5		T3	4
all_values[12]	2005	1		T1	3		T2	5		T3	4
all_values[13]	2005	1		T1	3		T2	5		T3	4
all_values[14]	2005	1		T1	3		T2	5		T3	4
all_values[15]	2005	1		T1	3		T2	5		T3	4
all_values[16]	2005	1		T1	3		T2	5		T3	4
all_values[17]	2005	1		T1	3		T2	5		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33713	1		T1	54		T2	87		T3	70
auto[1]	2377	1		T2	3		T3	2		T17	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32892	1		T1	54		T2	90		T3	72
auto[1]	3198	1		T52	115		T53	122		T54	56

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1568	1		T1	3		T2	5		T3	4
all_values[0]	auto[0]	auto[1]	79	1		T52	5		T53	3		T54	3
all_values[0]	auto[1]	auto[0]	262	1		T17	3		T14	2		T15	2
all_values[0]	auto[1]	auto[1]	96	1		T52	2		T53	5		T54	1
all_values[1]	auto[0]	auto[0]	1568	1		T1	3		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	90	1		T52	7		T54	3		T55	1
all_values[1]	auto[1]	auto[0]	264	1		T2	3		T3	2		T10	2
all_values[1]	auto[1]	auto[1]	83	1		T52	1		T54	1		T55	4
all_values[2]	auto[0]	auto[0]	1808	1		T1	3		T2	5		T3	4
all_values[2]	auto[0]	auto[1]	83	1		T52	1		T53	3		T54	1
all_values[2]	auto[1]	auto[0]	12	1		T52	1		T212	2		T213	1
all_values[2]	auto[1]	auto[1]	102	1		T52	5		T53	5		T54	2
all_values[3]	auto[0]	auto[0]	1813	1		T1	3		T2	5		T3	4
all_values[3]	auto[0]	auto[1]	83	1		T52	6		T54	1		T55	3
all_values[3]	auto[1]	auto[0]	20	1		T55	1		T214	4		T215	1
all_values[3]	auto[1]	auto[1]	89	1		T52	2		T53	7		T54	3
all_values[4]	auto[0]	auto[0]	1812	1		T1	3		T2	5		T3	4
all_values[4]	auto[0]	auto[1]	91	1		T52	2		T53	1		T54	3
all_values[4]	auto[1]	auto[0]	21	1		T52	1		T53	1		T55	2
all_values[4]	auto[1]	auto[1]	81	1		T52	4		T53	6		T54	1
all_values[5]	auto[0]	auto[0]	1810	1		T1	3		T2	5		T3	4
all_values[5]	auto[0]	auto[1]	93	1		T53	4		T54	1		T55	2
all_values[5]	auto[1]	auto[0]	21	1		T52	2		T56	1		T214	3
all_values[5]	auto[1]	auto[1]	81	1		T52	3		T53	4		T54	2
all_values[6]	auto[0]	auto[0]	1812	1		T1	3		T2	5		T3	4
all_values[6]	auto[0]	auto[1]	94	1		T52	5		T53	3		T56	3
all_values[6]	auto[1]	auto[0]	17	1		T54	1		T56	1		T216	1
all_values[6]	auto[1]	auto[1]	82	1		T52	2		T53	4		T55	5
all_values[7]	auto[0]	auto[0]	1809	1		T1	3		T2	5		T3	4
all_values[7]	auto[0]	auto[1]	90	1		T52	2		T53	3		T55	1
all_values[7]	auto[1]	auto[0]	15	1		T53	1		T56	1		T216	1
all_values[7]	auto[1]	auto[1]	91	1		T52	6		T53	4		T54	4
all_values[8]	auto[0]	auto[0]	1813	1		T1	3		T2	5		T3	4
all_values[8]	auto[0]	auto[1]	73	1		T52	4		T53	1		T55	3
all_values[8]	auto[1]	auto[0]	14	1		T54	4		T56	1		T217	2
all_values[8]	auto[1]	auto[1]	105	1		T52	3		T53	6		T55	2
all_values[9]	auto[0]	auto[0]	1808	1		T1	3		T2	5		T3	4
all_values[9]	auto[0]	auto[1]	104	1		T52	5		T53	5		T55	3
all_values[9]	auto[1]	auto[0]	11	1		T217	1		T218	1		T219	2
all_values[9]	auto[1]	auto[1]	82	1		T52	2		T53	2		T54	4
all_values[10]	auto[0]	auto[0]	1801	1		T1	3		T2	5		T3	4
all_values[10]	auto[0]	auto[1]	99	1		T52	2		T53	4		T55	4
all_values[10]	auto[1]	auto[0]	25	1		T54	3		T56	1		T216	4
all_values[10]	auto[1]	auto[1]	80	1		T52	6		T53	4		T55	1
all_values[11]	auto[0]	auto[0]	1806	1		T1	3		T2	5		T3	4
all_values[11]	auto[0]	auto[1]	113	1		T52	3		T53	5		T54	3
all_values[11]	auto[1]	auto[0]	19	1		T52	2		T215	1		T220	1
all_values[11]	auto[1]	auto[1]	67	1		T52	2		T53	3		T54	1
all_values[12]	auto[0]	auto[0]	1809	1		T1	3		T2	5		T3	4
all_values[12]	auto[0]	auto[1]	84	1		T53	4		T54	2		T56	3
all_values[12]	auto[1]	auto[0]	33	1		T52	1		T54	1		T55	1
all_values[12]	auto[1]	auto[1]	79	1		T52	4		T53	1		T56	2
all_values[13]	auto[0]	auto[0]	1813	1		T1	3		T2	5		T3	4
all_values[13]	auto[0]	auto[1]	97	1		T53	7		T54	3		T55	3
all_values[13]	auto[1]	auto[0]	12	1		T52	2		T215	1		T221	1
all_values[13]	auto[1]	auto[1]	83	1		T52	3		T53	1		T54	1
all_values[14]	auto[0]	auto[0]	1811	1		T1	3		T2	5		T3	4
all_values[14]	auto[0]	auto[1]	104	1		T52	4		T53	1		T54	3
all_values[14]	auto[1]	auto[0]	12	1		T56	1		T222	1		T223	1
all_values[14]	auto[1]	auto[1]	78	1		T52	3		T53	7		T54	1
all_values[15]	auto[0]	auto[0]	1806	1		T1	3		T2	5		T3	4
all_values[15]	auto[0]	auto[1]	84	1		T52	6		T53	1		T54	2
all_values[15]	auto[1]	auto[0]	11	1		T222	4		T220	1		T224	1
all_values[15]	auto[1]	auto[1]	104	1		T52	1		T53	7		T54	2
all_values[16]	auto[0]	auto[0]	1810	1		T1	3		T2	5		T3	4
all_values[16]	auto[0]	auto[1]	77	1		T52	4		T53	5		T54	2
all_values[16]	auto[1]	auto[0]	17	1		T52	1		T215	1		T213	4
all_values[16]	auto[1]	auto[1]	101	1		T52	3		T53	2		T54	2
all_values[17]	auto[0]	auto[0]	1806	1		T1	3		T2	5		T3	4
all_values[17]	auto[0]	auto[1]	92	1		T52	3		T53	1		T54	1
all_values[17]	auto[1]	auto[0]	23	1		T53	3		T217	1		T216	1
all_values[17]	auto[1]	auto[1]	84	1		T52	4		T53	3		T54	3