Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2005	1		T1	3		T2	5		T3	4
all_pins[1]	2005	1		T1	3		T2	5		T3	4
all_pins[2]	2005	1		T1	3		T2	5		T3	4
all_pins[3]	2005	1		T1	3		T2	5		T3	4
all_pins[4]	2005	1		T1	3		T2	5		T3	4
all_pins[5]	2005	1		T1	3		T2	5		T3	4
all_pins[6]	2005	1		T1	3		T2	5		T3	4
all_pins[7]	2005	1		T1	3		T2	5		T3	4
all_pins[8]	2005	1		T1	3		T2	5		T3	4
all_pins[9]	2005	1		T1	3		T2	5		T3	4
all_pins[10]	2005	1		T1	3		T2	5		T3	4
all_pins[11]	2005	1		T1	3		T2	5		T3	4
all_pins[12]	2005	1		T1	3		T2	5		T3	4
all_pins[13]	2005	1		T1	3		T2	5		T3	4
all_pins[14]	2005	1		T1	3		T2	5		T3	4
all_pins[15]	2005	1		T1	3		T2	5		T3	4
all_pins[16]	2005	1		T1	3		T2	5		T3	4
all_pins[17]	2005	1		T1	3		T2	5		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	35313	1		T1	54		T2	89		T3	71
values[0x1]	777	1		T2	1		T3	1		T10	1
transitions[0x0=>0x1]	614	1		T2	1		T3	1		T10	1
transitions[0x1=>0x0]	616	1		T2	1		T3	1		T10	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1977	1		T1	3		T2	5		T3	4
all_pins[0]	values[0x1]	28	1		T52	1		T53	2		T56	1
all_pins[0]	transitions[0x0=>0x1]	23	1		T53	2		T56	1		T214	1
all_pins[0]	transitions[0x1=>0x0]	117	1		T2	1		T3	1		T10	1
all_pins[1]	values[0x0]	1883	1		T1	3		T2	4		T3	3
all_pins[1]	values[0x1]	122	1		T2	1		T3	1		T10	1
all_pins[1]	transitions[0x0=>0x1]	115	1		T2	1		T3	1		T10	1
all_pins[1]	transitions[0x1=>0x0]	32	1		T52	1		T53	1		T55	1
all_pins[2]	values[0x0]	1966	1		T1	3		T2	5		T3	4
all_pins[2]	values[0x1]	39	1		T52	1		T53	1		T55	1
all_pins[2]	transitions[0x0=>0x1]	28	1		T52	1		T53	1		T56	1
all_pins[2]	transitions[0x1=>0x0]	34	1		T52	2		T53	4		T54	1
all_pins[3]	values[0x0]	1960	1		T1	3		T2	5		T3	4
all_pins[3]	values[0x1]	45	1		T52	2		T53	4		T54	1
all_pins[3]	transitions[0x0=>0x1]	39	1		T52	2		T53	3		T54	1
all_pins[3]	transitions[0x1=>0x0]	40	1		T52	3		T53	1		T54	1
all_pins[4]	values[0x0]	1959	1		T1	3		T2	5		T3	4
all_pins[4]	values[0x1]	46	1		T52	3		T53	2		T54	1
all_pins[4]	transitions[0x0=>0x1]	32	1		T52	1		T53	2		T54	1
all_pins[4]	transitions[0x1=>0x0]	30	1		T53	2		T217	3		T225	2
all_pins[5]	values[0x0]	1961	1		T1	3		T2	5		T3	4
all_pins[5]	values[0x1]	44	1		T52	2		T53	2		T55	2
all_pins[5]	transitions[0x0=>0x1]	34	1		T52	2		T53	2		T55	2
all_pins[5]	transitions[0x1=>0x0]	24	1		T53	1		T56	1		T216	1
all_pins[6]	values[0x0]	1971	1		T1	3		T2	5		T3	4
all_pins[6]	values[0x1]	34	1		T53	1		T56	1		T216	1
all_pins[6]	transitions[0x0=>0x1]	28	1		T53	1		T214	2		T215	1
all_pins[6]	transitions[0x1=>0x0]	33	1		T52	4		T53	2		T54	2
all_pins[7]	values[0x0]	1966	1		T1	3		T2	5		T3	4
all_pins[7]	values[0x1]	39	1		T52	4		T53	2		T54	2
all_pins[7]	transitions[0x0=>0x1]	26	1		T52	3		T53	1		T54	2
all_pins[7]	transitions[0x1=>0x0]	33	1		T52	1		T55	2		T216	1
all_pins[8]	values[0x0]	1959	1		T1	3		T2	5		T3	4
all_pins[8]	values[0x1]	46	1		T52	2		T53	1		T55	2
all_pins[8]	transitions[0x0=>0x1]	39	1		T52	1		T53	1		T55	2
all_pins[8]	transitions[0x1=>0x0]	25	1		T53	1		T54	1		T225	3
all_pins[9]	values[0x0]	1973	1		T1	3		T2	5		T3	4
all_pins[9]	values[0x1]	32	1		T52	1		T53	1		T54	1
all_pins[9]	transitions[0x0=>0x1]	23	1		T53	1		T54	1		T225	3
all_pins[9]	transitions[0x1=>0x0]	28	1		T52	2		T53	1		T55	1
all_pins[10]	values[0x0]	1968	1		T1	3		T2	5		T3	4
all_pins[10]	values[0x1]	37	1		T52	3		T53	1		T55	1
all_pins[10]	transitions[0x0=>0x1]	27	1		T52	2		T55	1		T217	2
all_pins[10]	transitions[0x1=>0x0]	25	1		T53	2		T55	2		T56	1
all_pins[11]	values[0x0]	1970	1		T1	3		T2	5		T3	4
all_pins[11]	values[0x1]	35	1		T52	1		T53	3		T55	2
all_pins[11]	transitions[0x0=>0x1]	29	1		T52	1		T53	3		T55	2
all_pins[11]	transitions[0x1=>0x0]	34	1		T52	3		T56	1		T217	1
all_pins[12]	values[0x0]	1965	1		T1	3		T2	5		T3	4
all_pins[12]	values[0x1]	40	1		T52	3		T56	2		T217	3
all_pins[12]	transitions[0x0=>0x1]	28	1		T52	1		T56	2		T217	2
all_pins[12]	transitions[0x1=>0x0]	27	1		T53	1		T55	2		T56	2
all_pins[13]	values[0x0]	1966	1		T1	3		T2	5		T3	4
all_pins[13]	values[0x1]	39	1		T52	2		T53	1		T55	2
all_pins[13]	transitions[0x0=>0x1]	31	1		T52	2		T55	2		T56	2
all_pins[13]	transitions[0x1=>0x0]	22	1		T52	2		T54	1		T55	2
all_pins[14]	values[0x0]	1975	1		T1	3		T2	5		T3	4
all_pins[14]	values[0x1]	30	1		T52	2		T53	1		T54	1
all_pins[14]	transitions[0x0=>0x1]	21	1		T52	1		T55	2		T225	2
all_pins[14]	transitions[0x1=>0x0]	42	1		T53	2		T54	1		T55	1
all_pins[15]	values[0x0]	1954	1		T1	3		T2	5		T3	4
all_pins[15]	values[0x1]	51	1		T52	1		T53	3		T54	2
all_pins[15]	transitions[0x0=>0x1]	38	1		T52	1		T53	2		T55	1
all_pins[15]	transitions[0x1=>0x0]	31	1		T52	1		T53	1		T56	3
all_pins[16]	values[0x0]	1961	1		T1	3		T2	5		T3	4
all_pins[16]	values[0x1]	44	1		T52	1		T53	2		T54	2
all_pins[16]	transitions[0x0=>0x1]	33	1		T52	1		T53	2		T54	2
all_pins[16]	transitions[0x1=>0x0]	15	1		T52	2		T53	1		T54	1
all_pins[17]	values[0x0]	1979	1		T1	3		T2	5		T3	4
all_pins[17]	values[0x1]	26	1		T52	2		T53	1		T54	1
all_pins[17]	transitions[0x0=>0x1]	20	1		T52	2		T54	1		T56	1
all_pins[17]	transitions[0x1=>0x0]	24	1		T52	1		T53	1		T214	1