Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	179	1		T52	7		T53	7		T54	4
all_values[1]	179	1		T52	7		T53	7		T54	4
all_values[2]	179	1		T52	7		T53	7		T54	4
all_values[3]	179	1		T52	7		T53	7		T54	4
all_values[4]	179	1		T52	7		T53	7		T54	4
all_values[5]	179	1		T52	7		T53	7		T54	4
all_values[6]	179	1		T52	7		T53	7		T54	4
all_values[7]	179	1		T52	7		T53	7		T54	4
all_values[8]	179	1		T52	7		T53	7		T54	4
all_values[9]	179	1		T52	7		T53	7		T54	4
all_values[10]	179	1		T52	7		T53	7		T54	4
all_values[11]	179	1		T52	7		T53	7		T54	4
all_values[12]	179	1		T52	7		T53	7		T54	4
all_values[13]	179	1		T52	7		T53	7		T54	4
all_values[14]	179	1		T52	7		T53	7		T54	4
all_values[15]	179	1		T52	7		T53	7		T54	4
all_values[16]	179	1		T52	7		T53	7		T54	4
all_values[17]	179	1		T52	7		T53	7		T54	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1785	1		T52	76		T53	59		T54	48
auto[1]	1437	1		T52	50		T53	67		T54	24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	588	1		T52	29		T53	21		T54	16
auto[1]	2634	1		T52	97		T53	105		T54	56

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1927	1		T52	80		T53	68		T54	44
auto[1]	1295	1		T52	46		T53	58		T54	28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	20	1		T52	1		T55	4		T225	2
all_values[0]	auto[0]	auto[0]	auto[1]	37	1		T52	3		T53	2		T54	1
all_values[0]	auto[0]	auto[1]	auto[0]	14	1		T217	2		T225	2		T226	2
all_values[0]	auto[0]	auto[1]	auto[1]	45	1		T52	1		T53	1		T54	1
all_values[0]	auto[1]	auto[0]	auto[1]	39	1		T52	1		T53	2		T54	2
all_values[0]	auto[1]	auto[1]	auto[1]	24	1		T52	1		T53	2		T56	1
all_values[1]	auto[0]	auto[0]	auto[0]	19	1		T53	4		T56	2		T216	2
all_values[1]	auto[0]	auto[0]	auto[1]	37	1		T52	3		T54	1		T55	1
all_values[1]	auto[0]	auto[1]	auto[0]	17	1		T53	3		T214	2		T215	2
all_values[1]	auto[0]	auto[1]	auto[1]	34	1		T55	2		T217	3		T216	1
all_values[1]	auto[1]	auto[0]	auto[1]	43	1		T52	3		T54	3		T55	1
all_values[1]	auto[1]	auto[1]	auto[1]	29	1		T52	1		T217	3		T225	1
all_values[2]	auto[0]	auto[0]	auto[0]	16	1		T52	2		T54	1		T227	2
all_values[2]	auto[0]	auto[0]	auto[1]	35	1		T217	1		T225	2		T216	1
all_values[2]	auto[0]	auto[1]	auto[0]	11	1		T212	3		T213	1		T228	2
all_values[2]	auto[0]	auto[1]	auto[1]	43	1		T52	4		T53	1		T54	2
all_values[2]	auto[1]	auto[0]	auto[1]	40	1		T53	2		T54	1		T55	2
all_values[2]	auto[1]	auto[1]	auto[1]	34	1		T52	1		T53	4		T56	1
all_values[3]	auto[0]	auto[0]	auto[0]	22	1		T53	1		T216	1		T220	3
all_values[3]	auto[0]	auto[0]	auto[1]	31	1		T52	4		T55	2		T56	2
all_values[3]	auto[0]	auto[1]	auto[0]	15	1		T55	1		T214	4		T215	1
all_values[3]	auto[0]	auto[1]	auto[1]	33	1		T52	1		T53	4		T54	1
all_values[3]	auto[1]	auto[0]	auto[1]	43	1		T52	2		T53	1		T54	2
all_values[3]	auto[1]	auto[1]	auto[1]	35	1		T53	1		T54	1		T55	1
all_values[4]	auto[0]	auto[0]	auto[0]	21	1		T52	2		T56	1		T217	3
all_values[4]	auto[0]	auto[0]	auto[1]	30	1		T54	1		T56	1		T216	1
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T53	1		T55	2		T217	4
all_values[4]	auto[0]	auto[1]	auto[1]	31	1		T52	2		T53	2		T54	1
all_values[4]	auto[1]	auto[0]	auto[1]	44	1		T52	1		T53	1		T54	2
all_values[4]	auto[1]	auto[1]	auto[1]	36	1		T52	2		T53	3		T55	1
all_values[5]	auto[0]	auto[0]	auto[0]	22	1		T52	3		T54	1		T56	3
all_values[5]	auto[0]	auto[0]	auto[1]	38	1		T53	2		T55	1		T217	1
all_values[5]	auto[0]	auto[1]	auto[0]	14	1		T52	2		T56	1		T214	2
all_values[5]	auto[0]	auto[1]	auto[1]	33	1		T52	1		T53	1		T54	1
all_values[5]	auto[1]	auto[0]	auto[1]	43	1		T53	2		T54	1		T55	1
all_values[5]	auto[1]	auto[1]	auto[1]	29	1		T52	1		T53	2		T54	1
all_values[6]	auto[0]	auto[0]	auto[0]	20	1		T52	1		T53	1		T54	4
all_values[6]	auto[0]	auto[0]	auto[1]	41	1		T52	2		T53	1		T56	1
all_values[6]	auto[0]	auto[1]	auto[0]	14	1		T214	2		T221	2		T223	1
all_values[6]	auto[0]	auto[1]	auto[1]	39	1		T52	1		T53	2		T55	3
all_values[6]	auto[1]	auto[0]	auto[1]	35	1		T52	2		T53	2		T217	1
all_values[6]	auto[1]	auto[1]	auto[1]	30	1		T52	1		T53	1		T55	1
all_values[7]	auto[0]	auto[0]	auto[0]	21	1		T56	1		T225	2		T216	1
all_values[7]	auto[0]	auto[0]	auto[1]	32	1		T55	1		T56	1		T217	3
all_values[7]	auto[0]	auto[1]	auto[0]	9	1		T53	1		T215	1		T222	1
all_values[7]	auto[0]	auto[1]	auto[1]	38	1		T52	1		T53	1		T54	2
all_values[7]	auto[1]	auto[0]	auto[1]	40	1		T52	2		T53	2		T54	1
all_values[7]	auto[1]	auto[1]	auto[1]	39	1		T52	4		T53	3		T54	1
all_values[8]	auto[0]	auto[0]	auto[0]	23	1		T52	1		T53	1		T54	1
all_values[8]	auto[0]	auto[0]	auto[1]	25	1		T52	2		T53	1		T55	1
all_values[8]	auto[0]	auto[1]	auto[0]	10	1		T54	3		T56	1		T217	2
all_values[8]	auto[0]	auto[1]	auto[1]	38	1		T52	1		T53	3		T225	2
all_values[8]	auto[1]	auto[0]	auto[1]	48	1		T52	2		T53	1		T55	1
all_values[8]	auto[1]	auto[1]	auto[1]	35	1		T52	1		T53	1		T55	2
all_values[9]	auto[0]	auto[0]	auto[0]	18	1		T52	1		T53	1		T56	2
all_values[9]	auto[0]	auto[0]	auto[1]	50	1		T52	2		T53	1		T55	2
all_values[9]	auto[0]	auto[1]	auto[0]	7	1		T217	1		T218	1		T219	1
all_values[9]	auto[0]	auto[1]	auto[1]	39	1		T52	1		T53	1		T54	2
all_values[9]	auto[1]	auto[0]	auto[1]	39	1		T52	2		T53	4		T54	1
all_values[9]	auto[1]	auto[1]	auto[1]	26	1		T52	1		T54	1		T55	1
all_values[10]	auto[0]	auto[0]	auto[0]	13	1		T54	2		T56	1		T216	1
all_values[10]	auto[0]	auto[0]	auto[1]	39	1		T52	1		T53	2		T55	1
all_values[10]	auto[0]	auto[1]	auto[0]	19	1		T54	2		T216	3		T214	2
all_values[10]	auto[0]	auto[1]	auto[1]	37	1		T52	3		T53	1		T217	1
all_values[10]	auto[1]	auto[0]	auto[1]	42	1		T52	2		T53	2		T55	3
all_values[10]	auto[1]	auto[1]	auto[1]	29	1		T52	1		T53	2		T56	1
all_values[11]	auto[0]	auto[0]	auto[0]	16	1		T52	2		T215	2		T226	2
all_values[11]	auto[0]	auto[0]	auto[1]	48	1		T52	1		T53	1		T54	3
all_values[11]	auto[0]	auto[1]	auto[0]	14	1		T52	1		T215	2		T220	1
all_values[11]	auto[0]	auto[1]	auto[1]	33	1		T52	1		T53	2		T55	1
all_values[11]	auto[1]	auto[0]	auto[1]	44	1		T52	1		T53	2		T54	1
all_values[11]	auto[1]	auto[1]	auto[1]	24	1		T52	1		T53	2		T55	1
all_values[12]	auto[0]	auto[0]	auto[0]	20	1		T52	3		T53	3		T54	2
all_values[12]	auto[0]	auto[0]	auto[1]	38	1		T53	2		T54	1		T56	1
all_values[12]	auto[0]	auto[1]	auto[0]	24	1		T52	1		T55	2		T217	1
all_values[12]	auto[0]	auto[1]	auto[1]	30	1		T52	2		T53	1		T217	3
all_values[12]	auto[1]	auto[0]	auto[1]	39	1		T52	1		T53	1		T54	1
all_values[12]	auto[1]	auto[1]	auto[1]	28	1		T56	2		T217	3		T215	1
all_values[13]	auto[0]	auto[0]	auto[0]	27	1		T52	4		T56	2		T215	2
all_values[13]	auto[0]	auto[0]	auto[1]	39	1		T53	3		T54	3		T55	2
all_values[13]	auto[0]	auto[1]	auto[0]	5	1		T52	1		T221	1		T229	2
all_values[13]	auto[0]	auto[1]	auto[1]	36	1		T52	1		T53	1		T55	1
all_values[13]	auto[1]	auto[0]	auto[1]	46	1		T53	2		T54	1		T56	1
all_values[13]	auto[1]	auto[1]	auto[1]	26	1		T52	1		T53	1		T55	1
all_values[14]	auto[0]	auto[0]	auto[0]	21	1		T52	1		T56	2		T217	1
all_values[14]	auto[0]	auto[0]	auto[1]	52	1		T52	3		T54	3		T56	1
all_values[14]	auto[0]	auto[1]	auto[0]	10	1		T222	1		T223	1		T228	3
all_values[14]	auto[0]	auto[1]	auto[1]	30	1		T52	1		T53	4		T55	2
all_values[14]	auto[1]	auto[0]	auto[1]	42	1		T52	1		T53	1		T54	1
all_values[14]	auto[1]	auto[1]	auto[1]	24	1		T52	1		T53	2		T56	1
all_values[15]	auto[0]	auto[0]	auto[0]	16	1		T52	1		T225	1		T214	4
all_values[15]	auto[0]	auto[0]	auto[1]	38	1		T52	4		T54	1		T55	1
all_values[15]	auto[0]	auto[1]	auto[0]	7	1		T222	3		T220	1		T224	1
all_values[15]	auto[0]	auto[1]	auto[1]	42	1		T53	3		T55	1		T56	1
all_values[15]	auto[1]	auto[0]	auto[1]	41	1		T52	1		T53	1		T54	2
all_values[15]	auto[1]	auto[1]	auto[1]	35	1		T52	1		T53	3		T54	1
all_values[16]	auto[0]	auto[0]	auto[0]	21	1		T52	1		T53	1		T223	1
all_values[16]	auto[0]	auto[0]	auto[1]	29	1		T52	2		T53	1		T54	2
all_values[16]	auto[0]	auto[1]	auto[0]	10	1		T215	1		T213	3		T230	1
all_values[16]	auto[0]	auto[1]	auto[1]	45	1		T52	1		T53	2		T56	1
all_values[16]	auto[1]	auto[0]	auto[1]	44	1		T52	1		T53	3		T54	1
all_values[16]	auto[1]	auto[1]	auto[1]	30	1		T52	2		T54	1		T56	1
all_values[17]	auto[0]	auto[0]	auto[0]	18	1		T52	1		T53	2		T216	1
all_values[17]	auto[0]	auto[0]	auto[1]	37	1		T55	1		T217	2		T225	3
all_values[17]	auto[0]	auto[1]	auto[0]	17	1		T53	2		T217	2		T216	1
all_values[17]	auto[0]	auto[1]	auto[1]	37	1		T52	2		T53	1		T54	2
all_values[17]	auto[1]	auto[0]	auto[1]	43	1		T52	3		T54	1		T55	1
all_values[17]	auto[1]	auto[1]	auto[1]	27	1		T52	1		T53	2		T54	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal