Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.74 95.98 88.14 97.17 45.31 94.01 97.36 96.22


Total test records in report: 715
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T197 /workspace/coverage/default/39.usbdev_fifo_rst.266388971 Mar 07 01:50:29 PM PST 24 Mar 07 01:50:31 PM PST 24 193866281 ps
T587 /workspace/coverage/default/27.usbdev_smoke.968066278 Mar 07 01:49:54 PM PST 24 Mar 07 01:50:02 PM PST 24 8470647994 ps
T46 /workspace/coverage/default/3.usbdev_sec_cm.3320081749 Mar 07 01:48:41 PM PST 24 Mar 07 01:48:43 PM PST 24 446769589 ps
T82 /workspace/coverage/default/10.usbdev_nak_trans.3848933179 Mar 07 01:49:10 PM PST 24 Mar 07 01:49:19 PM PST 24 8484230820 ps
T588 /workspace/coverage/default/5.usbdev_smoke.3989141881 Mar 07 01:48:38 PM PST 24 Mar 07 01:48:48 PM PST 24 8478019190 ps
T589 /workspace/coverage/default/28.usbdev_out_stall.3991800040 Mar 07 01:50:10 PM PST 24 Mar 07 01:50:18 PM PST 24 8402077378 ps
T590 /workspace/coverage/default/23.usbdev_setup_trans_ignored.1539569323 Mar 07 01:49:43 PM PST 24 Mar 07 01:49:51 PM PST 24 8363550964 ps
T591 /workspace/coverage/default/21.usbdev_min_length_out_transaction.397757882 Mar 07 01:49:32 PM PST 24 Mar 07 01:49:41 PM PST 24 8364543239 ps
T592 /workspace/coverage/default/26.usbdev_in_trans.3354610543 Mar 07 01:49:46 PM PST 24 Mar 07 01:49:53 PM PST 24 8379987632 ps
T593 /workspace/coverage/default/17.usbdev_pkt_sent.1116836398 Mar 07 01:49:24 PM PST 24 Mar 07 01:49:31 PM PST 24 8449718748 ps
T594 /workspace/coverage/default/15.usbdev_min_length_out_transaction.562624051 Mar 07 01:49:25 PM PST 24 Mar 07 01:49:34 PM PST 24 8367247976 ps
T595 /workspace/coverage/default/35.usbdev_max_length_out_transaction.2779652642 Mar 07 01:50:27 PM PST 24 Mar 07 01:50:35 PM PST 24 8419754655 ps
T596 /workspace/coverage/default/32.usbdev_random_length_out_trans.1446961411 Mar 07 01:50:18 PM PST 24 Mar 07 01:50:27 PM PST 24 8372007679 ps
T597 /workspace/coverage/default/19.usbdev_in_trans.492826909 Mar 07 01:49:33 PM PST 24 Mar 07 01:49:42 PM PST 24 8380704817 ps
T598 /workspace/coverage/default/6.usbdev_av_buffer.1413247551 Mar 07 01:48:44 PM PST 24 Mar 07 01:48:52 PM PST 24 8367994961 ps
T599 /workspace/coverage/default/38.usbdev_out_stall.1530996612 Mar 07 01:50:27 PM PST 24 Mar 07 01:50:35 PM PST 24 8372337032 ps
T600 /workspace/coverage/default/30.usbdev_max_length_out_transaction.1275788307 Mar 07 01:50:18 PM PST 24 Mar 07 01:50:28 PM PST 24 8436199848 ps
T601 /workspace/coverage/default/39.usbdev_max_length_out_transaction.3737814998 Mar 07 01:50:30 PM PST 24 Mar 07 01:50:38 PM PST 24 8437055303 ps
T602 /workspace/coverage/default/38.usbdev_out_trans_nak.42059892 Mar 07 01:50:26 PM PST 24 Mar 07 01:50:34 PM PST 24 8404580676 ps
T603 /workspace/coverage/default/3.usbdev_random_length_out_trans.2600564184 Mar 07 01:48:29 PM PST 24 Mar 07 01:48:37 PM PST 24 8387559046 ps
T604 /workspace/coverage/default/18.usbdev_av_buffer.2001219079 Mar 07 01:49:32 PM PST 24 Mar 07 01:49:41 PM PST 24 8373595936 ps
T605 /workspace/coverage/default/40.usbdev_min_length_out_transaction.1876820880 Mar 07 01:50:32 PM PST 24 Mar 07 01:50:42 PM PST 24 8367431667 ps
T606 /workspace/coverage/default/33.usbdev_max_length_out_transaction.410856970 Mar 07 01:50:21 PM PST 24 Mar 07 01:50:28 PM PST 24 8405555023 ps
T80 /workspace/coverage/default/43.usbdev_nak_trans.1727127383 Mar 07 01:50:48 PM PST 24 Mar 07 01:50:56 PM PST 24 8439385854 ps
T198 /workspace/coverage/default/45.usbdev_fifo_rst.2507211851 Mar 07 01:50:44 PM PST 24 Mar 07 01:50:46 PM PST 24 81363841 ps
T607 /workspace/coverage/default/46.usbdev_setup_trans_ignored.2571102710 Mar 07 01:50:49 PM PST 24 Mar 07 01:50:57 PM PST 24 8355422311 ps
T608 /workspace/coverage/default/11.usbdev_smoke.695505550 Mar 07 01:49:10 PM PST 24 Mar 07 01:49:18 PM PST 24 8478578723 ps
T194 /workspace/coverage/default/2.usbdev_fifo_rst.106528180 Mar 07 01:48:28 PM PST 24 Mar 07 01:48:30 PM PST 24 243209115 ps
T609 /workspace/coverage/default/45.usbdev_max_length_out_transaction.1451606300 Mar 07 01:50:46 PM PST 24 Mar 07 01:50:54 PM PST 24 8411170251 ps
T139 /workspace/coverage/default/33.usbdev_smoke.3150200023 Mar 07 01:50:18 PM PST 24 Mar 07 01:50:26 PM PST 24 8484583180 ps
T610 /workspace/coverage/default/21.usbdev_setup_trans_ignored.1192620742 Mar 07 01:49:36 PM PST 24 Mar 07 01:49:44 PM PST 24 8447634253 ps
T188 /workspace/coverage/default/49.usbdev_av_buffer.4119155409 Mar 07 01:50:54 PM PST 24 Mar 07 01:51:03 PM PST 24 8372612589 ps
T611 /workspace/coverage/default/9.usbdev_out_stall.1874656714 Mar 07 01:49:08 PM PST 24 Mar 07 01:49:16 PM PST 24 8470634686 ps
T612 /workspace/coverage/default/23.usbdev_pkt_sent.1680178695 Mar 07 01:49:46 PM PST 24 Mar 07 01:49:53 PM PST 24 8432447547 ps
T613 /workspace/coverage/default/29.usbdev_random_length_out_trans.3825267346 Mar 07 01:50:13 PM PST 24 Mar 07 01:50:22 PM PST 24 8402735542 ps
T614 /workspace/coverage/default/28.usbdev_in_trans.915159870 Mar 07 01:50:09 PM PST 24 Mar 07 01:50:17 PM PST 24 8396547362 ps
T615 /workspace/coverage/default/45.usbdev_pkt_sent.3986178453 Mar 07 01:50:41 PM PST 24 Mar 07 01:50:49 PM PST 24 8455267991 ps
T616 /workspace/coverage/default/15.usbdev_pkt_sent.3938476921 Mar 07 01:49:23 PM PST 24 Mar 07 01:49:31 PM PST 24 8418158848 ps
T617 /workspace/coverage/default/44.usbdev_out_stall.2949474273 Mar 07 01:50:44 PM PST 24 Mar 07 01:50:51 PM PST 24 8394182002 ps
T618 /workspace/coverage/default/35.usbdev_pkt_sent.4164319654 Mar 07 01:50:27 PM PST 24 Mar 07 01:50:34 PM PST 24 8403819622 ps
T619 /workspace/coverage/default/39.usbdev_out_stall.4030190513 Mar 07 01:50:26 PM PST 24 Mar 07 01:50:34 PM PST 24 8396482991 ps
T620 /workspace/coverage/default/41.usbdev_pkt_sent.1118836900 Mar 07 01:50:41 PM PST 24 Mar 07 01:50:48 PM PST 24 8444571050 ps
T621 /workspace/coverage/default/30.usbdev_pkt_sent.1320978767 Mar 07 01:50:18 PM PST 24 Mar 07 01:50:26 PM PST 24 8535284046 ps
T622 /workspace/coverage/default/16.usbdev_random_length_out_trans.1394784478 Mar 07 01:49:23 PM PST 24 Mar 07 01:49:31 PM PST 24 8415118769 ps
T623 /workspace/coverage/default/42.usbdev_random_length_out_trans.3925664484 Mar 07 01:50:38 PM PST 24 Mar 07 01:50:46 PM PST 24 8377597530 ps
T89 /workspace/coverage/default/3.usbdev_nak_trans.2435304288 Mar 07 01:48:27 PM PST 24 Mar 07 01:48:34 PM PST 24 8424381367 ps
T83 /workspace/coverage/default/40.usbdev_nak_trans.376054937 Mar 07 01:50:38 PM PST 24 Mar 07 01:50:45 PM PST 24 8429242859 ps
T624 /workspace/coverage/default/25.usbdev_setup_trans_ignored.3318469017 Mar 07 01:49:48 PM PST 24 Mar 07 01:49:56 PM PST 24 8366481129 ps
T625 /workspace/coverage/default/0.usbdev_smoke.3331180683 Mar 07 01:48:16 PM PST 24 Mar 07 01:48:24 PM PST 24 8477611291 ps
T91 /workspace/coverage/default/44.usbdev_nak_trans.600958291 Mar 07 01:50:39 PM PST 24 Mar 07 01:50:49 PM PST 24 8430214956 ps
T626 /workspace/coverage/default/18.usbdev_fifo_rst.512643039 Mar 07 01:49:34 PM PST 24 Mar 07 01:49:36 PM PST 24 259428637 ps
T627 /workspace/coverage/default/15.usbdev_out_stall.869375791 Mar 07 01:49:26 PM PST 24 Mar 07 01:49:34 PM PST 24 8368071375 ps
T57 /workspace/coverage/default/4.usbdev_sec_cm.549320118 Mar 07 01:48:36 PM PST 24 Mar 07 01:48:37 PM PST 24 102594560 ps
T628 /workspace/coverage/default/3.usbdev_out_stall.3706624251 Mar 07 01:48:33 PM PST 24 Mar 07 01:48:41 PM PST 24 8463634293 ps
T629 /workspace/coverage/default/7.usbdev_in_trans.3328071419 Mar 07 01:48:43 PM PST 24 Mar 07 01:48:53 PM PST 24 8442392642 ps
T630 /workspace/coverage/default/22.usbdev_max_length_out_transaction.1290494541 Mar 07 01:49:49 PM PST 24 Mar 07 01:49:57 PM PST 24 8411543683 ps
T631 /workspace/coverage/default/24.usbdev_max_length_out_transaction.3020698569 Mar 07 01:49:42 PM PST 24 Mar 07 01:49:49 PM PST 24 8417761425 ps
T632 /workspace/coverage/default/0.usbdev_fifo_rst.58167721 Mar 07 01:48:16 PM PST 24 Mar 07 01:48:18 PM PST 24 262397126 ps
T633 /workspace/coverage/default/10.usbdev_pkt_sent.3577088844 Mar 07 01:49:09 PM PST 24 Mar 07 01:49:19 PM PST 24 8445297826 ps
T634 /workspace/coverage/default/20.usbdev_random_length_out_trans.829199606 Mar 07 01:49:38 PM PST 24 Mar 07 01:49:46 PM PST 24 8368015615 ps
T635 /workspace/coverage/default/7.usbdev_max_length_out_transaction.3059343174 Mar 07 01:48:53 PM PST 24 Mar 07 01:49:02 PM PST 24 8412247974 ps
T636 /workspace/coverage/default/27.usbdev_out_trans_nak.198306691 Mar 07 01:49:54 PM PST 24 Mar 07 01:50:02 PM PST 24 8368509913 ps
T637 /workspace/coverage/default/8.usbdev_av_buffer.1673407411 Mar 07 01:48:55 PM PST 24 Mar 07 01:49:03 PM PST 24 8372683871 ps
T638 /workspace/coverage/default/41.usbdev_min_length_out_transaction.568738480 Mar 07 01:50:37 PM PST 24 Mar 07 01:50:45 PM PST 24 8366040913 ps
T189 /workspace/coverage/default/42.usbdev_fifo_rst.2727470929 Mar 07 01:50:32 PM PST 24 Mar 07 01:50:34 PM PST 24 105008711 ps
T639 /workspace/coverage/default/17.usbdev_setup_trans_ignored.3053244639 Mar 07 01:49:22 PM PST 24 Mar 07 01:49:30 PM PST 24 8368301724 ps
T190 /workspace/coverage/default/26.usbdev_fifo_rst.965595268 Mar 07 01:50:01 PM PST 24 Mar 07 01:50:02 PM PST 24 146209461 ps
T640 /workspace/coverage/default/3.usbdev_fifo_rst.803215724 Mar 07 01:48:37 PM PST 24 Mar 07 01:48:39 PM PST 24 140241696 ps
T641 /workspace/coverage/default/35.usbdev_fifo_rst.4169493618 Mar 07 01:50:26 PM PST 24 Mar 07 01:50:27 PM PST 24 96879959 ps
T642 /workspace/coverage/default/2.usbdev_max_length_out_transaction.4088843457 Mar 07 01:48:27 PM PST 24 Mar 07 01:48:36 PM PST 24 8408556251 ps
T643 /workspace/coverage/default/42.usbdev_in_trans.2243490117 Mar 07 01:50:38 PM PST 24 Mar 07 01:50:47 PM PST 24 8408277305 ps
T644 /workspace/coverage/default/26.usbdev_min_length_out_transaction.2525181035 Mar 07 01:49:50 PM PST 24 Mar 07 01:49:58 PM PST 24 8367795015 ps
T48 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3674866624 Mar 07 01:00:35 PM PST 24 Mar 07 01:00:36 PM PST 24 167992548 ps
T52 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3954287374 Mar 07 01:00:52 PM PST 24 Mar 07 01:00:58 PM PST 24 30274934 ps
T41 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4230590712 Mar 07 01:00:24 PM PST 24 Mar 07 01:00:27 PM PST 24 258169303 ps
T42 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.79213087 Mar 07 01:00:26 PM PST 24 Mar 07 01:00:29 PM PST 24 479239832 ps
T53 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3983666866 Mar 07 01:00:09 PM PST 24 Mar 07 01:00:10 PM PST 24 104535002 ps
T49 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2734566366 Mar 07 01:00:37 PM PST 24 Mar 07 01:00:38 PM PST 24 54763578 ps
T43 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2381860596 Mar 07 01:00:34 PM PST 24 Mar 07 01:00:37 PM PST 24 181817899 ps
T72 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3464933762 Mar 07 01:00:10 PM PST 24 Mar 07 01:00:11 PM PST 24 35706664 ps
T47 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1137784717 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:15 PM PST 24 32553799 ps
T73 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2957887497 Mar 07 01:00:03 PM PST 24 Mar 07 01:00:04 PM PST 24 58290018 ps
T74 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.951959140 Mar 07 01:00:24 PM PST 24 Mar 07 01:00:28 PM PST 24 497861811 ps
T54 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1861128583 Mar 07 01:00:40 PM PST 24 Mar 07 01:00:41 PM PST 24 25960380 ps
T55 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1864088594 Mar 07 01:00:34 PM PST 24 Mar 07 01:00:35 PM PST 24 20509683 ps
T56 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3920273159 Mar 07 01:00:31 PM PST 24 Mar 07 01:00:32 PM PST 24 78260510 ps
T75 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2090986521 Mar 07 01:00:22 PM PST 24 Mar 07 01:00:24 PM PST 24 49114635 ps
T204 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.222155356 Mar 07 01:00:00 PM PST 24 Mar 07 01:00:04 PM PST 24 153307868 ps
T151 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.703569472 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:16 PM PST 24 146378923 ps
T76 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.655452636 Mar 07 01:00:13 PM PST 24 Mar 07 01:00:14 PM PST 24 45343861 ps
T217 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2094111672 Mar 07 01:00:29 PM PST 24 Mar 07 01:00:29 PM PST 24 27756588 ps
T225 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3399901984 Mar 07 01:00:43 PM PST 24 Mar 07 01:00:44 PM PST 24 22685057 ps
T152 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2324608615 Mar 07 01:00:15 PM PST 24 Mar 07 01:00:16 PM PST 24 76058894 ps
T169 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2214458771 Mar 07 01:00:28 PM PST 24 Mar 07 01:00:29 PM PST 24 40006351 ps
T216 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1992221388 Mar 07 01:00:10 PM PST 24 Mar 07 01:00:11 PM PST 24 31457406 ps
T50 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.186401571 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:14 PM PST 24 39442993 ps
T153 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1238350001 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:16 PM PST 24 83666732 ps
T170 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1858594723 Mar 07 01:00:17 PM PST 24 Mar 07 01:00:19 PM PST 24 122218775 ps
T159 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.839791952 Mar 07 01:00:05 PM PST 24 Mar 07 01:00:08 PM PST 24 77719518 ps
T160 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1362281575 Mar 07 01:00:07 PM PST 24 Mar 07 01:00:11 PM PST 24 387574447 ps
T158 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.635239191 Mar 07 01:00:07 PM PST 24 Mar 07 01:00:10 PM PST 24 257394009 ps
T161 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1304288683 Mar 07 01:00:39 PM PST 24 Mar 07 01:00:40 PM PST 24 53045229 ps
T214 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1344401629 Mar 07 01:00:29 PM PST 24 Mar 07 01:00:30 PM PST 24 39454809 ps
T154 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.820744974 Mar 07 01:00:36 PM PST 24 Mar 07 01:00:38 PM PST 24 144686904 ps
T155 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1586808824 Mar 07 01:00:24 PM PST 24 Mar 07 01:00:26 PM PST 24 79155803 ps
T162 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1601700822 Mar 07 01:00:24 PM PST 24 Mar 07 01:00:25 PM PST 24 23861809 ps
T163 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1789508967 Mar 07 01:00:25 PM PST 24 Mar 07 01:00:26 PM PST 24 72999204 ps
T164 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.262729435 Mar 07 01:00:22 PM PST 24 Mar 07 01:00:24 PM PST 24 42991608 ps
T215 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1665344001 Mar 07 01:00:28 PM PST 24 Mar 07 01:00:28 PM PST 24 28071210 ps
T171 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2920920845 Mar 07 01:00:26 PM PST 24 Mar 07 01:00:27 PM PST 24 45233598 ps
T222 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.126813229 Mar 07 01:00:33 PM PST 24 Mar 07 01:00:34 PM PST 24 21629509 ps
T156 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1319270525 Mar 07 01:00:09 PM PST 24 Mar 07 01:00:12 PM PST 24 96820795 ps
T157 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.985720528 Mar 07 01:00:44 PM PST 24 Mar 07 01:00:47 PM PST 24 141079996 ps
T645 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2402958909 Mar 07 01:00:26 PM PST 24 Mar 07 01:00:27 PM PST 24 50069631 ps
T220 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3271484670 Mar 07 01:00:26 PM PST 24 Mar 07 01:00:26 PM PST 24 29148850 ps
T201 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4214604623 Mar 07 01:00:33 PM PST 24 Mar 07 01:00:34 PM PST 24 86851636 ps
T203 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.238220210 Mar 07 01:00:07 PM PST 24 Mar 07 01:00:08 PM PST 24 85216790 ps
T646 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2830080424 Mar 07 01:00:17 PM PST 24 Mar 07 01:00:19 PM PST 24 122407491 ps
T226 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1787140234 Mar 07 01:00:36 PM PST 24 Mar 07 01:00:37 PM PST 24 22080009 ps
T205 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1372643424 Mar 07 01:00:28 PM PST 24 Mar 07 01:00:29 PM PST 24 79489342 ps
T165 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4218684599 Mar 07 01:00:10 PM PST 24 Mar 07 01:00:11 PM PST 24 69660759 ps
T166 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1956363939 Mar 07 01:00:33 PM PST 24 Mar 07 01:00:34 PM PST 24 31742420 ps
T647 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3425983739 Mar 07 01:00:18 PM PST 24 Mar 07 01:00:19 PM PST 24 105864680 ps
T648 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1303111008 Mar 07 01:00:13 PM PST 24 Mar 07 01:00:15 PM PST 24 122393441 ps
T224 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3843099354 Mar 07 01:00:56 PM PST 24 Mar 07 01:00:57 PM PST 24 46703166 ps
T206 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1474348653 Mar 07 01:00:12 PM PST 24 Mar 07 01:00:14 PM PST 24 160520544 ps
T168 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.657053137 Mar 07 01:00:30 PM PST 24 Mar 07 01:00:31 PM PST 24 61051841 ps
T208 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.24924941 Mar 07 01:00:29 PM PST 24 Mar 07 01:00:32 PM PST 24 140419164 ps
T649 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2447716656 Mar 07 01:00:27 PM PST 24 Mar 07 01:00:29 PM PST 24 204724012 ps
T207 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3632283184 Mar 07 01:00:29 PM PST 24 Mar 07 01:00:30 PM PST 24 68340472 ps
T650 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.828357482 Mar 07 01:00:33 PM PST 24 Mar 07 01:00:35 PM PST 24 135447511 ps
T202 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2482527972 Mar 07 01:00:15 PM PST 24 Mar 07 01:00:17 PM PST 24 194134553 ps
T651 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2776832741 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:03 PM PST 24 83919566 ps
T652 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2316344199 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:16 PM PST 24 60272187 ps
T227 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1052879128 Mar 07 01:00:41 PM PST 24 Mar 07 01:00:42 PM PST 24 129792302 ps
T653 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4134493870 Mar 07 01:00:11 PM PST 24 Mar 07 01:00:12 PM PST 24 86925127 ps
T212 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1065970111 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:15 PM PST 24 30767695 ps
T167 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2333916779 Mar 07 01:00:12 PM PST 24 Mar 07 01:00:13 PM PST 24 128286024 ps
T654 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3497384634 Mar 07 01:00:35 PM PST 24 Mar 07 01:00:38 PM PST 24 220528630 ps
T221 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2959238147 Mar 07 01:00:24 PM PST 24 Mar 07 01:00:25 PM PST 24 31656576 ps
T655 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2618332519 Mar 07 01:00:20 PM PST 24 Mar 07 01:00:21 PM PST 24 45672251 ps
T656 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2272445840 Mar 07 01:00:12 PM PST 24 Mar 07 01:00:17 PM PST 24 469796744 ps
T657 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3335885451 Mar 07 01:00:40 PM PST 24 Mar 07 01:00:43 PM PST 24 191171935 ps
T658 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2654118926 Mar 07 01:00:19 PM PST 24 Mar 07 01:00:20 PM PST 24 42563566 ps
T659 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.456849360 Mar 07 01:00:13 PM PST 24 Mar 07 01:00:15 PM PST 24 40707050 ps
T660 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3104731955 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:15 PM PST 24 50480749 ps
T661 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1842976667 Mar 07 01:00:13 PM PST 24 Mar 07 01:00:14 PM PST 24 73069937 ps
T662 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2156776112 Mar 07 01:00:08 PM PST 24 Mar 07 01:00:17 PM PST 24 370634772 ps
T663 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1297218071 Mar 07 01:00:34 PM PST 24 Mar 07 01:00:36 PM PST 24 139443876 ps
T223 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3484042180 Mar 07 01:00:29 PM PST 24 Mar 07 01:00:35 PM PST 24 40456941 ps
T664 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3396997087 Mar 07 01:00:24 PM PST 24 Mar 07 01:00:26 PM PST 24 43146670 ps
T665 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.325906063 Mar 07 01:00:08 PM PST 24 Mar 07 01:00:10 PM PST 24 379116943 ps
T666 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.651618051 Mar 07 01:00:46 PM PST 24 Mar 07 01:00:48 PM PST 24 60843257 ps
T210 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.807441168 Mar 07 01:00:27 PM PST 24 Mar 07 01:00:30 PM PST 24 280606280 ps
T667 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3981165990 Mar 07 01:00:21 PM PST 24 Mar 07 01:00:23 PM PST 24 38954537 ps
T213 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.704789758 Mar 07 01:00:52 PM PST 24 Mar 07 01:00:53 PM PST 24 25349784 ps
T668 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3703099777 Mar 07 01:00:18 PM PST 24 Mar 07 01:00:20 PM PST 24 171050161 ps
T669 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.565098397 Mar 07 01:00:16 PM PST 24 Mar 07 01:00:17 PM PST 24 43618406 ps
T670 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.808220845 Mar 07 01:00:12 PM PST 24 Mar 07 01:00:15 PM PST 24 281492461 ps
T671 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2072674047 Mar 07 01:00:13 PM PST 24 Mar 07 01:00:21 PM PST 24 368007446 ps
T672 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3576524675 Mar 07 01:00:15 PM PST 24 Mar 07 01:00:16 PM PST 24 30133058 ps
T673 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2175059298 Mar 07 01:00:15 PM PST 24 Mar 07 01:00:17 PM PST 24 212141145 ps
T674 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1617971037 Mar 07 01:00:30 PM PST 24 Mar 07 01:00:31 PM PST 24 41156919 ps
T675 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2840617426 Mar 07 01:00:10 PM PST 24 Mar 07 01:00:11 PM PST 24 86167537 ps
T228 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1609377820 Mar 07 01:00:35 PM PST 24 Mar 07 01:00:36 PM PST 24 51319038 ps
T51 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3802923946 Mar 07 01:00:02 PM PST 24 Mar 07 01:00:03 PM PST 24 33139786 ps
T229 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3448799049 Mar 07 01:00:19 PM PST 24 Mar 07 01:00:19 PM PST 24 27225370 ps
T676 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3934574056 Mar 07 01:00:02 PM PST 24 Mar 07 01:00:06 PM PST 24 334437947 ps
T677 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4127363266 Mar 07 01:00:44 PM PST 24 Mar 07 01:00:47 PM PST 24 239296904 ps
T218 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2856904158 Mar 07 01:00:32 PM PST 24 Mar 07 01:00:33 PM PST 24 61173033 ps
T678 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.169046978 Mar 07 01:00:06 PM PST 24 Mar 07 01:00:07 PM PST 24 142130435 ps
T679 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2756918175 Mar 07 01:00:09 PM PST 24 Mar 07 01:00:11 PM PST 24 126326306 ps
T219 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.691620105 Mar 07 01:00:22 PM PST 24 Mar 07 01:00:23 PM PST 24 24091844 ps
T680 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4203028434 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:17 PM PST 24 255348141 ps
T681 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3742227060 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:17 PM PST 24 90013915 ps
T172 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3713117593 Mar 07 01:00:46 PM PST 24 Mar 07 01:00:48 PM PST 24 38671555 ps
T211 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4241252763 Mar 07 01:00:32 PM PST 24 Mar 07 01:00:34 PM PST 24 143050815 ps
T682 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2301075430 Mar 07 01:00:24 PM PST 24 Mar 07 01:00:26 PM PST 24 55942011 ps
T683 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2465631431 Mar 07 01:00:15 PM PST 24 Mar 07 01:00:15 PM PST 24 41082886 ps
T684 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.180988937 Mar 07 01:00:02 PM PST 24 Mar 07 01:00:03 PM PST 24 165558880 ps
T685 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.861585677 Mar 07 01:00:27 PM PST 24 Mar 07 01:00:28 PM PST 24 28082756 ps
T686 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3906472212 Mar 07 01:00:10 PM PST 24 Mar 07 01:00:12 PM PST 24 41547319 ps
T687 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2398836818 Mar 07 01:00:03 PM PST 24 Mar 07 01:00:05 PM PST 24 177220449 ps
T688 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.562408360 Mar 07 01:00:30 PM PST 24 Mar 07 01:00:31 PM PST 24 35544902 ps
T689 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2322261613 Mar 07 01:00:13 PM PST 24 Mar 07 01:00:14 PM PST 24 52542959 ps
T690 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.691650720 Mar 07 01:00:12 PM PST 24 Mar 07 01:00:13 PM PST 24 19385858 ps
T691 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1497812044 Mar 07 01:00:44 PM PST 24 Mar 07 01:00:45 PM PST 24 26943461 ps
T230 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2342797368 Mar 07 01:00:20 PM PST 24 Mar 07 01:00:20 PM PST 24 35668219 ps
T692 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1511929318 Mar 07 01:00:08 PM PST 24 Mar 07 01:00:10 PM PST 24 74017591 ps
T693 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.177806562 Mar 07 01:00:40 PM PST 24 Mar 07 01:00:42 PM PST 24 185062042 ps
T694 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2743830106 Mar 07 01:00:34 PM PST 24 Mar 07 01:00:35 PM PST 24 45740517 ps
T695 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.942063879 Mar 07 01:00:11 PM PST 24 Mar 07 01:00:12 PM PST 24 144578318 ps
T231 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1553490518 Mar 07 01:00:02 PM PST 24 Mar 07 01:00:05 PM PST 24 210746293 ps
T696 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1956976168 Mar 07 01:00:29 PM PST 24 Mar 07 01:00:30 PM PST 24 42582976 ps
T697 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3760146326 Mar 07 01:00:30 PM PST 24 Mar 07 01:00:31 PM PST 24 111242860 ps
T698 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2128317745 Mar 07 01:00:22 PM PST 24 Mar 07 01:00:25 PM PST 24 391991664 ps
T699 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2441939594 Mar 07 01:00:58 PM PST 24 Mar 07 01:00:59 PM PST 24 33980321 ps
T700 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2845652661 Mar 07 01:00:36 PM PST 24 Mar 07 01:00:37 PM PST 24 27833302 ps
T701 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2982773231 Mar 07 01:00:35 PM PST 24 Mar 07 01:00:36 PM PST 24 74643847 ps
T702 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1458130086 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:16 PM PST 24 123939287 ps
T703 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4092354863 Mar 07 01:00:10 PM PST 24 Mar 07 01:00:11 PM PST 24 49968099 ps
T704 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.395643405 Mar 07 01:00:47 PM PST 24 Mar 07 01:00:48 PM PST 24 20320426 ps
T232 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2290817784 Mar 07 01:00:04 PM PST 24 Mar 07 01:00:07 PM PST 24 227210342 ps
T209 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2154439648 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:18 PM PST 24 432549222 ps
T705 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3485514621 Mar 07 01:00:23 PM PST 24 Mar 07 01:00:25 PM PST 24 99580831 ps
T706 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3940465988 Mar 07 01:00:06 PM PST 24 Mar 07 01:00:07 PM PST 24 78071805 ps
T707 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3905733757 Mar 07 01:00:36 PM PST 24 Mar 07 01:00:37 PM PST 24 74616510 ps
T708 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.542724830 Mar 07 01:00:19 PM PST 24 Mar 07 01:00:20 PM PST 24 25346418 ps
T709 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4188371752 Mar 07 01:00:19 PM PST 24 Mar 07 01:00:25 PM PST 24 48250172 ps
T710 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2159290018 Mar 07 01:00:13 PM PST 24 Mar 07 01:00:16 PM PST 24 85262652 ps
T711 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4293911941 Mar 07 01:00:38 PM PST 24 Mar 07 01:00:39 PM PST 24 45345706 ps
T712 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3074994439 Mar 07 01:00:44 PM PST 24 Mar 07 01:00:45 PM PST 24 29389144 ps
T713 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2150179530 Mar 07 01:00:21 PM PST 24 Mar 07 01:00:23 PM PST 24 112071505 ps
T714 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3811902243 Mar 07 01:00:10 PM PST 24 Mar 07 01:00:12 PM PST 24 62709436 ps
T715 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1686390610 Mar 07 01:00:32 PM PST 24 Mar 07 01:00:33 PM PST 24 47994925 ps

Test location /workspace/coverage/default/38.usbdev_in_trans.477200731
Short name T2
Test name
Test status
Simulation time 8460288027 ps
CPU time 7.62 seconds
Started Mar 07 01:50:31 PM PST 24
Finished Mar 07 01:50:39 PM PST 24
Peak memory 202452 kb
Host smart-04943e71-3506-4c34-84b6-3ce3d03410b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47720
0731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.477200731
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2488993644
Short name T14
Test name
Test status
Simulation time 8506687154 ps
CPU time 7.38 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:17 PM PST 24
Peak memory 202404 kb
Host smart-923e5bc8-add2-4de6-bcc2-0f779765b3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24889
93644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2488993644
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3954287374
Short name T52
Test name
Test status
Simulation time 30274934 ps
CPU time 0.64 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:00:58 PM PST 24
Peak memory 201880 kb
Host smart-ab60508b-d877-49c2-8110-7a9db3af9630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3954287374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3954287374
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.79213087
Short name T42
Test name
Test status
Simulation time 479239832 ps
CPU time 3.05 seconds
Started Mar 07 01:00:26 PM PST 24
Finished Mar 07 01:00:29 PM PST 24
Peak memory 202792 kb
Host smart-41eb6274-0edb-47c4-841b-5aa6e7b36285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=79213087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.79213087
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.752118636
Short name T173
Test name
Test status
Simulation time 58601926 ps
CPU time 1.42 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 202480 kb
Host smart-d37bee69-d735-4c33-a94a-b529f44dee62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75211
8636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.752118636
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4230590712
Short name T41
Test name
Test status
Simulation time 258169303 ps
CPU time 2.75 seconds
Started Mar 07 01:00:24 PM PST 24
Finished Mar 07 01:00:27 PM PST 24
Peak memory 202624 kb
Host smart-2bd6dfb8-aefd-4c1c-86fa-a7a4027e64c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4230590712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4230590712
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3140945042
Short name T12
Test name
Test status
Simulation time 8417327688 ps
CPU time 7.31 seconds
Started Mar 07 01:49:21 PM PST 24
Finished Mar 07 01:49:28 PM PST 24
Peak memory 202460 kb
Host smart-72fa963f-bdad-405c-848e-a074b8498a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31409
45042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3140945042
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3983666866
Short name T53
Test name
Test status
Simulation time 104535002 ps
CPU time 0.73 seconds
Started Mar 07 01:00:09 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 201920 kb
Host smart-0cd27d90-e01c-4233-af40-a72558298fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3983666866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3983666866
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3617360551
Short name T44
Test name
Test status
Simulation time 87124521 ps
CPU time 0.88 seconds
Started Mar 07 01:48:26 PM PST 24
Finished Mar 07 01:48:27 PM PST 24
Peak memory 217324 kb
Host smart-cfced87d-60b9-42d4-a52e-6be55cc85596
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3617360551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3617360551
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2806986246
Short name T1
Test name
Test status
Simulation time 8373898346 ps
CPU time 9.13 seconds
Started Mar 07 01:49:30 PM PST 24
Finished Mar 07 01:49:40 PM PST 24
Peak memory 202488 kb
Host smart-885f7a71-979a-4d41-9410-435b38c966b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
86246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2806986246
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1137784717
Short name T47
Test name
Test status
Simulation time 32553799 ps
CPU time 0.75 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:15 PM PST 24
Peak memory 202284 kb
Host smart-0acd356a-7554-4d21-a552-d1b6e5560fe4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137784717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1137784717
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1992221388
Short name T216
Test name
Test status
Simulation time 31457406 ps
CPU time 0.61 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:11 PM PST 24
Peak memory 201868 kb
Host smart-e616bcfc-1fe0-43df-8fb8-d3c9867191a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1992221388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1992221388
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.790683400
Short name T11
Test name
Test status
Simulation time 8428296613 ps
CPU time 7.19 seconds
Started Mar 07 01:49:55 PM PST 24
Finished Mar 07 01:50:03 PM PST 24
Peak memory 202448 kb
Host smart-6bc1cbe4-9bd4-40b5-bab6-995bcdf5badd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79068
3400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.790683400
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_smoke.541910756
Short name T69
Test name
Test status
Simulation time 8474534253 ps
CPU time 7.68 seconds
Started Mar 07 01:50:28 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202552 kb
Host smart-57f72b09-3197-4fbc-bbaf-04701b4fd5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54191
0756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.541910756
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1609377820
Short name T228
Test name
Test status
Simulation time 51319038 ps
CPU time 0.67 seconds
Started Mar 07 01:00:35 PM PST 24
Finished Mar 07 01:00:36 PM PST 24
Peak memory 201884 kb
Host smart-65e4849f-c59e-4ee2-a1b6-fb2dc30fa397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609377820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1609377820
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.4241252763
Short name T211
Test name
Test status
Simulation time 143050815 ps
CPU time 2.4 seconds
Started Mar 07 01:00:32 PM PST 24
Finished Mar 07 01:00:34 PM PST 24
Peak memory 202676 kb
Host smart-288ad0d3-343f-48cf-a0d7-a18b3bbe3b72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4241252763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.4241252763
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3165188098
Short name T67
Test name
Test status
Simulation time 8485927221 ps
CPU time 7.67 seconds
Started Mar 07 01:50:31 PM PST 24
Finished Mar 07 01:50:40 PM PST 24
Peak memory 202456 kb
Host smart-52a88a5a-b5b1-4642-8331-3f6178b5d22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31651
88098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3165188098
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1485802576
Short name T16
Test name
Test status
Simulation time 8479707539 ps
CPU time 7.31 seconds
Started Mar 07 01:51:00 PM PST 24
Finished Mar 07 01:51:08 PM PST 24
Peak memory 202448 kb
Host smart-3d8a9a6c-7167-4561-bcf7-16d98f6b234d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14858
02576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1485802576
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2376180609
Short name T528
Test name
Test status
Simulation time 8378174056 ps
CPU time 9.41 seconds
Started Mar 07 01:48:37 PM PST 24
Finished Mar 07 01:48:46 PM PST 24
Peak memory 202392 kb
Host smart-ee6b1d6f-88c8-4583-8a68-1a3fb52de8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
80609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2376180609
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2435550755
Short name T126
Test name
Test status
Simulation time 8448893515 ps
CPU time 8.18 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 01:51:08 PM PST 24
Peak memory 202508 kb
Host smart-fbf10b5c-3feb-4568-a102-92a5f833a7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24355
50755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2435550755
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1563550356
Short name T149
Test name
Test status
Simulation time 8470292795 ps
CPU time 9.39 seconds
Started Mar 07 01:49:25 PM PST 24
Finished Mar 07 01:49:35 PM PST 24
Peak memory 202464 kb
Host smart-2f4d10fe-ecc9-419d-9a2a-39d6422268ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15635
50356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1563550356
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.56528905
Short name T180
Test name
Test status
Simulation time 8395158712 ps
CPU time 7.51 seconds
Started Mar 07 01:49:49 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 202568 kb
Host smart-2839a8f6-4315-4b9d-a8fb-d024389960ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56528
905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.56528905
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_smoke.116535031
Short name T134
Test name
Test status
Simulation time 8515754520 ps
CPU time 7.45 seconds
Started Mar 07 01:49:50 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 202516 kb
Host smart-d637928e-8818-4a92-965f-1f9d3f483cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11653
5031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.116535031
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1665344001
Short name T215
Test name
Test status
Simulation time 28071210 ps
CPU time 0.65 seconds
Started Mar 07 01:00:28 PM PST 24
Finished Mar 07 01:00:28 PM PST 24
Peak memory 201820 kb
Host smart-aa4c061b-db56-4468-bf33-2551029fbea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1665344001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1665344001
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2910442724
Short name T174
Test name
Test status
Simulation time 51530684 ps
CPU time 1.33 seconds
Started Mar 07 01:49:21 PM PST 24
Finished Mar 07 01:49:22 PM PST 24
Peak memory 202448 kb
Host smart-841be262-efef-42b4-9cdc-1b74dc4ab6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29104
42724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2910442724
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1601700822
Short name T162
Test name
Test status
Simulation time 23861809 ps
CPU time 0.84 seconds
Started Mar 07 01:00:24 PM PST 24
Finished Mar 07 01:00:25 PM PST 24
Peak memory 202464 kb
Host smart-3b5aaec3-6c43-4372-8856-43e388bf27e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601700822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1601700822
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2154439648
Short name T209
Test name
Test status
Simulation time 432549222 ps
CPU time 4.24 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:18 PM PST 24
Peak memory 202660 kb
Host smart-c2721f29-1404-41b3-bfda-f1f9ff40138e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2154439648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2154439648
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2094111672
Short name T217
Test name
Test status
Simulation time 27756588 ps
CPU time 0.65 seconds
Started Mar 07 01:00:29 PM PST 24
Finished Mar 07 01:00:29 PM PST 24
Peak memory 201936 kb
Host smart-dd9d4714-7c04-49b4-9509-b1943a80a872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2094111672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2094111672
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1698782635
Short name T45
Test name
Test status
Simulation time 101432100 ps
CPU time 0.9 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:18 PM PST 24
Peak memory 217288 kb
Host smart-24174c8b-dd8a-42e1-ab0a-9f2827373565
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1698782635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1698782635
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.703569472
Short name T151
Test name
Test status
Simulation time 146378923 ps
CPU time 1.88 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 202664 kb
Host smart-1f5c5daa-7f0f-45f3-8001-935e6330c67e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=703569472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.703569472
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.655452636
Short name T76
Test name
Test status
Simulation time 45343861 ps
CPU time 0.84 seconds
Started Mar 07 01:00:13 PM PST 24
Finished Mar 07 01:00:14 PM PST 24
Peak memory 202352 kb
Host smart-cb371f8c-287c-43ee-bc82-97ef058ee394
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655452636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.655452636
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3150200023
Short name T139
Test name
Test status
Simulation time 8484583180 ps
CPU time 7.38 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:26 PM PST 24
Peak memory 202496 kb
Host smart-e6ecfa65-f8fa-426c-8e90-8f1b5f301e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502
00023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3150200023
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3674866624
Short name T48
Test name
Test status
Simulation time 167992548 ps
CPU time 1.54 seconds
Started Mar 07 01:00:35 PM PST 24
Finished Mar 07 01:00:36 PM PST 24
Peak memory 202648 kb
Host smart-06d76a4c-2051-4873-8b12-1aee8d0a2f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674866624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.3674866624
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/21.usbdev_smoke.4125171211
Short name T144
Test name
Test status
Simulation time 8473192648 ps
CPU time 7.6 seconds
Started Mar 07 01:49:38 PM PST 24
Finished Mar 07 01:49:47 PM PST 24
Peak memory 202464 kb
Host smart-000d4716-09ba-4055-b093-a0fad034809c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41251
71211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.4125171211
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3881749577
Short name T265
Test name
Test status
Simulation time 8370648627 ps
CPU time 7.59 seconds
Started Mar 07 01:48:15 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 202512 kb
Host smart-c0db2bf1-58ca-4747-a8d5-2c2c66f724d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38817
49577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3881749577
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.695505550
Short name T608
Test name
Test status
Simulation time 8478578723 ps
CPU time 7.53 seconds
Started Mar 07 01:49:10 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 202484 kb
Host smart-ae3806c9-8df3-4e4d-a9b1-3642f235dc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69550
5550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.695505550
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_smoke.71581214
Short name T146
Test name
Test status
Simulation time 8473665966 ps
CPU time 9.68 seconds
Started Mar 07 01:49:24 PM PST 24
Finished Mar 07 01:49:34 PM PST 24
Peak memory 202508 kb
Host smart-52654acc-5cd3-4698-b0c2-6dd49713c413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71581
214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.71581214
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_smoke.509686925
Short name T141
Test name
Test status
Simulation time 8472492865 ps
CPU time 9.53 seconds
Started Mar 07 01:49:31 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202580 kb
Host smart-b4c35b6a-d4d9-4e60-b871-341a05a34f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50968
6925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.509686925
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_smoke.810370172
Short name T129
Test name
Test status
Simulation time 8471746984 ps
CPU time 7.82 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202536 kb
Host smart-08394550-347e-4392-94be-a3b47560516e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81037
0172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.810370172
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3713117593
Short name T172
Test name
Test status
Simulation time 38671555 ps
CPU time 1 seconds
Started Mar 07 01:00:46 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 202624 kb
Host smart-8917b50e-4076-4286-89d0-ec76ef9f698f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713117593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.3713117593
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1627720738
Short name T102
Test name
Test status
Simulation time 8398103503 ps
CPU time 7.28 seconds
Started Mar 07 01:48:17 PM PST 24
Finished Mar 07 01:48:24 PM PST 24
Peak memory 202448 kb
Host smart-aaaf8404-a334-44ab-a25f-e7ee8d31015d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16277
20738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1627720738
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2553350360
Short name T453
Test name
Test status
Simulation time 8405771654 ps
CPU time 7.7 seconds
Started Mar 07 01:48:15 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 202456 kb
Host smart-10a6640a-264b-4f02-b9ce-63d1b665d0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25533
50360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2553350360
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3848933179
Short name T82
Test name
Test status
Simulation time 8484230820 ps
CPU time 7.92 seconds
Started Mar 07 01:49:10 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 202532 kb
Host smart-8b63e5a5-db51-4a05-9d10-4aa83eb9fc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38489
33179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3848933179
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2291371618
Short name T93
Test name
Test status
Simulation time 8429199287 ps
CPU time 9.15 seconds
Started Mar 07 01:49:13 PM PST 24
Finished Mar 07 01:49:22 PM PST 24
Peak memory 202508 kb
Host smart-e16fc8e6-90df-4268-8841-fb697c2e6d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22913
71618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2291371618
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2048682654
Short name T378
Test name
Test status
Simulation time 8433029621 ps
CPU time 8.6 seconds
Started Mar 07 01:49:13 PM PST 24
Finished Mar 07 01:49:22 PM PST 24
Peak memory 202480 kb
Host smart-10fdf7e2-83e0-4ff9-9baa-7a7fcd9dbc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486
82654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2048682654
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3185424340
Short name T13
Test name
Test status
Simulation time 8411594778 ps
CPU time 7.17 seconds
Started Mar 07 01:49:07 PM PST 24
Finished Mar 07 01:49:15 PM PST 24
Peak memory 202456 kb
Host smart-310b3b32-fc40-415c-b6e4-2f21c7e3a87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31854
24340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3185424340
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1667099143
Short name T104
Test name
Test status
Simulation time 8440018407 ps
CPU time 7.96 seconds
Started Mar 07 01:49:28 PM PST 24
Finished Mar 07 01:49:36 PM PST 24
Peak memory 202452 kb
Host smart-951babbe-f8c3-4e67-8885-3b9734a871af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16670
99143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1667099143
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2542470546
Short name T478
Test name
Test status
Simulation time 8422706714 ps
CPU time 9.78 seconds
Started Mar 07 01:49:26 PM PST 24
Finished Mar 07 01:49:36 PM PST 24
Peak memory 202504 kb
Host smart-6625a848-7053-4f4a-a31a-102692363c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25424
70546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2542470546
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.499543044
Short name T95
Test name
Test status
Simulation time 8435319251 ps
CPU time 10.05 seconds
Started Mar 07 01:49:21 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202476 kb
Host smart-90fb96cb-c46e-4b45-aa0a-6d4e48481592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49954
3044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.499543044
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2435304288
Short name T89
Test name
Test status
Simulation time 8424381367 ps
CPU time 7.31 seconds
Started Mar 07 01:48:27 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 202504 kb
Host smart-704b5f04-fa8d-4f39-ace8-166987249826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24353
04288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2435304288
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1727127383
Short name T80
Test name
Test status
Simulation time 8439385854 ps
CPU time 7.43 seconds
Started Mar 07 01:50:48 PM PST 24
Finished Mar 07 01:50:56 PM PST 24
Peak memory 202452 kb
Host smart-270d570a-d3f2-41a6-a601-e386ffb6016f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17271
27383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1727127383
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.839791952
Short name T159
Test name
Test status
Simulation time 77719518 ps
CPU time 2.04 seconds
Started Mar 07 01:00:05 PM PST 24
Finished Mar 07 01:00:08 PM PST 24
Peak memory 202632 kb
Host smart-821296a5-82e0-439d-8c49-21d46a7fca49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839791952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.839791952
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1586808824
Short name T155
Test name
Test status
Simulation time 79155803 ps
CPU time 2.47 seconds
Started Mar 07 01:00:24 PM PST 24
Finished Mar 07 01:00:26 PM PST 24
Peak memory 210872 kb
Host smart-eb2ad0dd-8d3c-4717-a8b9-0f7adc03473a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586808824 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.1586808824
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2920920845
Short name T171
Test name
Test status
Simulation time 45233598 ps
CPU time 0.83 seconds
Started Mar 07 01:00:26 PM PST 24
Finished Mar 07 01:00:27 PM PST 24
Peak memory 202328 kb
Host smart-9edfe90d-f834-4b5d-9d9c-f3af27f09b65
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920920845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2920920845
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3906472212
Short name T686
Test name
Test status
Simulation time 41547319 ps
CPU time 1.23 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 202596 kb
Host smart-0c7efb50-59e3-41d1-a2b6-219c69137199
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3906472212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3906472212
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.180988937
Short name T684
Test name
Test status
Simulation time 165558880 ps
CPU time 1.57 seconds
Started Mar 07 01:00:02 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 202640 kb
Host smart-410b4533-63e2-46a6-a775-509ba6bed93c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180988937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_cs
r_outstanding.180988937
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1238350001
Short name T153
Test name
Test status
Simulation time 83666732 ps
CPU time 2.54 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 202596 kb
Host smart-0e15c8f6-237a-467d-87dc-f63c33d0c621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1238350001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1238350001
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.635239191
Short name T158
Test name
Test status
Simulation time 257394009 ps
CPU time 2.97 seconds
Started Mar 07 01:00:07 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 202620 kb
Host smart-a6ce32a1-8c79-41f4-81cd-ee978049a1e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=635239191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.635239191
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1511929318
Short name T692
Test name
Test status
Simulation time 74017591 ps
CPU time 1.94 seconds
Started Mar 07 01:00:08 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 202576 kb
Host smart-64a0893a-7f60-4830-97f9-064699609ac5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511929318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1511929318
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2156776112
Short name T662
Test name
Test status
Simulation time 370634772 ps
CPU time 8.52 seconds
Started Mar 07 01:00:08 PM PST 24
Finished Mar 07 01:00:17 PM PST 24
Peak memory 202620 kb
Host smart-32e97217-6f28-4bde-af19-f8f0869aa516
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156776112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2156776112
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3802923946
Short name T51
Test name
Test status
Simulation time 33139786 ps
CPU time 0.74 seconds
Started Mar 07 01:00:02 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 202420 kb
Host smart-c0b1c7ea-a0e8-455f-9db1-95d8a888c0d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802923946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3802923946
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1842976667
Short name T661
Test name
Test status
Simulation time 73069937 ps
CPU time 1.12 seconds
Started Mar 07 01:00:13 PM PST 24
Finished Mar 07 01:00:14 PM PST 24
Peak memory 218504 kb
Host smart-11041901-b52b-4dda-a731-68cf2b4ddc19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842976667 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.1842976667
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4092354863
Short name T703
Test name
Test status
Simulation time 49968099 ps
CPU time 0.8 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:11 PM PST 24
Peak memory 202456 kb
Host smart-8d2c3f2b-edcc-41af-87a8-585b7e106889
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092354863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4092354863
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2342797368
Short name T230
Test name
Test status
Simulation time 35668219 ps
CPU time 0.62 seconds
Started Mar 07 01:00:20 PM PST 24
Finished Mar 07 01:00:20 PM PST 24
Peak memory 201784 kb
Host smart-82a9932e-4bf0-4432-8d09-1a459e5ae028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2342797368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2342797368
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.262729435
Short name T164
Test name
Test status
Simulation time 42991608 ps
CPU time 1.29 seconds
Started Mar 07 01:00:22 PM PST 24
Finished Mar 07 01:00:24 PM PST 24
Peak memory 202576 kb
Host smart-a0790f4c-0475-4740-99f4-a6e0a6b5e477
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=262729435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.262729435
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2272445840
Short name T656
Test name
Test status
Simulation time 469796744 ps
CPU time 4.25 seconds
Started Mar 07 01:00:12 PM PST 24
Finished Mar 07 01:00:17 PM PST 24
Peak memory 202528 kb
Host smart-4bb8ae5e-a41d-4094-bb49-673050564e49
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2272445840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2272445840
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4134493870
Short name T653
Test name
Test status
Simulation time 86925127 ps
CPU time 1.01 seconds
Started Mar 07 01:00:11 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 202484 kb
Host smart-714d9b73-4110-4f9d-999f-2f04347e4b75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134493870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.4134493870
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2840617426
Short name T675
Test name
Test status
Simulation time 86167537 ps
CPU time 1.35 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:11 PM PST 24
Peak memory 202596 kb
Host smart-c694e756-282f-4395-9c26-8d7e92f42827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2840617426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2840617426
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2290817784
Short name T232
Test name
Test status
Simulation time 227210342 ps
CPU time 2.54 seconds
Started Mar 07 01:00:04 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 202532 kb
Host smart-3fbc2b04-3c41-453a-9271-e8195ae684df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2290817784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2290817784
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.169046978
Short name T678
Test name
Test status
Simulation time 142130435 ps
CPU time 1.8 seconds
Started Mar 07 01:00:06 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 210820 kb
Host smart-8a6caac6-acfb-4ee3-930d-c88f7d04ac1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169046978 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.169046978
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.704789758
Short name T213
Test name
Test status
Simulation time 25349784 ps
CPU time 0.66 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:00:53 PM PST 24
Peak memory 201860 kb
Host smart-8e336fbc-8249-4672-bbca-2f5d48a6f2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=704789758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.704789758
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.651618051
Short name T666
Test name
Test status
Simulation time 60843257 ps
CPU time 1.44 seconds
Started Mar 07 01:00:46 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 202508 kb
Host smart-c02eafbf-a694-40c3-bfcc-3694aab3a4ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651618051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_c
sr_outstanding.651618051
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.951959140
Short name T74
Test name
Test status
Simulation time 497861811 ps
CPU time 4.41 seconds
Started Mar 07 01:00:24 PM PST 24
Finished Mar 07 01:00:28 PM PST 24
Peak memory 202808 kb
Host smart-63a0696d-c14d-4828-b341-884222f1374d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=951959140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.951959140
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2150179530
Short name T713
Test name
Test status
Simulation time 112071505 ps
CPU time 1.6 seconds
Started Mar 07 01:00:21 PM PST 24
Finished Mar 07 01:00:23 PM PST 24
Peak memory 210928 kb
Host smart-18def001-c2e6-4b1f-8742-553c325c1e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150179530 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2150179530
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2618332519
Short name T655
Test name
Test status
Simulation time 45672251 ps
CPU time 0.79 seconds
Started Mar 07 01:00:20 PM PST 24
Finished Mar 07 01:00:21 PM PST 24
Peak memory 202424 kb
Host smart-44c66a5f-ab98-4f75-a8ff-fd2c58fe7cba
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618332519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2618332519
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3920273159
Short name T56
Test name
Test status
Simulation time 78260510 ps
CPU time 0.67 seconds
Started Mar 07 01:00:31 PM PST 24
Finished Mar 07 01:00:32 PM PST 24
Peak memory 201832 kb
Host smart-687699d4-8967-4d2c-af83-8663a3e6b091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3920273159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3920273159
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.808220845
Short name T670
Test name
Test status
Simulation time 281492461 ps
CPU time 3.03 seconds
Started Mar 07 01:00:12 PM PST 24
Finished Mar 07 01:00:15 PM PST 24
Peak memory 202628 kb
Host smart-fa669a74-7ea6-4839-839d-8163104d10f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=808220845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.808220845
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3632283184
Short name T207
Test name
Test status
Simulation time 68340472 ps
CPU time 1.14 seconds
Started Mar 07 01:00:29 PM PST 24
Finished Mar 07 01:00:30 PM PST 24
Peak memory 211812 kb
Host smart-5598e75d-5cfd-4f2f-b85d-04e5e637b8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632283184 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.3632283184
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2333916779
Short name T167
Test name
Test status
Simulation time 128286024 ps
CPU time 1.01 seconds
Started Mar 07 01:00:12 PM PST 24
Finished Mar 07 01:00:13 PM PST 24
Peak memory 202612 kb
Host smart-f29a2804-b908-410a-9220-5604438642e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333916779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2333916779
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2316344199
Short name T652
Test name
Test status
Simulation time 60272187 ps
CPU time 1.43 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 202648 kb
Host smart-30cf6ab5-a963-4ade-908d-82c2b7ef723b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316344199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.2316344199
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.4203028434
Short name T680
Test name
Test status
Simulation time 255348141 ps
CPU time 2.82 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:17 PM PST 24
Peak memory 202516 kb
Host smart-2b600690-205b-4332-aa51-17107753b62b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4203028434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.4203028434
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2402958909
Short name T645
Test name
Test status
Simulation time 50069631 ps
CPU time 1.48 seconds
Started Mar 07 01:00:26 PM PST 24
Finished Mar 07 01:00:27 PM PST 24
Peak memory 210920 kb
Host smart-6aa0e28a-f7ec-4740-9a3d-68df9544cdc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402958909 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.2402958909
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1789508967
Short name T163
Test name
Test status
Simulation time 72999204 ps
CPU time 0.98 seconds
Started Mar 07 01:00:25 PM PST 24
Finished Mar 07 01:00:26 PM PST 24
Peak memory 202668 kb
Host smart-f49b71c7-270e-4e88-8ad0-7922e254b0f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789508967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1789508967
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3905733757
Short name T707
Test name
Test status
Simulation time 74616510 ps
CPU time 1.02 seconds
Started Mar 07 01:00:36 PM PST 24
Finished Mar 07 01:00:37 PM PST 24
Peak memory 202468 kb
Host smart-889d6040-c1ca-4def-bb6b-3ec479a17c05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905733757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.3905733757
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3811902243
Short name T714
Test name
Test status
Simulation time 62709436 ps
CPU time 1.79 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 202668 kb
Host smart-c1768bb0-866b-4735-97f3-9fe8e21054cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3811902243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3811902243
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.24924941
Short name T208
Test name
Test status
Simulation time 140419164 ps
CPU time 2.56 seconds
Started Mar 07 01:00:29 PM PST 24
Finished Mar 07 01:00:32 PM PST 24
Peak memory 202532 kb
Host smart-2b888160-5f67-4ebe-89e1-11e17f2e95d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=24924941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.24924941
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.177806562
Short name T693
Test name
Test status
Simulation time 185062042 ps
CPU time 1.83 seconds
Started Mar 07 01:00:40 PM PST 24
Finished Mar 07 01:00:42 PM PST 24
Peak memory 210896 kb
Host smart-20f5f3e7-e7be-4be3-99f8-4e8ad64739cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177806562 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.177806562
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.657053137
Short name T168
Test name
Test status
Simulation time 61051841 ps
CPU time 0.88 seconds
Started Mar 07 01:00:30 PM PST 24
Finished Mar 07 01:00:31 PM PST 24
Peak memory 202344 kb
Host smart-c00e6022-bf2e-4bbd-bc67-138ea4c345e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657053137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.657053137
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1956976168
Short name T696
Test name
Test status
Simulation time 42582976 ps
CPU time 0.99 seconds
Started Mar 07 01:00:29 PM PST 24
Finished Mar 07 01:00:30 PM PST 24
Peak memory 202556 kb
Host smart-7f805484-b0ff-4adc-9d81-617095ea3238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956976168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.1956976168
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.820744974
Short name T154
Test name
Test status
Simulation time 144686904 ps
CPU time 2.08 seconds
Started Mar 07 01:00:36 PM PST 24
Finished Mar 07 01:00:38 PM PST 24
Peak memory 202640 kb
Host smart-868a2456-480f-49f0-9dbf-1cef6a181566
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=820744974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.820744974
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.985720528
Short name T157
Test name
Test status
Simulation time 141079996 ps
CPU time 1.68 seconds
Started Mar 07 01:00:44 PM PST 24
Finished Mar 07 01:00:47 PM PST 24
Peak memory 211064 kb
Host smart-f37e8a08-3ae1-444b-840a-5404e4475a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985720528 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.985720528
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2743830106
Short name T694
Test name
Test status
Simulation time 45740517 ps
CPU time 0.79 seconds
Started Mar 07 01:00:34 PM PST 24
Finished Mar 07 01:00:35 PM PST 24
Peak memory 202316 kb
Host smart-a8d537d3-0938-4f92-ad8f-0e54ee3050a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743830106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2743830106
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2482527972
Short name T202
Test name
Test status
Simulation time 194134553 ps
CPU time 2.11 seconds
Started Mar 07 01:00:15 PM PST 24
Finished Mar 07 01:00:17 PM PST 24
Peak memory 202644 kb
Host smart-50a1a544-e1f9-4a6a-9d4d-1dd11bfed55b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2482527972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2482527972
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2381860596
Short name T43
Test name
Test status
Simulation time 181817899 ps
CPU time 2.54 seconds
Started Mar 07 01:00:34 PM PST 24
Finished Mar 07 01:00:37 PM PST 24
Peak memory 202616 kb
Host smart-3d029d82-b08a-48e2-a3a2-00a83cd4d429
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2381860596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2381860596
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.828357482
Short name T650
Test name
Test status
Simulation time 135447511 ps
CPU time 1.83 seconds
Started Mar 07 01:00:33 PM PST 24
Finished Mar 07 01:00:35 PM PST 24
Peak memory 210876 kb
Host smart-8c497f92-24ca-4f67-b90b-dfb4c73c04be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828357482 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.828357482
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1304288683
Short name T161
Test name
Test status
Simulation time 53045229 ps
CPU time 0.83 seconds
Started Mar 07 01:00:39 PM PST 24
Finished Mar 07 01:00:40 PM PST 24
Peak memory 202476 kb
Host smart-ad9288ba-62c6-490a-8902-7519cac6ee07
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304288683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1304288683
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1297218071
Short name T663
Test name
Test status
Simulation time 139443876 ps
CPU time 1.59 seconds
Started Mar 07 01:00:34 PM PST 24
Finished Mar 07 01:00:36 PM PST 24
Peak memory 202728 kb
Host smart-ac47c669-fe29-4fda-a333-e07014a2a1b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297218071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.1297218071
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2159290018
Short name T710
Test name
Test status
Simulation time 85262652 ps
CPU time 2.56 seconds
Started Mar 07 01:00:13 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 202568 kb
Host smart-4649b791-6073-4fbe-9953-99019092621c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2159290018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2159290018
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2982773231
Short name T701
Test name
Test status
Simulation time 74643847 ps
CPU time 1.14 seconds
Started Mar 07 01:00:35 PM PST 24
Finished Mar 07 01:00:36 PM PST 24
Peak memory 210896 kb
Host smart-83168eb9-386c-4196-bc12-b438e7d52fea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982773231 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.2982773231
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3576524675
Short name T672
Test name
Test status
Simulation time 30133058 ps
CPU time 0.87 seconds
Started Mar 07 01:00:15 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 202408 kb
Host smart-b0ac262c-12cc-49b0-aeda-cb23f888920a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576524675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3576524675
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1474348653
Short name T206
Test name
Test status
Simulation time 160520544 ps
CPU time 1.63 seconds
Started Mar 07 01:00:12 PM PST 24
Finished Mar 07 01:00:14 PM PST 24
Peak memory 202680 kb
Host smart-6b829c33-d044-412c-af4b-1742887d8b18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474348653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.1474348653
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2447716656
Short name T649
Test name
Test status
Simulation time 204724012 ps
CPU time 2.33 seconds
Started Mar 07 01:00:27 PM PST 24
Finished Mar 07 01:00:29 PM PST 24
Peak memory 202624 kb
Host smart-10b30432-a661-4545-9dde-5a7558874a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2447716656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2447716656
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3396997087
Short name T664
Test name
Test status
Simulation time 43146670 ps
CPU time 1.32 seconds
Started Mar 07 01:00:24 PM PST 24
Finished Mar 07 01:00:26 PM PST 24
Peak memory 211956 kb
Host smart-4c6afaae-fb2d-4568-ae0b-38bcce626a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396997087 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.3396997087
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2734566366
Short name T49
Test name
Test status
Simulation time 54763578 ps
CPU time 0.98 seconds
Started Mar 07 01:00:37 PM PST 24
Finished Mar 07 01:00:38 PM PST 24
Peak memory 202604 kb
Host smart-b26d9fff-a3fc-48d2-860f-6d6b1c79b2fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734566366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2734566366
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3497384634
Short name T654
Test name
Test status
Simulation time 220528630 ps
CPU time 2.79 seconds
Started Mar 07 01:00:35 PM PST 24
Finished Mar 07 01:00:38 PM PST 24
Peak memory 202556 kb
Host smart-c2fb7342-2fab-4165-a99d-b0fc58f2ff93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3497384634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3497384634
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3335885451
Short name T657
Test name
Test status
Simulation time 191171935 ps
CPU time 2.8 seconds
Started Mar 07 01:00:40 PM PST 24
Finished Mar 07 01:00:43 PM PST 24
Peak memory 210816 kb
Host smart-b2dd7c71-6f77-4689-91bb-4d858171508a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335885451 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3335885451
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.562408360
Short name T688
Test name
Test status
Simulation time 35544902 ps
CPU time 0.8 seconds
Started Mar 07 01:00:30 PM PST 24
Finished Mar 07 01:00:31 PM PST 24
Peak memory 202340 kb
Host smart-dec1ce19-ab9f-4292-90e4-6de68db4dfa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562408360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.562408360
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3448799049
Short name T229
Test name
Test status
Simulation time 27225370 ps
CPU time 0.64 seconds
Started Mar 07 01:00:19 PM PST 24
Finished Mar 07 01:00:19 PM PST 24
Peak memory 201900 kb
Host smart-a5787770-8c67-4d39-9e9f-add6e524d3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3448799049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3448799049
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3934574056
Short name T676
Test name
Test status
Simulation time 334437947 ps
CPU time 3.83 seconds
Started Mar 07 01:00:02 PM PST 24
Finished Mar 07 01:00:06 PM PST 24
Peak memory 202564 kb
Host smart-2a20bc4f-51bd-4d32-9039-9706076a7e95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934574056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3934574056
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3104731955
Short name T660
Test name
Test status
Simulation time 50480749 ps
CPU time 0.82 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:15 PM PST 24
Peak memory 202452 kb
Host smart-8fd012c6-c243-4391-99d3-9bff443ef9d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104731955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3104731955
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2756918175
Short name T679
Test name
Test status
Simulation time 126326306 ps
CPU time 1.73 seconds
Started Mar 07 01:00:09 PM PST 24
Finished Mar 07 01:00:11 PM PST 24
Peak memory 202724 kb
Host smart-29919c36-540f-4bea-8546-0f68afde4066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756918175 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.2756918175
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2465631431
Short name T683
Test name
Test status
Simulation time 41082886 ps
CPU time 0.79 seconds
Started Mar 07 01:00:15 PM PST 24
Finished Mar 07 01:00:15 PM PST 24
Peak memory 202388 kb
Host smart-7f529be6-61b6-4cfa-8ec5-75e825b5a3b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465631431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2465631431
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.456849360
Short name T659
Test name
Test status
Simulation time 40707050 ps
CPU time 1.38 seconds
Started Mar 07 01:00:13 PM PST 24
Finished Mar 07 01:00:15 PM PST 24
Peak memory 202588 kb
Host smart-8ebb76d7-25da-41e3-a3e7-fe089456ade0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=456849360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.456849360
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.325906063
Short name T665
Test name
Test status
Simulation time 379116943 ps
CPU time 2.6 seconds
Started Mar 07 01:00:08 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 202536 kb
Host smart-529c0d81-aae4-41bd-aee0-3a99df166ec7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=325906063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.325906063
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3703099777
Short name T668
Test name
Test status
Simulation time 171050161 ps
CPU time 1.54 seconds
Started Mar 07 01:00:18 PM PST 24
Finished Mar 07 01:00:20 PM PST 24
Peak memory 202536 kb
Host smart-0f101da6-172d-4e9b-8038-e113f3d5bb5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703099777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.3703099777
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1319270525
Short name T156
Test name
Test status
Simulation time 96820795 ps
CPU time 2.93 seconds
Started Mar 07 01:00:09 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 202480 kb
Host smart-c8630205-4d72-422d-9559-236760b7680f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1319270525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1319270525
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1553490518
Short name T231
Test name
Test status
Simulation time 210746293 ps
CPU time 2.54 seconds
Started Mar 07 01:00:02 PM PST 24
Finished Mar 07 01:00:05 PM PST 24
Peak memory 202668 kb
Host smart-80d9c940-65a6-4c28-8b4b-3305b00b7adb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1553490518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1553490518
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.565098397
Short name T669
Test name
Test status
Simulation time 43618406 ps
CPU time 0.66 seconds
Started Mar 07 01:00:16 PM PST 24
Finished Mar 07 01:00:17 PM PST 24
Peak memory 201872 kb
Host smart-f8185401-79dd-406b-b374-13411f3ab1b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=565098397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.565098397
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1787140234
Short name T226
Test name
Test status
Simulation time 22080009 ps
CPU time 0.62 seconds
Started Mar 07 01:00:36 PM PST 24
Finished Mar 07 01:00:37 PM PST 24
Peak memory 201932 kb
Host smart-b5348f68-cd50-41de-8a87-9828879a5c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1787140234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1787140234
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2845652661
Short name T700
Test name
Test status
Simulation time 27833302 ps
CPU time 0.63 seconds
Started Mar 07 01:00:36 PM PST 24
Finished Mar 07 01:00:37 PM PST 24
Peak memory 201776 kb
Host smart-582ef797-709c-496a-9a8a-73d17087a4cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2845652661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2845652661
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.4293911941
Short name T711
Test name
Test status
Simulation time 45345706 ps
CPU time 0.67 seconds
Started Mar 07 01:00:38 PM PST 24
Finished Mar 07 01:00:39 PM PST 24
Peak memory 201804 kb
Host smart-3f339bf2-45c1-4188-8721-32ea56c04cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4293911941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.4293911941
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3484042180
Short name T223
Test name
Test status
Simulation time 40456941 ps
CPU time 0.73 seconds
Started Mar 07 01:00:29 PM PST 24
Finished Mar 07 01:00:35 PM PST 24
Peak memory 201824 kb
Host smart-4c482069-2e90-4fb5-95d3-69f42c4aaf14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3484042180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3484042180
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.861585677
Short name T685
Test name
Test status
Simulation time 28082756 ps
CPU time 0.61 seconds
Started Mar 07 01:00:27 PM PST 24
Finished Mar 07 01:00:28 PM PST 24
Peak memory 201808 kb
Host smart-5074b8c6-f74d-4d3a-9203-98981e1b41d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=861585677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.861585677
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2072674047
Short name T671
Test name
Test status
Simulation time 368007446 ps
CPU time 8.36 seconds
Started Mar 07 01:00:13 PM PST 24
Finished Mar 07 01:00:21 PM PST 24
Peak memory 202448 kb
Host smart-f24ba1c1-6dfd-422c-a395-e739fe93aafc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072674047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2072674047
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.186401571
Short name T50
Test name
Test status
Simulation time 39442993 ps
CPU time 0.73 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:14 PM PST 24
Peak memory 202424 kb
Host smart-884aa909-9d02-47e1-b24f-7785c348ea62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186401571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.186401571
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3940465988
Short name T706
Test name
Test status
Simulation time 78071805 ps
CPU time 1.25 seconds
Started Mar 07 01:00:06 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 202712 kb
Host smart-4ccfae5e-121c-4065-a6b0-8f35870b709c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940465988 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.3940465988
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2322261613
Short name T689
Test name
Test status
Simulation time 52542959 ps
CPU time 0.8 seconds
Started Mar 07 01:00:13 PM PST 24
Finished Mar 07 01:00:14 PM PST 24
Peak memory 202228 kb
Host smart-89e04832-f2ac-44b1-a60a-4bf3082625e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322261613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2322261613
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.691650720
Short name T690
Test name
Test status
Simulation time 19385858 ps
CPU time 0.63 seconds
Started Mar 07 01:00:12 PM PST 24
Finished Mar 07 01:00:13 PM PST 24
Peak memory 201816 kb
Host smart-be64e803-3baf-423f-bcc8-6a0dae447b20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=691650720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.691650720
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3485514621
Short name T705
Test name
Test status
Simulation time 99580831 ps
CPU time 1.42 seconds
Started Mar 07 01:00:23 PM PST 24
Finished Mar 07 01:00:25 PM PST 24
Peak memory 202544 kb
Host smart-6ffc920f-2106-4733-b651-ad8991bec70b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3485514621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3485514621
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2776832741
Short name T651
Test name
Test status
Simulation time 83919566 ps
CPU time 2.25 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 202552 kb
Host smart-7358c2f9-5285-47ad-adf7-3a6392edbb0d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2776832741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2776832741
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.942063879
Short name T695
Test name
Test status
Simulation time 144578318 ps
CPU time 1.69 seconds
Started Mar 07 01:00:11 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 202568 kb
Host smart-768e3b43-9eea-4d07-a342-d61c847d228b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942063879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_cs
r_outstanding.942063879
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1458130086
Short name T702
Test name
Test status
Simulation time 123939287 ps
CPU time 1.47 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 202556 kb
Host smart-4695a69e-c0e8-4806-ae2f-79cb9f735171
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1458130086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1458130086
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.807441168
Short name T210
Test name
Test status
Simulation time 280606280 ps
CPU time 2.78 seconds
Started Mar 07 01:00:27 PM PST 24
Finished Mar 07 01:00:30 PM PST 24
Peak memory 202572 kb
Host smart-7800ad44-2b2d-4c5d-9e9b-dbc407051a07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=807441168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.807441168
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3271484670
Short name T220
Test name
Test status
Simulation time 29148850 ps
CPU time 0.66 seconds
Started Mar 07 01:00:26 PM PST 24
Finished Mar 07 01:00:26 PM PST 24
Peak memory 201872 kb
Host smart-2c313c82-dc02-4b98-8271-a8e5e1766305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3271484670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3271484670
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1497812044
Short name T691
Test name
Test status
Simulation time 26943461 ps
CPU time 0.62 seconds
Started Mar 07 01:00:44 PM PST 24
Finished Mar 07 01:00:45 PM PST 24
Peak memory 201976 kb
Host smart-ab8d5bf6-e8dd-4ccf-8a27-b6d8e8022321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1497812044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1497812044
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.126813229
Short name T222
Test name
Test status
Simulation time 21629509 ps
CPU time 0.62 seconds
Started Mar 07 01:00:33 PM PST 24
Finished Mar 07 01:00:34 PM PST 24
Peak memory 201904 kb
Host smart-48da77a1-2a4b-4b30-8340-e7c4f652255d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126813229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.126813229
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1052879128
Short name T227
Test name
Test status
Simulation time 129792302 ps
CPU time 0.76 seconds
Started Mar 07 01:00:41 PM PST 24
Finished Mar 07 01:00:42 PM PST 24
Peak memory 201880 kb
Host smart-27e7fe4b-a59b-4e5e-8ad0-dc771b489093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1052879128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1052879128
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1686390610
Short name T715
Test name
Test status
Simulation time 47994925 ps
CPU time 0.67 seconds
Started Mar 07 01:00:32 PM PST 24
Finished Mar 07 01:00:33 PM PST 24
Peak memory 201876 kb
Host smart-50aa5097-6406-4479-89f0-6e2090140c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1686390610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1686390610
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.691620105
Short name T219
Test name
Test status
Simulation time 24091844 ps
CPU time 0.62 seconds
Started Mar 07 01:00:22 PM PST 24
Finished Mar 07 01:00:23 PM PST 24
Peak memory 201868 kb
Host smart-27f1fd86-582d-4cf0-9157-677352288c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=691620105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.691620105
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3843099354
Short name T224
Test name
Test status
Simulation time 46703166 ps
CPU time 0.65 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:00:57 PM PST 24
Peak memory 201896 kb
Host smart-d0dcbeb5-62f6-47fc-ada8-e2022f575c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3843099354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3843099354
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1362281575
Short name T160
Test name
Test status
Simulation time 387574447 ps
CPU time 3.73 seconds
Started Mar 07 01:00:07 PM PST 24
Finished Mar 07 01:00:11 PM PST 24
Peak memory 202676 kb
Host smart-0c9d6839-2251-43a3-bc8f-47c88e8e9671
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362281575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1362281575
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2324608615
Short name T152
Test name
Test status
Simulation time 76058894 ps
CPU time 1.09 seconds
Started Mar 07 01:00:15 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 218308 kb
Host smart-a951235a-a7e3-410e-be07-08d25569a977
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324608615 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2324608615
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4188371752
Short name T709
Test name
Test status
Simulation time 48250172 ps
CPU time 0.85 seconds
Started Mar 07 01:00:19 PM PST 24
Finished Mar 07 01:00:25 PM PST 24
Peak memory 202464 kb
Host smart-57b0bdfa-59e0-4a8d-a507-c60cd35470a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188371752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.4188371752
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1065970111
Short name T212
Test name
Test status
Simulation time 30767695 ps
CPU time 0.65 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:15 PM PST 24
Peak memory 201788 kb
Host smart-bb5f2eda-40e8-47aa-8c6a-e2ee3be4e457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1065970111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1065970111
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.222155356
Short name T204
Test name
Test status
Simulation time 153307868 ps
CPU time 3.78 seconds
Started Mar 07 01:00:00 PM PST 24
Finished Mar 07 01:00:04 PM PST 24
Peak memory 202608 kb
Host smart-c3835ed0-56f2-42ff-b54c-66d78a909089
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=222155356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.222155356
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1303111008
Short name T648
Test name
Test status
Simulation time 122393441 ps
CPU time 1.58 seconds
Started Mar 07 01:00:13 PM PST 24
Finished Mar 07 01:00:15 PM PST 24
Peak memory 202660 kb
Host smart-a10abc57-f586-40d0-ae1c-6e3cea677111
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303111008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.1303111008
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2398836818
Short name T687
Test name
Test status
Simulation time 177220449 ps
CPU time 2.18 seconds
Started Mar 07 01:00:03 PM PST 24
Finished Mar 07 01:00:05 PM PST 24
Peak memory 202660 kb
Host smart-a678db38-c5b2-44f3-acab-07b86af88a93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2398836818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2398836818
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1344401629
Short name T214
Test name
Test status
Simulation time 39454809 ps
CPU time 0.65 seconds
Started Mar 07 01:00:29 PM PST 24
Finished Mar 07 01:00:30 PM PST 24
Peak memory 201888 kb
Host smart-aee86d51-955c-41e8-a547-70428579eadd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1344401629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1344401629
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.395643405
Short name T704
Test name
Test status
Simulation time 20320426 ps
CPU time 0.63 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 201920 kb
Host smart-ff35dc09-32d3-4977-833e-f9973e1674cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=395643405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.395643405
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1861128583
Short name T54
Test name
Test status
Simulation time 25960380 ps
CPU time 0.65 seconds
Started Mar 07 01:00:40 PM PST 24
Finished Mar 07 01:00:41 PM PST 24
Peak memory 201836 kb
Host smart-e82e1a0b-cb63-4ebc-acd2-e9009e44965f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1861128583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1861128583
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2856904158
Short name T218
Test name
Test status
Simulation time 61173033 ps
CPU time 0.67 seconds
Started Mar 07 01:00:32 PM PST 24
Finished Mar 07 01:00:33 PM PST 24
Peak memory 201880 kb
Host smart-3322dd35-4438-46ed-bee1-1d372283d0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2856904158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2856904158
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1864088594
Short name T55
Test name
Test status
Simulation time 20509683 ps
CPU time 0.64 seconds
Started Mar 07 01:00:34 PM PST 24
Finished Mar 07 01:00:35 PM PST 24
Peak memory 201736 kb
Host smart-fea92837-82f5-4702-a0ff-d0abc957425c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1864088594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1864088594
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2441939594
Short name T699
Test name
Test status
Simulation time 33980321 ps
CPU time 0.65 seconds
Started Mar 07 01:00:58 PM PST 24
Finished Mar 07 01:00:59 PM PST 24
Peak memory 201872 kb
Host smart-9d32e5e4-fcd6-443b-a4b6-9fb773e62387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2441939594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2441939594
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3399901984
Short name T225
Test name
Test status
Simulation time 22685057 ps
CPU time 0.64 seconds
Started Mar 07 01:00:43 PM PST 24
Finished Mar 07 01:00:44 PM PST 24
Peak memory 201876 kb
Host smart-6a977078-c8e0-4fb4-b667-d2bf5f932c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3399901984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3399901984
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3074994439
Short name T712
Test name
Test status
Simulation time 29389144 ps
CPU time 0.64 seconds
Started Mar 07 01:00:44 PM PST 24
Finished Mar 07 01:00:45 PM PST 24
Peak memory 201888 kb
Host smart-600c5f9a-afdc-4610-a955-a4d207078680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3074994439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3074994439
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2090986521
Short name T75
Test name
Test status
Simulation time 49114635 ps
CPU time 1.38 seconds
Started Mar 07 01:00:22 PM PST 24
Finished Mar 07 01:00:24 PM PST 24
Peak memory 212320 kb
Host smart-1d5569d5-887f-4c5e-9530-33fbaa636ac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090986521 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.2090986521
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3464933762
Short name T72
Test name
Test status
Simulation time 35706664 ps
CPU time 0.94 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:11 PM PST 24
Peak memory 202628 kb
Host smart-ac389ccf-708d-4813-8612-ee5e995a444e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464933762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3464933762
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2959238147
Short name T221
Test name
Test status
Simulation time 31656576 ps
CPU time 0.65 seconds
Started Mar 07 01:00:24 PM PST 24
Finished Mar 07 01:00:25 PM PST 24
Peak memory 201816 kb
Host smart-ac2e663f-2b53-4516-93a0-96c4d16492a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2959238147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2959238147
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2654118926
Short name T658
Test name
Test status
Simulation time 42563566 ps
CPU time 1.01 seconds
Started Mar 07 01:00:19 PM PST 24
Finished Mar 07 01:00:20 PM PST 24
Peak memory 202544 kb
Host smart-3f0e259d-669c-489c-808b-9cf3a0b2cb40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654118926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.2654118926
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3742227060
Short name T681
Test name
Test status
Simulation time 90013915 ps
CPU time 2.45 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:17 PM PST 24
Peak memory 202664 kb
Host smart-a7cbb026-d008-45a0-8df1-6452122685f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3742227060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3742227060
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2301075430
Short name T682
Test name
Test status
Simulation time 55942011 ps
CPU time 1.64 seconds
Started Mar 07 01:00:24 PM PST 24
Finished Mar 07 01:00:26 PM PST 24
Peak memory 210912 kb
Host smart-15078cfd-94b2-4276-8e38-9f90d687c324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301075430 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.2301075430
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4218684599
Short name T165
Test name
Test status
Simulation time 69660759 ps
CPU time 1.01 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:11 PM PST 24
Peak memory 202696 kb
Host smart-85e8f5ad-32c0-49f7-9c32-d650e7d54198
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218684599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4218684599
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.542724830
Short name T708
Test name
Test status
Simulation time 25346418 ps
CPU time 0.62 seconds
Started Mar 07 01:00:19 PM PST 24
Finished Mar 07 01:00:20 PM PST 24
Peak memory 201912 kb
Host smart-4dd676ff-eb17-4268-b79c-ff3deed517cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=542724830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.542724830
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1372643424
Short name T205
Test name
Test status
Simulation time 79489342 ps
CPU time 0.99 seconds
Started Mar 07 01:00:28 PM PST 24
Finished Mar 07 01:00:29 PM PST 24
Peak memory 202560 kb
Host smart-74115ec4-c716-4a8a-9692-b4f3e3d98b9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372643424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.1372643424
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3425983739
Short name T647
Test name
Test status
Simulation time 105864680 ps
CPU time 1.52 seconds
Started Mar 07 01:00:18 PM PST 24
Finished Mar 07 01:00:19 PM PST 24
Peak memory 202508 kb
Host smart-b80fa4f6-30a9-448b-83ec-269a2c9220ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3425983739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3425983739
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2128317745
Short name T698
Test name
Test status
Simulation time 391991664 ps
CPU time 2.98 seconds
Started Mar 07 01:00:22 PM PST 24
Finished Mar 07 01:00:25 PM PST 24
Peak memory 202648 kb
Host smart-b8dc4479-3232-45fa-a720-0ab289885cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2128317745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2128317745
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3760146326
Short name T697
Test name
Test status
Simulation time 111242860 ps
CPU time 1.66 seconds
Started Mar 07 01:00:30 PM PST 24
Finished Mar 07 01:00:31 PM PST 24
Peak memory 213164 kb
Host smart-b56daf90-7677-4cc1-a78f-d0e5ea7c329a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760146326 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.3760146326
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2214458771
Short name T169
Test name
Test status
Simulation time 40006351 ps
CPU time 0.78 seconds
Started Mar 07 01:00:28 PM PST 24
Finished Mar 07 01:00:29 PM PST 24
Peak memory 202388 kb
Host smart-ccbee3fe-f78d-4c90-84f8-ce2b059ea0c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214458771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2214458771
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2957887497
Short name T73
Test name
Test status
Simulation time 58290018 ps
CPU time 1.39 seconds
Started Mar 07 01:00:03 PM PST 24
Finished Mar 07 01:00:04 PM PST 24
Peak memory 202668 kb
Host smart-8c147c8f-fe3d-4534-bf97-d3822a596da8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957887497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.2957887497
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2175059298
Short name T673
Test name
Test status
Simulation time 212141145 ps
CPU time 2.19 seconds
Started Mar 07 01:00:15 PM PST 24
Finished Mar 07 01:00:17 PM PST 24
Peak memory 202564 kb
Host smart-183467f3-7289-4b9b-b509-28b94a6b5bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2175059298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2175059298
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.238220210
Short name T203
Test name
Test status
Simulation time 85216790 ps
CPU time 1.23 seconds
Started Mar 07 01:00:07 PM PST 24
Finished Mar 07 01:00:08 PM PST 24
Peak memory 210844 kb
Host smart-0270f361-1f0a-4ef7-954a-0fa54c6147e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238220210 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.238220210
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1956363939
Short name T166
Test name
Test status
Simulation time 31742420 ps
CPU time 0.82 seconds
Started Mar 07 01:00:33 PM PST 24
Finished Mar 07 01:00:34 PM PST 24
Peak memory 202284 kb
Host smart-2d18b05f-bf12-4247-b39d-e4ac78c95863
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956363939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1956363939
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2830080424
Short name T646
Test name
Test status
Simulation time 122407491 ps
CPU time 1.45 seconds
Started Mar 07 01:00:17 PM PST 24
Finished Mar 07 01:00:19 PM PST 24
Peak memory 202640 kb
Host smart-6bbc7254-d39f-4d5a-9299-b81be59f1321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830080424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.2830080424
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4214604623
Short name T201
Test name
Test status
Simulation time 86851636 ps
CPU time 1.31 seconds
Started Mar 07 01:00:33 PM PST 24
Finished Mar 07 01:00:34 PM PST 24
Peak memory 202596 kb
Host smart-c55e55d3-6157-493e-a731-203822911133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4214604623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4214604623
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3981165990
Short name T667
Test name
Test status
Simulation time 38954537 ps
CPU time 1.16 seconds
Started Mar 07 01:00:21 PM PST 24
Finished Mar 07 01:00:23 PM PST 24
Peak memory 202644 kb
Host smart-36fc29bc-336b-468e-9676-b8d3fb8a33f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981165990 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.3981165990
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1617971037
Short name T674
Test name
Test status
Simulation time 41156919 ps
CPU time 0.83 seconds
Started Mar 07 01:00:30 PM PST 24
Finished Mar 07 01:00:31 PM PST 24
Peak memory 202472 kb
Host smart-dd071c91-a405-47ef-9573-6b2bb39a82fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617971037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1617971037
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1858594723
Short name T170
Test name
Test status
Simulation time 122218775 ps
CPU time 1.51 seconds
Started Mar 07 01:00:17 PM PST 24
Finished Mar 07 01:00:19 PM PST 24
Peak memory 202528 kb
Host smart-b6b669a1-ac6a-42fa-af21-029d4011a4c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858594723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.1858594723
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4127363266
Short name T677
Test name
Test status
Simulation time 239296904 ps
CPU time 2.4 seconds
Started Mar 07 01:00:44 PM PST 24
Finished Mar 07 01:00:47 PM PST 24
Peak memory 202608 kb
Host smart-e79423de-e840-4326-891f-d6ea551b0b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4127363266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4127363266
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2289784828
Short name T490
Test name
Test status
Simulation time 8369033585 ps
CPU time 9.09 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:25 PM PST 24
Peak memory 202492 kb
Host smart-b7552d22-a4dc-4b09-a33a-fc70d4ed09f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
84828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2289784828
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.58167721
Short name T632
Test name
Test status
Simulation time 262397126 ps
CPU time 2.02 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:18 PM PST 24
Peak memory 202468 kb
Host smart-815bc306-24fa-4f92-a2c6-7c713f99ef56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58167
721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.58167721
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1134541712
Short name T551
Test name
Test status
Simulation time 8434770918 ps
CPU time 7.89 seconds
Started Mar 07 01:48:22 PM PST 24
Finished Mar 07 01:48:30 PM PST 24
Peak memory 202392 kb
Host smart-dda1dacf-5f95-444b-933e-9c9776234313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11345
41712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1134541712
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3568576018
Short name T289
Test name
Test status
Simulation time 8419387973 ps
CPU time 8.69 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:25 PM PST 24
Peak memory 202516 kb
Host smart-80a36ba3-f383-4239-8515-aceab373e504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35685
76018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3568576018
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2240995834
Short name T433
Test name
Test status
Simulation time 8377886193 ps
CPU time 7.57 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:24 PM PST 24
Peak memory 202472 kb
Host smart-cc22d001-a71e-4192-8a49-12e837b0ba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
95834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2240995834
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3561904949
Short name T440
Test name
Test status
Simulation time 8431898110 ps
CPU time 9.26 seconds
Started Mar 07 01:48:17 PM PST 24
Finished Mar 07 01:48:27 PM PST 24
Peak memory 202536 kb
Host smart-7db007c2-f9cf-4bf4-9205-78d88a5c1013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35619
04949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3561904949
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3477317503
Short name T37
Test name
Test status
Simulation time 8434714115 ps
CPU time 7.26 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 202472 kb
Host smart-4add72bc-d3a3-477d-89f8-23112a54ebdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34773
17503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3477317503
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2517407413
Short name T124
Test name
Test status
Simulation time 8415237127 ps
CPU time 7.41 seconds
Started Mar 07 01:48:21 PM PST 24
Finished Mar 07 01:48:28 PM PST 24
Peak memory 202392 kb
Host smart-1fd5f02b-3881-4a88-952c-12ac449b8d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
07413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2517407413
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1831379474
Short name T181
Test name
Test status
Simulation time 8365040278 ps
CPU time 8.58 seconds
Started Mar 07 01:48:15 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 202572 kb
Host smart-75c6a08e-21e9-425e-9075-d94a5493faf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313
79474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1831379474
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1573446089
Short name T321
Test name
Test status
Simulation time 8358798744 ps
CPU time 8.39 seconds
Started Mar 07 01:48:15 PM PST 24
Finished Mar 07 01:48:24 PM PST 24
Peak memory 202496 kb
Host smart-d9c53c41-e034-42b9-b242-c345b8ff3684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15734
46089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1573446089
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3331180683
Short name T625
Test name
Test status
Simulation time 8477611291 ps
CPU time 8.07 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:24 PM PST 24
Peak memory 202492 kb
Host smart-69aabed4-cfd1-47f5-b499-16145057668f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33311
80683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3331180683
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2371683129
Short name T31
Test name
Test status
Simulation time 8370259147 ps
CPU time 8.27 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:24 PM PST 24
Peak memory 202492 kb
Host smart-660d9533-2c2b-4fc2-a80b-a8b600420f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23716
83129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2371683129
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.4131591022
Short name T333
Test name
Test status
Simulation time 171768528 ps
CPU time 1.83 seconds
Started Mar 07 01:48:24 PM PST 24
Finished Mar 07 01:48:27 PM PST 24
Peak memory 202432 kb
Host smart-30a80fb9-dff0-4a08-ad9b-6919a626e029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
91022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.4131591022
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1103719488
Short name T503
Test name
Test status
Simulation time 8429243693 ps
CPU time 8.91 seconds
Started Mar 07 01:48:17 PM PST 24
Finished Mar 07 01:48:26 PM PST 24
Peak memory 202452 kb
Host smart-271f468a-2e11-416f-ac38-eb5303d536ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11037
19488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1103719488
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2545025209
Short name T244
Test name
Test status
Simulation time 8405298668 ps
CPU time 7.46 seconds
Started Mar 07 01:48:17 PM PST 24
Finished Mar 07 01:48:25 PM PST 24
Peak memory 202592 kb
Host smart-c5256602-e0f0-4b9b-aa85-a59f3b67fd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25450
25209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2545025209
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2449654809
Short name T388
Test name
Test status
Simulation time 8371272647 ps
CPU time 7.22 seconds
Started Mar 07 01:48:19 PM PST 24
Finished Mar 07 01:48:27 PM PST 24
Peak memory 202336 kb
Host smart-6e3319ca-d30c-4d0d-848a-4ec592346491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24496
54809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2449654809
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1339404364
Short name T392
Test name
Test status
Simulation time 8408315938 ps
CPU time 7.26 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:23 PM PST 24
Peak memory 202352 kb
Host smart-dfaa939a-ab1c-4512-aa06-03297970a717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
04364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1339404364
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3633946097
Short name T494
Test name
Test status
Simulation time 8369481461 ps
CPU time 9.09 seconds
Started Mar 07 01:48:27 PM PST 24
Finished Mar 07 01:48:36 PM PST 24
Peak memory 202504 kb
Host smart-e0b65b51-bd83-49b1-b126-9116e45a8281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36339
46097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3633946097
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3480032813
Short name T362
Test name
Test status
Simulation time 8385798130 ps
CPU time 7.8 seconds
Started Mar 07 01:48:14 PM PST 24
Finished Mar 07 01:48:22 PM PST 24
Peak memory 202512 kb
Host smart-92c3a7a1-1cbf-400e-8c7a-20a127496e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34800
32813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3480032813
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.794048729
Short name T337
Test name
Test status
Simulation time 8388025525 ps
CPU time 7.39 seconds
Started Mar 07 01:48:16 PM PST 24
Finished Mar 07 01:48:24 PM PST 24
Peak memory 202348 kb
Host smart-616563be-c1e6-4b99-af0d-6909ce81fe8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79404
8729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.794048729
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_smoke.4230659113
Short name T137
Test name
Test status
Simulation time 8473950794 ps
CPU time 7.57 seconds
Started Mar 07 01:48:15 PM PST 24
Finished Mar 07 01:48:22 PM PST 24
Peak memory 202452 kb
Host smart-0d4a0d3f-b82e-4360-907e-67b324d33fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
59113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.4230659113
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.863791170
Short name T305
Test name
Test status
Simulation time 8366571740 ps
CPU time 9.92 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:20 PM PST 24
Peak memory 202460 kb
Host smart-5cb84a53-d55e-4dd6-aa7e-34628d133335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86379
1170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.863791170
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3584126274
Short name T488
Test name
Test status
Simulation time 222816591 ps
CPU time 1.83 seconds
Started Mar 07 01:49:10 PM PST 24
Finished Mar 07 01:49:13 PM PST 24
Peak memory 202420 kb
Host smart-0b5fad75-755a-440b-9373-e2333b921f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35841
26274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3584126274
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.4280020704
Short name T114
Test name
Test status
Simulation time 8399206213 ps
CPU time 7.35 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:17 PM PST 24
Peak memory 202536 kb
Host smart-3331aa39-f9bd-4671-bcfd-4544d320f789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42800
20704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.4280020704
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1160119902
Short name T532
Test name
Test status
Simulation time 8414000804 ps
CPU time 7.15 seconds
Started Mar 07 01:49:07 PM PST 24
Finished Mar 07 01:49:14 PM PST 24
Peak memory 202436 kb
Host smart-b3b6d6fa-d13e-404e-a67b-e7802519c563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11601
19902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1160119902
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1614333590
Short name T409
Test name
Test status
Simulation time 8362361154 ps
CPU time 7.9 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 202484 kb
Host smart-b0dfee37-8f45-4fb5-acfb-f7928767a50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16143
33590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1614333590
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3191813790
Short name T480
Test name
Test status
Simulation time 8383877288 ps
CPU time 7.9 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:17 PM PST 24
Peak memory 202512 kb
Host smart-ca88c392-5099-4406-9b88-50552080a73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31918
13790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3191813790
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.3656250720
Short name T272
Test name
Test status
Simulation time 8415558681 ps
CPU time 7.49 seconds
Started Mar 07 01:49:11 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 202516 kb
Host smart-9b8b8eb4-ae93-46a5-b368-410044acb286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
50720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.3656250720
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3577088844
Short name T633
Test name
Test status
Simulation time 8445297826 ps
CPU time 9.73 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 202512 kb
Host smart-afeaa057-4368-488e-9146-c6c3d573e374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35770
88844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3577088844
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.1159438682
Short name T346
Test name
Test status
Simulation time 8386526079 ps
CPU time 8 seconds
Started Mar 07 01:49:13 PM PST 24
Finished Mar 07 01:49:22 PM PST 24
Peak memory 202492 kb
Host smart-9e173ce4-eab9-436c-9839-242ff07b3135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11594
38682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.1159438682
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.876826403
Short name T489
Test name
Test status
Simulation time 8384236141 ps
CPU time 8.47 seconds
Started Mar 07 01:49:08 PM PST 24
Finished Mar 07 01:49:16 PM PST 24
Peak memory 202492 kb
Host smart-1fd3822a-2d2b-4565-b548-ed98d65b0221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87682
6403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.876826403
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1898483053
Short name T539
Test name
Test status
Simulation time 8480142833 ps
CPU time 9.38 seconds
Started Mar 07 01:49:08 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 202460 kb
Host smart-dc97d9db-94c4-4195-aa07-74a9f06f1546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18984
83053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1898483053
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.942213895
Short name T200
Test name
Test status
Simulation time 8366648201 ps
CPU time 8.17 seconds
Started Mar 07 01:49:10 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 202472 kb
Host smart-81bb9d70-1cdb-4777-8f2f-83746bafe9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94221
3895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.942213895
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.846823106
Short name T38
Test name
Test status
Simulation time 189671727 ps
CPU time 1.65 seconds
Started Mar 07 01:49:15 PM PST 24
Finished Mar 07 01:49:17 PM PST 24
Peak memory 202428 kb
Host smart-c1da70c0-e7b5-4058-ba19-67dcb64e2810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84682
3106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.846823106
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1985113669
Short name T577
Test name
Test status
Simulation time 8428501933 ps
CPU time 7.71 seconds
Started Mar 07 01:49:12 PM PST 24
Finished Mar 07 01:49:20 PM PST 24
Peak memory 202480 kb
Host smart-662eaf1f-7139-40c1-a832-9de54db09a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19851
13669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1985113669
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1947950627
Short name T291
Test name
Test status
Simulation time 8407369062 ps
CPU time 9.07 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 202508 kb
Host smart-9040d52a-1338-429d-b013-62b9fc291ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19479
50627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1947950627
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1549895085
Short name T9
Test name
Test status
Simulation time 8366067543 ps
CPU time 7.23 seconds
Started Mar 07 01:49:13 PM PST 24
Finished Mar 07 01:49:21 PM PST 24
Peak memory 202512 kb
Host smart-b5e2dbb5-b0ad-44da-a2f5-a0d6a9c07e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15498
95085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1549895085
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1672043798
Short name T247
Test name
Test status
Simulation time 8386327580 ps
CPU time 7.77 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:17 PM PST 24
Peak memory 202472 kb
Host smart-b7eb2677-78c3-407d-9877-d0d322ae61fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16720
43798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1672043798
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.271373089
Short name T254
Test name
Test status
Simulation time 8396496356 ps
CPU time 7.22 seconds
Started Mar 07 01:49:15 PM PST 24
Finished Mar 07 01:49:22 PM PST 24
Peak memory 202452 kb
Host smart-59cdc345-5062-41cf-81d0-0b3b7a43b0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27137
3089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.271373089
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1261283939
Short name T293
Test name
Test status
Simulation time 8451982317 ps
CPU time 8.36 seconds
Started Mar 07 01:49:11 PM PST 24
Finished Mar 07 01:49:20 PM PST 24
Peak memory 202452 kb
Host smart-35ab51f6-cb2d-40fa-b85d-c4b70c8e13c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12612
83939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1261283939
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2257458422
Short name T62
Test name
Test status
Simulation time 8367482156 ps
CPU time 7.56 seconds
Started Mar 07 01:49:12 PM PST 24
Finished Mar 07 01:49:20 PM PST 24
Peak memory 202544 kb
Host smart-3d88817e-565a-4a17-8954-7dbf7d10ab17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22574
58422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2257458422
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3045754659
Short name T316
Test name
Test status
Simulation time 8360094439 ps
CPU time 7.79 seconds
Started Mar 07 01:49:11 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 202508 kb
Host smart-98cc6461-f8fe-492a-a9e3-ce2c9ad4de92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30457
54659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3045754659
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1801194176
Short name T432
Test name
Test status
Simulation time 8372322638 ps
CPU time 7.57 seconds
Started Mar 07 01:49:11 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 202472 kb
Host smart-2f86975a-404b-478d-bbe2-677ee149da98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18011
94176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1801194176
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1005236508
Short name T296
Test name
Test status
Simulation time 40880371 ps
CPU time 1.19 seconds
Started Mar 07 01:49:08 PM PST 24
Finished Mar 07 01:49:09 PM PST 24
Peak memory 202464 kb
Host smart-b7e3d17a-af83-4d5e-978f-eb9acc20a8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10052
36508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1005236508
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.988892568
Short name T579
Test name
Test status
Simulation time 8408819609 ps
CPU time 10.06 seconds
Started Mar 07 01:49:13 PM PST 24
Finished Mar 07 01:49:23 PM PST 24
Peak memory 202496 kb
Host smart-de1ef8ee-13df-4710-aef1-de5cd51dd1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98889
2568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.988892568
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2438025187
Short name T5
Test name
Test status
Simulation time 8365734214 ps
CPU time 8.19 seconds
Started Mar 07 01:49:07 PM PST 24
Finished Mar 07 01:49:15 PM PST 24
Peak memory 202512 kb
Host smart-a399913d-8bfd-41cd-980c-626ae8d3339e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24380
25187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2438025187
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1568838401
Short name T23
Test name
Test status
Simulation time 8389693564 ps
CPU time 7.16 seconds
Started Mar 07 01:49:11 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 202472 kb
Host smart-378b2b44-da8f-46d5-9022-b563213b987b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
38401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1568838401
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2520111553
Short name T303
Test name
Test status
Simulation time 8453188943 ps
CPU time 7.71 seconds
Started Mar 07 01:49:13 PM PST 24
Finished Mar 07 01:49:21 PM PST 24
Peak memory 202508 kb
Host smart-7a9b0dbf-4b25-4c25-84c3-29a4cf47d891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
11553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2520111553
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1128822231
Short name T420
Test name
Test status
Simulation time 8422781296 ps
CPU time 8.28 seconds
Started Mar 07 01:49:08 PM PST 24
Finished Mar 07 01:49:16 PM PST 24
Peak memory 202444 kb
Host smart-51cc6c26-d9a9-4f32-a912-f2881f8b936c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11288
22231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1128822231
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2518305665
Short name T357
Test name
Test status
Simulation time 8355344514 ps
CPU time 7.4 seconds
Started Mar 07 01:49:16 PM PST 24
Finished Mar 07 01:49:24 PM PST 24
Peak memory 202448 kb
Host smart-a83db8ca-56fd-4a7e-a61a-d50fc63fbc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25183
05665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2518305665
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1820835701
Short name T460
Test name
Test status
Simulation time 8365814613 ps
CPU time 7.11 seconds
Started Mar 07 01:49:08 PM PST 24
Finished Mar 07 01:49:15 PM PST 24
Peak memory 202388 kb
Host smart-3554683c-e0fd-4b33-90ea-ccc2b451706c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
35701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1820835701
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.859642147
Short name T278
Test name
Test status
Simulation time 8409804111 ps
CPU time 9.64 seconds
Started Mar 07 01:49:21 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202488 kb
Host smart-3e11a123-09dd-4f9f-b882-0083ae2db3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85964
2147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.859642147
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.921369939
Short name T306
Test name
Test status
Simulation time 8364463875 ps
CPU time 7.32 seconds
Started Mar 07 01:49:19 PM PST 24
Finished Mar 07 01:49:26 PM PST 24
Peak memory 202428 kb
Host smart-c56f3de3-eb92-4255-bbb0-20b2d6fd19bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92136
9939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.921369939
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2345644218
Short name T242
Test name
Test status
Simulation time 8376865277 ps
CPU time 7.67 seconds
Started Mar 07 01:49:20 PM PST 24
Finished Mar 07 01:49:28 PM PST 24
Peak memory 202484 kb
Host smart-ad335239-62ed-4a7e-87f3-74dd31487876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23456
44218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2345644218
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1730421588
Short name T510
Test name
Test status
Simulation time 8394853878 ps
CPU time 8.13 seconds
Started Mar 07 01:49:23 PM PST 24
Finished Mar 07 01:49:32 PM PST 24
Peak memory 202412 kb
Host smart-0d8412cd-8b09-4c2b-a8d2-24316f5b3f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17304
21588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1730421588
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2498041698
Short name T63
Test name
Test status
Simulation time 8448799947 ps
CPU time 7.85 seconds
Started Mar 07 01:49:11 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 202508 kb
Host smart-b0d9009d-03dc-4161-9679-6b3b8bbabd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980
41698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2498041698
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.762231641
Short name T437
Test name
Test status
Simulation time 8409813016 ps
CPU time 8.3 seconds
Started Mar 07 01:49:10 PM PST 24
Finished Mar 07 01:49:19 PM PST 24
Peak memory 202544 kb
Host smart-b988aad3-085c-45a0-b08f-7b6c22672d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76223
1641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.762231641
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4108189718
Short name T416
Test name
Test status
Simulation time 8355030358 ps
CPU time 7.15 seconds
Started Mar 07 01:49:10 PM PST 24
Finished Mar 07 01:49:18 PM PST 24
Peak memory 202576 kb
Host smart-85a74a67-0c37-492d-9b9a-0e4a6e4359da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41081
89718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4108189718
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.4079259284
Short name T585
Test name
Test status
Simulation time 8368257084 ps
CPU time 7.91 seconds
Started Mar 07 01:49:20 PM PST 24
Finished Mar 07 01:49:28 PM PST 24
Peak memory 202496 kb
Host smart-5164563b-b10e-4fb7-835b-ffa00faf9574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40792
59284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.4079259284
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.627296356
Short name T127
Test name
Test status
Simulation time 8427373707 ps
CPU time 8.58 seconds
Started Mar 07 01:49:22 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202460 kb
Host smart-f47f7d7d-3df0-4a13-9041-993cb2bcacff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62729
6356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.627296356
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1220876691
Short name T351
Test name
Test status
Simulation time 8405321043 ps
CPU time 7.39 seconds
Started Mar 07 01:49:23 PM PST 24
Finished Mar 07 01:49:30 PM PST 24
Peak memory 202376 kb
Host smart-47d923c4-e29c-4925-b7a1-6de15b1a488a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12208
76691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1220876691
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2765872069
Short name T473
Test name
Test status
Simulation time 8368434657 ps
CPU time 7.17 seconds
Started Mar 07 01:49:14 PM PST 24
Finished Mar 07 01:49:22 PM PST 24
Peak memory 202540 kb
Host smart-98c0c337-91c9-4fb3-9869-2d2f21b93242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
72069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2765872069
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3023204973
Short name T285
Test name
Test status
Simulation time 8423133504 ps
CPU time 7.42 seconds
Started Mar 07 01:49:24 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202404 kb
Host smart-bb56681d-4ac1-4cc2-9a05-20145cf448f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30232
04973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3023204973
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2257546846
Short name T271
Test name
Test status
Simulation time 8385715071 ps
CPU time 7.38 seconds
Started Mar 07 01:49:23 PM PST 24
Finished Mar 07 01:49:30 PM PST 24
Peak memory 202480 kb
Host smart-cd091055-c89c-4603-82ea-f78db77db6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22575
46846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2257546846
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1872295979
Short name T502
Test name
Test status
Simulation time 8394454453 ps
CPU time 7.54 seconds
Started Mar 07 01:49:20 PM PST 24
Finished Mar 07 01:49:29 PM PST 24
Peak memory 202504 kb
Host smart-eac71ba4-4309-497d-91ab-a457a4560503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18722
95979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1872295979
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1819945159
Short name T562
Test name
Test status
Simulation time 8406732160 ps
CPU time 7.38 seconds
Started Mar 07 01:49:23 PM PST 24
Finished Mar 07 01:49:30 PM PST 24
Peak memory 202384 kb
Host smart-1de7b5ee-915b-49a2-a724-e931614b8346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18199
45159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1819945159
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1440132863
Short name T261
Test name
Test status
Simulation time 8357198878 ps
CPU time 8.34 seconds
Started Mar 07 01:49:21 PM PST 24
Finished Mar 07 01:49:30 PM PST 24
Peak memory 202516 kb
Host smart-2a1c0e9a-4057-4be3-b73f-c2fb0dd689aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14401
32863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1440132863
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3560702383
Short name T186
Test name
Test status
Simulation time 8479819802 ps
CPU time 7.87 seconds
Started Mar 07 01:49:23 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202476 kb
Host smart-aab0a985-e181-41b7-97e9-532323692f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35607
02383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3560702383
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.201243862
Short name T565
Test name
Test status
Simulation time 8379481031 ps
CPU time 7.73 seconds
Started Mar 07 01:49:23 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202520 kb
Host smart-b294e9b1-068d-4b97-b5e8-9164ddaea7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20124
3862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.201243862
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.191275230
Short name T382
Test name
Test status
Simulation time 140904898 ps
CPU time 1.58 seconds
Started Mar 07 01:49:28 PM PST 24
Finished Mar 07 01:49:30 PM PST 24
Peak memory 202492 kb
Host smart-d7d98dbc-1642-4cd5-973d-c95edce45be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19127
5230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.191275230
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3457434049
Short name T118
Test name
Test status
Simulation time 8418204325 ps
CPU time 7.01 seconds
Started Mar 07 01:49:28 PM PST 24
Finished Mar 07 01:49:36 PM PST 24
Peak memory 202452 kb
Host smart-452dad91-5aca-4f1b-b986-7fff84799f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34574
34049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3457434049
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2860878462
Short name T493
Test name
Test status
Simulation time 8411514997 ps
CPU time 9.51 seconds
Started Mar 07 01:49:24 PM PST 24
Finished Mar 07 01:49:34 PM PST 24
Peak memory 202488 kb
Host smart-5c0c12ed-10c1-4064-9186-8e746e1c5437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28608
78462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2860878462
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.562624051
Short name T594
Test name
Test status
Simulation time 8367247976 ps
CPU time 8.87 seconds
Started Mar 07 01:49:25 PM PST 24
Finished Mar 07 01:49:34 PM PST 24
Peak memory 202516 kb
Host smart-7df92b03-b465-4787-8ffc-7263d30e1455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56262
4051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.562624051
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.869375791
Short name T627
Test name
Test status
Simulation time 8368071375 ps
CPU time 8.29 seconds
Started Mar 07 01:49:26 PM PST 24
Finished Mar 07 01:49:34 PM PST 24
Peak memory 202404 kb
Host smart-83a11901-4259-41df-89be-68cc3675bb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86937
5791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.869375791
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3150911427
Short name T543
Test name
Test status
Simulation time 8388169516 ps
CPU time 7.56 seconds
Started Mar 07 01:49:25 PM PST 24
Finished Mar 07 01:49:32 PM PST 24
Peak memory 202512 kb
Host smart-e3162b21-ffef-456c-8f98-d62a160112a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509
11427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3150911427
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3938476921
Short name T616
Test name
Test status
Simulation time 8418158848 ps
CPU time 7.62 seconds
Started Mar 07 01:49:23 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202404 kb
Host smart-bdc805bf-f407-42ce-9ecd-2560cbdaa825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39384
76921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3938476921
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.1147736083
Short name T279
Test name
Test status
Simulation time 8383458221 ps
CPU time 7.16 seconds
Started Mar 07 01:49:25 PM PST 24
Finished Mar 07 01:49:33 PM PST 24
Peak memory 202556 kb
Host smart-f7125632-eca8-44f6-b85f-249711ed3ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11477
36083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.1147736083
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3741996037
Short name T525
Test name
Test status
Simulation time 8357778152 ps
CPU time 7.55 seconds
Started Mar 07 01:49:21 PM PST 24
Finished Mar 07 01:49:29 PM PST 24
Peak memory 202500 kb
Host smart-88b7cb41-d87e-464c-a741-18be267d44be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37419
96037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3741996037
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.136647693
Short name T251
Test name
Test status
Simulation time 8373724015 ps
CPU time 7.98 seconds
Started Mar 07 01:49:25 PM PST 24
Finished Mar 07 01:49:34 PM PST 24
Peak memory 202448 kb
Host smart-3188234c-b563-4f90-b8dc-2e964ff78e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13664
7693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.136647693
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1273225524
Short name T531
Test name
Test status
Simulation time 147105152 ps
CPU time 1.2 seconds
Started Mar 07 01:49:27 PM PST 24
Finished Mar 07 01:49:28 PM PST 24
Peak memory 202492 kb
Host smart-bd74ab6c-db6f-4218-9273-f0bce194a286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
25524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1273225524
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.590443895
Short name T355
Test name
Test status
Simulation time 8403310521 ps
CPU time 7.63 seconds
Started Mar 07 01:49:29 PM PST 24
Finished Mar 07 01:49:38 PM PST 24
Peak memory 202568 kb
Host smart-38a26afb-d8b9-46ec-b0ec-9802c7b72d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59044
3895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.590443895
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2296520021
Short name T465
Test name
Test status
Simulation time 8415410599 ps
CPU time 7.44 seconds
Started Mar 07 01:49:29 PM PST 24
Finished Mar 07 01:49:37 PM PST 24
Peak memory 202568 kb
Host smart-1840aae8-a598-4f46-99c4-14a33bf7435e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22965
20021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2296520021
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3389284131
Short name T529
Test name
Test status
Simulation time 8366109117 ps
CPU time 8.1 seconds
Started Mar 07 01:49:29 PM PST 24
Finished Mar 07 01:49:37 PM PST 24
Peak memory 202568 kb
Host smart-b3db9562-a288-467c-a707-0394281b0bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33892
84131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3389284131
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2280215274
Short name T65
Test name
Test status
Simulation time 8447442776 ps
CPU time 7.49 seconds
Started Mar 07 01:49:26 PM PST 24
Finished Mar 07 01:49:34 PM PST 24
Peak memory 202508 kb
Host smart-02cdcc70-6cca-494e-b169-bc24c67ca84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22802
15274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2280215274
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2017687130
Short name T405
Test name
Test status
Simulation time 8361377271 ps
CPU time 7.55 seconds
Started Mar 07 01:49:26 PM PST 24
Finished Mar 07 01:49:34 PM PST 24
Peak memory 202532 kb
Host smart-51f10b4b-3b31-4ca5-8eb0-4c52d5e388c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20176
87130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2017687130
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3181121518
Short name T125
Test name
Test status
Simulation time 8393107798 ps
CPU time 7.79 seconds
Started Mar 07 01:49:28 PM PST 24
Finished Mar 07 01:49:36 PM PST 24
Peak memory 202452 kb
Host smart-6f4f832e-290d-4eb7-9b8a-3665c2b90f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31811
21518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3181121518
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.1394784478
Short name T622
Test name
Test status
Simulation time 8415118769 ps
CPU time 7.4 seconds
Started Mar 07 01:49:23 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202492 kb
Host smart-57b4bdff-c8a4-416d-acc9-3175f70dc504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13947
84478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.1394784478
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1705860401
Short name T410
Test name
Test status
Simulation time 8359113888 ps
CPU time 8.91 seconds
Started Mar 07 01:49:28 PM PST 24
Finished Mar 07 01:49:38 PM PST 24
Peak memory 202572 kb
Host smart-9551633b-2440-4db0-84e9-706ca3923a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17058
60401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1705860401
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2579524076
Short name T356
Test name
Test status
Simulation time 8367249827 ps
CPU time 8.67 seconds
Started Mar 07 01:49:20 PM PST 24
Finished Mar 07 01:49:29 PM PST 24
Peak memory 202512 kb
Host smart-fddb378e-4a1b-4ed1-b026-03e4b5525a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25795
24076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2579524076
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.4100264465
Short name T485
Test name
Test status
Simulation time 98850421 ps
CPU time 1.23 seconds
Started Mar 07 01:49:31 PM PST 24
Finished Mar 07 01:49:33 PM PST 24
Peak memory 202460 kb
Host smart-02713645-c503-4481-81ba-3ffd907fce11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41002
64465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.4100264465
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.281420046
Short name T417
Test name
Test status
Simulation time 8415628866 ps
CPU time 8.47 seconds
Started Mar 07 01:49:24 PM PST 24
Finished Mar 07 01:49:33 PM PST 24
Peak memory 202508 kb
Host smart-fb28c88a-6c22-4e61-96c5-04747aec8862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28142
0046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.281420046
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3483722993
Short name T274
Test name
Test status
Simulation time 8407646485 ps
CPU time 7.44 seconds
Started Mar 07 01:49:34 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202500 kb
Host smart-919b632b-5822-4c05-bfd9-d6637dd87de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34837
22993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3483722993
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2283997718
Short name T7
Test name
Test status
Simulation time 8367384805 ps
CPU time 7.44 seconds
Started Mar 07 01:49:33 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202536 kb
Host smart-7a1f0228-a8bb-49d0-acab-90556e512f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22839
97718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2283997718
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.965446229
Short name T325
Test name
Test status
Simulation time 8375421599 ps
CPU time 7.28 seconds
Started Mar 07 01:49:31 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 202444 kb
Host smart-2d461ca3-1c44-4d04-be48-34df06e92a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96544
6229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.965446229
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2474943026
Short name T393
Test name
Test status
Simulation time 8383201106 ps
CPU time 9.22 seconds
Started Mar 07 01:49:31 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202516 kb
Host smart-8970139a-3c41-40bb-8210-271cc315fb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24749
43026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2474943026
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1116836398
Short name T593
Test name
Test status
Simulation time 8449718748 ps
CPU time 7.45 seconds
Started Mar 07 01:49:24 PM PST 24
Finished Mar 07 01:49:31 PM PST 24
Peak memory 202508 kb
Host smart-5420c0fd-3015-4d4b-9b72-55fefc8b3b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11168
36398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1116836398
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.2872886098
Short name T34
Test name
Test status
Simulation time 8415017153 ps
CPU time 7.25 seconds
Started Mar 07 01:49:31 PM PST 24
Finished Mar 07 01:49:39 PM PST 24
Peak memory 202448 kb
Host smart-3088de9d-bf25-435f-8e37-dc7c6e678f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28728
86098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.2872886098
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3053244639
Short name T639
Test name
Test status
Simulation time 8368301724 ps
CPU time 7.75 seconds
Started Mar 07 01:49:22 PM PST 24
Finished Mar 07 01:49:30 PM PST 24
Peak memory 202508 kb
Host smart-b7c87cd2-c389-45a3-939c-d0b59c6e4af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
44639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3053244639
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3169993978
Short name T583
Test name
Test status
Simulation time 8485160200 ps
CPU time 7.56 seconds
Started Mar 07 01:49:19 PM PST 24
Finished Mar 07 01:49:27 PM PST 24
Peak memory 202460 kb
Host smart-eba02fcf-3979-48d7-b155-fe4029e3e2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31699
93978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3169993978
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2001219079
Short name T604
Test name
Test status
Simulation time 8373595936 ps
CPU time 7.13 seconds
Started Mar 07 01:49:32 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 202536 kb
Host smart-ee501534-f9b3-495a-b528-806685e16687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20012
19079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2001219079
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.512643039
Short name T626
Test name
Test status
Simulation time 259428637 ps
CPU time 2.01 seconds
Started Mar 07 01:49:34 PM PST 24
Finished Mar 07 01:49:36 PM PST 24
Peak memory 202444 kb
Host smart-4a516399-d901-4b91-a247-1ec703ff474d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51264
3039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.512643039
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2533500333
Short name T394
Test name
Test status
Simulation time 8428513260 ps
CPU time 7.78 seconds
Started Mar 07 01:49:32 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 202508 kb
Host smart-5c673dba-5a04-46d9-a739-d16b6479df69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25335
00333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2533500333
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.906181322
Short name T283
Test name
Test status
Simulation time 8415059627 ps
CPU time 7.94 seconds
Started Mar 07 01:49:31 PM PST 24
Finished Mar 07 01:49:40 PM PST 24
Peak memory 202556 kb
Host smart-065f25c0-2c5d-4549-b23f-83c901333c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90618
1322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.906181322
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1362061288
Short name T339
Test name
Test status
Simulation time 8369686888 ps
CPU time 7.25 seconds
Started Mar 07 01:49:36 PM PST 24
Finished Mar 07 01:49:44 PM PST 24
Peak memory 202448 kb
Host smart-0aba5c93-9383-4fa1-9eb9-176fd0249b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13620
61288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1362061288
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3524174486
Short name T524
Test name
Test status
Simulation time 8390046943 ps
CPU time 8.96 seconds
Started Mar 07 01:49:36 PM PST 24
Finished Mar 07 01:49:45 PM PST 24
Peak memory 202512 kb
Host smart-d38180b9-9a32-48f7-a717-f21fa73b3cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35241
74486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3524174486
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2229878174
Short name T476
Test name
Test status
Simulation time 8457404924 ps
CPU time 7.63 seconds
Started Mar 07 01:49:32 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 202528 kb
Host smart-5dc942df-91a6-420c-886a-1ef0b9c15b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22298
78174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2229878174
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.157269706
Short name T71
Test name
Test status
Simulation time 8401574836 ps
CPU time 8.51 seconds
Started Mar 07 01:49:31 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202580 kb
Host smart-c4117030-ffaa-47e4-927b-05106cffe339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15726
9706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.157269706
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3159495200
Short name T586
Test name
Test status
Simulation time 8358627203 ps
CPU time 7.63 seconds
Started Mar 07 01:49:30 PM PST 24
Finished Mar 07 01:49:37 PM PST 24
Peak memory 202488 kb
Host smart-9a7bd25b-dec6-4e50-80a1-aaf2821d74e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31594
95200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3159495200
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2463311963
Short name T68
Test name
Test status
Simulation time 8486325111 ps
CPU time 7.92 seconds
Started Mar 07 01:49:33 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202532 kb
Host smart-1ac6bdd6-188d-44db-bcdc-b1d82e0bc0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24633
11963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2463311963
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3373865739
Short name T435
Test name
Test status
Simulation time 8365966522 ps
CPU time 7.88 seconds
Started Mar 07 01:49:36 PM PST 24
Finished Mar 07 01:49:44 PM PST 24
Peak memory 202512 kb
Host smart-efa80327-bce7-4d44-998f-8cecf62da689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33738
65739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3373865739
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2541624930
Short name T556
Test name
Test status
Simulation time 146189695 ps
CPU time 1.43 seconds
Started Mar 07 01:49:32 PM PST 24
Finished Mar 07 01:49:35 PM PST 24
Peak memory 202428 kb
Host smart-c993ec43-bc9a-4cab-93b0-94000cadf396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25416
24930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2541624930
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.492826909
Short name T597
Test name
Test status
Simulation time 8380704817 ps
CPU time 7.98 seconds
Started Mar 07 01:49:33 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202524 kb
Host smart-4f2723b8-ea34-4836-8ac8-02d017afcf38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49282
6909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.492826909
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1542136808
Short name T6
Test name
Test status
Simulation time 8419658034 ps
CPU time 7.3 seconds
Started Mar 07 01:49:37 PM PST 24
Finished Mar 07 01:49:45 PM PST 24
Peak memory 202328 kb
Host smart-deff7a7d-b515-4b34-a652-29f1cc593047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15421
36808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1542136808
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1845900788
Short name T353
Test name
Test status
Simulation time 8388274129 ps
CPU time 9.55 seconds
Started Mar 07 01:49:43 PM PST 24
Finished Mar 07 01:49:52 PM PST 24
Peak memory 202508 kb
Host smart-0aa203a9-7425-4ee6-9b72-36f2f5ae5031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18459
00788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1845900788
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1924085710
Short name T245
Test name
Test status
Simulation time 8372118843 ps
CPU time 7.52 seconds
Started Mar 07 01:49:37 PM PST 24
Finished Mar 07 01:49:45 PM PST 24
Peak memory 202484 kb
Host smart-ca929d66-a276-46df-9e65-810160f2ea64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19240
85710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1924085710
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2833206726
Short name T521
Test name
Test status
Simulation time 8400234222 ps
CPU time 7.37 seconds
Started Mar 07 01:49:34 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202448 kb
Host smart-e2a35018-4f0b-4f4e-b6a9-ddf71a24a790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28332
06726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2833206726
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.4224380168
Short name T4
Test name
Test status
Simulation time 8379669772 ps
CPU time 7.43 seconds
Started Mar 07 01:49:34 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202452 kb
Host smart-6e91d74b-b904-4ea1-8291-356c1f694294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42243
80168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.4224380168
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1725528318
Short name T349
Test name
Test status
Simulation time 8356093385 ps
CPU time 7.83 seconds
Started Mar 07 01:49:33 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202436 kb
Host smart-627c1a11-7260-4a94-85f0-e26275907109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17255
28318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1725528318
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1964756278
Short name T345
Test name
Test status
Simulation time 8373500975 ps
CPU time 7.27 seconds
Started Mar 07 01:48:27 PM PST 24
Finished Mar 07 01:48:35 PM PST 24
Peak memory 202384 kb
Host smart-7e29850e-5c76-4c82-a137-629088e95ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19647
56278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1964756278
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.106528180
Short name T194
Test name
Test status
Simulation time 243209115 ps
CPU time 2.09 seconds
Started Mar 07 01:48:28 PM PST 24
Finished Mar 07 01:48:30 PM PST 24
Peak memory 202484 kb
Host smart-4bbf6b6e-70c8-4fb0-afe8-1d1b65333ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10652
8180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.106528180
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3569406109
Short name T128
Test name
Test status
Simulation time 8413131223 ps
CPU time 9.6 seconds
Started Mar 07 01:48:30 PM PST 24
Finished Mar 07 01:48:40 PM PST 24
Peak memory 202448 kb
Host smart-1c63afb2-0828-456f-8343-1cc667c385e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35694
06109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3569406109
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.4088843457
Short name T642
Test name
Test status
Simulation time 8408556251 ps
CPU time 8.62 seconds
Started Mar 07 01:48:27 PM PST 24
Finished Mar 07 01:48:36 PM PST 24
Peak memory 202440 kb
Host smart-ec5feed5-4ecb-4972-9676-803d17c6c540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40888
43457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.4088843457
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3218983463
Short name T257
Test name
Test status
Simulation time 8363948706 ps
CPU time 7.57 seconds
Started Mar 07 01:48:26 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 202484 kb
Host smart-5236e389-ac84-4503-93b1-9f3db8d0fd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32189
83463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3218983463
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.712181859
Short name T96
Test name
Test status
Simulation time 8378409154 ps
CPU time 7.59 seconds
Started Mar 07 01:48:26 PM PST 24
Finished Mar 07 01:48:33 PM PST 24
Peak memory 202428 kb
Host smart-e6872ee1-b084-4f55-b2d3-d7b0c350764c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71218
1859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.712181859
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2414831546
Short name T461
Test name
Test status
Simulation time 8494388002 ps
CPU time 7.82 seconds
Started Mar 07 01:48:28 PM PST 24
Finished Mar 07 01:48:36 PM PST 24
Peak memory 202524 kb
Host smart-7cd68a09-3a14-418e-8d76-9de889308b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24148
31546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2414831546
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.4178650125
Short name T552
Test name
Test status
Simulation time 8437898057 ps
CPU time 7.18 seconds
Started Mar 07 01:48:26 PM PST 24
Finished Mar 07 01:48:33 PM PST 24
Peak memory 202452 kb
Host smart-7e6a444e-43b3-4ab1-9098-2516b1e118b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41786
50125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.4178650125
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3536703535
Short name T250
Test name
Test status
Simulation time 8377135176 ps
CPU time 7.95 seconds
Started Mar 07 01:48:28 PM PST 24
Finished Mar 07 01:48:36 PM PST 24
Peak memory 202540 kb
Host smart-5b68bb27-7fba-453a-b870-d7d420196e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35367
03535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3536703535
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3370024725
Short name T487
Test name
Test status
Simulation time 8355714024 ps
CPU time 9.07 seconds
Started Mar 07 01:48:25 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 202492 kb
Host smart-49132ff7-0f8b-4d03-895e-565c6330b6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33700
24725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3370024725
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.514412453
Short name T15
Test name
Test status
Simulation time 8468931009 ps
CPU time 7.91 seconds
Started Mar 07 01:48:26 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 202580 kb
Host smart-ebdaa655-9120-4299-b2f7-98f0ab1a82e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51441
2453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.514412453
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2539123043
Short name T370
Test name
Test status
Simulation time 8382471638 ps
CPU time 7.22 seconds
Started Mar 07 01:49:36 PM PST 24
Finished Mar 07 01:49:44 PM PST 24
Peak memory 202444 kb
Host smart-cfa3df28-c2f2-473b-b128-31f789c80d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391
23043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2539123043
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.708772600
Short name T523
Test name
Test status
Simulation time 63432397 ps
CPU time 1.59 seconds
Started Mar 07 01:49:39 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 202400 kb
Host smart-a3db0ef4-efbe-4acd-9b92-35055133232d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70877
2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.708772600
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.699295501
Short name T111
Test name
Test status
Simulation time 8432563315 ps
CPU time 9.33 seconds
Started Mar 07 01:49:38 PM PST 24
Finished Mar 07 01:49:47 PM PST 24
Peak memory 202504 kb
Host smart-f223d160-2f8a-48de-b4e9-046efa3e37df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69929
5501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.699295501
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.382809209
Short name T544
Test name
Test status
Simulation time 8490514885 ps
CPU time 7.83 seconds
Started Mar 07 01:49:37 PM PST 24
Finished Mar 07 01:49:45 PM PST 24
Peak memory 202492 kb
Host smart-3fbefaae-63eb-451b-a266-00673337e457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38280
9209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.382809209
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.404224626
Short name T282
Test name
Test status
Simulation time 8366416683 ps
CPU time 7.23 seconds
Started Mar 07 01:49:33 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 202492 kb
Host smart-80d04e34-d19a-4779-a2fb-dbf38ea96cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40422
4626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.404224626
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.590522561
Short name T105
Test name
Test status
Simulation time 8406571240 ps
CPU time 7.37 seconds
Started Mar 07 01:49:38 PM PST 24
Finished Mar 07 01:49:45 PM PST 24
Peak memory 202392 kb
Host smart-dfbe2b61-3a8d-41c9-a220-1fce08a17fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59052
2561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.590522561
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2038763416
Short name T185
Test name
Test status
Simulation time 8397870018 ps
CPU time 8.08 seconds
Started Mar 07 01:49:33 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202484 kb
Host smart-22c1b9b1-ba6e-4d08-bfdc-6f3b350daa18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20387
63416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2038763416
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.739942468
Short name T481
Test name
Test status
Simulation time 8399364415 ps
CPU time 7.94 seconds
Started Mar 07 01:49:41 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202512 kb
Host smart-dede8983-3266-4a3d-aacf-5e9ba5faa49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73994
2468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.739942468
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2446586245
Short name T438
Test name
Test status
Simulation time 8406485975 ps
CPU time 8.78 seconds
Started Mar 07 01:49:37 PM PST 24
Finished Mar 07 01:49:46 PM PST 24
Peak memory 202488 kb
Host smart-fc54adf3-62d5-43b3-9b97-9aa056433abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24465
86245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2446586245
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.829199606
Short name T634
Test name
Test status
Simulation time 8368015615 ps
CPU time 7.83 seconds
Started Mar 07 01:49:38 PM PST 24
Finished Mar 07 01:49:46 PM PST 24
Peak memory 202392 kb
Host smart-35c765ad-5437-4e8b-ac89-9f14d3c23446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82919
9606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.829199606
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.731578437
Short name T277
Test name
Test status
Simulation time 8362479941 ps
CPU time 7.49 seconds
Started Mar 07 01:49:38 PM PST 24
Finished Mar 07 01:49:46 PM PST 24
Peak memory 202196 kb
Host smart-b7b4f3e3-80d7-4ee5-88ce-e5cf0a8ac247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73157
8437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.731578437
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1814694703
Short name T136
Test name
Test status
Simulation time 8483673084 ps
CPU time 8.28 seconds
Started Mar 07 01:49:33 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202464 kb
Host smart-e6ead6f7-9757-4f5d-8c78-39e3ef4278ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18146
94703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1814694703
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3059765150
Short name T344
Test name
Test status
Simulation time 8374781499 ps
CPU time 8.43 seconds
Started Mar 07 01:49:33 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202460 kb
Host smart-1903f759-bb50-40af-8b45-dcd2b0c6149f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30597
65150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3059765150
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.185585380
Short name T458
Test name
Test status
Simulation time 258255607 ps
CPU time 1.99 seconds
Started Mar 07 01:49:40 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202364 kb
Host smart-b5c19266-f80d-4753-90f4-6722554bc733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18558
5380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.185585380
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.308665624
Short name T175
Test name
Test status
Simulation time 8467238161 ps
CPU time 8.97 seconds
Started Mar 07 01:49:34 PM PST 24
Finished Mar 07 01:49:44 PM PST 24
Peak memory 202528 kb
Host smart-0e7ec864-92ed-4f45-b340-1a388163ac93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30866
5624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.308665624
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.343008534
Short name T300
Test name
Test status
Simulation time 8403233995 ps
CPU time 7.44 seconds
Started Mar 07 01:49:39 PM PST 24
Finished Mar 07 01:49:47 PM PST 24
Peak memory 202440 kb
Host smart-e229b83e-0098-4be5-9c55-88c7519d58d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34300
8534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.343008534
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.397757882
Short name T591
Test name
Test status
Simulation time 8364543239 ps
CPU time 7.95 seconds
Started Mar 07 01:49:32 PM PST 24
Finished Mar 07 01:49:41 PM PST 24
Peak memory 202508 kb
Host smart-28af9bf7-862f-45ca-93fc-d58e932b01df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39775
7882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.397757882
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.426213538
Short name T97
Test name
Test status
Simulation time 8422190711 ps
CPU time 7.28 seconds
Started Mar 07 01:49:36 PM PST 24
Finished Mar 07 01:49:44 PM PST 24
Peak memory 202464 kb
Host smart-781d0895-d7af-449e-b2a8-61f841db76c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42621
3538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.426213538
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1711298263
Short name T470
Test name
Test status
Simulation time 8407549612 ps
CPU time 7.75 seconds
Started Mar 07 01:49:39 PM PST 24
Finished Mar 07 01:49:48 PM PST 24
Peak memory 202432 kb
Host smart-7d5321c9-3a0d-434c-8d68-486b415b4d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17112
98263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1711298263
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1391958136
Short name T451
Test name
Test status
Simulation time 8456610255 ps
CPU time 7.84 seconds
Started Mar 07 01:49:41 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202508 kb
Host smart-d6a94060-e556-4f08-b2a4-778f2a411a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
58136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1391958136
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.3016241103
Short name T397
Test name
Test status
Simulation time 8403684259 ps
CPU time 7.12 seconds
Started Mar 07 01:49:43 PM PST 24
Finished Mar 07 01:49:50 PM PST 24
Peak memory 202492 kb
Host smart-3bfde4d4-7c97-44bf-8b27-91f31eb01913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30162
41103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.3016241103
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1192620742
Short name T610
Test name
Test status
Simulation time 8447634253 ps
CPU time 7.67 seconds
Started Mar 07 01:49:36 PM PST 24
Finished Mar 07 01:49:44 PM PST 24
Peak memory 202460 kb
Host smart-09fd9f67-9c62-4447-b4f0-3ff9fe8919e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11926
20742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1192620742
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2690376837
Short name T29
Test name
Test status
Simulation time 8373517156 ps
CPU time 7.36 seconds
Started Mar 07 01:49:35 PM PST 24
Finished Mar 07 01:49:42 PM PST 24
Peak memory 202512 kb
Host smart-edf18f7a-91b3-4ab8-b2c5-562df2c02ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26903
76837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2690376837
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1290494541
Short name T630
Test name
Test status
Simulation time 8411543683 ps
CPU time 8 seconds
Started Mar 07 01:49:49 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 202472 kb
Host smart-ce04c337-516e-4052-b2bf-40db85d4f48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12904
94541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1290494541
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1902962391
Short name T256
Test name
Test status
Simulation time 8377423436 ps
CPU time 7.55 seconds
Started Mar 07 01:49:46 PM PST 24
Finished Mar 07 01:49:54 PM PST 24
Peak memory 202504 kb
Host smart-3d643536-ce58-4d60-9afe-48b5617c2065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19029
62391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1902962391
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3340998259
Short name T380
Test name
Test status
Simulation time 8379602019 ps
CPU time 7.42 seconds
Started Mar 07 01:49:42 PM PST 24
Finished Mar 07 01:49:50 PM PST 24
Peak memory 202460 kb
Host smart-0afce6ef-7711-44ee-a42d-ec936827b456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33409
98259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3340998259
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2021465575
Short name T446
Test name
Test status
Simulation time 8487876017 ps
CPU time 8.41 seconds
Started Mar 07 01:49:42 PM PST 24
Finished Mar 07 01:49:51 PM PST 24
Peak memory 202488 kb
Host smart-e0163cc0-0c4c-4082-a9fc-42636070d35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20214
65575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2021465575
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2693476318
Short name T384
Test name
Test status
Simulation time 8430484134 ps
CPU time 9.37 seconds
Started Mar 07 01:49:40 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202540 kb
Host smart-58cc40ee-d652-46f4-ada9-34e1016ea38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26934
76318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2693476318
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3529354092
Short name T530
Test name
Test status
Simulation time 8402620158 ps
CPU time 6.83 seconds
Started Mar 07 01:49:40 PM PST 24
Finished Mar 07 01:49:47 PM PST 24
Peak memory 202404 kb
Host smart-4b8a1e1c-75da-4363-940b-97688c47ea86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35293
54092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3529354092
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.402195380
Short name T383
Test name
Test status
Simulation time 8367304719 ps
CPU time 7.56 seconds
Started Mar 07 01:49:42 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202564 kb
Host smart-fafb646f-6460-4478-a919-93c90deebb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40219
5380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.402195380
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2464725495
Short name T135
Test name
Test status
Simulation time 8475598727 ps
CPU time 9.56 seconds
Started Mar 07 01:49:35 PM PST 24
Finished Mar 07 01:49:44 PM PST 24
Peak memory 202496 kb
Host smart-792b79c6-defa-4bb5-9db5-76c642be2571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24647
25495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2464725495
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.4012794403
Short name T498
Test name
Test status
Simulation time 8465834660 ps
CPU time 6.97 seconds
Started Mar 07 01:49:46 PM PST 24
Finished Mar 07 01:49:53 PM PST 24
Peak memory 202452 kb
Host smart-3a23d2a1-e6e1-47f6-922d-aab344b65f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40127
94403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.4012794403
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.661521059
Short name T546
Test name
Test status
Simulation time 85261825 ps
CPU time 1.19 seconds
Started Mar 07 01:49:38 PM PST 24
Finished Mar 07 01:49:40 PM PST 24
Peak memory 202444 kb
Host smart-6ad7aea9-6e1a-42f8-b337-809c11e51fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66152
1059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.661521059
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3075232679
Short name T240
Test name
Test status
Simulation time 8438905265 ps
CPU time 7.4 seconds
Started Mar 07 01:49:44 PM PST 24
Finished Mar 07 01:49:52 PM PST 24
Peak memory 202380 kb
Host smart-7f450f58-04a3-42c7-b18a-67fe70181993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30752
32679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3075232679
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3729167460
Short name T358
Test name
Test status
Simulation time 8405939430 ps
CPU time 7.46 seconds
Started Mar 07 01:49:42 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202512 kb
Host smart-dc442579-2c09-4d62-b6e4-875913d8a6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37291
67460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3729167460
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2564778716
Short name T519
Test name
Test status
Simulation time 8373376663 ps
CPU time 8.26 seconds
Started Mar 07 01:49:41 PM PST 24
Finished Mar 07 01:49:50 PM PST 24
Peak memory 202484 kb
Host smart-b2079826-8e68-4c04-9e1e-746dee03f360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25647
78716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2564778716
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1149187624
Short name T98
Test name
Test status
Simulation time 8457107147 ps
CPU time 7.74 seconds
Started Mar 07 01:49:39 PM PST 24
Finished Mar 07 01:49:48 PM PST 24
Peak memory 202508 kb
Host smart-1aa27801-e594-44bc-b837-90faa409661c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11491
87624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1149187624
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2896677986
Short name T492
Test name
Test status
Simulation time 8403475108 ps
CPU time 7.72 seconds
Started Mar 07 01:49:41 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202496 kb
Host smart-8e09e68d-8e0d-4efd-a846-a2db43a2e20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28966
77986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2896677986
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2597426347
Short name T504
Test name
Test status
Simulation time 8406153670 ps
CPU time 7.1 seconds
Started Mar 07 01:49:40 PM PST 24
Finished Mar 07 01:49:47 PM PST 24
Peak memory 202504 kb
Host smart-5c7c0b68-ac49-4a76-bff1-83851ea96a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25974
26347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2597426347
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1680178695
Short name T612
Test name
Test status
Simulation time 8432447547 ps
CPU time 7.32 seconds
Started Mar 07 01:49:46 PM PST 24
Finished Mar 07 01:49:53 PM PST 24
Peak memory 202508 kb
Host smart-c8e37697-90ea-4c87-9265-57bddcf96bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16801
78695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1680178695
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3000853257
Short name T8
Test name
Test status
Simulation time 8413596121 ps
CPU time 7.49 seconds
Started Mar 07 01:49:46 PM PST 24
Finished Mar 07 01:49:53 PM PST 24
Peak memory 202396 kb
Host smart-01205255-c71c-4fd8-87f8-f3cb1dc4acea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008
53257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3000853257
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1539569323
Short name T590
Test name
Test status
Simulation time 8363550964 ps
CPU time 7.86 seconds
Started Mar 07 01:49:43 PM PST 24
Finished Mar 07 01:49:51 PM PST 24
Peak memory 202508 kb
Host smart-db728248-b666-4532-b6ce-98d0854bb825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15395
69323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1539569323
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1652986249
Short name T30
Test name
Test status
Simulation time 8481983992 ps
CPU time 8.43 seconds
Started Mar 07 01:49:40 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202520 kb
Host smart-84e645fa-35db-4f26-8356-b7c5e3e9fe3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16529
86249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1652986249
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.4149552530
Short name T32
Test name
Test status
Simulation time 8373193296 ps
CPU time 7.49 seconds
Started Mar 07 01:49:41 PM PST 24
Finished Mar 07 01:49:48 PM PST 24
Peak memory 202444 kb
Host smart-df98990a-6e74-4f1a-8d77-ca2aae9d81d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41495
52530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.4149552530
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2937533437
Short name T569
Test name
Test status
Simulation time 85269135 ps
CPU time 1.72 seconds
Started Mar 07 01:49:41 PM PST 24
Finished Mar 07 01:49:43 PM PST 24
Peak memory 201392 kb
Host smart-b3c95d37-e8fd-4cad-a9c3-5d58100d7adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29375
33437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2937533437
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.360905048
Short name T364
Test name
Test status
Simulation time 8418131851 ps
CPU time 7.93 seconds
Started Mar 07 01:49:42 PM PST 24
Finished Mar 07 01:49:50 PM PST 24
Peak memory 202460 kb
Host smart-40151570-3b4b-404c-aae0-f73b9dc9d73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36090
5048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.360905048
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3020698569
Short name T631
Test name
Test status
Simulation time 8417761425 ps
CPU time 7.14 seconds
Started Mar 07 01:49:42 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202496 kb
Host smart-8922b6b8-72bf-48b5-a38e-b5fe73f5e7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30206
98569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3020698569
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3260423764
Short name T475
Test name
Test status
Simulation time 8369385422 ps
CPU time 8.51 seconds
Started Mar 07 01:49:48 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 202484 kb
Host smart-620e88b1-4eca-4dda-9157-ebf8a82409a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32604
23764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3260423764
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3822220238
Short name T386
Test name
Test status
Simulation time 8441912930 ps
CPU time 7.67 seconds
Started Mar 07 01:49:50 PM PST 24
Finished Mar 07 01:49:58 PM PST 24
Peak memory 202512 kb
Host smart-e2c8de1a-be07-4d51-bc63-c655c4fa1e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38222
20238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3822220238
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.4213389153
Short name T419
Test name
Test status
Simulation time 8404154369 ps
CPU time 7.68 seconds
Started Mar 07 01:49:49 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 202508 kb
Host smart-c42b8ca6-1430-4d7a-ac69-42e217813971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42133
89153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.4213389153
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.959228930
Short name T368
Test name
Test status
Simulation time 8494770645 ps
CPU time 7.7 seconds
Started Mar 07 01:49:41 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202460 kb
Host smart-56b9d352-da05-4ec9-8a62-2d38d91e982d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95922
8930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.959228930
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2588846641
Short name T241
Test name
Test status
Simulation time 8393979591 ps
CPU time 8.43 seconds
Started Mar 07 01:49:50 PM PST 24
Finished Mar 07 01:49:59 PM PST 24
Peak memory 202516 kb
Host smart-f39a73a5-3ad6-4abe-bf6d-e504327e0f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25888
46641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2588846641
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2865535776
Short name T391
Test name
Test status
Simulation time 8361213418 ps
CPU time 7.81 seconds
Started Mar 07 01:49:47 PM PST 24
Finished Mar 07 01:49:55 PM PST 24
Peak memory 202508 kb
Host smart-988e7334-ed01-4291-8486-3122fc3e2b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28655
35776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2865535776
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2420036565
Short name T545
Test name
Test status
Simulation time 8477033669 ps
CPU time 8.14 seconds
Started Mar 07 01:49:41 PM PST 24
Finished Mar 07 01:49:49 PM PST 24
Peak memory 202484 kb
Host smart-246a0cf6-1348-48b0-9511-8a44db006194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24200
36565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2420036565
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3416232087
Short name T444
Test name
Test status
Simulation time 8375908885 ps
CPU time 8.3 seconds
Started Mar 07 01:49:49 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 202480 kb
Host smart-e40afb24-b5b1-42cd-b679-922ce8de9aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34162
32087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3416232087
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3465687777
Short name T187
Test name
Test status
Simulation time 38617108 ps
CPU time 1.02 seconds
Started Mar 07 01:49:52 PM PST 24
Finished Mar 07 01:49:53 PM PST 24
Peak memory 202408 kb
Host smart-dce27da5-3b93-4b39-9610-4c45b0142962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34656
87777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3465687777
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2943724
Short name T237
Test name
Test status
Simulation time 8403879791 ps
CPU time 8.1 seconds
Started Mar 07 01:49:53 PM PST 24
Finished Mar 07 01:50:01 PM PST 24
Peak memory 201744 kb
Host smart-25a45f97-f09b-41aa-a9ec-d0a7f993caf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29437
24 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2943724
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1923574814
Short name T310
Test name
Test status
Simulation time 8451239757 ps
CPU time 7.03 seconds
Started Mar 07 01:49:51 PM PST 24
Finished Mar 07 01:49:58 PM PST 24
Peak memory 202456 kb
Host smart-74cf2ffd-196a-4b92-bd63-e64631548d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
74814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1923574814
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2799294216
Short name T573
Test name
Test status
Simulation time 8391862350 ps
CPU time 7.27 seconds
Started Mar 07 01:49:47 PM PST 24
Finished Mar 07 01:49:56 PM PST 24
Peak memory 202480 kb
Host smart-53f2be93-1bb0-4ebf-b027-5d53f65ee69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27992
94216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2799294216
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.215266540
Short name T273
Test name
Test status
Simulation time 8398985270 ps
CPU time 7.59 seconds
Started Mar 07 01:49:51 PM PST 24
Finished Mar 07 01:49:59 PM PST 24
Peak memory 202564 kb
Host smart-02166a8c-a3d5-45cd-a225-a8e69c48c88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21526
6540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.215266540
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3152534048
Short name T275
Test name
Test status
Simulation time 8368215525 ps
CPU time 8.59 seconds
Started Mar 07 01:49:53 PM PST 24
Finished Mar 07 01:50:01 PM PST 24
Peak memory 202444 kb
Host smart-bc10a8a1-690e-4e19-8178-1ba541ef1ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31525
34048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3152534048
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3154030837
Short name T343
Test name
Test status
Simulation time 8405884346 ps
CPU time 8.84 seconds
Started Mar 07 01:49:48 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 202480 kb
Host smart-eb2865b4-b077-414a-85c8-ce0ec53dfc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31540
30837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3154030837
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.3922688676
Short name T466
Test name
Test status
Simulation time 8382287526 ps
CPU time 7.48 seconds
Started Mar 07 01:49:40 PM PST 24
Finished Mar 07 01:49:48 PM PST 24
Peak memory 202556 kb
Host smart-8cad8d1d-81de-42e2-9be7-9300ab1edf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39226
88676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.3922688676
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3318469017
Short name T624
Test name
Test status
Simulation time 8366481129 ps
CPU time 7.28 seconds
Started Mar 07 01:49:48 PM PST 24
Finished Mar 07 01:49:56 PM PST 24
Peak memory 202428 kb
Host smart-9cc6bbd2-0464-4ca1-b903-5babf2b84cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33184
69017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3318469017
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2383638661
Short name T477
Test name
Test status
Simulation time 8373404817 ps
CPU time 7.19 seconds
Started Mar 07 01:49:46 PM PST 24
Finished Mar 07 01:49:54 PM PST 24
Peak memory 202512 kb
Host smart-08aa72dc-0ff6-4c35-8812-f5c1b040440f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
38661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2383638661
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.965595268
Short name T190
Test name
Test status
Simulation time 146209461 ps
CPU time 1.32 seconds
Started Mar 07 01:50:01 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 202460 kb
Host smart-17b60d73-c6b1-47a0-89f7-013e7d634038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96559
5268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.965595268
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3354610543
Short name T592
Test name
Test status
Simulation time 8379987632 ps
CPU time 7.28 seconds
Started Mar 07 01:49:46 PM PST 24
Finished Mar 07 01:49:53 PM PST 24
Peak memory 202452 kb
Host smart-84e4ae27-67c9-4670-b60a-84342fe27b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33546
10543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3354610543
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3646410601
Short name T428
Test name
Test status
Simulation time 8411589398 ps
CPU time 7.52 seconds
Started Mar 07 01:49:51 PM PST 24
Finished Mar 07 01:49:58 PM PST 24
Peak memory 202568 kb
Host smart-f5beb94b-829d-46fd-a1ee-5aa0d8951fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36464
10601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3646410601
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2525181035
Short name T644
Test name
Test status
Simulation time 8367795015 ps
CPU time 8.05 seconds
Started Mar 07 01:49:50 PM PST 24
Finished Mar 07 01:49:58 PM PST 24
Peak memory 202572 kb
Host smart-aafc5cb9-4a38-405e-9af2-30845e638097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25251
81035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2525181035
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.4079910004
Short name T101
Test name
Test status
Simulation time 8425176727 ps
CPU time 7.48 seconds
Started Mar 07 01:49:43 PM PST 24
Finished Mar 07 01:49:51 PM PST 24
Peak memory 202504 kb
Host smart-ca5d070f-a6bb-4344-a9e7-6d533a889156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40799
10004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.4079910004
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3898395718
Short name T297
Test name
Test status
Simulation time 8375109224 ps
CPU time 8.48 seconds
Started Mar 07 01:49:55 PM PST 24
Finished Mar 07 01:50:03 PM PST 24
Peak memory 202508 kb
Host smart-53c94dde-25c4-42f7-80ce-403627c3130c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38983
95718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3898395718
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3386771106
Short name T354
Test name
Test status
Simulation time 8383081214 ps
CPU time 7.77 seconds
Started Mar 07 01:49:56 PM PST 24
Finished Mar 07 01:50:04 PM PST 24
Peak memory 202448 kb
Host smart-d4f62053-0546-427f-b1da-9064093529e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33867
71106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3386771106
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2591166380
Short name T414
Test name
Test status
Simulation time 8392580187 ps
CPU time 8.79 seconds
Started Mar 07 01:49:53 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 202372 kb
Host smart-d0fb511d-0292-4615-a5f1-e7b1ce24723e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25911
66380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2591166380
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3675096951
Short name T399
Test name
Test status
Simulation time 8382666425 ps
CPU time 7.65 seconds
Started Mar 07 01:49:50 PM PST 24
Finished Mar 07 01:49:58 PM PST 24
Peak memory 202568 kb
Host smart-bd2cb037-6289-48ea-9fc6-f7ea1fdc9a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36750
96951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3675096951
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1611650478
Short name T474
Test name
Test status
Simulation time 8358244755 ps
CPU time 7.29 seconds
Started Mar 07 01:49:43 PM PST 24
Finished Mar 07 01:49:51 PM PST 24
Peak memory 202508 kb
Host smart-daa9dafc-3cc7-4609-94d9-acf13d054c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16116
50478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1611650478
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2042315985
Short name T483
Test name
Test status
Simulation time 8472384943 ps
CPU time 9 seconds
Started Mar 07 01:49:53 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 201716 kb
Host smart-35d5fe11-6fcf-4cae-b17c-9e7ac7f2bfa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
15985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2042315985
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2434451922
Short name T324
Test name
Test status
Simulation time 8371871460 ps
CPU time 7.65 seconds
Started Mar 07 01:49:59 PM PST 24
Finished Mar 07 01:50:07 PM PST 24
Peak memory 202508 kb
Host smart-85940a47-1ba8-4e31-8a02-6e189d3e5fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344
51922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2434451922
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3084756181
Short name T179
Test name
Test status
Simulation time 176567794 ps
CPU time 1.71 seconds
Started Mar 07 01:49:55 PM PST 24
Finished Mar 07 01:49:57 PM PST 24
Peak memory 202448 kb
Host smart-390fb9b5-fcf8-4e13-8bb6-ef6f21ef8379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30847
56181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3084756181
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2135569997
Short name T116
Test name
Test status
Simulation time 8427399315 ps
CPU time 7.67 seconds
Started Mar 07 01:49:57 PM PST 24
Finished Mar 07 01:50:05 PM PST 24
Peak memory 202452 kb
Host smart-12a937a8-4497-4069-a5f1-4fb572626521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21355
69997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2135569997
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.194315771
Short name T436
Test name
Test status
Simulation time 8415228214 ps
CPU time 7.64 seconds
Started Mar 07 01:49:55 PM PST 24
Finished Mar 07 01:50:03 PM PST 24
Peak memory 202572 kb
Host smart-6675a3e1-bc52-41d2-adba-b8207548a3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19431
5771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.194315771
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2229424304
Short name T347
Test name
Test status
Simulation time 8365054013 ps
CPU time 8.31 seconds
Started Mar 07 01:49:55 PM PST 24
Finished Mar 07 01:50:04 PM PST 24
Peak memory 202460 kb
Host smart-1b8340bc-fe43-4454-87ca-d3b17326bdea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22294
24304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2229424304
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.582959343
Short name T462
Test name
Test status
Simulation time 8530296855 ps
CPU time 7.52 seconds
Started Mar 07 01:49:55 PM PST 24
Finished Mar 07 01:50:03 PM PST 24
Peak memory 202480 kb
Host smart-550360f4-2f52-4410-988e-60501043aa26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58295
9343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.582959343
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2889991935
Short name T22
Test name
Test status
Simulation time 8389943441 ps
CPU time 7.17 seconds
Started Mar 07 01:49:53 PM PST 24
Finished Mar 07 01:50:00 PM PST 24
Peak memory 202512 kb
Host smart-a4780652-8505-4f5e-a8b0-9ca33cde336c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28899
91935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2889991935
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.198306691
Short name T636
Test name
Test status
Simulation time 8368509913 ps
CPU time 7.82 seconds
Started Mar 07 01:49:54 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 202484 kb
Host smart-e80ccbfb-516d-492f-aba6-4942fedd550d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19830
6691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.198306691
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2136241409
Short name T288
Test name
Test status
Simulation time 8361618701 ps
CPU time 9.11 seconds
Started Mar 07 01:49:56 PM PST 24
Finished Mar 07 01:50:06 PM PST 24
Peak memory 202456 kb
Host smart-2db42480-7b43-4465-a8d8-91f3255c30bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
41409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2136241409
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.968066278
Short name T587
Test name
Test status
Simulation time 8470647994 ps
CPU time 7.92 seconds
Started Mar 07 01:49:54 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 202452 kb
Host smart-290b2227-d612-4200-91d4-c8d23dce2d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96806
6278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.968066278
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.4134665085
Short name T471
Test name
Test status
Simulation time 8364761004 ps
CPU time 8.59 seconds
Started Mar 07 01:49:54 PM PST 24
Finished Mar 07 01:50:02 PM PST 24
Peak memory 202464 kb
Host smart-8d1384a1-2405-4de9-af4d-da5d34aea22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41346
65085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.4134665085
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3115568615
Short name T372
Test name
Test status
Simulation time 154918283 ps
CPU time 1.32 seconds
Started Mar 07 01:50:11 PM PST 24
Finished Mar 07 01:50:13 PM PST 24
Peak memory 202404 kb
Host smart-90d5746b-01a6-4572-9228-2eaada6dc4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31155
68615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3115568615
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.915159870
Short name T614
Test name
Test status
Simulation time 8396547362 ps
CPU time 7.28 seconds
Started Mar 07 01:50:09 PM PST 24
Finished Mar 07 01:50:17 PM PST 24
Peak memory 202512 kb
Host smart-0b26f16c-6067-4227-afa0-65ce0fae8488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91515
9870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.915159870
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3576551771
Short name T327
Test name
Test status
Simulation time 8418664971 ps
CPU time 7.68 seconds
Started Mar 07 01:50:10 PM PST 24
Finished Mar 07 01:50:17 PM PST 24
Peak memory 202500 kb
Host smart-34b7379c-76b4-4dbb-bf43-954608b98fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35765
51771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3576551771
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2929681320
Short name T389
Test name
Test status
Simulation time 8361591869 ps
CPU time 8.21 seconds
Started Mar 07 01:50:12 PM PST 24
Finished Mar 07 01:50:20 PM PST 24
Peak memory 202572 kb
Host smart-7c238835-d006-4d8c-b2f5-8d161f45b6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29296
81320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2929681320
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.3991800040
Short name T589
Test name
Test status
Simulation time 8402077378 ps
CPU time 8.49 seconds
Started Mar 07 01:50:10 PM PST 24
Finished Mar 07 01:50:18 PM PST 24
Peak memory 202524 kb
Host smart-adb4c954-1762-4852-bf03-4b0a2f1169ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
00040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3991800040
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.98336475
Short name T464
Test name
Test status
Simulation time 8397026278 ps
CPU time 7.23 seconds
Started Mar 07 01:50:10 PM PST 24
Finished Mar 07 01:50:18 PM PST 24
Peak memory 202468 kb
Host smart-a273aa0d-de0d-41a7-ab10-796c81aff21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98336
475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.98336475
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1605769380
Short name T77
Test name
Test status
Simulation time 8433659356 ps
CPU time 8.1 seconds
Started Mar 07 01:49:56 PM PST 24
Finished Mar 07 01:50:05 PM PST 24
Peak memory 202460 kb
Host smart-84fd2a06-2b7b-4e06-a123-827df001c4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16057
69380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1605769380
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2246604346
Short name T307
Test name
Test status
Simulation time 8367797441 ps
CPU time 7.48 seconds
Started Mar 07 01:50:15 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202492 kb
Host smart-ce3f9087-8728-4468-9cce-56ab6c7cabf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22466
04346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2246604346
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2449884328
Short name T329
Test name
Test status
Simulation time 8361119611 ps
CPU time 9.54 seconds
Started Mar 07 01:49:58 PM PST 24
Finished Mar 07 01:50:08 PM PST 24
Peak memory 202356 kb
Host smart-8e05fcb4-348e-4f45-935f-1c8aaea7b613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24498
84328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2449884328
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.249516541
Short name T27
Test name
Test status
Simulation time 8473778324 ps
CPU time 8.02 seconds
Started Mar 07 01:49:58 PM PST 24
Finished Mar 07 01:50:07 PM PST 24
Peak memory 202284 kb
Host smart-f97307c3-50b0-4c3d-a4a7-ee23620ecd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
6541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.249516541
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1865382506
Short name T448
Test name
Test status
Simulation time 8370725754 ps
CPU time 8.17 seconds
Started Mar 07 01:50:11 PM PST 24
Finished Mar 07 01:50:19 PM PST 24
Peak memory 202452 kb
Host smart-b4b8141a-46b8-40b7-a43a-0fe22d771161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18653
82506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1865382506
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1914232972
Short name T484
Test name
Test status
Simulation time 127056178 ps
CPU time 1.3 seconds
Started Mar 07 01:50:17 PM PST 24
Finished Mar 07 01:50:19 PM PST 24
Peak memory 202424 kb
Host smart-a426f210-4af3-4719-92d1-a9c60f5309b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19142
32972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1914232972
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2121749591
Short name T497
Test name
Test status
Simulation time 8424232259 ps
CPU time 7.7 seconds
Started Mar 07 01:50:13 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202536 kb
Host smart-4c9f450c-3047-4ad4-a83e-b62129c6f34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
49591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2121749591
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.263606841
Short name T422
Test name
Test status
Simulation time 8408128792 ps
CPU time 7.42 seconds
Started Mar 07 01:50:13 PM PST 24
Finished Mar 07 01:50:21 PM PST 24
Peak memory 202432 kb
Host smart-f3d6e83f-4f8c-47c5-a9fd-9bd35b5c95c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26360
6841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.263606841
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1967472511
Short name T527
Test name
Test status
Simulation time 8360581695 ps
CPU time 9.22 seconds
Started Mar 07 01:50:13 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202500 kb
Host smart-5b697130-8516-4c96-b8db-69d05742fb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19674
72511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1967472511
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2343163315
Short name T106
Test name
Test status
Simulation time 8403277126 ps
CPU time 7.47 seconds
Started Mar 07 01:50:13 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202524 kb
Host smart-755f8e9d-8e41-412a-a718-a6399741cb32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23431
63315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2343163315
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.415126892
Short name T268
Test name
Test status
Simulation time 8394976118 ps
CPU time 7.32 seconds
Started Mar 07 01:50:17 PM PST 24
Finished Mar 07 01:50:24 PM PST 24
Peak memory 201972 kb
Host smart-ff96e8ac-3c9d-4f7e-ad3b-faaba61b1891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41512
6892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.415126892
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2553696374
Short name T264
Test name
Test status
Simulation time 8375734433 ps
CPU time 7.91 seconds
Started Mar 07 01:50:19 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 202500 kb
Host smart-12ba4267-9ee2-43e5-9f7c-b7780c91082d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25536
96374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2553696374
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.4220261077
Short name T123
Test name
Test status
Simulation time 8394370333 ps
CPU time 9 seconds
Started Mar 07 01:50:14 PM PST 24
Finished Mar 07 01:50:23 PM PST 24
Peak memory 202492 kb
Host smart-dd580859-3d10-4647-a82e-29cf2e843d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42202
61077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.4220261077
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.3825267346
Short name T613
Test name
Test status
Simulation time 8402735542 ps
CPU time 7.8 seconds
Started Mar 07 01:50:13 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202460 kb
Host smart-379b9ec6-f382-468d-8f48-0f5b2b713710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38252
67346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.3825267346
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1021685742
Short name T363
Test name
Test status
Simulation time 8369441199 ps
CPU time 8.25 seconds
Started Mar 07 01:50:13 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202452 kb
Host smart-79ff7860-3ca7-41da-bcc5-2031090060dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10216
85742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1021685742
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1580868749
Short name T140
Test name
Test status
Simulation time 8479508913 ps
CPU time 8.09 seconds
Started Mar 07 01:50:12 PM PST 24
Finished Mar 07 01:50:20 PM PST 24
Peak memory 202496 kb
Host smart-aa3ff751-4f72-4aea-ae2c-dd509d2620da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15808
68749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1580868749
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2286945052
Short name T199
Test name
Test status
Simulation time 8392071118 ps
CPU time 7.81 seconds
Started Mar 07 01:48:26 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 202480 kb
Host smart-5880ffcd-8e0f-491b-a022-8eacc346e2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869
45052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2286945052
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.803215724
Short name T640
Test name
Test status
Simulation time 140241696 ps
CPU time 1.58 seconds
Started Mar 07 01:48:37 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 202456 kb
Host smart-939162f5-197d-4ded-a20c-a54ef298d5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80321
5724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.803215724
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.4179330443
Short name T534
Test name
Test status
Simulation time 8450752664 ps
CPU time 8.1 seconds
Started Mar 07 01:48:29 PM PST 24
Finished Mar 07 01:48:37 PM PST 24
Peak memory 202452 kb
Host smart-8d2172e2-8efb-45af-aeee-9c62592a61f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41793
30443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.4179330443
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3289223730
Short name T572
Test name
Test status
Simulation time 8413166681 ps
CPU time 7.5 seconds
Started Mar 07 01:48:36 PM PST 24
Finished Mar 07 01:48:44 PM PST 24
Peak memory 202516 kb
Host smart-1ed38541-eac9-42ee-a2c2-a7772fd6f29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32892
23730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3289223730
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2903460343
Short name T491
Test name
Test status
Simulation time 8365079005 ps
CPU time 8.3 seconds
Started Mar 07 01:48:38 PM PST 24
Finished Mar 07 01:48:46 PM PST 24
Peak memory 202452 kb
Host smart-b5b02f7c-b47e-48cc-957f-e596b7bc7be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
60343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2903460343
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3706624251
Short name T628
Test name
Test status
Simulation time 8463634293 ps
CPU time 7.39 seconds
Started Mar 07 01:48:33 PM PST 24
Finished Mar 07 01:48:41 PM PST 24
Peak memory 202496 kb
Host smart-80e54bf1-c779-4464-a4e0-c86245908862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37066
24251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3706624251
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3259962505
Short name T323
Test name
Test status
Simulation time 8375048275 ps
CPU time 7.26 seconds
Started Mar 07 01:48:36 PM PST 24
Finished Mar 07 01:48:44 PM PST 24
Peak memory 202452 kb
Host smart-0d7fad0b-3582-4ef7-a3bb-30c0bf9f6bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32599
62505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3259962505
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2445335403
Short name T110
Test name
Test status
Simulation time 8503011258 ps
CPU time 9.79 seconds
Started Mar 07 01:48:30 PM PST 24
Finished Mar 07 01:48:40 PM PST 24
Peak memory 202536 kb
Host smart-470b88f2-8827-4f39-aa29-ea9c8f02eb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24453
35403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2445335403
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.2600564184
Short name T603
Test name
Test status
Simulation time 8387559046 ps
CPU time 7.19 seconds
Started Mar 07 01:48:29 PM PST 24
Finished Mar 07 01:48:37 PM PST 24
Peak memory 202492 kb
Host smart-e2c4bba6-bb61-4f56-83af-3de2182d3d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26005
64184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.2600564184
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3320081749
Short name T46
Test name
Test status
Simulation time 446769589 ps
CPU time 1.26 seconds
Started Mar 07 01:48:41 PM PST 24
Finished Mar 07 01:48:43 PM PST 24
Peak memory 218524 kb
Host smart-7ca1f885-23e8-4645-8b99-da5d6d619885
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3320081749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3320081749
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2884920630
Short name T258
Test name
Test status
Simulation time 8364586499 ps
CPU time 7.54 seconds
Started Mar 07 01:48:29 PM PST 24
Finished Mar 07 01:48:36 PM PST 24
Peak memory 202540 kb
Host smart-9d911441-9229-4071-a087-092bd47b7421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28849
20630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2884920630
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3358681700
Short name T578
Test name
Test status
Simulation time 8469772411 ps
CPU time 7.61 seconds
Started Mar 07 01:48:27 PM PST 24
Finished Mar 07 01:48:34 PM PST 24
Peak memory 202508 kb
Host smart-ba72c472-47d0-4bc9-b722-16f7f1b78f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33586
81700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3358681700
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.309987038
Short name T24
Test name
Test status
Simulation time 8374841537 ps
CPU time 7.71 seconds
Started Mar 07 01:50:15 PM PST 24
Finished Mar 07 01:50:23 PM PST 24
Peak memory 202508 kb
Host smart-7de9d4ec-ffa5-4812-b8f0-31cd1e558dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30998
7038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.309987038
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2120403689
Short name T182
Test name
Test status
Simulation time 57469724 ps
CPU time 1.59 seconds
Started Mar 07 01:50:21 PM PST 24
Finished Mar 07 01:50:23 PM PST 24
Peak memory 202448 kb
Host smart-c904e6d6-698d-4d9c-bfe6-958962556b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21204
03689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2120403689
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.4261020306
Short name T431
Test name
Test status
Simulation time 8399882923 ps
CPU time 7.68 seconds
Started Mar 07 01:50:14 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202508 kb
Host smart-51ac0511-7af0-4015-a054-dcc1d12dfd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42610
20306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.4261020306
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1275788307
Short name T600
Test name
Test status
Simulation time 8436199848 ps
CPU time 9.06 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 202484 kb
Host smart-7cef0514-e2bc-46b2-9b8e-53c6bd3123ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12757
88307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1275788307
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2059442147
Short name T286
Test name
Test status
Simulation time 8361350267 ps
CPU time 9.79 seconds
Started Mar 07 01:50:20 PM PST 24
Finished Mar 07 01:50:30 PM PST 24
Peak memory 202516 kb
Host smart-e8700672-9248-458b-98b6-af1a83fad7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20594
42147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2059442147
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3372116476
Short name T87
Test name
Test status
Simulation time 8433588487 ps
CPU time 7.42 seconds
Started Mar 07 01:50:17 PM PST 24
Finished Mar 07 01:50:25 PM PST 24
Peak memory 202456 kb
Host smart-ecbc3c10-a38b-4a65-8309-23d3df4226af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33721
16476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3372116476
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2284512148
Short name T270
Test name
Test status
Simulation time 8406912662 ps
CPU time 7.94 seconds
Started Mar 07 01:50:17 PM PST 24
Finished Mar 07 01:50:25 PM PST 24
Peak memory 202512 kb
Host smart-7a174395-b8e6-43d9-8e69-fb7b33d79b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22845
12148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2284512148
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1490810961
Short name T526
Test name
Test status
Simulation time 8385759168 ps
CPU time 7.49 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:26 PM PST 24
Peak memory 202504 kb
Host smart-8edb00bb-ddac-4730-8571-9687995fd63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14908
10961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1490810961
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1320978767
Short name T621
Test name
Test status
Simulation time 8535284046 ps
CPU time 8.35 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:26 PM PST 24
Peak memory 202492 kb
Host smart-26160f2a-0c7b-43ee-955e-6e318c392273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209
78767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1320978767
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1998161404
Short name T559
Test name
Test status
Simulation time 8384952549 ps
CPU time 7.41 seconds
Started Mar 07 01:50:19 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 202500 kb
Host smart-a27f3bdd-0ce9-407b-b0bb-e180400a4e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981
61404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1998161404
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1129250168
Short name T558
Test name
Test status
Simulation time 8364957107 ps
CPU time 8.79 seconds
Started Mar 07 01:50:16 PM PST 24
Finished Mar 07 01:50:25 PM PST 24
Peak memory 202504 kb
Host smart-b2537a1f-62ed-41d0-bca5-ced72f6e5c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292
50168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1129250168
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.4292389985
Short name T499
Test name
Test status
Simulation time 8475078550 ps
CPU time 8.55 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 202464 kb
Host smart-7a8a9326-b610-4c11-b598-a772c9f00fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
89985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.4292389985
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1095974611
Short name T322
Test name
Test status
Simulation time 8369819091 ps
CPU time 7.5 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:26 PM PST 24
Peak memory 202492 kb
Host smart-d8fcec11-ead9-48f2-a734-6cb98fbeb41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10959
74611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1095974611
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1129010735
Short name T421
Test name
Test status
Simulation time 177031632 ps
CPU time 1.95 seconds
Started Mar 07 01:50:15 PM PST 24
Finished Mar 07 01:50:17 PM PST 24
Peak memory 202268 kb
Host smart-7db49556-f2bc-45de-8679-25b5a94c2180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11290
10735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1129010735
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1463674556
Short name T411
Test name
Test status
Simulation time 8491709345 ps
CPU time 7.65 seconds
Started Mar 07 01:50:15 PM PST 24
Finished Mar 07 01:50:23 PM PST 24
Peak memory 202460 kb
Host smart-31822a63-bb51-4571-9dfa-55fc6c1b911f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14636
74556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1463674556
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2576798768
Short name T450
Test name
Test status
Simulation time 8409098243 ps
CPU time 7.36 seconds
Started Mar 07 01:50:16 PM PST 24
Finished Mar 07 01:50:23 PM PST 24
Peak memory 202556 kb
Host smart-3bf51c55-ca28-46be-8102-e751b258df4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25767
98768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2576798768
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3847939140
Short name T452
Test name
Test status
Simulation time 8376304114 ps
CPU time 7.95 seconds
Started Mar 07 01:50:14 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202500 kb
Host smart-a2aa6d9b-9566-454b-b063-cf1e88786d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38479
39140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3847939140
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1246189810
Short name T92
Test name
Test status
Simulation time 8420560471 ps
CPU time 7.18 seconds
Started Mar 07 01:50:19 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 202504 kb
Host smart-eb4f0215-fe29-424a-a801-5e878666c0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12461
89810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1246189810
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2453917186
Short name T292
Test name
Test status
Simulation time 8406719796 ps
CPU time 7.38 seconds
Started Mar 07 01:50:14 PM PST 24
Finished Mar 07 01:50:21 PM PST 24
Peak memory 202456 kb
Host smart-a3622153-41fe-4f6c-8166-9700ea7d59fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24539
17186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2453917186
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.598561070
Short name T561
Test name
Test status
Simulation time 8403033947 ps
CPU time 7.1 seconds
Started Mar 07 01:50:13 PM PST 24
Finished Mar 07 01:50:21 PM PST 24
Peak memory 202452 kb
Host smart-242fdbef-14d2-429c-98ab-9ec6dcb33d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59856
1070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.598561070
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3030208918
Short name T10
Test name
Test status
Simulation time 8459901522 ps
CPU time 7.07 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:26 PM PST 24
Peak memory 202492 kb
Host smart-0e43e1c7-3a07-465f-8511-ae254c8a83e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
08918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3030208918
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.4000286645
Short name T239
Test name
Test status
Simulation time 8383229543 ps
CPU time 7.47 seconds
Started Mar 07 01:50:15 PM PST 24
Finished Mar 07 01:50:23 PM PST 24
Peak memory 202468 kb
Host smart-f2565695-a6cc-4612-9230-cd4c322cce62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
86645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.4000286645
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.890830044
Short name T390
Test name
Test status
Simulation time 8356880460 ps
CPU time 7.27 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:26 PM PST 24
Peak memory 202492 kb
Host smart-8da154b2-4c40-445b-8c06-27008c4c0f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89083
0044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.890830044
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1090358032
Short name T143
Test name
Test status
Simulation time 8494664235 ps
CPU time 7.15 seconds
Started Mar 07 01:50:14 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202516 kb
Host smart-fe00d0bf-d501-4d5b-b695-07bf8ee53d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10903
58032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1090358032
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2033216273
Short name T26
Test name
Test status
Simulation time 8371848516 ps
CPU time 7.81 seconds
Started Mar 07 01:50:17 PM PST 24
Finished Mar 07 01:50:25 PM PST 24
Peak memory 202504 kb
Host smart-a758c3d7-91a7-400c-8725-78a9123cb3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20332
16273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2033216273
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1538195143
Short name T243
Test name
Test status
Simulation time 66207528 ps
CPU time 1.6 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:20 PM PST 24
Peak memory 202500 kb
Host smart-66ae1ce7-6212-4f08-83a5-c06eea0450e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15381
95143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1538195143
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.57329872
Short name T456
Test name
Test status
Simulation time 8380544564 ps
CPU time 7.94 seconds
Started Mar 07 01:50:23 PM PST 24
Finished Mar 07 01:50:31 PM PST 24
Peak memory 202568 kb
Host smart-f5c47be1-fee4-46a9-8a7b-693de3908c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57329
872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.57329872
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2213061779
Short name T319
Test name
Test status
Simulation time 8411798467 ps
CPU time 9.85 seconds
Started Mar 07 01:50:16 PM PST 24
Finished Mar 07 01:50:26 PM PST 24
Peak memory 202512 kb
Host smart-98c6f8e1-e875-4fb7-8a12-3d425e038fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22130
61779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2213061779
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2657153880
Short name T81
Test name
Test status
Simulation time 8431781548 ps
CPU time 8.96 seconds
Started Mar 07 01:50:19 PM PST 24
Finished Mar 07 01:50:29 PM PST 24
Peak memory 202504 kb
Host smart-84637a8e-eceb-4f0c-8b8b-4922434344d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26571
53880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2657153880
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1346437815
Short name T454
Test name
Test status
Simulation time 8416137752 ps
CPU time 7.58 seconds
Started Mar 07 01:50:15 PM PST 24
Finished Mar 07 01:50:22 PM PST 24
Peak memory 202460 kb
Host smart-51d2554d-ffbe-4ae7-90f9-aa4937adf640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13464
37815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1346437815
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.924430331
Short name T177
Test name
Test status
Simulation time 8404571802 ps
CPU time 7.87 seconds
Started Mar 07 01:50:21 PM PST 24
Finished Mar 07 01:50:29 PM PST 24
Peak memory 202512 kb
Host smart-3f4a7ac6-f1cc-4648-8e0f-6073899d24a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92443
0331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.924430331
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2455762420
Short name T318
Test name
Test status
Simulation time 8440806181 ps
CPU time 9.1 seconds
Started Mar 07 01:50:15 PM PST 24
Finished Mar 07 01:50:24 PM PST 24
Peak memory 202236 kb
Host smart-3a32f6ce-2ba8-44ac-9f24-9ca022403229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24557
62420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2455762420
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1446961411
Short name T596
Test name
Test status
Simulation time 8372007679 ps
CPU time 7.77 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 202452 kb
Host smart-ccd03f70-922c-4525-bc67-df11d809e44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14469
61411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1446961411
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2959450231
Short name T290
Test name
Test status
Simulation time 8362918800 ps
CPU time 7.59 seconds
Started Mar 07 01:50:20 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 202444 kb
Host smart-53974e4d-5844-4552-9b1c-ed8f422b7b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29594
50231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2959450231
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.278148487
Short name T138
Test name
Test status
Simulation time 8474308418 ps
CPU time 7.19 seconds
Started Mar 07 01:50:12 PM PST 24
Finished Mar 07 01:50:19 PM PST 24
Peak memory 202496 kb
Host smart-16b3fdd9-a2b2-4693-bdea-640132b3b131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27814
8487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.278148487
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.967033076
Short name T442
Test name
Test status
Simulation time 8374882231 ps
CPU time 7.41 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:25 PM PST 24
Peak memory 202480 kb
Host smart-8d490789-cce8-4a9e-b0a3-bf4f9ea122a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96703
3076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.967033076
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1921768022
Short name T439
Test name
Test status
Simulation time 50899107 ps
CPU time 1.43 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 202400 kb
Host smart-d5d21a15-e2af-4cdd-bfb9-6255eba4015a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19217
68022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1921768022
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3439985202
Short name T348
Test name
Test status
Simulation time 8415934415 ps
CPU time 9.09 seconds
Started Mar 07 01:50:19 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 202436 kb
Host smart-557f38df-0b92-4a33-a7ae-998a4a02ccfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
85202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3439985202
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.410856970
Short name T606
Test name
Test status
Simulation time 8405555023 ps
CPU time 7.42 seconds
Started Mar 07 01:50:21 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 202408 kb
Host smart-4461863a-7be6-4ef2-b09e-ca09f6ba76cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085
6970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.410856970
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.108121428
Short name T320
Test name
Test status
Simulation time 8365704486 ps
CPU time 7.79 seconds
Started Mar 07 01:50:19 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 202496 kb
Host smart-9e11cfd1-8623-4a33-a5d3-e89fe47449eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10812
1428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.108121428
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2115569880
Short name T86
Test name
Test status
Simulation time 8380334376 ps
CPU time 8.68 seconds
Started Mar 07 01:50:20 PM PST 24
Finished Mar 07 01:50:29 PM PST 24
Peak memory 202432 kb
Host smart-078194e9-1bc3-465b-9f04-7381d6f9b2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21155
69880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2115569880
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2733316239
Short name T332
Test name
Test status
Simulation time 8378210145 ps
CPU time 7.97 seconds
Started Mar 07 01:50:23 PM PST 24
Finished Mar 07 01:50:32 PM PST 24
Peak memory 202452 kb
Host smart-2218f3fc-eb65-44bb-a5d5-9c45aee497e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27333
16239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2733316239
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1430072580
Short name T500
Test name
Test status
Simulation time 8397927096 ps
CPU time 7.62 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202404 kb
Host smart-9f3127ff-3103-4548-a24c-a268ea77edf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14300
72580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1430072580
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.478385065
Short name T115
Test name
Test status
Simulation time 8380642435 ps
CPU time 8.3 seconds
Started Mar 07 01:50:15 PM PST 24
Finished Mar 07 01:50:23 PM PST 24
Peak memory 202452 kb
Host smart-a438ceb7-d95e-479c-b2fd-c8426f0390de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47838
5065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.478385065
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1654891967
Short name T331
Test name
Test status
Simulation time 8423277041 ps
CPU time 7.59 seconds
Started Mar 07 01:50:20 PM PST 24
Finished Mar 07 01:50:29 PM PST 24
Peak memory 202496 kb
Host smart-6af89a14-527e-4d1e-a873-4441fd115f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16548
91967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1654891967
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1601737140
Short name T17
Test name
Test status
Simulation time 8361260656 ps
CPU time 7.4 seconds
Started Mar 07 01:50:18 PM PST 24
Finished Mar 07 01:50:26 PM PST 24
Peak memory 202504 kb
Host smart-113e6566-0e2e-40de-b417-f7b51ade9c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16017
37140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1601737140
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2287339254
Short name T176
Test name
Test status
Simulation time 83275209 ps
CPU time 1.18 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 202356 kb
Host smart-258c4160-805b-40c3-8dd2-a91656ab93bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22873
39254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2287339254
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3845330277
Short name T117
Test name
Test status
Simulation time 8440994318 ps
CPU time 8.54 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202472 kb
Host smart-9b3c8ab2-34fd-49a5-b05a-5c5dcbc891f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38453
30277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3845330277
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.509012542
Short name T236
Test name
Test status
Simulation time 8403715503 ps
CPU time 8.5 seconds
Started Mar 07 01:50:23 PM PST 24
Finished Mar 07 01:50:32 PM PST 24
Peak memory 202536 kb
Host smart-baa06c91-0c55-4f8b-b679-3924bf11317b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50901
2542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.509012542
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2915311569
Short name T248
Test name
Test status
Simulation time 8364574679 ps
CPU time 7.89 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202424 kb
Host smart-6dd51dba-bb16-401e-b4d8-56068c0d2bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
11569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2915311569
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1725136026
Short name T84
Test name
Test status
Simulation time 8423631798 ps
CPU time 7.79 seconds
Started Mar 07 01:50:21 PM PST 24
Finished Mar 07 01:50:29 PM PST 24
Peak memory 202448 kb
Host smart-8e43b326-23f9-4a06-b745-05140c0285f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17251
36026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1725136026
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2082204927
Short name T246
Test name
Test status
Simulation time 8397116511 ps
CPU time 8.22 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202512 kb
Host smart-236eb4cb-db94-4e2c-9d48-e872e11e1635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
04927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2082204927
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.746021836
Short name T295
Test name
Test status
Simulation time 8381919093 ps
CPU time 7.66 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202432 kb
Host smart-c13ab8d5-44b3-47b6-a24c-5cf6814b4d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74602
1836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.746021836
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2274908716
Short name T109
Test name
Test status
Simulation time 8421276440 ps
CPU time 7.64 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202456 kb
Host smart-83fe53c8-37ae-4a43-ab55-d34032624b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
08716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2274908716
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1257949519
Short name T447
Test name
Test status
Simulation time 8358473838 ps
CPU time 8.91 seconds
Started Mar 07 01:50:24 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202460 kb
Host smart-dcbc291c-34f0-4b2b-81d4-e1d59308d912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12579
49519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1257949519
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2284688703
Short name T352
Test name
Test status
Simulation time 8376199291 ps
CPU time 7.74 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202472 kb
Host smart-f8e55635-2c80-4a94-adb4-9dafff7f7461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22846
88703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2284688703
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.4169493618
Short name T641
Test name
Test status
Simulation time 96879959 ps
CPU time 1.24 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:27 PM PST 24
Peak memory 202480 kb
Host smart-6c90d091-6a4f-4556-b349-f730e3f5b468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41694
93618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.4169493618
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3118920675
Short name T404
Test name
Test status
Simulation time 8382512177 ps
CPU time 9.11 seconds
Started Mar 07 01:50:23 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202464 kb
Host smart-4f6a3d78-e4db-4069-824c-f944ab3ef7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31189
20675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3118920675
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2779652642
Short name T595
Test name
Test status
Simulation time 8419754655 ps
CPU time 7.99 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:35 PM PST 24
Peak memory 202500 kb
Host smart-e8b3df9d-f81c-4c0f-981e-975fada951ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27796
52642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2779652642
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1171264917
Short name T449
Test name
Test status
Simulation time 8364390643 ps
CPU time 7.57 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202516 kb
Host smart-e8d0e2f1-0ac7-48c2-94ff-eefbeafeaf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11712
64917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1171264917
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.247301636
Short name T79
Test name
Test status
Simulation time 8412912598 ps
CPU time 8.34 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202496 kb
Host smart-d6c7713c-3022-43c6-9f4f-fffba55712b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24730
1636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.247301636
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2055295789
Short name T570
Test name
Test status
Simulation time 8393660575 ps
CPU time 8.51 seconds
Started Mar 07 01:50:24 PM PST 24
Finished Mar 07 01:50:32 PM PST 24
Peak memory 202452 kb
Host smart-56a58172-9d6f-41e8-a9bb-005a14b6b3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20552
95789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2055295789
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2161355339
Short name T234
Test name
Test status
Simulation time 8392650909 ps
CPU time 7.36 seconds
Started Mar 07 01:50:22 PM PST 24
Finished Mar 07 01:50:29 PM PST 24
Peak memory 202464 kb
Host smart-72ddedf7-cf6e-488e-9eb1-7adde8678901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21613
55339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2161355339
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.4164319654
Short name T618
Test name
Test status
Simulation time 8403819622 ps
CPU time 7.13 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202528 kb
Host smart-a46d23e0-2bbf-430b-9a01-3ed664e77538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643
19654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4164319654
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.1212523232
Short name T60
Test name
Test status
Simulation time 8444872496 ps
CPU time 7.42 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:32 PM PST 24
Peak memory 202472 kb
Host smart-13a83805-118f-4699-b0b3-5ee437105a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12125
23232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.1212523232
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2107441754
Short name T537
Test name
Test status
Simulation time 8354931089 ps
CPU time 8.16 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202492 kb
Host smart-3814b48c-1f7f-42c2-abec-e3817e9dbecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21074
41754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2107441754
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.676836659
Short name T517
Test name
Test status
Simulation time 8473902587 ps
CPU time 7.34 seconds
Started Mar 07 01:50:24 PM PST 24
Finished Mar 07 01:50:31 PM PST 24
Peak memory 202476 kb
Host smart-f9de51e1-19ab-4929-a3a8-3b6d1de87467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67683
6659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.676836659
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.13976583
Short name T576
Test name
Test status
Simulation time 8366417423 ps
CPU time 9.43 seconds
Started Mar 07 01:50:28 PM PST 24
Finished Mar 07 01:50:38 PM PST 24
Peak memory 202476 kb
Host smart-d4a7ec8a-3cc0-4e50-8d73-d4cb4be1e7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13976
583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.13976583
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2594618870
Short name T233
Test name
Test status
Simulation time 189601728 ps
CPU time 2.04 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:28 PM PST 24
Peak memory 202444 kb
Host smart-19cebaa8-4048-4912-bc1e-f20543b17c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25946
18870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2594618870
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2032390194
Short name T108
Test name
Test status
Simulation time 8419986328 ps
CPU time 8.46 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202448 kb
Host smart-fc55f212-5812-491c-81cd-4628f12ac774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20323
90194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2032390194
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3187570785
Short name T441
Test name
Test status
Simulation time 8370905862 ps
CPU time 8.58 seconds
Started Mar 07 01:50:28 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202496 kb
Host smart-09627c21-163b-4405-96eb-3dd2bde64f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31875
70785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3187570785
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.25673269
Short name T90
Test name
Test status
Simulation time 8442603586 ps
CPU time 7.82 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202504 kb
Host smart-d9c485cf-30f8-4880-8414-fe3af0848d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25673
269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.25673269
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3196303476
Short name T457
Test name
Test status
Simulation time 8401116749 ps
CPU time 8.42 seconds
Started Mar 07 01:50:28 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202496 kb
Host smart-b2da3a1e-56aa-4489-948f-4948e38af5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31963
03476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3196303476
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1034329031
Short name T407
Test name
Test status
Simulation time 8369453612 ps
CPU time 8.57 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:38 PM PST 24
Peak memory 202488 kb
Host smart-9995ae73-5500-4f83-b5aa-2dccd7507448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10343
29031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1034329031
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3322262914
Short name T501
Test name
Test status
Simulation time 8403680928 ps
CPU time 7.58 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:35 PM PST 24
Peak memory 202496 kb
Host smart-340757ef-f642-46a9-9988-b7ab91bc8f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33222
62914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3322262914
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2680229012
Short name T555
Test name
Test status
Simulation time 8364645544 ps
CPU time 7.81 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202448 kb
Host smart-7c5810ee-3fc7-4780-a3bd-79c8df5f4425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26802
29012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2680229012
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1458648019
Short name T269
Test name
Test status
Simulation time 8361964320 ps
CPU time 8.62 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202448 kb
Host smart-b903f8f1-4c55-4135-a086-05fe2b1ce8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14586
48019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1458648019
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3314569408
Short name T276
Test name
Test status
Simulation time 8374770854 ps
CPU time 8.38 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202404 kb
Host smart-576e059a-9107-40e5-9213-4daa12670d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145
69408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3314569408
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3987094200
Short name T505
Test name
Test status
Simulation time 170912146 ps
CPU time 1.49 seconds
Started Mar 07 01:50:31 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 201832 kb
Host smart-2c0daf2b-2b80-454d-ab18-475cd23bad3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39870
94200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3987094200
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3189109565
Short name T35
Test name
Test status
Simulation time 8409619057 ps
CPU time 7.37 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202364 kb
Host smart-c124e044-0d84-4549-b0a1-ab2a2ac02d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31891
09565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3189109565
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.4237316528
Short name T262
Test name
Test status
Simulation time 8364439514 ps
CPU time 8.21 seconds
Started Mar 07 01:50:28 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202404 kb
Host smart-9cc713be-4b75-4fdb-add2-ef9f6cbdf097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42373
16528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.4237316528
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3730404266
Short name T78
Test name
Test status
Simulation time 8413320375 ps
CPU time 7.36 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202488 kb
Host smart-47e95eb7-d613-43c2-b864-6e8f98bc13a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37304
04266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3730404266
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1172611554
Short name T512
Test name
Test status
Simulation time 8402148123 ps
CPU time 7.22 seconds
Started Mar 07 01:50:28 PM PST 24
Finished Mar 07 01:50:35 PM PST 24
Peak memory 202352 kb
Host smart-86b0a33e-a233-417c-8c5e-6174c20e8d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11726
11554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1172611554
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3206042775
Short name T375
Test name
Test status
Simulation time 8375230304 ps
CPU time 9.88 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:39 PM PST 24
Peak memory 202328 kb
Host smart-1b594cbd-243f-4dc9-82b6-e589c2e35d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32060
42775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3206042775
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.598706654
Short name T359
Test name
Test status
Simulation time 8458574139 ps
CPU time 7.88 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202488 kb
Host smart-7a8767a0-d080-4b82-ae71-d10d2f0c5bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59870
6654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.598706654
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1087852116
Short name T580
Test name
Test status
Simulation time 8395613037 ps
CPU time 7.96 seconds
Started Mar 07 01:50:31 PM PST 24
Finished Mar 07 01:50:39 PM PST 24
Peak memory 202392 kb
Host smart-2821ed4d-2795-4281-a783-764351c1f1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10878
52116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1087852116
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3849071546
Short name T568
Test name
Test status
Simulation time 8366022173 ps
CPU time 7.28 seconds
Started Mar 07 01:50:28 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202484 kb
Host smart-86822aa2-8033-428c-8e09-10097358b02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38490
71546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3849071546
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3342768869
Short name T550
Test name
Test status
Simulation time 8472323394 ps
CPU time 7.43 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202512 kb
Host smart-3437e83f-534c-4ebe-92af-f0d1057493f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33427
68869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3342768869
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.123385033
Short name T547
Test name
Test status
Simulation time 8368712332 ps
CPU time 7.71 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202564 kb
Host smart-0ad49a55-aba8-40e7-b337-35ebabb13d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12338
5033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.123385033
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3299771987
Short name T308
Test name
Test status
Simulation time 8408915856 ps
CPU time 7.33 seconds
Started Mar 07 01:50:25 PM PST 24
Finished Mar 07 01:50:33 PM PST 24
Peak memory 202512 kb
Host smart-12f43ff2-dc01-418d-95a3-ed0029d95aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
71987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3299771987
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3486987265
Short name T401
Test name
Test status
Simulation time 8365948109 ps
CPU time 7.33 seconds
Started Mar 07 01:50:23 PM PST 24
Finished Mar 07 01:50:31 PM PST 24
Peak memory 202392 kb
Host smart-6fed241c-d1ec-4f0d-8704-39a10afe23a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34869
87265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3486987265
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3328512755
Short name T107
Test name
Test status
Simulation time 8424125576 ps
CPU time 7.18 seconds
Started Mar 07 01:50:30 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202508 kb
Host smart-a674eb79-2fd4-423b-80fa-7e0019a8e4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
12755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3328512755
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1530996612
Short name T599
Test name
Test status
Simulation time 8372337032 ps
CPU time 7.31 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:35 PM PST 24
Peak memory 202428 kb
Host smart-bba72086-6940-4e26-bacf-dbd1bf4cf7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15309
96612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1530996612
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.42059892
Short name T602
Test name
Test status
Simulation time 8404580676 ps
CPU time 7.14 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202432 kb
Host smart-ccbb6a22-a164-4eba-85df-dcbd473f4cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42059
892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.42059892
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1850206419
Short name T582
Test name
Test status
Simulation time 8403163877 ps
CPU time 9.58 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202476 kb
Host smart-e7231851-981e-48dd-ae54-a07d9378855d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18502
06419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1850206419
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2432877436
Short name T418
Test name
Test status
Simulation time 8380815134 ps
CPU time 7.81 seconds
Started Mar 07 01:50:24 PM PST 24
Finished Mar 07 01:50:32 PM PST 24
Peak memory 202564 kb
Host smart-5993175f-9d46-46c4-b632-9229b7ec8acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24328
77436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2432877436
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3244669406
Short name T369
Test name
Test status
Simulation time 8360023004 ps
CPU time 9.65 seconds
Started Mar 07 01:50:31 PM PST 24
Finished Mar 07 01:50:42 PM PST 24
Peak memory 202444 kb
Host smart-f076d443-3db9-4adf-84b1-0f4b9abc3316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32446
69406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3244669406
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1345895713
Short name T25
Test name
Test status
Simulation time 8370799941 ps
CPU time 7.27 seconds
Started Mar 07 01:50:28 PM PST 24
Finished Mar 07 01:50:35 PM PST 24
Peak memory 202508 kb
Host smart-db9aa0b6-8cf6-4815-9f38-59c16889d5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13458
95713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1345895713
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.266388971
Short name T197
Test name
Test status
Simulation time 193866281 ps
CPU time 1.53 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:31 PM PST 24
Peak memory 202456 kb
Host smart-5d58a78b-0dc4-46cf-a06a-d7087840dccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26638
8971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.266388971
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3648275195
Short name T58
Test name
Test status
Simulation time 8447664152 ps
CPU time 7.4 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:35 PM PST 24
Peak memory 202492 kb
Host smart-1c3cfbda-6cf8-47be-8644-dd087d4db65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36482
75195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3648275195
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3737814998
Short name T601
Test name
Test status
Simulation time 8437055303 ps
CPU time 8.32 seconds
Started Mar 07 01:50:30 PM PST 24
Finished Mar 07 01:50:38 PM PST 24
Peak memory 202568 kb
Host smart-dcfcdfb0-0548-4f5b-8eaf-a880ef841b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37378
14998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3737814998
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3985651774
Short name T541
Test name
Test status
Simulation time 8363005930 ps
CPU time 7.09 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202436 kb
Host smart-59726fc9-83e1-4617-84cc-02b5a765c818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39856
51774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3985651774
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2590112324
Short name T99
Test name
Test status
Simulation time 8406678655 ps
CPU time 7.31 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202476 kb
Host smart-6dcdeccd-8720-49d5-ac42-1f36a162643c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901
12324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2590112324
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.4030190513
Short name T619
Test name
Test status
Simulation time 8396482991 ps
CPU time 7.69 seconds
Started Mar 07 01:50:26 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202456 kb
Host smart-162eeedd-3797-4372-9ab6-9a33d7b44778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40301
90513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.4030190513
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1620659062
Short name T581
Test name
Test status
Simulation time 8379453943 ps
CPU time 7.22 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:37 PM PST 24
Peak memory 202452 kb
Host smart-5994fc64-030c-46ea-8959-6bf73236f32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16206
59062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1620659062
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3845438249
Short name T121
Test name
Test status
Simulation time 8405982304 ps
CPU time 8.4 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:38 PM PST 24
Peak memory 202480 kb
Host smart-da1b7aee-4ec8-4dd8-af3b-235f676ea65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38454
38249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3845438249
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2667820789
Short name T377
Test name
Test status
Simulation time 8419585415 ps
CPU time 7.44 seconds
Started Mar 07 01:50:29 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202572 kb
Host smart-fa7ba4f8-ef33-4202-acbf-1fa4df6f9517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26678
20789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2667820789
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3537800218
Short name T120
Test name
Test status
Simulation time 8477528011 ps
CPU time 9.44 seconds
Started Mar 07 01:50:27 PM PST 24
Finished Mar 07 01:50:36 PM PST 24
Peak memory 202440 kb
Host smart-168c4054-c835-47b3-9aa5-0a4cabd15e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35378
00218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3537800218
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1348028763
Short name T252
Test name
Test status
Simulation time 8368450467 ps
CPU time 7.66 seconds
Started Mar 07 01:48:35 PM PST 24
Finished Mar 07 01:48:43 PM PST 24
Peak memory 202480 kb
Host smart-9cb70e4f-2a23-4955-94e3-8b3b382864e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13480
28763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1348028763
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.997004517
Short name T406
Test name
Test status
Simulation time 99389703 ps
CPU time 1.25 seconds
Started Mar 07 01:48:37 PM PST 24
Finished Mar 07 01:48:39 PM PST 24
Peak memory 202436 kb
Host smart-d789528c-b07a-4060-aa01-316e89a6f546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99700
4517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.997004517
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2987089638
Short name T415
Test name
Test status
Simulation time 8394225565 ps
CPU time 7.6 seconds
Started Mar 07 01:48:35 PM PST 24
Finished Mar 07 01:48:43 PM PST 24
Peak memory 202508 kb
Host smart-1c8c68c2-b199-41cb-ac3e-09fc1f4e77cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29870
89638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2987089638
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2634861966
Short name T536
Test name
Test status
Simulation time 8404758227 ps
CPU time 9.69 seconds
Started Mar 07 01:48:38 PM PST 24
Finished Mar 07 01:48:48 PM PST 24
Peak memory 202488 kb
Host smart-1787c140-b946-4df9-bece-f4da56b78e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26348
61966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2634861966
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3173737415
Short name T486
Test name
Test status
Simulation time 8364474660 ps
CPU time 7.45 seconds
Started Mar 07 01:48:39 PM PST 24
Finished Mar 07 01:48:47 PM PST 24
Peak memory 202396 kb
Host smart-2903498b-142b-486f-8002-64ae05662d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
37415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3173737415
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.4258960397
Short name T103
Test name
Test status
Simulation time 8385417232 ps
CPU time 7.63 seconds
Started Mar 07 01:48:34 PM PST 24
Finished Mar 07 01:48:42 PM PST 24
Peak memory 202432 kb
Host smart-9da23493-ecf1-46de-9134-b7446287b5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42589
60397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.4258960397
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2922946465
Short name T575
Test name
Test status
Simulation time 8401701877 ps
CPU time 6.93 seconds
Started Mar 07 01:48:35 PM PST 24
Finished Mar 07 01:48:42 PM PST 24
Peak memory 202452 kb
Host smart-e3f28087-3c56-4dcc-bf75-216040c6e97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29229
46465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2922946465
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.2919248269
Short name T70
Test name
Test status
Simulation time 8382662320 ps
CPU time 7.37 seconds
Started Mar 07 01:48:42 PM PST 24
Finished Mar 07 01:48:49 PM PST 24
Peak memory 202500 kb
Host smart-927765bd-596e-4cc5-b43c-cfd0ebc456b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29192
48269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.2919248269
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.549320118
Short name T57
Test name
Test status
Simulation time 102594560 ps
CPU time 0.9 seconds
Started Mar 07 01:48:36 PM PST 24
Finished Mar 07 01:48:37 PM PST 24
Peak memory 217220 kb
Host smart-7433fdcf-9572-43d0-bea7-e87cf0a4bbc4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=549320118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.549320118
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3693246610
Short name T253
Test name
Test status
Simulation time 8366280824 ps
CPU time 7.06 seconds
Started Mar 07 01:48:34 PM PST 24
Finished Mar 07 01:48:41 PM PST 24
Peak memory 202436 kb
Host smart-955e52b8-f7cd-4200-bfca-ed0ae5f530dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36932
46610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3693246610
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.25231378
Short name T28
Test name
Test status
Simulation time 8476577458 ps
CPU time 7.93 seconds
Started Mar 07 01:48:37 PM PST 24
Finished Mar 07 01:48:45 PM PST 24
Peak memory 202484 kb
Host smart-a1d42697-f6db-4885-8753-75b39866d987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25231
378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.25231378
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.748776211
Short name T366
Test name
Test status
Simulation time 8369381515 ps
CPU time 7.24 seconds
Started Mar 07 01:50:42 PM PST 24
Finished Mar 07 01:50:50 PM PST 24
Peak memory 202580 kb
Host smart-083139bd-a2d3-4813-b274-4e352de045ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74877
6211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.748776211
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2766374298
Short name T459
Test name
Test status
Simulation time 302851493 ps
CPU time 2.25 seconds
Started Mar 07 01:50:37 PM PST 24
Finished Mar 07 01:50:39 PM PST 24
Peak memory 202432 kb
Host smart-d1defdee-95a6-47fb-8cd8-85d4800cd4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27663
74298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2766374298
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2203202449
Short name T413
Test name
Test status
Simulation time 8379017197 ps
CPU time 7.85 seconds
Started Mar 07 01:50:39 PM PST 24
Finished Mar 07 01:50:47 PM PST 24
Peak memory 202512 kb
Host smart-b4422bea-4b25-4fc1-8c41-c2282286fe50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22032
02449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2203202449
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1209730200
Short name T472
Test name
Test status
Simulation time 8408720632 ps
CPU time 7.49 seconds
Started Mar 07 01:50:37 PM PST 24
Finished Mar 07 01:50:45 PM PST 24
Peak memory 202452 kb
Host smart-1caaadce-4524-4287-baea-8b7a157c2513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12097
30200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1209730200
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1876820880
Short name T605
Test name
Test status
Simulation time 8367431667 ps
CPU time 9.49 seconds
Started Mar 07 01:50:32 PM PST 24
Finished Mar 07 01:50:42 PM PST 24
Peak memory 202444 kb
Host smart-88bd432c-b54c-49e8-9fa4-06fa80c3325a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18768
20880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1876820880
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.376054937
Short name T83
Test name
Test status
Simulation time 8429242859 ps
CPU time 7.44 seconds
Started Mar 07 01:50:38 PM PST 24
Finished Mar 07 01:50:45 PM PST 24
Peak memory 202504 kb
Host smart-28223027-71e8-4be3-9305-25a11b52a561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37605
4937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.376054937
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1462303732
Short name T309
Test name
Test status
Simulation time 8374107195 ps
CPU time 7.48 seconds
Started Mar 07 01:50:37 PM PST 24
Finished Mar 07 01:50:45 PM PST 24
Peak memory 202480 kb
Host smart-3054e7bf-0a00-4747-bd58-eeb475a2d5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
03732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1462303732
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3653639781
Short name T336
Test name
Test status
Simulation time 8390796742 ps
CPU time 8.79 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:50 PM PST 24
Peak memory 202444 kb
Host smart-17a456e7-4808-40eb-ba83-47815a91da86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36536
39781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3653639781
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.117228613
Short name T387
Test name
Test status
Simulation time 8395622674 ps
CPU time 7.52 seconds
Started Mar 07 01:50:35 PM PST 24
Finished Mar 07 01:50:43 PM PST 24
Peak memory 202512 kb
Host smart-60e9833e-ee80-43ec-936a-d7d2c893bdb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
8613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.117228613
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.4209920539
Short name T18
Test name
Test status
Simulation time 8413490283 ps
CPU time 7.03 seconds
Started Mar 07 01:50:34 PM PST 24
Finished Mar 07 01:50:42 PM PST 24
Peak memory 202436 kb
Host smart-7a53c645-b189-45d6-80f6-3978ab68d210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42099
20539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.4209920539
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1153650249
Short name T430
Test name
Test status
Simulation time 8366045756 ps
CPU time 7.94 seconds
Started Mar 07 01:50:34 PM PST 24
Finished Mar 07 01:50:42 PM PST 24
Peak memory 202508 kb
Host smart-e389be22-6469-4b8f-a184-5b589d0b370c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11536
50249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1153650249
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2784770435
Short name T147
Test name
Test status
Simulation time 8473526535 ps
CPU time 8.76 seconds
Started Mar 07 01:50:34 PM PST 24
Finished Mar 07 01:50:42 PM PST 24
Peak memory 202512 kb
Host smart-b510b935-c119-425d-a7f3-87df7c0e673c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27847
70435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2784770435
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2210259189
Short name T371
Test name
Test status
Simulation time 8379664895 ps
CPU time 8.3 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202512 kb
Host smart-7224135e-8d66-4762-a550-b05c713eb9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22102
59189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2210259189
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1660006506
Short name T178
Test name
Test status
Simulation time 156145285 ps
CPU time 1.13 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:41 PM PST 24
Peak memory 202464 kb
Host smart-2bbde300-1acf-4f1d-92db-5d97c70ec054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16600
06506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1660006506
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3669692897
Short name T112
Test name
Test status
Simulation time 8438429466 ps
CPU time 8.04 seconds
Started Mar 07 01:50:35 PM PST 24
Finished Mar 07 01:50:44 PM PST 24
Peak memory 202436 kb
Host smart-58511825-2107-45e0-8ee9-a19959e2fa0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36696
92897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3669692897
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.4261170036
Short name T350
Test name
Test status
Simulation time 8450506387 ps
CPU time 7.58 seconds
Started Mar 07 01:50:31 PM PST 24
Finished Mar 07 01:50:40 PM PST 24
Peak memory 202472 kb
Host smart-fe0ab2a4-e8f8-4580-87d0-47b859776ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42611
70036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.4261170036
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.568738480
Short name T638
Test name
Test status
Simulation time 8366040913 ps
CPU time 7.46 seconds
Started Mar 07 01:50:37 PM PST 24
Finished Mar 07 01:50:45 PM PST 24
Peak memory 202396 kb
Host smart-57cf1fc7-a349-4dae-a7ac-8b1568de41a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56873
8480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.568738480
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1981047687
Short name T196
Test name
Test status
Simulation time 8428679107 ps
CPU time 9.6 seconds
Started Mar 07 01:50:32 PM PST 24
Finished Mar 07 01:50:42 PM PST 24
Peak memory 202496 kb
Host smart-905e674b-e8f7-4eb1-abb1-fa62e397ddf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19810
47687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1981047687
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2506857427
Short name T423
Test name
Test status
Simulation time 8375151765 ps
CPU time 7.29 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202564 kb
Host smart-a1406bc9-8008-479f-9de7-c757af5f224e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25068
57427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2506857427
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3399077316
Short name T195
Test name
Test status
Simulation time 8419055909 ps
CPU time 7.55 seconds
Started Mar 07 01:50:35 PM PST 24
Finished Mar 07 01:50:43 PM PST 24
Peak memory 202512 kb
Host smart-e23b4efc-d920-49d0-be1d-c76a58acf199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33990
77316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3399077316
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1118836900
Short name T620
Test name
Test status
Simulation time 8444571050 ps
CPU time 7.31 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202488 kb
Host smart-c6dc2a7a-4263-45ea-9191-dd25600af261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11188
36900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1118836900
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1393228180
Short name T496
Test name
Test status
Simulation time 8378539877 ps
CPU time 7.23 seconds
Started Mar 07 01:50:36 PM PST 24
Finished Mar 07 01:50:44 PM PST 24
Peak memory 202464 kb
Host smart-a0084271-d43d-4328-b28b-91fc45f22bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932
28180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1393228180
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.4084061543
Short name T469
Test name
Test status
Simulation time 8364520265 ps
CPU time 7.52 seconds
Started Mar 07 01:50:36 PM PST 24
Finished Mar 07 01:50:44 PM PST 24
Peak memory 202512 kb
Host smart-b85abbad-aed8-45c7-92d3-979bc1559cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40840
61543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.4084061543
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1317805583
Short name T132
Test name
Test status
Simulation time 8476808909 ps
CPU time 7.23 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202564 kb
Host smart-97c7f944-6da4-453b-91f3-9363b2d5cb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13178
05583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1317805583
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3019717835
Short name T508
Test name
Test status
Simulation time 8373105737 ps
CPU time 9.49 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202488 kb
Host smart-d93465fb-3cf5-417c-b823-caeae80b91b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30197
17835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3019717835
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2727470929
Short name T189
Test name
Test status
Simulation time 105008711 ps
CPU time 1.19 seconds
Started Mar 07 01:50:32 PM PST 24
Finished Mar 07 01:50:34 PM PST 24
Peak memory 202424 kb
Host smart-d83c8a97-de6d-4bc9-a67f-e1e7008c9b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27274
70929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2727470929
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2243490117
Short name T643
Test name
Test status
Simulation time 8408277305 ps
CPU time 8.6 seconds
Started Mar 07 01:50:38 PM PST 24
Finished Mar 07 01:50:47 PM PST 24
Peak memory 202508 kb
Host smart-c9d8dc5a-5637-41d6-b65c-4371aa901262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22434
90117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2243490117
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2214422246
Short name T395
Test name
Test status
Simulation time 8410324536 ps
CPU time 7.46 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202504 kb
Host smart-50a8a102-748e-428c-8e4c-5c63edd93017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22144
22246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2214422246
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.848380430
Short name T540
Test name
Test status
Simulation time 8382638234 ps
CPU time 7.47 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202516 kb
Host smart-41da211e-6715-4526-a2ec-cb23bcbce1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84838
0430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.848380430
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3401050613
Short name T514
Test name
Test status
Simulation time 8460897471 ps
CPU time 7.79 seconds
Started Mar 07 01:50:43 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202536 kb
Host smart-f9d1fbe8-4f05-414e-9ade-a51fee18eeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34010
50613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3401050613
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.669715177
Short name T396
Test name
Test status
Simulation time 8373144948 ps
CPU time 7.07 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202488 kb
Host smart-061bbecf-8bcc-4e15-9317-ca1a53b70661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66971
5177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.669715177
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1895894956
Short name T342
Test name
Test status
Simulation time 8408134865 ps
CPU time 7.51 seconds
Started Mar 07 01:50:39 PM PST 24
Finished Mar 07 01:50:47 PM PST 24
Peak memory 202516 kb
Host smart-737e69a4-874b-4ee1-a5e1-524bb924ffab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18958
94956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1895894956
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2793030843
Short name T379
Test name
Test status
Simulation time 8387251950 ps
CPU time 8.8 seconds
Started Mar 07 01:50:38 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202448 kb
Host smart-85870fdb-8b71-42b2-bce4-10602d35019c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27930
30843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2793030843
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.3925664484
Short name T623
Test name
Test status
Simulation time 8377597530 ps
CPU time 7.14 seconds
Started Mar 07 01:50:38 PM PST 24
Finished Mar 07 01:50:46 PM PST 24
Peak memory 202436 kb
Host smart-8925b3a3-d8a7-4c93-8276-368e0eae7429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39256
64484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.3925664484
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3485429966
Short name T402
Test name
Test status
Simulation time 8363936530 ps
CPU time 7.34 seconds
Started Mar 07 01:50:39 PM PST 24
Finished Mar 07 01:50:46 PM PST 24
Peak memory 202508 kb
Host smart-a7f8cb91-bbe0-4ff9-9018-77b1c1d7af9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34854
29966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3485429966
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3160191335
Short name T513
Test name
Test status
Simulation time 8483871974 ps
CPU time 7.33 seconds
Started Mar 07 01:50:38 PM PST 24
Finished Mar 07 01:50:46 PM PST 24
Peak memory 202516 kb
Host smart-9e38a906-a203-4258-ac1d-6b963fac3af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31601
91335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3160191335
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.372034949
Short name T192
Test name
Test status
Simulation time 8376143433 ps
CPU time 9.12 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:50 PM PST 24
Peak memory 202512 kb
Host smart-59d81636-af0c-45bd-9350-7404c51b2aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37203
4949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.372034949
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3550886417
Short name T39
Test name
Test status
Simulation time 218512577 ps
CPU time 2.26 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:46 PM PST 24
Peak memory 202516 kb
Host smart-52ac29af-1a3e-400a-9466-95ade6881d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35508
86417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3550886417
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2775761742
Short name T119
Test name
Test status
Simulation time 8445438279 ps
CPU time 8.59 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 202444 kb
Host smart-59f4c37a-78e7-4f3b-bb65-cdd51982a524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27757
61742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2775761742
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.4196430415
Short name T553
Test name
Test status
Simulation time 8408943102 ps
CPU time 7.52 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202448 kb
Host smart-0d9376bd-73cb-45fa-9229-d4b64dd90e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41964
30415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.4196430415
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2240488649
Short name T412
Test name
Test status
Simulation time 8378744458 ps
CPU time 6.98 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202388 kb
Host smart-7f4d5ae1-3c21-491c-9753-5731ba702144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22404
88649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2240488649
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1851540685
Short name T191
Test name
Test status
Simulation time 8412095338 ps
CPU time 7.16 seconds
Started Mar 07 01:50:39 PM PST 24
Finished Mar 07 01:50:47 PM PST 24
Peak memory 202444 kb
Host smart-af08e619-9a0f-4144-a004-d43fe722b9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18515
40685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1851540685
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2024958297
Short name T515
Test name
Test status
Simulation time 8376496563 ps
CPU time 7.69 seconds
Started Mar 07 01:50:48 PM PST 24
Finished Mar 07 01:50:56 PM PST 24
Peak memory 202512 kb
Host smart-d5b8f7b8-17d6-44f4-bd58-54a57389827a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20249
58297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2024958297
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.694918401
Short name T326
Test name
Test status
Simulation time 8433132382 ps
CPU time 7.39 seconds
Started Mar 07 01:50:34 PM PST 24
Finished Mar 07 01:50:42 PM PST 24
Peak memory 202524 kb
Host smart-8d6db8cc-627f-439b-bfc1-ca60dc5481df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69491
8401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.694918401
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3494366348
Short name T311
Test name
Test status
Simulation time 8404502764 ps
CPU time 7.72 seconds
Started Mar 07 01:50:38 PM PST 24
Finished Mar 07 01:50:46 PM PST 24
Peak memory 202492 kb
Host smart-52ca44af-634f-4b41-90a8-4b4ac1ed0d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34943
66348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3494366348
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2443996073
Short name T334
Test name
Test status
Simulation time 8363669314 ps
CPU time 8.16 seconds
Started Mar 07 01:50:42 PM PST 24
Finished Mar 07 01:50:50 PM PST 24
Peak memory 202508 kb
Host smart-47eb77a0-8da2-4f85-abbb-981ffb91a4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24439
96073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2443996073
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2284749624
Short name T150
Test name
Test status
Simulation time 8478448905 ps
CPU time 8.06 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 202448 kb
Host smart-4bed646b-d0eb-4953-8146-bb6d581d91c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22847
49624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2284749624
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1812228890
Short name T33
Test name
Test status
Simulation time 8372134068 ps
CPU time 8.37 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202512 kb
Host smart-d85f52cd-0142-44be-9505-f9b01a8e10fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18122
28890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1812228890
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.722928438
Short name T263
Test name
Test status
Simulation time 62333999 ps
CPU time 2.01 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:43 PM PST 24
Peak memory 202400 kb
Host smart-efc4fb18-4671-4d90-942a-03274571531b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72292
8438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.722928438
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3760936226
Short name T312
Test name
Test status
Simulation time 8443810709 ps
CPU time 7.45 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202564 kb
Host smart-a37afd78-1501-411c-9721-182143075047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
36226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3760936226
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3070539679
Short name T341
Test name
Test status
Simulation time 8367095651 ps
CPU time 7.39 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:48 PM PST 24
Peak memory 202452 kb
Host smart-97836c1f-0269-4cb6-a53c-0ace6c8fbdd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30705
39679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3070539679
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.600958291
Short name T91
Test name
Test status
Simulation time 8430214956 ps
CPU time 9.48 seconds
Started Mar 07 01:50:39 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 202512 kb
Host smart-6d163813-be2e-4927-9a4d-0eff82d9ce57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60095
8291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.600958291
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2949474273
Short name T617
Test name
Test status
Simulation time 8394182002 ps
CPU time 7.48 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202564 kb
Host smart-58257aaf-5d89-4c65-bcbb-c5b7e1c59883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29494
74273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2949474273
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3059831562
Short name T374
Test name
Test status
Simulation time 8390967246 ps
CPU time 7.25 seconds
Started Mar 07 01:50:42 PM PST 24
Finished Mar 07 01:50:50 PM PST 24
Peak memory 202588 kb
Host smart-8b83bdd2-9ebe-46b7-b42c-5af8340ae7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30598
31562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3059831562
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2612389118
Short name T567
Test name
Test status
Simulation time 8427749411 ps
CPU time 9.88 seconds
Started Mar 07 01:50:48 PM PST 24
Finished Mar 07 01:50:59 PM PST 24
Peak memory 202512 kb
Host smart-6ec3c454-acaf-4849-831f-59a0cc382a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26123
89118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2612389118
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.1245501412
Short name T284
Test name
Test status
Simulation time 8384538057 ps
CPU time 7.04 seconds
Started Mar 07 01:50:38 PM PST 24
Finished Mar 07 01:50:45 PM PST 24
Peak memory 202488 kb
Host smart-9cc97799-87c9-479a-849d-17479a4ce9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12455
01412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.1245501412
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_smoke.987282439
Short name T133
Test name
Test status
Simulation time 8475752666 ps
CPU time 7.36 seconds
Started Mar 07 01:50:49 PM PST 24
Finished Mar 07 01:50:56 PM PST 24
Peak memory 202456 kb
Host smart-25ebb9e7-8e41-4e57-ad6b-4f655e2c752a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98728
2439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.987282439
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2021885190
Short name T294
Test name
Test status
Simulation time 8370566359 ps
CPU time 7.71 seconds
Started Mar 07 01:50:38 PM PST 24
Finished Mar 07 01:50:46 PM PST 24
Peak memory 202512 kb
Host smart-43ce9977-fd3c-412f-90ae-deba59cf162f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20218
85190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2021885190
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2507211851
Short name T198
Test name
Test status
Simulation time 81363841 ps
CPU time 1.77 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:46 PM PST 24
Peak memory 202412 kb
Host smart-96ac6828-7df0-410d-9b96-13d3c96de694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25072
11851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2507211851
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3299340456
Short name T463
Test name
Test status
Simulation time 8453901699 ps
CPU time 7.99 seconds
Started Mar 07 01:50:40 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 202508 kb
Host smart-795f6343-3868-43ff-aba0-501439115724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32993
40456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3299340456
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1451606300
Short name T609
Test name
Test status
Simulation time 8411170251 ps
CPU time 7.72 seconds
Started Mar 07 01:50:46 PM PST 24
Finished Mar 07 01:50:54 PM PST 24
Peak memory 202492 kb
Host smart-ef7f891c-8a77-4944-9619-9e999b342f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14516
06300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1451606300
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2950796143
Short name T376
Test name
Test status
Simulation time 8402352198 ps
CPU time 9.61 seconds
Started Mar 07 01:50:49 PM PST 24
Finished Mar 07 01:50:59 PM PST 24
Peak memory 202516 kb
Host smart-29525330-1b4a-4654-87cc-93be89cf26f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29507
96143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2950796143
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.863649411
Short name T88
Test name
Test status
Simulation time 8423256792 ps
CPU time 7.98 seconds
Started Mar 07 01:50:37 PM PST 24
Finished Mar 07 01:50:45 PM PST 24
Peak memory 202484 kb
Host smart-f6df98cd-0923-4ae3-b0ff-5a4e188185a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86364
9411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.863649411
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.322103278
Short name T266
Test name
Test status
Simulation time 8387175025 ps
CPU time 9.69 seconds
Started Mar 07 01:50:49 PM PST 24
Finished Mar 07 01:50:59 PM PST 24
Peak memory 202480 kb
Host smart-d9e1592f-63ea-41d2-a3f9-4f629532a873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
3278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.322103278
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1718363567
Short name T287
Test name
Test status
Simulation time 8378824800 ps
CPU time 8.23 seconds
Started Mar 07 01:50:43 PM PST 24
Finished Mar 07 01:50:52 PM PST 24
Peak memory 202460 kb
Host smart-7c37b54b-6fbb-42da-b485-55cd72daed8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17183
63567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1718363567
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3986178453
Short name T615
Test name
Test status
Simulation time 8455267991 ps
CPU time 7.79 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 202448 kb
Host smart-edb15390-5825-4124-a773-cc3b651fdaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39861
78453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3986178453
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.256602864
Short name T563
Test name
Test status
Simulation time 8377489415 ps
CPU time 7.46 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 202448 kb
Host smart-14592786-07b4-4580-9d7d-f2c61550b045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25660
2864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.256602864
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1052201889
Short name T19
Test name
Test status
Simulation time 8358608447 ps
CPU time 7.82 seconds
Started Mar 07 01:50:39 PM PST 24
Finished Mar 07 01:50:47 PM PST 24
Peak memory 202452 kb
Host smart-3fac4ca2-24be-489b-82fb-1d2d4d66f624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10522
01889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1052201889
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3398049207
Short name T574
Test name
Test status
Simulation time 8474376689 ps
CPU time 7.8 seconds
Started Mar 07 01:50:41 PM PST 24
Finished Mar 07 01:50:49 PM PST 24
Peak memory 202488 kb
Host smart-489e52ea-4ab5-4dc5-a3d1-faed5e9388ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33980
49207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3398049207
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1430823393
Short name T298
Test name
Test status
Simulation time 8370112125 ps
CPU time 8.21 seconds
Started Mar 07 01:50:43 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202508 kb
Host smart-08c3ae76-e8f4-4622-bb9f-532fb7985653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308
23393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1430823393
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2475408354
Short name T40
Test name
Test status
Simulation time 60759511 ps
CPU time 1.32 seconds
Started Mar 07 01:50:51 PM PST 24
Finished Mar 07 01:50:53 PM PST 24
Peak memory 202488 kb
Host smart-abf9b8ca-37e1-4435-8c94-469b57c5e387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
08354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2475408354
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2590131046
Short name T482
Test name
Test status
Simulation time 8436607481 ps
CPU time 8.11 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 01:51:07 PM PST 24
Peak memory 202504 kb
Host smart-8e6e4eef-34b0-479b-a581-d06b28232cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901
31046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2590131046
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2374436001
Short name T566
Test name
Test status
Simulation time 8413650503 ps
CPU time 7.22 seconds
Started Mar 07 01:51:03 PM PST 24
Finished Mar 07 01:51:11 PM PST 24
Peak memory 202492 kb
Host smart-aa69874b-8def-480e-8a69-9bf13d6ef4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23744
36001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2374436001
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.4048748769
Short name T64
Test name
Test status
Simulation time 8388016608 ps
CPU time 8.37 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:53 PM PST 24
Peak memory 202508 kb
Host smart-85b148c4-26e7-45af-acea-bf3e4d6642cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40487
48769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.4048748769
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2974216251
Short name T255
Test name
Test status
Simulation time 8404053864 ps
CPU time 7.7 seconds
Started Mar 07 01:50:47 PM PST 24
Finished Mar 07 01:50:55 PM PST 24
Peak memory 202496 kb
Host smart-c4bdadda-a4fa-41a7-9e52-e798312cb8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29742
16251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2974216251
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3945555406
Short name T511
Test name
Test status
Simulation time 8378192019 ps
CPU time 9.93 seconds
Started Mar 07 01:50:48 PM PST 24
Finished Mar 07 01:50:59 PM PST 24
Peak memory 202452 kb
Host smart-20bceca9-80d6-40c8-a57e-9e0cfdd45121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39455
55406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3945555406
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3864115750
Short name T66
Test name
Test status
Simulation time 8362369558 ps
CPU time 9.2 seconds
Started Mar 07 01:50:48 PM PST 24
Finished Mar 07 01:50:58 PM PST 24
Peak memory 202452 kb
Host smart-a5ae41c3-672b-4928-93fc-3cf6c5f8add0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38641
15750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3864115750
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2571102710
Short name T607
Test name
Test status
Simulation time 8355422311 ps
CPU time 7.64 seconds
Started Mar 07 01:50:49 PM PST 24
Finished Mar 07 01:50:57 PM PST 24
Peak memory 202476 kb
Host smart-d7a16731-3166-41d1-9dd0-b09e90cdc0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25711
02710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2571102710
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2677781717
Short name T373
Test name
Test status
Simulation time 8370577849 ps
CPU time 7.44 seconds
Started Mar 07 01:50:46 PM PST 24
Finished Mar 07 01:50:54 PM PST 24
Peak memory 202452 kb
Host smart-9d10ba1e-c43c-47e6-934c-2f89058a0584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26777
81717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2677781717
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2442413959
Short name T535
Test name
Test status
Simulation time 277885471 ps
CPU time 2.06 seconds
Started Mar 07 01:50:43 PM PST 24
Finished Mar 07 01:50:45 PM PST 24
Peak memory 202380 kb
Host smart-f562ec3e-33b8-4670-96cc-653b1f79c7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24424
13959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2442413959
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3445983251
Short name T507
Test name
Test status
Simulation time 8431662369 ps
CPU time 7.02 seconds
Started Mar 07 01:50:45 PM PST 24
Finished Mar 07 01:50:52 PM PST 24
Peak memory 202464 kb
Host smart-2ebc3d58-e1b2-4585-97c5-cdbdfb63e5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34459
83251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3445983251
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.4125832567
Short name T424
Test name
Test status
Simulation time 8427857846 ps
CPU time 7.41 seconds
Started Mar 07 01:50:43 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202500 kb
Host smart-221d12b9-aeec-43a2-b12d-12268b56384c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41258
32567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.4125832567
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.376186288
Short name T434
Test name
Test status
Simulation time 8365711029 ps
CPU time 7.25 seconds
Started Mar 07 01:50:52 PM PST 24
Finished Mar 07 01:50:59 PM PST 24
Peak memory 202492 kb
Host smart-eb5ce175-5aeb-440b-b3a1-ea64e0e00cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37618
6288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.376186288
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2344408466
Short name T100
Test name
Test status
Simulation time 8440624860 ps
CPU time 9.14 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:53 PM PST 24
Peak memory 202460 kb
Host smart-0d5f809f-4a77-438b-a601-f86618c70a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
08466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2344408466
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1232397889
Short name T571
Test name
Test status
Simulation time 8390630768 ps
CPU time 7.37 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:52 PM PST 24
Peak memory 202464 kb
Host smart-ffa05d35-9216-431a-9457-336a3504faea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
97889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1232397889
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1276583561
Short name T479
Test name
Test status
Simulation time 8378382195 ps
CPU time 9.09 seconds
Started Mar 07 01:50:42 PM PST 24
Finished Mar 07 01:50:52 PM PST 24
Peak memory 202448 kb
Host smart-cdae6cd6-d000-4865-a6a7-184b89405caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12765
83561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1276583561
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.622510640
Short name T385
Test name
Test status
Simulation time 8456805765 ps
CPU time 7.67 seconds
Started Mar 07 01:50:50 PM PST 24
Finished Mar 07 01:50:58 PM PST 24
Peak memory 202448 kb
Host smart-ecb611e1-5b92-46b3-9fe9-8bafbdf489ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62251
0640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.622510640
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.2671541110
Short name T367
Test name
Test status
Simulation time 8366962689 ps
CPU time 7.62 seconds
Started Mar 07 01:50:43 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202400 kb
Host smart-b357fc16-de83-4a88-958e-eb8eb8b5721d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26715
41110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.2671541110
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2532053662
Short name T299
Test name
Test status
Simulation time 8358070199 ps
CPU time 7.21 seconds
Started Mar 07 01:50:49 PM PST 24
Finished Mar 07 01:50:56 PM PST 24
Peak memory 202480 kb
Host smart-01d4c2ea-0f3a-4147-b33a-d35de1f9e856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25320
53662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2532053662
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3073744085
Short name T142
Test name
Test status
Simulation time 8474979000 ps
CPU time 7.59 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 01:51:07 PM PST 24
Peak memory 202484 kb
Host smart-4df5f984-cc10-4880-be5a-c99106d2194d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30737
44085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3073744085
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.4020826598
Short name T259
Test name
Test status
Simulation time 8377488611 ps
CPU time 7.53 seconds
Started Mar 07 01:50:52 PM PST 24
Finished Mar 07 01:50:59 PM PST 24
Peak memory 202508 kb
Host smart-1d805e2b-6cea-40b8-88ca-df0acb0ac787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40208
26598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.4020826598
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.4032628194
Short name T183
Test name
Test status
Simulation time 70374155 ps
CPU time 1.59 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 01:51:01 PM PST 24
Peak memory 202456 kb
Host smart-bec644b8-14a0-4382-afd3-cb8cb18fdb42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40326
28194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.4032628194
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1981167924
Short name T338
Test name
Test status
Simulation time 8541849115 ps
CPU time 7.59 seconds
Started Mar 07 01:50:44 PM PST 24
Finished Mar 07 01:50:52 PM PST 24
Peak memory 202508 kb
Host smart-4241c65f-a413-4b70-a62f-a4d898e15903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19811
67924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1981167924
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2120127949
Short name T238
Test name
Test status
Simulation time 8420125074 ps
CPU time 7.52 seconds
Started Mar 07 01:50:49 PM PST 24
Finished Mar 07 01:50:57 PM PST 24
Peak memory 202464 kb
Host smart-492fed31-e480-41cc-8713-e98a9a4b2096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21201
27949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2120127949
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3032844646
Short name T381
Test name
Test status
Simulation time 8367160392 ps
CPU time 9.49 seconds
Started Mar 07 01:51:00 PM PST 24
Finished Mar 07 01:51:09 PM PST 24
Peak memory 202412 kb
Host smart-d5d75056-248b-4073-b682-0f324611b258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30328
44646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3032844646
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1002121652
Short name T403
Test name
Test status
Simulation time 8415051577 ps
CPU time 7.79 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 01:51:07 PM PST 24
Peak memory 202504 kb
Host smart-5b2f4817-605f-4546-81fc-ab019137a5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10021
21652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1002121652
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1213264775
Short name T455
Test name
Test status
Simulation time 8381530968 ps
CPU time 8.16 seconds
Started Mar 07 01:50:43 PM PST 24
Finished Mar 07 01:50:51 PM PST 24
Peak memory 202528 kb
Host smart-7a1a87f2-f1e2-4d78-8f6f-93dfaf63663d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12132
64775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1213264775
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.766415472
Short name T522
Test name
Test status
Simulation time 8372536140 ps
CPU time 9.44 seconds
Started Mar 07 01:50:45 PM PST 24
Finished Mar 07 01:50:54 PM PST 24
Peak memory 202512 kb
Host smart-04b7034d-be0b-4171-807d-15135ada8a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76641
5472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.766415472
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3917323601
Short name T549
Test name
Test status
Simulation time 8398694741 ps
CPU time 7.21 seconds
Started Mar 07 01:50:47 PM PST 24
Finished Mar 07 01:50:54 PM PST 24
Peak memory 202624 kb
Host smart-a247537c-8b82-4a2a-ae9d-efd27537a9fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39173
23601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3917323601
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.924812533
Short name T429
Test name
Test status
Simulation time 8407232071 ps
CPU time 8.36 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 01:51:08 PM PST 24
Peak memory 202464 kb
Host smart-900e92a8-dccb-4f17-8223-825112e24a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92481
2533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.924812533
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1668541896
Short name T20
Test name
Test status
Simulation time 8357024524 ps
CPU time 7.77 seconds
Started Mar 07 01:50:47 PM PST 24
Finished Mar 07 01:50:55 PM PST 24
Peak memory 202636 kb
Host smart-8ae507b5-4510-4bde-8d01-2c08ebb657ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16685
41896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1668541896
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2562560909
Short name T148
Test name
Test status
Simulation time 8555803291 ps
CPU time 7.79 seconds
Started Mar 07 01:50:47 PM PST 24
Finished Mar 07 01:50:55 PM PST 24
Peak memory 202644 kb
Host smart-951b7956-ede3-4bc5-82e3-f53d4bd0659b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25625
60909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2562560909
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4119155409
Short name T188
Test name
Test status
Simulation time 8372612589 ps
CPU time 8.92 seconds
Started Mar 07 01:50:54 PM PST 24
Finished Mar 07 01:51:03 PM PST 24
Peak memory 202536 kb
Host smart-f33b9790-d91e-4f69-975f-9074095124d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41191
55409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4119155409
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3449226415
Short name T560
Test name
Test status
Simulation time 42194393 ps
CPU time 1.05 seconds
Started Mar 07 01:50:52 PM PST 24
Finished Mar 07 01:50:54 PM PST 24
Peak memory 202464 kb
Host smart-d71f6ffd-8a3b-4ccd-81a3-2af6b4280fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34492
26415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3449226415
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2573775610
Short name T554
Test name
Test status
Simulation time 8473165111 ps
CPU time 9.38 seconds
Started Mar 07 01:51:02 PM PST 24
Finished Mar 07 01:51:12 PM PST 24
Peak memory 202460 kb
Host smart-b5286f65-5883-4c9a-b565-66222783774b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25737
75610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2573775610
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.487393385
Short name T335
Test name
Test status
Simulation time 8408786121 ps
CPU time 7.14 seconds
Started Mar 07 01:50:53 PM PST 24
Finished Mar 07 01:51:01 PM PST 24
Peak memory 202500 kb
Host smart-025d6680-4dc2-409a-947a-e594b3731cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48739
3385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.487393385
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2019053958
Short name T427
Test name
Test status
Simulation time 8367228506 ps
CPU time 7.84 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 01:51:08 PM PST 24
Peak memory 202444 kb
Host smart-62baa2c6-97dc-49c3-aff5-69831307a2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20190
53958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2019053958
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.679579674
Short name T516
Test name
Test status
Simulation time 8410848141 ps
CPU time 8.49 seconds
Started Mar 07 01:50:58 PM PST 24
Finished Mar 07 01:51:07 PM PST 24
Peak memory 202488 kb
Host smart-b5fd7097-1600-44df-84c0-ee847f3a725d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67957
9674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.679579674
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2424423912
Short name T249
Test name
Test status
Simulation time 8393197819 ps
CPU time 8.4 seconds
Started Mar 07 01:50:54 PM PST 24
Finished Mar 07 01:51:02 PM PST 24
Peak memory 202488 kb
Host smart-8f12d199-a059-41da-9c09-1b13eafb7266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24244
23912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2424423912
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2874158465
Short name T235
Test name
Test status
Simulation time 8405900780 ps
CPU time 7.26 seconds
Started Mar 07 01:51:02 PM PST 24
Finished Mar 07 01:51:10 PM PST 24
Peak memory 202404 kb
Host smart-028fda82-d7b3-4b4e-b43b-e8b69d125e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28741
58465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2874158465
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3775494771
Short name T445
Test name
Test status
Simulation time 8401546950 ps
CPU time 7.39 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 01:51:07 PM PST 24
Peak memory 202500 kb
Host smart-7670dc65-55e6-4fbc-a135-622c62c7a8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37754
94771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3775494771
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3536625980
Short name T557
Test name
Test status
Simulation time 8368380815 ps
CPU time 7.22 seconds
Started Mar 07 01:51:01 PM PST 24
Finished Mar 07 01:51:09 PM PST 24
Peak memory 202388 kb
Host smart-b2b72cf9-f977-4bdb-a6a5-f3f9c2175c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35366
25980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3536625980
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3751061414
Short name T130
Test name
Test status
Simulation time 8476597006 ps
CPU time 8.28 seconds
Started Mar 07 01:51:09 PM PST 24
Finished Mar 07 01:51:18 PM PST 24
Peak memory 202508 kb
Host smart-c7b1b0f1-062a-43f3-b4b6-61de070ded9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
61414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3751061414
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.903065400
Short name T340
Test name
Test status
Simulation time 8367971243 ps
CPU time 7.1 seconds
Started Mar 07 01:48:35 PM PST 24
Finished Mar 07 01:48:43 PM PST 24
Peak memory 202468 kb
Host smart-af1e2753-5eba-4b9a-900a-97bef71bff3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90306
5400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.903065400
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4167802266
Short name T400
Test name
Test status
Simulation time 173580866 ps
CPU time 1.87 seconds
Started Mar 07 01:48:40 PM PST 24
Finished Mar 07 01:48:42 PM PST 24
Peak memory 202356 kb
Host smart-6ba06516-9feb-451f-a50c-1eb43ac2d47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41678
02266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4167802266
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3825616933
Short name T495
Test name
Test status
Simulation time 8452169384 ps
CPU time 9.55 seconds
Started Mar 07 01:48:34 PM PST 24
Finished Mar 07 01:48:43 PM PST 24
Peak memory 202496 kb
Host smart-8ba7f86a-f275-4b93-92df-a30680af2c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
16933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3825616933
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.424187027
Short name T304
Test name
Test status
Simulation time 8435078819 ps
CPU time 9.6 seconds
Started Mar 07 01:48:35 PM PST 24
Finished Mar 07 01:48:45 PM PST 24
Peak memory 202480 kb
Host smart-6f65af93-69f6-4623-9bed-4e2446e95c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42418
7027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.424187027
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2749425876
Short name T328
Test name
Test status
Simulation time 8404406379 ps
CPU time 7.12 seconds
Started Mar 07 01:48:38 PM PST 24
Finished Mar 07 01:48:46 PM PST 24
Peak memory 202452 kb
Host smart-1eb5f0f3-383c-463e-a1e5-58c00612324b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
25876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2749425876
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3945345967
Short name T506
Test name
Test status
Simulation time 8373239444 ps
CPU time 7.43 seconds
Started Mar 07 01:48:36 PM PST 24
Finished Mar 07 01:48:43 PM PST 24
Peak memory 202496 kb
Host smart-40308c7a-35b8-423c-8b56-1cc25a6045d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
45967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3945345967
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4116419357
Short name T36
Test name
Test status
Simulation time 8430114479 ps
CPU time 8.23 seconds
Started Mar 07 01:48:40 PM PST 24
Finished Mar 07 01:48:48 PM PST 24
Peak memory 202404 kb
Host smart-3d9d7026-0d95-40c4-9e3e-32988a82cab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41164
19357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4116419357
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1464351
Short name T281
Test name
Test status
Simulation time 8400876921 ps
CPU time 7.82 seconds
Started Mar 07 01:48:39 PM PST 24
Finished Mar 07 01:48:47 PM PST 24
Peak memory 202548 kb
Host smart-401852c1-4f4a-4e15-a909-bbad6d690b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14643
51 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1464351
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.677751981
Short name T61
Test name
Test status
Simulation time 8357500769 ps
CPU time 8.91 seconds
Started Mar 07 01:48:36 PM PST 24
Finished Mar 07 01:48:45 PM PST 24
Peak memory 202448 kb
Host smart-93caecc0-68a9-4458-939e-50c0a36d0f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67775
1981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.677751981
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3989141881
Short name T588
Test name
Test status
Simulation time 8478019190 ps
CPU time 9.78 seconds
Started Mar 07 01:48:38 PM PST 24
Finished Mar 07 01:48:48 PM PST 24
Peak memory 202452 kb
Host smart-7baa4166-7521-4cd4-9c18-c1c20df72cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39891
41881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3989141881
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1413247551
Short name T598
Test name
Test status
Simulation time 8367994961 ps
CPU time 7.2 seconds
Started Mar 07 01:48:44 PM PST 24
Finished Mar 07 01:48:52 PM PST 24
Peak memory 202384 kb
Host smart-395a1118-1a68-4faf-aa30-9f6500814d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14132
47551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1413247551
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1107210438
Short name T542
Test name
Test status
Simulation time 8394428707 ps
CPU time 8.63 seconds
Started Mar 07 01:48:43 PM PST 24
Finished Mar 07 01:48:52 PM PST 24
Peak memory 202444 kb
Host smart-c2338686-11b7-4233-916f-b391230ccc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11072
10438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1107210438
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1166503585
Short name T301
Test name
Test status
Simulation time 8407422428 ps
CPU time 9.69 seconds
Started Mar 07 01:48:44 PM PST 24
Finished Mar 07 01:48:54 PM PST 24
Peak memory 202496 kb
Host smart-5bfb59a3-6c69-441c-ad07-9311e216d77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11665
03585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1166503585
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2537578798
Short name T584
Test name
Test status
Simulation time 8377102626 ps
CPU time 7.49 seconds
Started Mar 07 01:48:44 PM PST 24
Finished Mar 07 01:48:52 PM PST 24
Peak memory 202492 kb
Host smart-2b51ea9d-5040-4609-be16-a2cb63a7438d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25375
78798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2537578798
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.927358941
Short name T509
Test name
Test status
Simulation time 8382966479 ps
CPU time 7.9 seconds
Started Mar 07 01:48:42 PM PST 24
Finished Mar 07 01:48:50 PM PST 24
Peak memory 202508 kb
Host smart-17a46f33-3ecf-44d1-bcd2-a81ca0143481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92735
8941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.927358941
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.347438650
Short name T360
Test name
Test status
Simulation time 8371293482 ps
CPU time 8.36 seconds
Started Mar 07 01:48:44 PM PST 24
Finished Mar 07 01:48:53 PM PST 24
Peak memory 202460 kb
Host smart-42402248-2fd9-42b4-825e-eccdd033a845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34743
8650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.347438650
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.691748158
Short name T122
Test name
Test status
Simulation time 8423816030 ps
CPU time 7.49 seconds
Started Mar 07 01:48:44 PM PST 24
Finished Mar 07 01:48:52 PM PST 24
Peak memory 202516 kb
Host smart-f4931957-41c2-45ed-9ecf-7ca3854ddcde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69174
8158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.691748158
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.3050615498
Short name T548
Test name
Test status
Simulation time 8385832755 ps
CPU time 7.18 seconds
Started Mar 07 01:48:43 PM PST 24
Finished Mar 07 01:48:50 PM PST 24
Peak memory 202508 kb
Host smart-45ecd7e7-9045-4b0a-83c5-90e665d8fa3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30506
15498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.3050615498
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3827694900
Short name T59
Test name
Test status
Simulation time 8439472267 ps
CPU time 9.15 seconds
Started Mar 07 01:48:45 PM PST 24
Finished Mar 07 01:48:54 PM PST 24
Peak memory 202488 kb
Host smart-4b43ebe4-bdce-48e6-8c1d-3879dc640f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38276
94900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3827694900
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.631120113
Short name T317
Test name
Test status
Simulation time 8474675792 ps
CPU time 8.77 seconds
Started Mar 07 01:48:35 PM PST 24
Finished Mar 07 01:48:44 PM PST 24
Peak memory 202512 kb
Host smart-52443488-1e02-4859-9b1d-abee15cfbd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63112
0113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.631120113
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2943837903
Short name T193
Test name
Test status
Simulation time 8377251081 ps
CPU time 7.79 seconds
Started Mar 07 01:48:43 PM PST 24
Finished Mar 07 01:48:52 PM PST 24
Peak memory 202508 kb
Host smart-5164c518-fd5e-4a8e-ade1-2be07c0c9f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29438
37903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2943837903
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1891045450
Short name T408
Test name
Test status
Simulation time 72892046 ps
CPU time 1.35 seconds
Started Mar 07 01:48:54 PM PST 24
Finished Mar 07 01:48:55 PM PST 24
Peak memory 202412 kb
Host smart-2f377d7d-900d-4e6e-9ae7-46aca8c25bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18910
45450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1891045450
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3328071419
Short name T629
Test name
Test status
Simulation time 8442392642 ps
CPU time 9.58 seconds
Started Mar 07 01:48:43 PM PST 24
Finished Mar 07 01:48:53 PM PST 24
Peak memory 202580 kb
Host smart-54ce8bfd-eecd-4ce5-b34c-cfa101f8f04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33280
71419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3328071419
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3059343174
Short name T635
Test name
Test status
Simulation time 8412247974 ps
CPU time 8.3 seconds
Started Mar 07 01:48:53 PM PST 24
Finished Mar 07 01:49:02 PM PST 24
Peak memory 202396 kb
Host smart-ecad7761-27c6-4fc1-8532-1ecfa500947c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30593
43174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3059343174
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.705212220
Short name T365
Test name
Test status
Simulation time 8363371906 ps
CPU time 8.4 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:49:04 PM PST 24
Peak memory 202488 kb
Host smart-73af4c69-08b9-4b28-bdeb-40f96e52a4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70521
2220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.705212220
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1068819829
Short name T94
Test name
Test status
Simulation time 8411423348 ps
CPU time 7.77 seconds
Started Mar 07 01:48:46 PM PST 24
Finished Mar 07 01:48:54 PM PST 24
Peak memory 202512 kb
Host smart-e1272f26-0688-468d-a2d8-e1db043b584e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
19829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1068819829
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1959789818
Short name T518
Test name
Test status
Simulation time 8416185289 ps
CPU time 9.02 seconds
Started Mar 07 01:48:53 PM PST 24
Finished Mar 07 01:49:02 PM PST 24
Peak memory 202508 kb
Host smart-74df314e-7143-44dd-9ea5-836def529cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19597
89818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1959789818
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2543879813
Short name T260
Test name
Test status
Simulation time 8401125646 ps
CPU time 8.23 seconds
Started Mar 07 01:48:52 PM PST 24
Finished Mar 07 01:49:00 PM PST 24
Peak memory 202428 kb
Host smart-eeb011f6-6ca1-4145-a607-fb316637c8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
79813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2543879813
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1385626726
Short name T520
Test name
Test status
Simulation time 8417979700 ps
CPU time 7.63 seconds
Started Mar 07 01:48:43 PM PST 24
Finished Mar 07 01:48:52 PM PST 24
Peak memory 202524 kb
Host smart-61566c54-fa74-48b7-ba9e-32db4f56e60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
26726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1385626726
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2437828183
Short name T315
Test name
Test status
Simulation time 8394450929 ps
CPU time 8.05 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 202492 kb
Host smart-48966034-6d64-4769-a0cd-d839b82f9440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24378
28183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2437828183
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.549854765
Short name T443
Test name
Test status
Simulation time 8356294846 ps
CPU time 9.63 seconds
Started Mar 07 01:48:45 PM PST 24
Finished Mar 07 01:48:55 PM PST 24
Peak memory 202440 kb
Host smart-91abadf0-59db-45d7-870c-4c34d99541de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54985
4765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.549854765
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.4140677279
Short name T131
Test name
Test status
Simulation time 8473762757 ps
CPU time 7.84 seconds
Started Mar 07 01:48:44 PM PST 24
Finished Mar 07 01:48:52 PM PST 24
Peak memory 202516 kb
Host smart-da6a8a3c-f3b4-4c2f-b253-f2ca740ee821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41406
77279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.4140677279
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1673407411
Short name T637
Test name
Test status
Simulation time 8372683871 ps
CPU time 7.95 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 202480 kb
Host smart-21f5fb8d-16f5-4f55-9fa4-cedc4419e082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
07411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1673407411
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1760900822
Short name T314
Test name
Test status
Simulation time 67581463 ps
CPU time 1.77 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:48:57 PM PST 24
Peak memory 202416 kb
Host smart-d32a02cc-3f38-4f96-86e4-2331c6df30dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17609
00822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1760900822
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3716506335
Short name T3
Test name
Test status
Simulation time 8435568383 ps
CPU time 8.77 seconds
Started Mar 07 01:48:53 PM PST 24
Finished Mar 07 01:49:02 PM PST 24
Peak memory 202452 kb
Host smart-01718b0c-767f-4b0f-aaa0-137174acdddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37165
06335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3716506335
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2913600001
Short name T564
Test name
Test status
Simulation time 8409604802 ps
CPU time 7.71 seconds
Started Mar 07 01:48:52 PM PST 24
Finished Mar 07 01:49:00 PM PST 24
Peak memory 202440 kb
Host smart-78c612c4-7bb3-45da-83e4-5fc748e45295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29136
00001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2913600001
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2312232360
Short name T302
Test name
Test status
Simulation time 8361908823 ps
CPU time 7.66 seconds
Started Mar 07 01:48:54 PM PST 24
Finished Mar 07 01:49:02 PM PST 24
Peak memory 202488 kb
Host smart-2d0a0e72-bf9d-47ce-a2eb-f1a73ff9b80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23122
32360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2312232360
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.4179647825
Short name T538
Test name
Test status
Simulation time 8395904068 ps
CPU time 7.19 seconds
Started Mar 07 01:48:53 PM PST 24
Finished Mar 07 01:49:00 PM PST 24
Peak memory 202492 kb
Host smart-f0843434-9ca9-4912-b00d-42f6ccdebbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41796
47825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.4179647825
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3842701787
Short name T426
Test name
Test status
Simulation time 8375959742 ps
CPU time 8.1 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 202504 kb
Host smart-8978843c-9548-4281-89aa-286ef9662232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38427
01787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3842701787
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2565614499
Short name T21
Test name
Test status
Simulation time 8376165937 ps
CPU time 7.46 seconds
Started Mar 07 01:48:54 PM PST 24
Finished Mar 07 01:49:02 PM PST 24
Peak memory 202452 kb
Host smart-d2b1f381-8088-44ac-9797-4af65e506d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25656
14499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2565614499
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3165383838
Short name T113
Test name
Test status
Simulation time 8442433100 ps
CPU time 7.48 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 202456 kb
Host smart-6611668d-a7e5-4354-bcfa-4749fbe46b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
83838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3165383838
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2190108153
Short name T361
Test name
Test status
Simulation time 8369241773 ps
CPU time 7.79 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 202504 kb
Host smart-89c6489f-32b6-4c13-8523-945c7b95be00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21901
08153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2190108153
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.551429193
Short name T280
Test name
Test status
Simulation time 8362524461 ps
CPU time 7.68 seconds
Started Mar 07 01:48:53 PM PST 24
Finished Mar 07 01:49:01 PM PST 24
Peak memory 202464 kb
Host smart-a3cac2e4-86c0-4b66-bb21-d6f82af6458e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55142
9193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.551429193
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3093146801
Short name T145
Test name
Test status
Simulation time 8488242396 ps
CPU time 7.95 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 202516 kb
Host smart-75b26a70-135b-46a6-85ad-967381c5c4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30931
46801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3093146801
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3791207203
Short name T267
Test name
Test status
Simulation time 8369648615 ps
CPU time 7.58 seconds
Started Mar 07 01:48:57 PM PST 24
Finished Mar 07 01:49:05 PM PST 24
Peak memory 202508 kb
Host smart-a90a5e97-c423-46e1-a080-287c720bb2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37912
07203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3791207203
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1297164525
Short name T425
Test name
Test status
Simulation time 8430769630 ps
CPU time 8.58 seconds
Started Mar 07 01:49:08 PM PST 24
Finished Mar 07 01:49:16 PM PST 24
Peak memory 202460 kb
Host smart-ae531527-ec95-4a58-980c-edd5dc840fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
64525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1297164525
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1246272342
Short name T330
Test name
Test status
Simulation time 8415057696 ps
CPU time 7.99 seconds
Started Mar 07 01:49:07 PM PST 24
Finished Mar 07 01:49:15 PM PST 24
Peak memory 202484 kb
Host smart-62f16414-635a-4b1b-b8fb-e2e9c4007fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12462
72342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1246272342
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.4273752722
Short name T533
Test name
Test status
Simulation time 8376424917 ps
CPU time 7.2 seconds
Started Mar 07 01:49:08 PM PST 24
Finished Mar 07 01:49:16 PM PST 24
Peak memory 202492 kb
Host smart-551d53f2-774f-4004-8c3f-1d2731b3bf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42737
52722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4273752722
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2307336414
Short name T85
Test name
Test status
Simulation time 8417372434 ps
CPU time 7.56 seconds
Started Mar 07 01:48:55 PM PST 24
Finished Mar 07 01:49:03 PM PST 24
Peak memory 202512 kb
Host smart-870ca46d-0c95-4b12-80e0-409f4640adb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
36414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2307336414
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1874656714
Short name T611
Test name
Test status
Simulation time 8470634686 ps
CPU time 8.32 seconds
Started Mar 07 01:49:08 PM PST 24
Finished Mar 07 01:49:16 PM PST 24
Peak memory 202496 kb
Host smart-bc46214e-b289-438f-a48e-6579cb9f572a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18746
56714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1874656714
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.563536695
Short name T467
Test name
Test status
Simulation time 8411256366 ps
CPU time 7.7 seconds
Started Mar 07 01:49:07 PM PST 24
Finished Mar 07 01:49:15 PM PST 24
Peak memory 202516 kb
Host smart-3ad786bd-dc86-4215-b56e-b90c9ae8f19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56353
6695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.563536695
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2022221901
Short name T313
Test name
Test status
Simulation time 8455923683 ps
CPU time 9.52 seconds
Started Mar 07 01:48:54 PM PST 24
Finished Mar 07 01:49:04 PM PST 24
Peak memory 202448 kb
Host smart-897e23b7-fac7-4ce5-9aa4-f1b34f459c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20222
21901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2022221901
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.4137776629
Short name T398
Test name
Test status
Simulation time 8361368849 ps
CPU time 7.63 seconds
Started Mar 07 01:49:09 PM PST 24
Finished Mar 07 01:49:17 PM PST 24
Peak memory 202440 kb
Host smart-e2d43512-5b44-408b-a7b9-04b6ed9dd30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41377
76629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.4137776629
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4115630064
Short name T468
Test name
Test status
Simulation time 8361538089 ps
CPU time 9.17 seconds
Started Mar 07 01:48:54 PM PST 24
Finished Mar 07 01:49:04 PM PST 24
Peak memory 202500 kb
Host smart-359f8327-8caa-4952-92a5-163f36ff1f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156
30064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4115630064
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1090121688
Short name T184
Test name
Test status
Simulation time 8476457069 ps
CPU time 7.81 seconds
Started Mar 07 01:48:52 PM PST 24
Finished Mar 07 01:49:00 PM PST 24
Peak memory 202484 kb
Host smart-054dbf21-6e4f-44a1-a1dd-dd035ac15473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10901
21688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1090121688
Directory /workspace/9.usbdev_smoke/latest
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