Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2245	1		T1	2		T2	5		T3	2
all_values[1]	2245	1		T1	2		T2	5		T3	2
all_values[2]	2245	1		T1	2		T2	5		T3	2
all_values[3]	2245	1		T1	2		T2	5		T3	2
all_values[4]	2245	1		T1	2		T2	5		T3	2
all_values[5]	2245	1		T1	2		T2	5		T3	2
all_values[6]	2245	1		T1	2		T2	5		T3	2
all_values[7]	2245	1		T1	2		T2	5		T3	2
all_values[8]	2245	1		T1	2		T2	5		T3	2
all_values[9]	2245	1		T1	2		T2	5		T3	2
all_values[10]	2245	1		T1	2		T2	5		T3	2
all_values[11]	2245	1		T1	2		T2	5		T3	2
all_values[12]	2245	1		T1	2		T2	5		T3	2
all_values[13]	2245	1		T1	2		T2	5		T3	2
all_values[14]	2245	1		T1	2		T2	5		T3	2
all_values[15]	2245	1		T1	2		T2	5		T3	2
all_values[16]	2245	1		T1	2		T2	5		T3	2
all_values[17]	2245	1		T1	2		T2	5		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37498	1		T1	36		T2	87		T3	36
auto[1]	2912	1		T2	3		T4	3		T9	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36303	1		T1	36		T2	90		T3	36
auto[1]	4107	1		T61	127		T63	69		T62	69

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1738	1		T1	2		T2	5		T3	2
all_values[0]	auto[0]	auto[1]	102	1		T61	2		T63	4		T64	1
all_values[0]	auto[1]	auto[0]	264	1		T4	3		T11	2		T12	3
all_values[0]	auto[1]	auto[1]	141	1		T61	5		T63	1		T62	4
all_values[1]	auto[0]	auto[0]	1725	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	118	1		T61	8		T63	2		T62	4
all_values[1]	auto[1]	auto[0]	289	1		T2	3		T9	3		T21	3
all_values[1]	auto[1]	auto[1]	113	1		T63	3		T62	1		T64	6
all_values[2]	auto[0]	auto[0]	2006	1		T1	2		T2	5		T3	2
all_values[2]	auto[0]	auto[1]	110	1		T61	6		T63	3		T64	4
all_values[2]	auto[1]	auto[0]	31	1		T63	2		T67	4		T216	1
all_values[2]	auto[1]	auto[1]	98	1		T61	2		T62	4		T64	3
all_values[3]	auto[0]	auto[0]	2001	1		T1	2		T2	5		T3	2
all_values[3]	auto[0]	auto[1]	112	1		T61	3		T63	4		T62	3
all_values[3]	auto[1]	auto[0]	21	1		T61	2		T62	2		T65	2
all_values[3]	auto[1]	auto[1]	111	1		T64	6		T67	1		T65	2
all_values[4]	auto[0]	auto[0]	1994	1		T1	2		T2	5		T3	2
all_values[4]	auto[0]	auto[1]	125	1		T61	6		T63	3		T62	4
all_values[4]	auto[1]	auto[0]	11	1		T67	1		T217	1		T221	2
all_values[4]	auto[1]	auto[1]	115	1		T61	2		T63	2		T62	1
all_values[5]	auto[0]	auto[0]	1994	1		T1	2		T2	5		T3	2
all_values[5]	auto[0]	auto[1]	113	1		T61	3		T63	3		T62	4
all_values[5]	auto[1]	auto[0]	22	1		T61	1		T67	2		T216	1
all_values[5]	auto[1]	auto[1]	116	1		T61	3		T63	1		T64	2
all_values[6]	auto[0]	auto[0]	1995	1		T1	2		T2	5		T3	2
all_values[6]	auto[0]	auto[1]	134	1		T61	4		T63	2		T62	3
all_values[6]	auto[1]	auto[0]	15	1		T66	3		T216	1		T222	1
all_values[6]	auto[1]	auto[1]	101	1		T61	4		T63	3		T62	2
all_values[7]	auto[0]	auto[0]	1992	1		T1	2		T2	5		T3	2
all_values[7]	auto[0]	auto[1]	118	1		T61	7		T63	3		T62	2
all_values[7]	auto[1]	auto[0]	18	1		T222	2		T223	2		T224	4
all_values[7]	auto[1]	auto[1]	117	1		T61	1		T63	1		T62	3
all_values[8]	auto[0]	auto[0]	1997	1		T1	2		T2	5		T3	2
all_values[8]	auto[0]	auto[1]	118	1		T61	2		T62	3		T64	8
all_values[8]	auto[1]	auto[0]	24	1		T63	1		T62	1		T67	4
all_values[8]	auto[1]	auto[1]	106	1		T61	6		T63	3		T65	1
all_values[9]	auto[0]	auto[0]	1997	1		T1	2		T2	5		T3	2
all_values[9]	auto[0]	auto[1]	121	1		T61	4		T63	4		T62	4
all_values[9]	auto[1]	auto[0]	20	1		T63	1		T225	2		T222	1
all_values[9]	auto[1]	auto[1]	107	1		T61	3		T62	1		T64	6
all_values[10]	auto[0]	auto[0]	2001	1		T1	2		T2	5		T3	2
all_values[10]	auto[0]	auto[1]	120	1		T61	6		T63	4		T62	2
all_values[10]	auto[1]	auto[0]	19	1		T61	1		T66	1		T216	1
all_values[10]	auto[1]	auto[1]	105	1		T61	1		T63	1		T62	3
all_values[11]	auto[0]	auto[0]	2002	1		T1	2		T2	5		T3	2
all_values[11]	auto[0]	auto[1]	112	1		T61	4		T63	3		T62	1
all_values[11]	auto[1]	auto[0]	26	1		T61	2		T65	3		T66	3
all_values[11]	auto[1]	auto[1]	105	1		T63	1		T62	3		T64	7
all_values[12]	auto[0]	auto[0]	1989	1		T1	2		T2	5		T3	2
all_values[12]	auto[0]	auto[1]	132	1		T61	3		T63	4		T62	4
all_values[12]	auto[1]	auto[0]	17	1		T63	1		T64	1		T216	2
all_values[12]	auto[1]	auto[1]	107	1		T61	5		T62	1		T64	2
all_values[13]	auto[0]	auto[0]	1994	1		T1	2		T2	5		T3	2
all_values[13]	auto[0]	auto[1]	103	1		T61	4		T63	3		T64	2
all_values[13]	auto[1]	auto[0]	21	1		T63	1		T62	5		T67	2
all_values[13]	auto[1]	auto[1]	127	1		T61	4		T63	1		T64	6
all_values[14]	auto[0]	auto[0]	1999	1		T1	2		T2	5		T3	2
all_values[14]	auto[0]	auto[1]	96	1		T61	4		T62	4		T64	4
all_values[14]	auto[1]	auto[0]	25	1		T67	5		T226	5		T227	4
all_values[14]	auto[1]	auto[1]	125	1		T61	4		T63	3		T62	1
all_values[15]	auto[0]	auto[0]	1992	1		T1	2		T2	5		T3	2
all_values[15]	auto[0]	auto[1]	131	1		T61	5		T64	5		T67	4
all_values[15]	auto[1]	auto[0]	21	1		T63	1		T62	1		T228	1
all_values[15]	auto[1]	auto[1]	101	1		T61	3		T62	4		T64	3
all_values[16]	auto[0]	auto[0]	1997	1		T1	2		T2	5		T3	2
all_values[16]	auto[0]	auto[1]	108	1		T61	6		T63	3		T64	4
all_values[16]	auto[1]	auto[0]	30	1		T63	1		T62	1		T64	1
all_values[16]	auto[1]	auto[1]	110	1		T64	3		T65	3		T66	1
all_values[17]	auto[0]	auto[0]	1999	1		T1	2		T2	5		T3	2
all_values[17]	auto[0]	auto[1]	113	1		T61	3		T63	4		T62	3
all_values[17]	auto[1]	auto[0]	17	1		T62	1		T67	2		T217	1
all_values[17]	auto[1]	auto[1]	116	1		T61	4		T64	2		T65	3