Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2245	1		T1	2		T2	5		T3	2
all_pins[1]	2245	1		T1	2		T2	5		T3	2
all_pins[2]	2245	1		T1	2		T2	5		T3	2
all_pins[3]	2245	1		T1	2		T2	5		T3	2
all_pins[4]	2245	1		T1	2		T2	5		T3	2
all_pins[5]	2245	1		T1	2		T2	5		T3	2
all_pins[6]	2245	1		T1	2		T2	5		T3	2
all_pins[7]	2245	1		T1	2		T2	5		T3	2
all_pins[8]	2245	1		T1	2		T2	5		T3	2
all_pins[9]	2245	1		T1	2		T2	5		T3	2
all_pins[10]	2245	1		T1	2		T2	5		T3	2
all_pins[11]	2245	1		T1	2		T2	5		T3	2
all_pins[12]	2245	1		T1	2		T2	5		T3	2
all_pins[13]	2245	1		T1	2		T2	5		T3	2
all_pins[14]	2245	1		T1	2		T2	5		T3	2
all_pins[15]	2245	1		T1	2		T2	5		T3	2
all_pins[16]	2245	1		T1	2		T2	5		T3	2
all_pins[17]	2245	1		T1	2		T2	5		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	39430	1		T1	36		T2	89		T3	36
values[0x1]	980	1		T2	1		T9	1		T21	1
transitions[0x0=>0x1]	754	1		T2	1		T9	1		T21	1
transitions[0x1=>0x0]	769	1		T2	1		T9	1		T21	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2186	1		T1	2		T2	5		T3	2
all_pins[0]	values[0x1]	59	1		T61	1		T63	1		T62	1
all_pins[0]	transitions[0x0=>0x1]	46	1		T61	1		T63	1		T62	1
all_pins[0]	transitions[0x1=>0x0]	122	1		T2	1		T9	1		T21	1
all_pins[1]	values[0x0]	2110	1		T1	2		T2	4		T3	2
all_pins[1]	values[0x1]	135	1		T2	1		T9	1		T21	1
all_pins[1]	transitions[0x0=>0x1]	122	1		T2	1		T9	1		T21	1
all_pins[1]	transitions[0x1=>0x0]	44	1		T61	1		T63	1		T62	3
all_pins[2]	values[0x0]	2188	1		T1	2		T2	5		T3	2
all_pins[2]	values[0x1]	57	1		T61	1		T63	1		T62	3
all_pins[2]	transitions[0x0=>0x1]	44	1		T61	1		T63	1		T62	3
all_pins[2]	transitions[0x1=>0x0]	41	1		T64	3		T67	1		T65	1
all_pins[3]	values[0x0]	2191	1		T1	2		T2	5		T3	2
all_pins[3]	values[0x1]	54	1		T64	3		T67	1		T65	1
all_pins[3]	transitions[0x0=>0x1]	42	1		T64	3		T65	1		T225	1
all_pins[3]	transitions[0x1=>0x0]	43	1		T61	2		T63	1		T62	1
all_pins[4]	values[0x0]	2190	1		T1	2		T2	5		T3	2
all_pins[4]	values[0x1]	55	1		T61	2		T63	1		T62	1
all_pins[4]	transitions[0x0=>0x1]	43	1		T61	2		T62	1		T64	2
all_pins[4]	transitions[0x1=>0x0]	36	1		T64	2		T65	2		T66	1
all_pins[5]	values[0x0]	2197	1		T1	2		T2	5		T3	2
all_pins[5]	values[0x1]	48	1		T63	1		T64	2		T65	2
all_pins[5]	transitions[0x0=>0x1]	35	1		T63	1		T64	1		T216	2
all_pins[5]	transitions[0x1=>0x0]	34	1		T61	1		T62	1		T216	1
all_pins[6]	values[0x0]	2198	1		T1	2		T2	5		T3	2
all_pins[6]	values[0x1]	47	1		T61	1		T62	1		T64	1
all_pins[6]	transitions[0x0=>0x1]	40	1		T61	1		T62	1		T64	1
all_pins[6]	transitions[0x1=>0x0]	35	1		T61	1		T63	1		T64	3
all_pins[7]	values[0x0]	2203	1		T1	2		T2	5		T3	2
all_pins[7]	values[0x1]	42	1		T61	1		T63	1		T64	3
all_pins[7]	transitions[0x0=>0x1]	34	1		T63	1		T64	3		T67	1
all_pins[7]	transitions[0x1=>0x0]	35	1		T61	2		T63	1		T66	1
all_pins[8]	values[0x0]	2202	1		T1	2		T2	5		T3	2
all_pins[8]	values[0x1]	43	1		T61	3		T63	1		T66	2
all_pins[8]	transitions[0x0=>0x1]	33	1		T61	2		T63	1		T66	2
all_pins[8]	transitions[0x1=>0x0]	34	1		T61	2		T62	1		T64	3
all_pins[9]	values[0x0]	2201	1		T1	2		T2	5		T3	2
all_pins[9]	values[0x1]	44	1		T61	3		T62	1		T64	3
all_pins[9]	transitions[0x0=>0x1]	35	1		T61	3		T62	1		T64	3
all_pins[9]	transitions[0x1=>0x0]	36	1		T63	1		T65	2		T216	1
all_pins[10]	values[0x0]	2200	1		T1	2		T2	5		T3	2
all_pins[10]	values[0x1]	45	1		T63	1		T67	1		T65	2
all_pins[10]	transitions[0x0=>0x1]	28	1		T63	1		T67	1		T65	2
all_pins[10]	transitions[0x1=>0x0]	35	1		T63	1		T64	2		T67	3
all_pins[11]	values[0x0]	2193	1		T1	2		T2	5		T3	2
all_pins[11]	values[0x1]	52	1		T63	1		T64	2		T67	3
all_pins[11]	transitions[0x0=>0x1]	33	1		T63	1		T64	1		T67	3
all_pins[11]	transitions[0x1=>0x0]	38	1		T61	2		T67	1		T65	4
all_pins[12]	values[0x0]	2188	1		T1	2		T2	5		T3	2
all_pins[12]	values[0x1]	57	1		T61	2		T64	1		T67	1
all_pins[12]	transitions[0x0=>0x1]	46	1		T61	1		T64	1		T67	1
all_pins[12]	transitions[0x1=>0x0]	36	1		T63	1		T64	3		T65	2
all_pins[13]	values[0x0]	2198	1		T1	2		T2	5		T3	2
all_pins[13]	values[0x1]	47	1		T61	1		T63	1		T64	3
all_pins[13]	transitions[0x0=>0x1]	33	1		T63	1		T64	2		T65	2
all_pins[13]	transitions[0x1=>0x0]	44	1		T61	2		T63	2		T64	2
all_pins[14]	values[0x0]	2187	1		T1	2		T2	5		T3	2
all_pins[14]	values[0x1]	58	1		T61	3		T63	2		T64	3
all_pins[14]	transitions[0x0=>0x1]	40	1		T61	2		T63	2		T64	3
all_pins[14]	transitions[0x1=>0x0]	21	1		T62	3		T64	1		T66	1
all_pins[15]	values[0x0]	2206	1		T1	2		T2	5		T3	2
all_pins[15]	values[0x1]	39	1		T61	1		T62	3		T64	1
all_pins[15]	transitions[0x0=>0x1]	31	1		T61	1		T62	3		T64	1
all_pins[15]	transitions[0x1=>0x0]	42	1		T65	2		T66	1		T217	2
all_pins[16]	values[0x0]	2195	1		T1	2		T2	5		T3	2
all_pins[16]	values[0x1]	50	1		T65	2		T66	1		T217	2
all_pins[16]	transitions[0x0=>0x1]	43	1		T65	2		T66	1		T217	1
all_pins[16]	transitions[0x1=>0x0]	41	1		T61	1		T64	2		T65	2
all_pins[17]	values[0x0]	2197	1		T1	2		T2	5		T3	2
all_pins[17]	values[0x1]	48	1		T61	1		T64	2		T65	2
all_pins[17]	transitions[0x0=>0x1]	26	1		T61	1		T64	2		T216	2
all_pins[17]	transitions[0x1=>0x0]	52	1		T61	1		T63	1		T62	1