Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	229	1		T61	7		T63	4		T62	4
all_values[1]	229	1		T61	7		T63	4		T62	4
all_values[2]	229	1		T61	7		T63	4		T62	4
all_values[3]	229	1		T61	7		T63	4		T62	4
all_values[4]	229	1		T61	7		T63	4		T62	4
all_values[5]	229	1		T61	7		T63	4		T62	4
all_values[6]	229	1		T61	7		T63	4		T62	4
all_values[7]	229	1		T61	7		T63	4		T62	4
all_values[8]	229	1		T61	7		T63	4		T62	4
all_values[9]	229	1		T61	7		T63	4		T62	4
all_values[10]	229	1		T61	7		T63	4		T62	4
all_values[11]	229	1		T61	7		T63	4		T62	4
all_values[12]	229	1		T61	7		T63	4		T62	4
all_values[13]	229	1		T61	7		T63	4		T62	4
all_values[14]	229	1		T61	7		T63	4		T62	4
all_values[15]	229	1		T61	7		T63	4		T62	4
all_values[16]	229	1		T61	7		T63	4		T62	4
all_values[17]	229	1		T61	7		T63	4		T62	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2343	1		T61	83		T63	50		T62	43
auto[1]	1779	1		T61	43		T63	22		T62	29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	739	1		T61	17		T63	20		T62	19
auto[1]	3383	1		T61	109		T63	52		T62	53

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2422	1		T61	71		T63	46		T62	50
auto[1]	1700	1		T61	55		T63	26		T62	22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	22	1		T61	1		T62	1		T64	4
all_values[0]	auto[0]	auto[0]	auto[1]	46	1		T63	1		T67	1		T66	1
all_values[0]	auto[0]	auto[1]	auto[0]	7	1		T65	1		T229	1		T230	2
all_values[0]	auto[0]	auto[1]	auto[1]	54	1		T61	3		T62	2		T64	1
all_values[0]	auto[1]	auto[0]	auto[1]	53	1		T61	1		T63	1		T64	2
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T61	2		T63	2		T62	1
all_values[1]	auto[0]	auto[0]	auto[0]	22	1		T65	3		T227	1		T221	1
all_values[1]	auto[0]	auto[0]	auto[1]	51	1		T61	4		T63	2		T62	1
all_values[1]	auto[0]	auto[1]	auto[0]	16	1		T65	1		T231	2		T232	2
all_values[1]	auto[0]	auto[1]	auto[1]	43	1		T63	1		T62	1		T64	2
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T61	3		T63	1		T62	1
all_values[1]	auto[1]	auto[1]	auto[1]	32	1		T62	1		T64	1		T67	2
all_values[2]	auto[0]	auto[0]	auto[0]	40	1		T63	1		T62	1		T64	1
all_values[2]	auto[0]	auto[0]	auto[1]	45	1		T61	3		T63	1		T64	2
all_values[2]	auto[0]	auto[1]	auto[0]	18	1		T63	1		T67	3		T227	1
all_values[2]	auto[0]	auto[1]	auto[1]	42	1		T62	2		T64	1		T65	3
all_values[2]	auto[1]	auto[0]	auto[1]	52	1		T61	2		T64	3		T65	1
all_values[2]	auto[1]	auto[1]	auto[1]	32	1		T61	2		T63	1		T62	1
all_values[3]	auto[0]	auto[0]	auto[0]	35	1		T61	3		T63	1		T62	1
all_values[3]	auto[0]	auto[0]	auto[1]	42	1		T61	1		T63	2		T62	1
all_values[3]	auto[0]	auto[1]	auto[0]	12	1		T61	2		T62	1		T65	2
all_values[3]	auto[0]	auto[1]	auto[1]	51	1		T64	2		T67	2		T65	1
all_values[3]	auto[1]	auto[0]	auto[1]	50	1		T63	1		T64	1		T67	1
all_values[3]	auto[1]	auto[1]	auto[1]	39	1		T61	1		T62	1		T64	1
all_values[4]	auto[0]	auto[0]	auto[0]	22	1		T65	1		T216	1		T217	1
all_values[4]	auto[0]	auto[0]	auto[1]	48	1		T61	3		T63	1		T62	3
all_values[4]	auto[0]	auto[1]	auto[0]	8	1		T67	1		T221	2		T231	1
all_values[4]	auto[0]	auto[1]	auto[1]	52	1		T61	1		T63	1		T64	1
all_values[4]	auto[1]	auto[0]	auto[1]	61	1		T61	3		T63	1		T62	1
all_values[4]	auto[1]	auto[1]	auto[1]	38	1		T63	1		T64	4		T67	2
all_values[5]	auto[0]	auto[0]	auto[0]	29	1		T61	1		T63	1		T62	1
all_values[5]	auto[0]	auto[0]	auto[1]	50	1		T61	3		T63	1		T62	2
all_values[5]	auto[0]	auto[1]	auto[0]	13	1		T61	1		T67	2		T228	1
all_values[5]	auto[0]	auto[1]	auto[1]	40	1		T61	1		T67	1		T65	1
all_values[5]	auto[1]	auto[0]	auto[1]	54	1		T62	1		T64	4		T65	1
all_values[5]	auto[1]	auto[1]	auto[1]	43	1		T61	1		T63	2		T64	1
all_values[6]	auto[0]	auto[0]	auto[0]	23	1		T64	1		T216	2		T228	2
all_values[6]	auto[0]	auto[0]	auto[1]	52	1		T61	1		T63	2		T62	1
all_values[6]	auto[0]	auto[1]	auto[0]	13	1		T66	3		T222	2		T233	1
all_values[6]	auto[0]	auto[1]	auto[1]	41	1		T61	2		T63	1		T64	1
all_values[6]	auto[1]	auto[0]	auto[1]	61	1		T61	3		T63	1		T62	1
all_values[6]	auto[1]	auto[1]	auto[1]	39	1		T61	1		T62	2		T65	1
all_values[7]	auto[0]	auto[0]	auto[0]	23	1		T63	1		T64	1		T222	1
all_values[7]	auto[0]	auto[0]	auto[1]	49	1		T61	2		T63	1		T62	2
all_values[7]	auto[0]	auto[1]	auto[0]	12	1		T222	3		T223	1		T224	1
all_values[7]	auto[0]	auto[1]	auto[1]	51	1		T61	1		T62	1		T64	2
all_values[7]	auto[1]	auto[0]	auto[1]	65	1		T61	3		T62	1		T64	1
all_values[7]	auto[1]	auto[1]	auto[1]	29	1		T61	1		T63	2		T64	3
all_values[8]	auto[0]	auto[0]	auto[0]	24	1		T63	1		T62	1		T67	1
all_values[8]	auto[0]	auto[0]	auto[1]	51	1		T61	1		T62	1		T64	4
all_values[8]	auto[0]	auto[1]	auto[0]	21	1		T63	1		T62	1		T67	3
all_values[8]	auto[0]	auto[1]	auto[1]	44	1		T61	2		T63	1		T65	1
all_values[8]	auto[1]	auto[0]	auto[1]	58	1		T61	2		T64	3		T65	2
all_values[8]	auto[1]	auto[1]	auto[1]	31	1		T61	2		T63	1		T62	1
all_values[9]	auto[0]	auto[0]	auto[0]	27	1		T61	1		T63	1		T217	1
all_values[9]	auto[0]	auto[0]	auto[1]	44	1		T61	1		T63	1		T62	2
all_values[9]	auto[0]	auto[1]	auto[0]	14	1		T225	2		T222	1		T221	1
all_values[9]	auto[0]	auto[1]	auto[1]	45	1		T64	2		T65	2		T66	3
all_values[9]	auto[1]	auto[0]	auto[1]	60	1		T61	1		T63	2		T62	2
all_values[9]	auto[1]	auto[1]	auto[1]	39	1		T61	4		T64	3		T67	1
all_values[10]	auto[0]	auto[0]	auto[0]	28	1		T61	1		T64	2		T65	1
all_values[10]	auto[0]	auto[0]	auto[1]	50	1		T61	2		T63	3		T64	2
all_values[10]	auto[0]	auto[1]	auto[0]	15	1		T66	1		T225	1		T226	1
all_values[10]	auto[0]	auto[1]	auto[1]	38	1		T61	1		T62	1		T67	1
all_values[10]	auto[1]	auto[0]	auto[1]	60	1		T61	2		T63	1		T62	3
all_values[10]	auto[1]	auto[1]	auto[1]	38	1		T61	1		T67	2		T66	2
all_values[11]	auto[0]	auto[0]	auto[0]	37	1		T61	3		T63	1		T62	1
all_values[11]	auto[0]	auto[0]	auto[1]	44	1		T61	2		T63	1		T62	1
all_values[11]	auto[0]	auto[1]	auto[0]	15	1		T61	1		T65	3		T66	3
all_values[11]	auto[0]	auto[1]	auto[1]	39	1		T63	1		T62	1		T64	3
all_values[11]	auto[1]	auto[0]	auto[1]	49	1		T61	1		T62	1		T67	1
all_values[11]	auto[1]	auto[1]	auto[1]	45	1		T63	1		T64	3		T67	2
all_values[12]	auto[0]	auto[0]	auto[0]	22	1		T63	1		T65	1		T216	1
all_values[12]	auto[0]	auto[0]	auto[1]	52	1		T61	3		T63	1		T62	1
all_values[12]	auto[0]	auto[1]	auto[0]	10	1		T64	1		T216	1		T225	1
all_values[12]	auto[0]	auto[1]	auto[1]	41	1		T61	1		T62	2		T64	1
all_values[12]	auto[1]	auto[0]	auto[1]	60	1		T61	3		T63	2		T62	1
all_values[12]	auto[1]	auto[1]	auto[1]	44	1		T64	3		T67	1		T65	3
all_values[13]	auto[0]	auto[0]	auto[0]	23	1		T63	1		T62	1		T67	1
all_values[13]	auto[0]	auto[0]	auto[1]	44	1		T61	2		T63	1		T64	2
all_values[13]	auto[0]	auto[1]	auto[0]	15	1		T62	3		T67	3		T65	2
all_values[13]	auto[0]	auto[1]	auto[1]	58	1		T61	3		T64	2		T65	2
all_values[13]	auto[1]	auto[0]	auto[1]	54	1		T61	1		T64	1		T66	2
all_values[13]	auto[1]	auto[1]	auto[1]	35	1		T61	1		T63	2		T64	2
all_values[14]	auto[0]	auto[0]	auto[0]	32	1		T63	2		T64	1		T66	1
all_values[14]	auto[0]	auto[0]	auto[1]	38	1		T61	2		T62	1		T64	2
all_values[14]	auto[0]	auto[1]	auto[0]	15	1		T67	4		T226	3		T227	2
all_values[14]	auto[0]	auto[1]	auto[1]	55	1		T61	2		T63	1		T62	2
all_values[14]	auto[1]	auto[0]	auto[1]	51	1		T61	2		T63	1		T62	1
all_values[14]	auto[1]	auto[1]	auto[1]	38	1		T61	1		T64	1		T65	2
all_values[15]	auto[0]	auto[0]	auto[0]	21	1		T63	2		T62	1		T65	1
all_values[15]	auto[0]	auto[0]	auto[1]	55	1		T61	3		T64	2		T67	1
all_values[15]	auto[0]	auto[1]	auto[0]	14	1		T63	2		T217	3		T221	1
all_values[15]	auto[0]	auto[1]	auto[1]	47	1		T62	2		T64	3		T67	1
all_values[15]	auto[1]	auto[0]	auto[1]	57	1		T61	1		T67	1		T65	3
all_values[15]	auto[1]	auto[1]	auto[1]	35	1		T61	3		T62	1		T64	2
all_values[16]	auto[0]	auto[0]	auto[0]	34	1		T61	2		T63	2		T62	4
all_values[16]	auto[0]	auto[0]	auto[1]	44	1		T61	2		T63	1		T64	4
all_values[16]	auto[0]	auto[1]	auto[0]	16	1		T64	1		T67	4		T65	2
all_values[16]	auto[0]	auto[1]	auto[1]	50	1		T64	1		T65	1		T216	2
all_values[16]	auto[1]	auto[0]	auto[1]	39	1		T61	3		T63	1		T216	1
all_values[16]	auto[1]	auto[1]	auto[1]	46	1		T64	1		T65	1		T66	2
all_values[17]	auto[0]	auto[0]	auto[0]	25	1		T61	1		T63	1		T62	1
all_values[17]	auto[0]	auto[0]	auto[1]	41	1		T61	1		T63	1		T62	1
all_values[17]	auto[0]	auto[1]	auto[0]	16	1		T62	1		T67	2		T217	1
all_values[17]	auto[0]	auto[1]	auto[1]	46	1		T61	1		T65	1		T66	1
all_values[17]	auto[1]	auto[0]	auto[1]	59	1		T61	3		T63	2		T64	3
all_values[17]	auto[1]	auto[1]	auto[1]	42	1		T61	1		T62	1		T64	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal