Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.88 96.34 88.53 97.17 45.31 94.22 97.36 96.22


Total test records in report: 800
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T235 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1419210233 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:15 PM PDT 24 319957831 ps
T756 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2914897976 Mar 10 12:22:19 PM PDT 24 Mar 10 12:22:22 PM PDT 24 73831745 ps
T224 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4106750046 Mar 10 12:21:38 PM PDT 24 Mar 10 12:21:39 PM PDT 24 28848406 ps
T757 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.351700774 Mar 10 12:23:05 PM PDT 24 Mar 10 12:23:06 PM PDT 24 24336881 ps
T758 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.554748135 Mar 10 12:22:25 PM PDT 24 Mar 10 12:22:27 PM PDT 24 43384241 ps
T759 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.548868612 Mar 10 12:24:31 PM PDT 24 Mar 10 12:24:33 PM PDT 24 105300923 ps
T760 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2362349905 Mar 10 12:23:20 PM PDT 24 Mar 10 12:23:22 PM PDT 24 45210611 ps
T761 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2252832746 Mar 10 12:22:17 PM PDT 24 Mar 10 12:22:20 PM PDT 24 111676395 ps
T762 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2737518303 Mar 10 12:22:59 PM PDT 24 Mar 10 12:23:00 PM PDT 24 63626837 ps
T763 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.111941663 Mar 10 12:22:59 PM PDT 24 Mar 10 12:22:59 PM PDT 24 24440223 ps
T764 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3006628242 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:56 PM PDT 24 75848025 ps
T765 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3768359299 Mar 10 12:33:50 PM PDT 24 Mar 10 12:33:54 PM PDT 24 471938365 ps
T57 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.94480093 Mar 10 12:29:21 PM PDT 24 Mar 10 12:29:23 PM PDT 24 49539491 ps
T766 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2556430313 Mar 10 12:22:21 PM PDT 24 Mar 10 12:22:23 PM PDT 24 22473066 ps
T767 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.244652396 Mar 10 12:21:58 PM PDT 24 Mar 10 12:22:00 PM PDT 24 58250688 ps
T768 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3472959684 Mar 10 12:22:19 PM PDT 24 Mar 10 12:22:20 PM PDT 24 24257524 ps
T769 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3102929257 Mar 10 12:22:19 PM PDT 24 Mar 10 12:22:21 PM PDT 24 129801199 ps
T770 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1266628925 Mar 10 12:22:34 PM PDT 24 Mar 10 12:22:34 PM PDT 24 20473814 ps
T771 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.50480031 Mar 10 12:21:53 PM PDT 24 Mar 10 12:21:55 PM PDT 24 54316292 ps
T178 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.800848751 Mar 10 12:22:12 PM PDT 24 Mar 10 12:22:13 PM PDT 24 33866017 ps
T772 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.204645467 Mar 10 12:22:33 PM PDT 24 Mar 10 12:22:34 PM PDT 24 22663460 ps
T773 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.154916719 Mar 10 12:21:40 PM PDT 24 Mar 10 12:21:41 PM PDT 24 80863753 ps
T774 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.299510579 Mar 10 12:22:36 PM PDT 24 Mar 10 12:22:39 PM PDT 24 82590670 ps
T775 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2212006732 Mar 10 12:32:22 PM PDT 24 Mar 10 12:32:23 PM PDT 24 27608297 ps
T776 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1656089897 Mar 10 12:22:12 PM PDT 24 Mar 10 12:22:13 PM PDT 24 36601567 ps
T777 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4026323703 Mar 10 12:23:20 PM PDT 24 Mar 10 12:23:24 PM PDT 24 290277326 ps
T778 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3346439799 Mar 10 12:23:20 PM PDT 24 Mar 10 12:23:21 PM PDT 24 70662861 ps
T779 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2441018659 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:55 PM PDT 24 163654773 ps
T780 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2285379610 Mar 10 12:27:04 PM PDT 24 Mar 10 12:27:06 PM PDT 24 130043939 ps
T781 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1457288309 Mar 10 12:22:25 PM PDT 24 Mar 10 12:22:26 PM PDT 24 26464956 ps
T782 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3044906783 Mar 10 12:22:32 PM PDT 24 Mar 10 12:22:33 PM PDT 24 27358258 ps
T783 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3069974125 Mar 10 12:23:20 PM PDT 24 Mar 10 12:23:21 PM PDT 24 35069281 ps
T784 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2934603680 Mar 10 12:22:29 PM PDT 24 Mar 10 12:22:30 PM PDT 24 76937128 ps
T234 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2573694345 Mar 10 12:22:11 PM PDT 24 Mar 10 12:22:14 PM PDT 24 138074780 ps
T785 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1641415527 Mar 10 12:21:45 PM PDT 24 Mar 10 12:21:46 PM PDT 24 75178331 ps
T786 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1334621110 Mar 10 12:21:56 PM PDT 24 Mar 10 12:21:57 PM PDT 24 29690382 ps
T787 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3875461511 Mar 10 12:21:54 PM PDT 24 Mar 10 12:21:57 PM PDT 24 239829745 ps
T788 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2332513845 Mar 10 12:21:56 PM PDT 24 Mar 10 12:21:58 PM PDT 24 56283217 ps
T789 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3361801284 Mar 10 12:22:57 PM PDT 24 Mar 10 12:22:59 PM PDT 24 180904246 ps
T790 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1257441606 Mar 10 12:23:37 PM PDT 24 Mar 10 12:23:39 PM PDT 24 129656467 ps
T791 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3749882026 Mar 10 12:21:38 PM PDT 24 Mar 10 12:21:39 PM PDT 24 40346408 ps
T792 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1835608134 Mar 10 12:22:10 PM PDT 24 Mar 10 12:22:12 PM PDT 24 79724920 ps
T793 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.338368559 Mar 10 12:27:06 PM PDT 24 Mar 10 12:27:08 PM PDT 24 129330619 ps
T794 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3637588301 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:55 PM PDT 24 148986756 ps
T795 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.417031874 Mar 10 12:19:05 PM PDT 24 Mar 10 12:19:07 PM PDT 24 250564321 ps
T796 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1658746254 Mar 10 12:19:06 PM PDT 24 Mar 10 12:19:10 PM PDT 24 338196990 ps
T797 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.472078945 Mar 10 12:22:27 PM PDT 24 Mar 10 12:22:29 PM PDT 24 54843424 ps
T798 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.58074473 Mar 10 12:22:34 PM PDT 24 Mar 10 12:22:36 PM PDT 24 61954542 ps
T799 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3911606319 Mar 10 12:23:58 PM PDT 24 Mar 10 12:23:59 PM PDT 24 27804857 ps
T800 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.546731462 Mar 10 12:22:08 PM PDT 24 Mar 10 12:22:11 PM PDT 24 269419868 ps

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1964085261
Short name T9
Test name
Test status
Simulation time 8421078657 ps
CPU time 7.46 seconds
Started Mar 10 01:56:31 PM PDT 24
Finished Mar 10 01:56:38 PM PDT 24
Peak memory 202544 kb
Host smart-e7476b7b-cfdc-45d8-8354-2ff8835aab06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19640
85261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1964085261
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.187097139
Short name T33
Test name
Test status
Simulation time 133123858 ps
CPU time 1.57 seconds
Started Mar 10 01:56:24 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202488 kb
Host smart-56dcc34e-3ebb-49f3-9ae5-121ea6f7abb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18709
7139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.187097139
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.183970143
Short name T216
Test name
Test status
Simulation time 29313174 ps
CPU time 0.66 seconds
Started Mar 10 12:21:55 PM PDT 24
Finished Mar 10 12:21:56 PM PDT 24
Peak memory 202212 kb
Host smart-43b1e3d4-dd22-48d4-9808-0359ed629b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=183970143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.183970143
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2020414110
Short name T49
Test name
Test status
Simulation time 66977796 ps
CPU time 2.14 seconds
Started Mar 10 12:22:19 PM PDT 24
Finished Mar 10 12:22:22 PM PDT 24
Peak memory 213784 kb
Host smart-55913477-172f-410a-9467-66508254e94b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020414110 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.2020414110
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2900189023
Short name T14
Test name
Test status
Simulation time 8471126613 ps
CPU time 7.35 seconds
Started Mar 10 01:58:21 PM PDT 24
Finished Mar 10 01:58:30 PM PDT 24
Peak memory 202592 kb
Host smart-78945f13-64f7-401b-b96e-9f7a909f54b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29001
89023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2900189023
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3881488815
Short name T52
Test name
Test status
Simulation time 118831723 ps
CPU time 0.93 seconds
Started Mar 10 01:56:08 PM PDT 24
Finished Mar 10 01:56:09 PM PDT 24
Peak memory 217520 kb
Host smart-c936d3e6-3cc3-4c34-9c0c-7e4349bd191e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3881488815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3881488815
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1818488866
Short name T225
Test name
Test status
Simulation time 28383651 ps
CPU time 0.7 seconds
Started Mar 10 12:22:35 PM PDT 24
Finished Mar 10 12:22:35 PM PDT 24
Peak memory 201756 kb
Host smart-5519aff7-97b7-4696-88dd-5aa40db9e243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1818488866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1818488866
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.41220737
Short name T185
Test name
Test status
Simulation time 277904243 ps
CPU time 2.22 seconds
Started Mar 10 01:57:08 PM PDT 24
Finished Mar 10 01:57:10 PM PDT 24
Peak memory 202588 kb
Host smart-1f9f67a6-3bda-4d35-bcf7-c9267bd1ec9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41220
737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.41220737
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.148364852
Short name T7
Test name
Test status
Simulation time 8431466044 ps
CPU time 7.75 seconds
Started Mar 10 01:57:20 PM PDT 24
Finished Mar 10 01:57:28 PM PDT 24
Peak memory 202496 kb
Host smart-575ff981-f6c2-489f-8758-a17f529671bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14836
4852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.148364852
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1364004243
Short name T170
Test name
Test status
Simulation time 61765197 ps
CPU time 1 seconds
Started Mar 10 12:23:21 PM PDT 24
Finished Mar 10 12:23:22 PM PDT 24
Peak memory 202368 kb
Host smart-b5237968-28f4-437b-9dfc-6623ac0ab20c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364004243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1364004243
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2670312372
Short name T83
Test name
Test status
Simulation time 273710245 ps
CPU time 3 seconds
Started Mar 10 12:22:54 PM PDT 24
Finished Mar 10 12:22:57 PM PDT 24
Peak memory 202528 kb
Host smart-232e8f27-f76a-4543-8e1f-bd300cf0d818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2670312372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2670312372
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3003590804
Short name T25
Test name
Test status
Simulation time 29747117 ps
CPU time 0.66 seconds
Started Mar 10 01:58:07 PM PDT 24
Finished Mar 10 01:58:08 PM PDT 24
Peak memory 202396 kb
Host smart-f6bc5db4-3e79-4ed1-8d49-983bea64cf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30035
90804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3003590804
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1042690385
Short name T198
Test name
Test status
Simulation time 8391447107 ps
CPU time 7.32 seconds
Started Mar 10 01:57:14 PM PDT 24
Finished Mar 10 01:57:21 PM PDT 24
Peak memory 202588 kb
Host smart-571a2c38-f20f-4a81-a4e5-a9671fdd31b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10426
90385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1042690385
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2174203936
Short name T227
Test name
Test status
Simulation time 24855726 ps
CPU time 0.64 seconds
Started Mar 10 12:23:35 PM PDT 24
Finished Mar 10 12:23:36 PM PDT 24
Peak memory 201676 kb
Host smart-d02f3a7e-8f50-4b8a-9fe4-927635929d2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2174203936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2174203936
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/23.usbdev_smoke.592539561
Short name T119
Test name
Test status
Simulation time 8472926594 ps
CPU time 7.68 seconds
Started Mar 10 01:57:14 PM PDT 24
Finished Mar 10 01:57:22 PM PDT 24
Peak memory 202576 kb
Host smart-14ca5eca-d93e-42b0-97d1-ced54da0f7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59253
9561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.592539561
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_smoke.257751852
Short name T153
Test name
Test status
Simulation time 8474513527 ps
CPU time 9.49 seconds
Started Mar 10 01:56:40 PM PDT 24
Finished Mar 10 01:56:50 PM PDT 24
Peak memory 202576 kb
Host smart-0d048d14-2d0a-4a46-a956-494b897191aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25775
1852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.257751852
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2186253515
Short name T15
Test name
Test status
Simulation time 8475772280 ps
CPU time 7.19 seconds
Started Mar 10 01:56:57 PM PDT 24
Finished Mar 10 01:57:05 PM PDT 24
Peak memory 202568 kb
Host smart-a0e174cc-abf7-4232-8ebe-b857e28910c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21862
53515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2186253515
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3025426946
Short name T746
Test name
Test status
Simulation time 26761629 ps
CPU time 0.64 seconds
Started Mar 10 12:22:33 PM PDT 24
Finished Mar 10 12:22:34 PM PDT 24
Peak memory 201704 kb
Host smart-2820573d-9a67-4cf1-857a-ab0fa3542a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3025426946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3025426946
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.586622624
Short name T209
Test name
Test status
Simulation time 202500590 ps
CPU time 2.69 seconds
Started Mar 10 12:21:42 PM PDT 24
Finished Mar 10 12:21:45 PM PDT 24
Peak memory 202632 kb
Host smart-11484594-f3b3-4dd3-9713-e0e71ac2705b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=586622624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.586622624
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/13.usbdev_smoke.199271100
Short name T36
Test name
Test status
Simulation time 8475046416 ps
CPU time 7.92 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:01 PM PDT 24
Peak memory 202576 kb
Host smart-33776f92-9104-4740-9d23-40a057491054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19927
1100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.199271100
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1766598596
Short name T146
Test name
Test status
Simulation time 8478950296 ps
CPU time 7.8 seconds
Started Mar 10 01:56:37 PM PDT 24
Finished Mar 10 01:56:45 PM PDT 24
Peak memory 202576 kb
Host smart-76fd2b17-2e6b-4850-b84b-b9b0e8dfda19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17665
98596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1766598596
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1313958446
Short name T152
Test name
Test status
Simulation time 8471500403 ps
CPU time 8.84 seconds
Started Mar 10 01:56:58 PM PDT 24
Finished Mar 10 01:57:07 PM PDT 24
Peak memory 202608 kb
Host smart-32da9c54-618b-468a-b2ef-7ec014420000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13139
58446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1313958446
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_smoke.187136584
Short name T141
Test name
Test status
Simulation time 8478453224 ps
CPU time 7.73 seconds
Started Mar 10 01:57:04 PM PDT 24
Finished Mar 10 01:57:12 PM PDT 24
Peak memory 202484 kb
Host smart-02e90fbc-7f79-44a3-a715-9c8490b65712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18713
6584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.187136584
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2425347125
Short name T158
Test name
Test status
Simulation time 8477493408 ps
CPU time 9.84 seconds
Started Mar 10 01:58:13 PM PDT 24
Finished Mar 10 01:58:22 PM PDT 24
Peak memory 202592 kb
Host smart-fafb6e8d-e08e-42c1-93a0-d28d1b9d1961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24253
47125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2425347125
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2212006732
Short name T775
Test name
Test status
Simulation time 27608297 ps
CPU time 0.64 seconds
Started Mar 10 12:32:22 PM PDT 24
Finished Mar 10 12:32:23 PM PDT 24
Peak memory 201740 kb
Host smart-d95f15d6-f3dc-46a2-8f16-efaf21b9f4c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2212006732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2212006732
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2700108012
Short name T167
Test name
Test status
Simulation time 280981739 ps
CPU time 3.1 seconds
Started Mar 10 12:22:18 PM PDT 24
Finished Mar 10 12:22:22 PM PDT 24
Peak memory 202684 kb
Host smart-14c92de1-f13d-4675-b381-5722139009ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2700108012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2700108012
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.732303733
Short name T65
Test name
Test status
Simulation time 25814850 ps
CPU time 0.73 seconds
Started Mar 10 12:22:26 PM PDT 24
Finished Mar 10 12:22:27 PM PDT 24
Peak memory 201808 kb
Host smart-1d7dae93-ae23-42bc-b169-dcb9d5a460c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=732303733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.732303733
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.94480093
Short name T57
Test name
Test status
Simulation time 49539491 ps
CPU time 0.81 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:29:23 PM PDT 24
Peak memory 202228 kb
Host smart-c981204f-b08a-42e9-94bc-c43d271f4525
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94480093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.94480093
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1638070776
Short name T188
Test name
Test status
Simulation time 191522095 ps
CPU time 2.15 seconds
Started Mar 10 01:57:47 PM PDT 24
Finished Mar 10 01:57:50 PM PDT 24
Peak memory 202556 kb
Host smart-ce6b45ce-008c-4265-8143-81526475c586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16380
70776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1638070776
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2513757367
Short name T164
Test name
Test status
Simulation time 142570624 ps
CPU time 2.64 seconds
Started Mar 10 12:33:57 PM PDT 24
Finished Mar 10 12:34:00 PM PDT 24
Peak memory 202496 kb
Host smart-c5b5610b-f394-431b-9207-a5f2a2fdc9a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2513757367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2513757367
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1410779303
Short name T4
Test name
Test status
Simulation time 8359437396 ps
CPU time 7.32 seconds
Started Mar 10 01:58:23 PM PDT 24
Finished Mar 10 01:58:31 PM PDT 24
Peak memory 202556 kb
Host smart-479fa05d-9fd5-4161-ad27-87e23f02f9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14107
79303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1410779303
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.243120590
Short name T138
Test name
Test status
Simulation time 8475252894 ps
CPU time 10.17 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202580 kb
Host smart-d08e2f50-ab75-4fbc-978e-71ed63c695c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24312
0590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.243120590
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3978517902
Short name T160
Test name
Test status
Simulation time 8475736804 ps
CPU time 8.01 seconds
Started Mar 10 01:57:36 PM PDT 24
Finished Mar 10 01:57:44 PM PDT 24
Peak memory 202580 kb
Host smart-301e7e73-3729-413a-81a3-c50cae292137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39785
17902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3978517902
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3812206858
Short name T56
Test name
Test status
Simulation time 58590511 ps
CPU time 0.83 seconds
Started Mar 10 12:33:10 PM PDT 24
Finished Mar 10 12:33:11 PM PDT 24
Peak memory 202272 kb
Host smart-adcdf397-ec48-402b-8a09-edfc0993939f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812206858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3812206858
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1518420148
Short name T737
Test name
Test status
Simulation time 92720866 ps
CPU time 2.78 seconds
Started Mar 10 12:22:13 PM PDT 24
Finished Mar 10 12:22:16 PM PDT 24
Peak memory 202452 kb
Host smart-638ea98c-b7eb-4aa7-a2e5-6ea0e89e5983
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1518420148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1518420148
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/default/42.usbdev_smoke.693012418
Short name T11
Test name
Test status
Simulation time 8474766121 ps
CPU time 9.07 seconds
Started Mar 10 01:58:29 PM PDT 24
Finished Mar 10 01:58:38 PM PDT 24
Peak memory 202604 kb
Host smart-3f337e0a-bfaf-4ed9-ba97-4b4d178bfca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69301
2418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.693012418
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3584457123
Short name T30
Test name
Test status
Simulation time 25169472 ps
CPU time 0.66 seconds
Started Mar 10 01:57:48 PM PDT 24
Finished Mar 10 01:57:49 PM PDT 24
Peak memory 202512 kb
Host smart-86c41a32-d6c7-4b91-bdfc-fdb2e6ddb5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35844
57123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3584457123
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1810354914
Short name T101
Test name
Test status
Simulation time 8385061557 ps
CPU time 8.8 seconds
Started Mar 10 01:57:17 PM PDT 24
Finished Mar 10 01:57:26 PM PDT 24
Peak memory 202472 kb
Host smart-b0d8a231-6539-49fd-8a2d-8a7189b8f7c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18103
54914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1810354914
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2968522061
Short name T184
Test name
Test status
Simulation time 146973167 ps
CPU time 2.34 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:56 PM PDT 24
Peak memory 202516 kb
Host smart-87d4e075-9ff4-4d1f-b492-1a33f1ffec83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2968522061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2968522061
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3014519869
Short name T173
Test name
Test status
Simulation time 368528772 ps
CPU time 8.36 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:29:30 PM PDT 24
Peak memory 202484 kb
Host smart-b9c0112d-aa86-4ea8-8a12-d88875aaf36f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014519869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3014519869
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1337159672
Short name T106
Test name
Test status
Simulation time 8394837336 ps
CPU time 7.66 seconds
Started Mar 10 01:56:08 PM PDT 24
Finished Mar 10 01:56:16 PM PDT 24
Peak memory 202576 kb
Host smart-a9be9881-a77a-458e-a21e-7d5f8e9a8497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13371
59672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1337159672
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3219576348
Short name T27
Test name
Test status
Simulation time 8444201562 ps
CPU time 7.9 seconds
Started Mar 10 01:56:39 PM PDT 24
Finished Mar 10 01:56:48 PM PDT 24
Peak memory 202560 kb
Host smart-58f05c59-e875-4bef-b2b6-4680ea7d8227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
76348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3219576348
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2758718881
Short name T109
Test name
Test status
Simulation time 8421875809 ps
CPU time 7.33 seconds
Started Mar 10 01:56:40 PM PDT 24
Finished Mar 10 01:56:47 PM PDT 24
Peak memory 202588 kb
Host smart-3b199f09-d14f-4520-8f4a-a96b154c2afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27587
18881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2758718881
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.673192165
Short name T87
Test name
Test status
Simulation time 8432578707 ps
CPU time 8.4 seconds
Started Mar 10 01:56:46 PM PDT 24
Finished Mar 10 01:56:54 PM PDT 24
Peak memory 202556 kb
Host smart-1f51b2dd-0a8f-4f25-a074-93e5b893aff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67319
2165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.673192165
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2637760079
Short name T635
Test name
Test status
Simulation time 8397761943 ps
CPU time 7.26 seconds
Started Mar 10 01:56:51 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202496 kb
Host smart-fb0d79af-83a7-475f-af0e-410738ba764a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26377
60079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2637760079
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2916891976
Short name T96
Test name
Test status
Simulation time 8433231910 ps
CPU time 7.36 seconds
Started Mar 10 01:56:51 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202572 kb
Host smart-7795417f-3850-42dd-bf8a-0753416d04d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29168
91976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2916891976
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2311737771
Short name T95
Test name
Test status
Simulation time 8383156361 ps
CPU time 7.68 seconds
Started Mar 10 01:56:51 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202560 kb
Host smart-087abbb0-3c3e-4a70-9b9d-92663d5418a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23117
37771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2311737771
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1009343380
Short name T104
Test name
Test status
Simulation time 8416268228 ps
CPU time 7.95 seconds
Started Mar 10 01:56:58 PM PDT 24
Finished Mar 10 01:57:07 PM PDT 24
Peak memory 202564 kb
Host smart-07930e1f-633e-43ac-a800-d6c16b85d66c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
43380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1009343380
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2745210410
Short name T91
Test name
Test status
Simulation time 8406099601 ps
CPU time 8.91 seconds
Started Mar 10 01:56:09 PM PDT 24
Finished Mar 10 01:56:18 PM PDT 24
Peak memory 202568 kb
Host smart-6fd71fb7-2d78-4093-80ac-1702be1c142d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27452
10410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2745210410
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3451261565
Short name T99
Test name
Test status
Simulation time 8403425227 ps
CPU time 7.11 seconds
Started Mar 10 01:57:28 PM PDT 24
Finished Mar 10 01:57:35 PM PDT 24
Peak memory 202576 kb
Host smart-afc4ec9e-8b1d-4be8-a5ac-d66adc022999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34512
61565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3451261565
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1658746254
Short name T796
Test name
Test status
Simulation time 338196990 ps
CPU time 4.08 seconds
Started Mar 10 12:19:06 PM PDT 24
Finished Mar 10 12:19:10 PM PDT 24
Peak memory 202452 kb
Host smart-f6f19da5-2ebd-416d-a1fe-aee80d36a859
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658746254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1658746254
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3067925610
Short name T60
Test name
Test status
Simulation time 36030740 ps
CPU time 0.75 seconds
Started Mar 10 12:21:38 PM PDT 24
Finished Mar 10 12:21:39 PM PDT 24
Peak memory 202044 kb
Host smart-085e69f6-7df6-45c5-bfb1-0d61290f13d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067925610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3067925610
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3570517075
Short name T80
Test name
Test status
Simulation time 136280544 ps
CPU time 1.66 seconds
Started Mar 10 12:24:22 PM PDT 24
Finished Mar 10 12:24:24 PM PDT 24
Peak memory 213568 kb
Host smart-8f3a4356-c92f-4c30-91eb-4b200f7c2158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570517075 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.3570517075
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.816944630
Short name T177
Test name
Test status
Simulation time 46735549 ps
CPU time 0.88 seconds
Started Mar 10 12:24:06 PM PDT 24
Finished Mar 10 12:24:07 PM PDT 24
Peak memory 201076 kb
Host smart-7688384d-e4f5-4f01-876b-ddfddb7ec7f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816944630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.816944630
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3637588301
Short name T794
Test name
Test status
Simulation time 148986756 ps
CPU time 2.04 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:55 PM PDT 24
Peak memory 202524 kb
Host smart-be6cec12-33a9-42cf-8ebe-3cb8be82c297
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3637588301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3637588301
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.299510579
Short name T774
Test name
Test status
Simulation time 82590670 ps
CPU time 2.21 seconds
Started Mar 10 12:22:36 PM PDT 24
Finished Mar 10 12:22:39 PM PDT 24
Peak memory 201408 kb
Host smart-38b431ac-67b1-42f7-9e40-7c974bb0a1eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=299510579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.299510579
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2441018659
Short name T779
Test name
Test status
Simulation time 163654773 ps
CPU time 1.56 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:55 PM PDT 24
Peak memory 202408 kb
Host smart-bf467a20-4576-4636-9919-8f43cb742433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441018659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.2441018659
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3590174519
Short name T212
Test name
Test status
Simulation time 148199767 ps
CPU time 1.76 seconds
Started Mar 10 12:33:54 PM PDT 24
Finished Mar 10 12:33:56 PM PDT 24
Peak memory 202596 kb
Host smart-e2a4d3dc-8a95-4bd0-add6-3aafbc2a1ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3590174519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3590174519
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3684464551
Short name T729
Test name
Test status
Simulation time 340602950 ps
CPU time 3.77 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:30:27 PM PDT 24
Peak memory 202448 kb
Host smart-c5531c56-e5b4-4346-bdbc-9cf3fe9ae3e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684464551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3684464551
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.338368559
Short name T793
Test name
Test status
Simulation time 129330619 ps
CPU time 1.83 seconds
Started Mar 10 12:27:06 PM PDT 24
Finished Mar 10 12:27:08 PM PDT 24
Peak memory 213676 kb
Host smart-44a143bd-4eb6-4658-93cf-9933752cb452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338368559 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.338368559
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3034809867
Short name T751
Test name
Test status
Simulation time 26867538 ps
CPU time 0.75 seconds
Started Mar 10 12:29:29 PM PDT 24
Finished Mar 10 12:29:30 PM PDT 24
Peak memory 202324 kb
Host smart-769849e2-dc1a-4dd8-a00c-ee2f4d5c232e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034809867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3034809867
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.554748135
Short name T758
Test name
Test status
Simulation time 43384241 ps
CPU time 1.36 seconds
Started Mar 10 12:22:25 PM PDT 24
Finished Mar 10 12:22:27 PM PDT 24
Peak memory 202512 kb
Host smart-ce6fdc98-cf4a-46c7-abd6-71c6364c6006
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=554748135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.554748135
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.417031874
Short name T795
Test name
Test status
Simulation time 250564321 ps
CPU time 2.43 seconds
Started Mar 10 12:19:05 PM PDT 24
Finished Mar 10 12:19:07 PM PDT 24
Peak memory 202416 kb
Host smart-7cbc2a3a-1c4b-4b1b-82bf-464eb3ddbd3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=417031874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.417031874
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2285379610
Short name T780
Test name
Test status
Simulation time 130043939 ps
CPU time 1.56 seconds
Started Mar 10 12:27:04 PM PDT 24
Finished Mar 10 12:27:06 PM PDT 24
Peak memory 202428 kb
Host smart-9419883f-cc98-46d9-9a3c-dba1e6b17ad6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285379610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.2285379610
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3006628242
Short name T764
Test name
Test status
Simulation time 75848025 ps
CPU time 2.09 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:56 PM PDT 24
Peak memory 202532 kb
Host smart-e19ed445-ee98-41f3-a6cb-c5eef91cad99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3006628242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3006628242
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1257441606
Short name T790
Test name
Test status
Simulation time 129656467 ps
CPU time 2.36 seconds
Started Mar 10 12:23:37 PM PDT 24
Finished Mar 10 12:23:39 PM PDT 24
Peak memory 202508 kb
Host smart-32220cb4-5bda-4c3a-b49f-b9694696dfdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1257441606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1257441606
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2332513845
Short name T788
Test name
Test status
Simulation time 56283217 ps
CPU time 1.62 seconds
Started Mar 10 12:21:56 PM PDT 24
Finished Mar 10 12:21:58 PM PDT 24
Peak memory 210656 kb
Host smart-5108d4e4-326a-441c-8fc3-9a23539b41ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332513845 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2332513845
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1334621110
Short name T786
Test name
Test status
Simulation time 29690382 ps
CPU time 0.96 seconds
Started Mar 10 12:21:56 PM PDT 24
Finished Mar 10 12:21:57 PM PDT 24
Peak memory 202256 kb
Host smart-36ff031f-a55c-4852-ae9c-6a9d07f7c24c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334621110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1334621110
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.926928382
Short name T717
Test name
Test status
Simulation time 23456113 ps
CPU time 0.65 seconds
Started Mar 10 12:21:56 PM PDT 24
Finished Mar 10 12:21:57 PM PDT 24
Peak memory 201584 kb
Host smart-f83a7d4d-86e2-4705-8344-ba8ab374faaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=926928382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.926928382
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.50480031
Short name T771
Test name
Test status
Simulation time 54316292 ps
CPU time 1.43 seconds
Started Mar 10 12:21:53 PM PDT 24
Finished Mar 10 12:21:55 PM PDT 24
Peak memory 202536 kb
Host smart-9c331d27-b9e4-4ae4-8b92-fdf1a9021054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50480031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_cs
r_outstanding.50480031
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3068557097
Short name T211
Test name
Test status
Simulation time 329118711 ps
CPU time 3.37 seconds
Started Mar 10 12:21:51 PM PDT 24
Finished Mar 10 12:21:55 PM PDT 24
Peak memory 202588 kb
Host smart-3add0446-2aef-4a83-b7a0-f9923fd6f692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3068557097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3068557097
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.60116792
Short name T220
Test name
Test status
Simulation time 317601357 ps
CPU time 2.82 seconds
Started Mar 10 12:21:51 PM PDT 24
Finished Mar 10 12:21:55 PM PDT 24
Peak memory 202508 kb
Host smart-d1888956-79d3-44f4-8827-6b5bcd1fb18b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=60116792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.60116792
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.244652396
Short name T767
Test name
Test status
Simulation time 58250688 ps
CPU time 1.66 seconds
Started Mar 10 12:21:58 PM PDT 24
Finished Mar 10 12:22:00 PM PDT 24
Peak memory 211200 kb
Host smart-39905aee-c7fa-4cc6-8af8-fa3c87ca9fd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244652396 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.244652396
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1322806039
Short name T724
Test name
Test status
Simulation time 73216222 ps
CPU time 1.16 seconds
Started Mar 10 12:21:56 PM PDT 24
Finished Mar 10 12:21:58 PM PDT 24
Peak memory 202492 kb
Host smart-766948e5-9bae-4fe2-ae3f-9b1f564d88e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322806039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1322806039
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1741728815
Short name T84
Test name
Test status
Simulation time 124511173 ps
CPU time 1.65 seconds
Started Mar 10 12:22:08 PM PDT 24
Finished Mar 10 12:22:09 PM PDT 24
Peak memory 202584 kb
Host smart-0b3d8926-940d-4b1a-995b-b366663ef2ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741728815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.1741728815
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3875461511
Short name T787
Test name
Test status
Simulation time 239829745 ps
CPU time 2.97 seconds
Started Mar 10 12:21:54 PM PDT 24
Finished Mar 10 12:21:57 PM PDT 24
Peak memory 202572 kb
Host smart-54aa7639-7b21-4ef6-b973-eb262c18eef1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875461511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3875461511
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1521666493
Short name T219
Test name
Test status
Simulation time 293444763 ps
CPU time 3.23 seconds
Started Mar 10 12:21:56 PM PDT 24
Finished Mar 10 12:22:00 PM PDT 24
Peak memory 202404 kb
Host smart-35134d56-e7ad-4ef3-8a64-325246be56bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1521666493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1521666493
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4034281994
Short name T733
Test name
Test status
Simulation time 88067562 ps
CPU time 2.71 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:23 PM PDT 24
Peak memory 210728 kb
Host smart-7273a2f1-adae-485a-8d30-75094e013bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034281994 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.4034281994
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3542792199
Short name T742
Test name
Test status
Simulation time 41976433 ps
CPU time 0.9 seconds
Started Mar 10 12:21:56 PM PDT 24
Finished Mar 10 12:21:57 PM PDT 24
Peak memory 202304 kb
Host smart-6de67e9f-2d2d-4850-811c-480288716bf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542792199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3542792199
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.4174142568
Short name T228
Test name
Test status
Simulation time 22954411 ps
CPU time 0.6 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:21 PM PDT 24
Peak memory 201704 kb
Host smart-6f831f30-6516-449f-ba42-d7aa4a7bafa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4174142568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.4174142568
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4207319056
Short name T728
Test name
Test status
Simulation time 136644231 ps
CPU time 1.65 seconds
Started Mar 10 12:22:03 PM PDT 24
Finished Mar 10 12:22:05 PM PDT 24
Peak memory 202512 kb
Host smart-8d0fa72a-65dc-4f24-a043-641f6ebe4da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207319056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.4207319056
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2424413051
Short name T750
Test name
Test status
Simulation time 71731741 ps
CPU time 2.18 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:22 PM PDT 24
Peak memory 202568 kb
Host smart-19c7d884-6cf5-46d9-bcd8-595b5fc269e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2424413051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2424413051
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1835608134
Short name T792
Test name
Test status
Simulation time 79724920 ps
CPU time 1.3 seconds
Started Mar 10 12:22:10 PM PDT 24
Finished Mar 10 12:22:12 PM PDT 24
Peak memory 202604 kb
Host smart-92a469ab-ed42-48df-bd29-4cb03cec7386
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835608134 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.1835608134
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3703675219
Short name T741
Test name
Test status
Simulation time 47091862 ps
CPU time 0.84 seconds
Started Mar 10 12:22:02 PM PDT 24
Finished Mar 10 12:22:03 PM PDT 24
Peak memory 202232 kb
Host smart-f233193a-8a7d-4004-b654-f95db82187a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703675219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3703675219
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2777207655
Short name T730
Test name
Test status
Simulation time 148857638 ps
CPU time 1.65 seconds
Started Mar 10 12:22:10 PM PDT 24
Finished Mar 10 12:22:12 PM PDT 24
Peak memory 202520 kb
Host smart-c3ace973-9d87-4fcf-b6a8-c0f84c324c69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777207655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.2777207655
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2914897976
Short name T756
Test name
Test status
Simulation time 73831745 ps
CPU time 2.28 seconds
Started Mar 10 12:22:19 PM PDT 24
Finished Mar 10 12:22:22 PM PDT 24
Peak memory 202684 kb
Host smart-dd1a6955-f1f3-4863-ac5c-75e124923d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2914897976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2914897976
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.546731462
Short name T800
Test name
Test status
Simulation time 269419868 ps
CPU time 2.91 seconds
Started Mar 10 12:22:08 PM PDT 24
Finished Mar 10 12:22:11 PM PDT 24
Peak memory 202984 kb
Host smart-1a7e46e1-2932-4be1-9628-fafd232af599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=546731462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.546731462
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4112252057
Short name T723
Test name
Test status
Simulation time 74305691 ps
CPU time 1.21 seconds
Started Mar 10 12:22:19 PM PDT 24
Finished Mar 10 12:22:21 PM PDT 24
Peak memory 210884 kb
Host smart-6526483f-31fc-4125-bb16-4928b28c3386
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112252057 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.4112252057
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1656089897
Short name T776
Test name
Test status
Simulation time 36601567 ps
CPU time 0.79 seconds
Started Mar 10 12:22:12 PM PDT 24
Finished Mar 10 12:22:13 PM PDT 24
Peak memory 202100 kb
Host smart-1c0fc5e5-dd81-475f-bb9b-bd230160a885
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656089897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1656089897
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.637846715
Short name T230
Test name
Test status
Simulation time 22453823 ps
CPU time 0.71 seconds
Started Mar 10 12:22:10 PM PDT 24
Finished Mar 10 12:22:11 PM PDT 24
Peak memory 201728 kb
Host smart-aab3924a-3e45-4014-abd3-e9f59f9ce1c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=637846715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.637846715
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.529916345
Short name T59
Test name
Test status
Simulation time 139633088 ps
CPU time 1.5 seconds
Started Mar 10 12:22:13 PM PDT 24
Finished Mar 10 12:22:15 PM PDT 24
Peak memory 202424 kb
Host smart-e187ef4d-7674-402e-80f2-7d365e87e918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529916345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_c
sr_outstanding.529916345
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2509933878
Short name T166
Test name
Test status
Simulation time 194562414 ps
CPU time 2.47 seconds
Started Mar 10 12:22:10 PM PDT 24
Finished Mar 10 12:22:12 PM PDT 24
Peak memory 202564 kb
Host smart-5b7a83c1-037d-49a2-8f3b-3a1ffbd62e58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2509933878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2509933878
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.58074473
Short name T798
Test name
Test status
Simulation time 61954542 ps
CPU time 2.06 seconds
Started Mar 10 12:22:34 PM PDT 24
Finished Mar 10 12:22:36 PM PDT 24
Peak memory 210944 kb
Host smart-89045eaf-9397-4154-9146-2999c71418cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58074473 -assert nopostproc +UVM_TESTNAME=usbde
v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.58074473
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.800848751
Short name T178
Test name
Test status
Simulation time 33866017 ps
CPU time 0.81 seconds
Started Mar 10 12:22:12 PM PDT 24
Finished Mar 10 12:22:13 PM PDT 24
Peak memory 202088 kb
Host smart-f01401af-6568-4f14-9980-bc63d8de2c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800848751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.800848751
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3472959684
Short name T768
Test name
Test status
Simulation time 24257524 ps
CPU time 0.68 seconds
Started Mar 10 12:22:19 PM PDT 24
Finished Mar 10 12:22:20 PM PDT 24
Peak memory 201932 kb
Host smart-ce50e1c0-68d1-4663-8af8-11b9262fba62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3472959684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3472959684
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4134114000
Short name T81
Test name
Test status
Simulation time 55346403 ps
CPU time 1.44 seconds
Started Mar 10 12:22:19 PM PDT 24
Finished Mar 10 12:22:21 PM PDT 24
Peak memory 202528 kb
Host smart-947cca0e-3850-4a78-85b3-dd9978a0e4b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134114000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.4134114000
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2877106334
Short name T162
Test name
Test status
Simulation time 45768559 ps
CPU time 1.44 seconds
Started Mar 10 12:22:26 PM PDT 24
Finished Mar 10 12:22:28 PM PDT 24
Peak memory 210756 kb
Host smart-134daaca-cc65-43dc-986f-6c2689ba7fa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877106334 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2877106334
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3261691449
Short name T722
Test name
Test status
Simulation time 31926579 ps
CPU time 0.79 seconds
Started Mar 10 12:22:42 PM PDT 24
Finished Mar 10 12:22:43 PM PDT 24
Peak memory 202276 kb
Host smart-e5ec6095-4f4b-4250-9a96-8d6b9f9437a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261691449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3261691449
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.577664988
Short name T721
Test name
Test status
Simulation time 133579721 ps
CPU time 1.55 seconds
Started Mar 10 12:22:27 PM PDT 24
Finished Mar 10 12:22:28 PM PDT 24
Peak memory 202488 kb
Host smart-f2025363-b302-40a6-97b4-8ebb9e808927
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577664988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_c
sr_outstanding.577664988
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3102929257
Short name T769
Test name
Test status
Simulation time 129801199 ps
CPU time 2.03 seconds
Started Mar 10 12:22:19 PM PDT 24
Finished Mar 10 12:22:21 PM PDT 24
Peak memory 202684 kb
Host smart-40a91228-7a9a-4b07-ba4e-3eef1f76069b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3102929257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3102929257
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1274201930
Short name T51
Test name
Test status
Simulation time 86355191 ps
CPU time 2.68 seconds
Started Mar 10 12:23:05 PM PDT 24
Finished Mar 10 12:23:08 PM PDT 24
Peak memory 210840 kb
Host smart-649f8808-6599-4c2d-b875-80a7f6988409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274201930 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.1274201930
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3069974125
Short name T783
Test name
Test status
Simulation time 35069281 ps
CPU time 0.96 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:21 PM PDT 24
Peak memory 202456 kb
Host smart-1567aa88-a67f-44a9-b6af-5b14c9d23eea
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069974125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3069974125
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.958704433
Short name T221
Test name
Test status
Simulation time 20779273 ps
CPU time 0.66 seconds
Started Mar 10 12:22:18 PM PDT 24
Finished Mar 10 12:22:19 PM PDT 24
Peak memory 202148 kb
Host smart-d2a82652-3de6-4bba-8e43-e67bb9afb0e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=958704433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.958704433
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.472078945
Short name T797
Test name
Test status
Simulation time 54843424 ps
CPU time 1.54 seconds
Started Mar 10 12:22:27 PM PDT 24
Finished Mar 10 12:22:29 PM PDT 24
Peak memory 202520 kb
Host smart-f50b2488-fd7b-462f-856a-ead2baa8fe98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472078945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_c
sr_outstanding.472078945
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2543550654
Short name T731
Test name
Test status
Simulation time 54353626 ps
CPU time 1.79 seconds
Started Mar 10 12:22:24 PM PDT 24
Finished Mar 10 12:22:27 PM PDT 24
Peak memory 202548 kb
Host smart-bcde7640-ada5-4cc9-8f01-ec2a7076fb40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2543550654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2543550654
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2573694345
Short name T234
Test name
Test status
Simulation time 138074780 ps
CPU time 2.74 seconds
Started Mar 10 12:22:11 PM PDT 24
Finished Mar 10 12:22:14 PM PDT 24
Peak memory 202528 kb
Host smart-f0e5c982-071d-4697-aa35-54d82e357f91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2573694345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2573694345
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2708356616
Short name T732
Test name
Test status
Simulation time 76068050 ps
CPU time 1.1 seconds
Started Mar 10 12:23:07 PM PDT 24
Finished Mar 10 12:23:08 PM PDT 24
Peak memory 202472 kb
Host smart-45f00f40-0ed7-4cac-b337-f95e6b4403ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708356616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2708356616
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2504947582
Short name T754
Test name
Test status
Simulation time 24356592 ps
CPU time 0.64 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:21 PM PDT 24
Peak memory 201284 kb
Host smart-4fc0a6bb-0809-4d45-8eba-abc55f12f686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2504947582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2504947582
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2737518303
Short name T762
Test name
Test status
Simulation time 63626837 ps
CPU time 1.46 seconds
Started Mar 10 12:22:59 PM PDT 24
Finished Mar 10 12:23:00 PM PDT 24
Peak memory 202572 kb
Host smart-91013a4a-1501-4b46-a2ff-26bfc83e5f70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737518303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.2737518303
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2252832746
Short name T761
Test name
Test status
Simulation time 111676395 ps
CPU time 1.69 seconds
Started Mar 10 12:22:17 PM PDT 24
Finished Mar 10 12:22:20 PM PDT 24
Peak memory 202596 kb
Host smart-8ad302da-e63a-476e-8c1b-9314fd116680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252832746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2252832746
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2934603680
Short name T784
Test name
Test status
Simulation time 76937128 ps
CPU time 1.33 seconds
Started Mar 10 12:22:29 PM PDT 24
Finished Mar 10 12:22:30 PM PDT 24
Peak memory 210828 kb
Host smart-2c05a34d-4edc-4ffc-a050-db66c07b86cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934603680 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.2934603680
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.469647753
Short name T738
Test name
Test status
Simulation time 55638919 ps
CPU time 1.07 seconds
Started Mar 10 12:22:35 PM PDT 24
Finished Mar 10 12:22:36 PM PDT 24
Peak memory 202876 kb
Host smart-36b3635a-0a9f-4966-8b25-47aad49a1027
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469647753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.469647753
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.871041730
Short name T61
Test name
Test status
Simulation time 19015368 ps
CPU time 0.72 seconds
Started Mar 10 12:22:29 PM PDT 24
Finished Mar 10 12:22:30 PM PDT 24
Peak memory 201728 kb
Host smart-b8a7f3c0-f902-4f09-858b-1e04202d04ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=871041730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.871041730
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2642199957
Short name T58
Test name
Test status
Simulation time 168589784 ps
CPU time 1.69 seconds
Started Mar 10 12:22:17 PM PDT 24
Finished Mar 10 12:22:20 PM PDT 24
Peak memory 202564 kb
Host smart-4b4f12a7-ad7d-4400-ba5c-964b2f18e928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642199957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.2642199957
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4003885311
Short name T163
Test name
Test status
Simulation time 129003520 ps
CPU time 1.95 seconds
Started Mar 10 12:22:19 PM PDT 24
Finished Mar 10 12:22:22 PM PDT 24
Peak memory 202588 kb
Host smart-79f00daa-1fe8-4e9f-846a-b80774424212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4003885311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4003885311
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2929931180
Short name T175
Test name
Test status
Simulation time 69921571 ps
CPU time 1.91 seconds
Started Mar 10 12:22:56 PM PDT 24
Finished Mar 10 12:22:58 PM PDT 24
Peak memory 202360 kb
Host smart-d9e60a41-82c6-474c-bbed-9cf5a9672db7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929931180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2929931180
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.529579939
Short name T752
Test name
Test status
Simulation time 37814409 ps
CPU time 0.75 seconds
Started Mar 10 12:18:38 PM PDT 24
Finished Mar 10 12:18:39 PM PDT 24
Peak memory 202236 kb
Host smart-b92b5534-0b8a-4b47-be72-febbb8aa66fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529579939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.529579939
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4011975414
Short name T734
Test name
Test status
Simulation time 117122703 ps
CPU time 1.71 seconds
Started Mar 10 12:19:14 PM PDT 24
Finished Mar 10 12:19:16 PM PDT 24
Peak memory 210820 kb
Host smart-9f3c058b-e396-4c85-9b3b-b9f98e2e3dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011975414 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.4011975414
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2087966465
Short name T176
Test name
Test status
Simulation time 44041414 ps
CPU time 0.84 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:10 PM PDT 24
Peak memory 201388 kb
Host smart-9a13a404-e9f5-482a-8c8f-74203f1770c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087966465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2087966465
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.472647572
Short name T222
Test name
Test status
Simulation time 24512348 ps
CPU time 0.64 seconds
Started Mar 10 12:27:04 PM PDT 24
Finished Mar 10 12:27:05 PM PDT 24
Peak memory 201688 kb
Host smart-1a907105-9333-4c88-9ae6-3c0fc1572add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=472647572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.472647572
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3361801284
Short name T789
Test name
Test status
Simulation time 180904246 ps
CPU time 2.17 seconds
Started Mar 10 12:22:57 PM PDT 24
Finished Mar 10 12:22:59 PM PDT 24
Peak memory 202456 kb
Host smart-90bde0e3-da12-4b65-a397-e51af3f041de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3361801284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3361801284
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3768359299
Short name T765
Test name
Test status
Simulation time 471938365 ps
CPU time 4.16 seconds
Started Mar 10 12:33:50 PM PDT 24
Finished Mar 10 12:33:54 PM PDT 24
Peak memory 202448 kb
Host smart-695762b2-5267-4a61-9353-1d489bb65e75
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3768359299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3768359299
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3057525869
Short name T736
Test name
Test status
Simulation time 143295327 ps
CPU time 1.43 seconds
Started Mar 10 12:26:40 PM PDT 24
Finished Mar 10 12:26:41 PM PDT 24
Peak memory 202464 kb
Host smart-fee4da30-a498-4868-be39-1d3e36582c42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057525869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.3057525869
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1604067256
Short name T50
Test name
Test status
Simulation time 131973458 ps
CPU time 1.85 seconds
Started Mar 10 12:33:45 PM PDT 24
Finished Mar 10 12:33:47 PM PDT 24
Peak memory 202508 kb
Host smart-a844a485-625f-41d2-81ff-e54de7a62a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1604067256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1604067256
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.111941663
Short name T763
Test name
Test status
Simulation time 24440223 ps
CPU time 0.65 seconds
Started Mar 10 12:22:59 PM PDT 24
Finished Mar 10 12:22:59 PM PDT 24
Peak memory 201668 kb
Host smart-3afff47b-c225-4c8e-ae31-0483a237275b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=111941663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.111941663
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3388823622
Short name T62
Test name
Test status
Simulation time 22179117 ps
CPU time 0.72 seconds
Started Mar 10 12:22:26 PM PDT 24
Finished Mar 10 12:22:27 PM PDT 24
Peak memory 201744 kb
Host smart-fa662ebf-1e59-4e71-8461-9627ef3f52ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3388823622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3388823622
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1457288309
Short name T781
Test name
Test status
Simulation time 26464956 ps
CPU time 0.62 seconds
Started Mar 10 12:22:25 PM PDT 24
Finished Mar 10 12:22:26 PM PDT 24
Peak memory 201692 kb
Host smart-57454961-6824-4b9d-827e-47c512dd45e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1457288309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1457288309
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2392610091
Short name T229
Test name
Test status
Simulation time 26292933 ps
CPU time 0.71 seconds
Started Mar 10 12:22:26 PM PDT 24
Finished Mar 10 12:22:27 PM PDT 24
Peak memory 201744 kb
Host smart-e4ee9d6d-8f04-49d3-a272-94600e5a2df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2392610091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2392610091
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3710301281
Short name T719
Test name
Test status
Simulation time 17721385 ps
CPU time 0.63 seconds
Started Mar 10 12:22:24 PM PDT 24
Finished Mar 10 12:22:25 PM PDT 24
Peak memory 201464 kb
Host smart-7b5c0356-a97f-4bb7-8778-62a466006654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3710301281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3710301281
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2556430313
Short name T766
Test name
Test status
Simulation time 22473066 ps
CPU time 0.68 seconds
Started Mar 10 12:22:21 PM PDT 24
Finished Mar 10 12:22:23 PM PDT 24
Peak memory 201780 kb
Host smart-74504f88-0fff-4ef1-bd2b-e0a7bcaf7f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2556430313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2556430313
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2456639371
Short name T739
Test name
Test status
Simulation time 24656451 ps
CPU time 0.65 seconds
Started Mar 10 12:22:27 PM PDT 24
Finished Mar 10 12:22:28 PM PDT 24
Peak memory 201700 kb
Host smart-137dabd1-e02a-4cbe-b40a-ebdbafad280c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2456639371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2456639371
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.781418478
Short name T727
Test name
Test status
Simulation time 26847630 ps
CPU time 0.64 seconds
Started Mar 10 12:22:24 PM PDT 24
Finished Mar 10 12:22:25 PM PDT 24
Peak memory 201540 kb
Host smart-0941f3e2-6df5-4a5f-96e6-9bb1f0a235f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=781418478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.781418478
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2804388597
Short name T174
Test name
Test status
Simulation time 125809655 ps
CPU time 3.45 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:17 PM PDT 24
Peak memory 202224 kb
Host smart-8b794c7c-3ed9-452c-9d18-4094dc82f3eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804388597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2804388597
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2852659763
Short name T172
Test name
Test status
Simulation time 361151543 ps
CPU time 8.87 seconds
Started Mar 10 12:24:28 PM PDT 24
Finished Mar 10 12:24:37 PM PDT 24
Peak memory 202348 kb
Host smart-7c67bb00-c5de-46b1-a7d6-123270f167aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852659763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2852659763
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3717528702
Short name T215
Test name
Test status
Simulation time 132406558 ps
CPU time 1.86 seconds
Started Mar 10 12:21:00 PM PDT 24
Finished Mar 10 12:21:02 PM PDT 24
Peak memory 210752 kb
Host smart-566ed7d8-34bd-4985-8b89-a62bffd4a840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717528702 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.3717528702
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2820420325
Short name T180
Test name
Test status
Simulation time 58226380 ps
CPU time 1 seconds
Started Mar 10 12:33:06 PM PDT 24
Finished Mar 10 12:33:07 PM PDT 24
Peak memory 202316 kb
Host smart-1bd224d6-8936-4c6c-b13f-d8c10c31502a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820420325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2820420325
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3940854313
Short name T63
Test name
Test status
Simulation time 29432799 ps
CPU time 0.66 seconds
Started Mar 10 12:21:29 PM PDT 24
Finished Mar 10 12:21:30 PM PDT 24
Peak memory 201756 kb
Host smart-eb640df9-0097-4cd8-9dfc-5626a1c8a0e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3940854313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3940854313
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1933265705
Short name T179
Test name
Test status
Simulation time 86860720 ps
CPU time 1.38 seconds
Started Mar 10 12:32:50 PM PDT 24
Finished Mar 10 12:32:52 PM PDT 24
Peak memory 202584 kb
Host smart-f50a59c6-ec10-48b9-84ab-75a83f25ae38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1933265705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1933265705
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1656608579
Short name T715
Test name
Test status
Simulation time 249328232 ps
CPU time 2.49 seconds
Started Mar 10 12:20:17 PM PDT 24
Finished Mar 10 12:20:20 PM PDT 24
Peak memory 202416 kb
Host smart-5011ad85-c0b5-44f0-812d-0aa34f5a2b17
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1656608579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1656608579
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1140801457
Short name T181
Test name
Test status
Simulation time 154972223 ps
CPU time 1.66 seconds
Started Mar 10 12:21:00 PM PDT 24
Finished Mar 10 12:21:02 PM PDT 24
Peak memory 202520 kb
Host smart-892cc7c1-26e2-4d55-98b5-92a66bae22bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140801457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.1140801457
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1621832030
Short name T210
Test name
Test status
Simulation time 44332489 ps
CPU time 1.45 seconds
Started Mar 10 12:24:27 PM PDT 24
Finished Mar 10 12:24:29 PM PDT 24
Peak memory 202516 kb
Host smart-729dddc3-7e9a-4684-9d98-e0ff3b83bf30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1621832030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1621832030
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1136757399
Short name T231
Test name
Test status
Simulation time 24349417 ps
CPU time 0.69 seconds
Started Mar 10 12:22:26 PM PDT 24
Finished Mar 10 12:22:27 PM PDT 24
Peak memory 201736 kb
Host smart-e5f1a8fd-ad5b-4626-bfa7-5b94574e1f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1136757399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1136757399
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2460464259
Short name T745
Test name
Test status
Simulation time 23222909 ps
CPU time 0.72 seconds
Started Mar 10 12:22:45 PM PDT 24
Finished Mar 10 12:22:46 PM PDT 24
Peak memory 201752 kb
Host smart-8ed7d8bb-76c2-40ea-914a-c214bf12ab87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2460464259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2460464259
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.447774857
Short name T226
Test name
Test status
Simulation time 30078866 ps
CPU time 0.68 seconds
Started Mar 10 12:22:33 PM PDT 24
Finished Mar 10 12:22:34 PM PDT 24
Peak memory 201800 kb
Host smart-738146e6-b90d-4ef6-a407-ebc681d1a115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=447774857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.447774857
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2585964383
Short name T747
Test name
Test status
Simulation time 29185859 ps
CPU time 0.68 seconds
Started Mar 10 12:22:33 PM PDT 24
Finished Mar 10 12:22:34 PM PDT 24
Peak memory 201868 kb
Host smart-b42f8870-eceb-4084-91b7-7f803b10326c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2585964383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2585964383
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.177971820
Short name T749
Test name
Test status
Simulation time 24682653 ps
CPU time 0.63 seconds
Started Mar 10 12:22:50 PM PDT 24
Finished Mar 10 12:22:51 PM PDT 24
Peak memory 202212 kb
Host smart-b206054e-5dd5-4d0c-a600-7a50509f2ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=177971820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.177971820
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1266628925
Short name T770
Test name
Test status
Simulation time 20473814 ps
CPU time 0.68 seconds
Started Mar 10 12:22:34 PM PDT 24
Finished Mar 10 12:22:34 PM PDT 24
Peak memory 201868 kb
Host smart-32a63f04-520b-43c8-884f-7d1afd1d7ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1266628925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1266628925
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2052018896
Short name T223
Test name
Test status
Simulation time 27603254 ps
CPU time 0.69 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:53 PM PDT 24
Peak memory 202148 kb
Host smart-6c519c30-6ed0-4704-b94f-1d7ea4907f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2052018896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2052018896
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2296468455
Short name T217
Test name
Test status
Simulation time 29316089 ps
CPU time 0.67 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:23:18 PM PDT 24
Peak memory 201716 kb
Host smart-790ec97b-b40d-4843-90c6-d6390701b54b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2296468455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2296468455
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2485563559
Short name T169
Test name
Test status
Simulation time 329518917 ps
CPU time 3.86 seconds
Started Mar 10 12:21:46 PM PDT 24
Finished Mar 10 12:21:51 PM PDT 24
Peak memory 202456 kb
Host smart-8e953d42-b068-4b73-bef6-5a6215f65e88
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485563559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2485563559
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3049115253
Short name T718
Test name
Test status
Simulation time 377714526 ps
CPU time 9.34 seconds
Started Mar 10 12:21:41 PM PDT 24
Finished Mar 10 12:21:51 PM PDT 24
Peak memory 202512 kb
Host smart-ca242a3b-1c58-4cd8-ad88-34e88b1a809f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049115253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3049115253
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2980167415
Short name T55
Test name
Test status
Simulation time 43200408 ps
CPU time 0.82 seconds
Started Mar 10 12:19:16 PM PDT 24
Finished Mar 10 12:19:17 PM PDT 24
Peak memory 202268 kb
Host smart-bd6c19b6-15c0-4b62-84bc-d3695bc6210e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980167415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2980167415
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.752312403
Short name T165
Test name
Test status
Simulation time 149551802 ps
CPU time 1.8 seconds
Started Mar 10 12:21:38 PM PDT 24
Finished Mar 10 12:21:40 PM PDT 24
Peak memory 213516 kb
Host smart-c1db5c3b-c7a9-4b59-878a-9c14012a3166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752312403 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.752312403
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3749882026
Short name T791
Test name
Test status
Simulation time 40346408 ps
CPU time 1.01 seconds
Started Mar 10 12:21:38 PM PDT 24
Finished Mar 10 12:21:39 PM PDT 24
Peak memory 202396 kb
Host smart-dbcb0005-6557-49b8-b7c9-a704587fae23
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749882026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3749882026
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1035225515
Short name T753
Test name
Test status
Simulation time 22287582 ps
CPU time 0.6 seconds
Started Mar 10 12:24:25 PM PDT 24
Finished Mar 10 12:24:26 PM PDT 24
Peak memory 201728 kb
Host smart-1fb66ec1-fa6e-4419-9189-dd27200e867a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1035225515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1035225515
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1588261069
Short name T168
Test name
Test status
Simulation time 45160415 ps
CPU time 1.32 seconds
Started Mar 10 12:19:51 PM PDT 24
Finished Mar 10 12:19:53 PM PDT 24
Peak memory 202736 kb
Host smart-01951da9-6c85-4676-a78a-494efd307061
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1588261069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1588261069
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2978607727
Short name T716
Test name
Test status
Simulation time 88823029 ps
CPU time 2.26 seconds
Started Mar 10 12:24:07 PM PDT 24
Finished Mar 10 12:24:09 PM PDT 24
Peak memory 201484 kb
Host smart-11d9d552-66ea-41a8-a34f-eb6b5b53092d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2978607727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2978607727
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2724863770
Short name T740
Test name
Test status
Simulation time 33743668 ps
CPU time 0.94 seconds
Started Mar 10 12:23:05 PM PDT 24
Finished Mar 10 12:23:06 PM PDT 24
Peak memory 201812 kb
Host smart-87e0da31-c755-403c-9ba9-1df0d0415790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724863770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.2724863770
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3348356770
Short name T743
Test name
Test status
Simulation time 265928868 ps
CPU time 3.52 seconds
Started Mar 10 12:19:42 PM PDT 24
Finished Mar 10 12:19:45 PM PDT 24
Peak memory 202972 kb
Host smart-0301895f-6b31-4b85-beee-a29603ed518c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3348356770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3348356770
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.391432433
Short name T233
Test name
Test status
Simulation time 26975911 ps
CPU time 0.69 seconds
Started Mar 10 12:22:34 PM PDT 24
Finished Mar 10 12:22:35 PM PDT 24
Peak memory 201784 kb
Host smart-417de304-5716-415d-bfdf-a9387ade899f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=391432433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.391432433
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.204645467
Short name T772
Test name
Test status
Simulation time 22663460 ps
CPU time 0.68 seconds
Started Mar 10 12:22:33 PM PDT 24
Finished Mar 10 12:22:34 PM PDT 24
Peak memory 201772 kb
Host smart-07497919-da1e-40b3-8511-70bc5a28c3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=204645467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.204645467
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4079653490
Short name T755
Test name
Test status
Simulation time 28794662 ps
CPU time 0.68 seconds
Started Mar 10 12:22:35 PM PDT 24
Finished Mar 10 12:22:35 PM PDT 24
Peak memory 201740 kb
Host smart-219d68ef-d20d-4287-92e2-7dffc154409c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4079653490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4079653490
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1834787637
Short name T66
Test name
Test status
Simulation time 25521738 ps
CPU time 0.68 seconds
Started Mar 10 12:23:14 PM PDT 24
Finished Mar 10 12:23:16 PM PDT 24
Peak memory 201712 kb
Host smart-2282093d-6486-4f61-a37b-7421f98f9c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1834787637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1834787637
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3044906783
Short name T782
Test name
Test status
Simulation time 27358258 ps
CPU time 0.6 seconds
Started Mar 10 12:22:32 PM PDT 24
Finished Mar 10 12:22:33 PM PDT 24
Peak memory 201932 kb
Host smart-257f67a0-e32e-4296-ab65-f2196f7a304d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3044906783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3044906783
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3279868860
Short name T67
Test name
Test status
Simulation time 26694714 ps
CPU time 0.64 seconds
Started Mar 10 12:22:37 PM PDT 24
Finished Mar 10 12:22:38 PM PDT 24
Peak memory 201724 kb
Host smart-c948e002-f02e-4908-85cd-38d7cdb945e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3279868860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3279868860
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3361932901
Short name T213
Test name
Test status
Simulation time 76461688 ps
CPU time 1.32 seconds
Started Mar 10 12:21:38 PM PDT 24
Finished Mar 10 12:21:40 PM PDT 24
Peak memory 211804 kb
Host smart-f337357b-e464-4e24-84e7-47736347beb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361932901 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.3361932901
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.351700774
Short name T757
Test name
Test status
Simulation time 24336881 ps
CPU time 0.66 seconds
Started Mar 10 12:23:05 PM PDT 24
Finished Mar 10 12:23:06 PM PDT 24
Peak memory 200784 kb
Host smart-fd6e54ca-148b-45d1-b3e5-1dda4c62ea65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=351700774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.351700774
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3007571454
Short name T735
Test name
Test status
Simulation time 63394296 ps
CPU time 1.49 seconds
Started Mar 10 12:21:38 PM PDT 24
Finished Mar 10 12:21:40 PM PDT 24
Peak memory 202388 kb
Host smart-d402a7c0-9beb-4401-9b77-8e5e2c0b8fb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007571454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.3007571454
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4026323703
Short name T777
Test name
Test status
Simulation time 290277326 ps
CPU time 3 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:24 PM PDT 24
Peak memory 202488 kb
Host smart-54727936-67ab-4018-a26c-45a0b5b1341d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4026323703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4026323703
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.176229576
Short name T744
Test name
Test status
Simulation time 76753462 ps
CPU time 2.49 seconds
Started Mar 10 12:23:03 PM PDT 24
Finished Mar 10 12:23:07 PM PDT 24
Peak memory 218036 kb
Host smart-d67a9efe-9776-44af-8e49-bc9424a1a5c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176229576 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.176229576
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1374281228
Short name T725
Test name
Test status
Simulation time 29431283 ps
CPU time 0.83 seconds
Started Mar 10 12:21:41 PM PDT 24
Finished Mar 10 12:21:42 PM PDT 24
Peak memory 202276 kb
Host smart-8a95a2a9-6e0f-490f-adf4-21e6aabcbbab
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374281228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1374281228
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.4106750046
Short name T224
Test name
Test status
Simulation time 28848406 ps
CPU time 0.6 seconds
Started Mar 10 12:21:38 PM PDT 24
Finished Mar 10 12:21:39 PM PDT 24
Peak memory 201920 kb
Host smart-4a3ed4e7-333b-4643-b9d1-6aa75f1352e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4106750046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.4106750046
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4220680389
Short name T182
Test name
Test status
Simulation time 40349726 ps
CPU time 0.98 seconds
Started Mar 10 12:21:41 PM PDT 24
Finished Mar 10 12:21:43 PM PDT 24
Peak memory 202560 kb
Host smart-e2c7c375-a62b-435d-bc8f-4de54eaeb13c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220680389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.4220680389
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2362349905
Short name T760
Test name
Test status
Simulation time 45210611 ps
CPU time 1.44 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:22 PM PDT 24
Peak memory 201764 kb
Host smart-db67b867-0e8b-4669-a455-1cef27a70fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2362349905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2362349905
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1641415527
Short name T785
Test name
Test status
Simulation time 75178331 ps
CPU time 1.15 seconds
Started Mar 10 12:21:45 PM PDT 24
Finished Mar 10 12:21:46 PM PDT 24
Peak memory 202604 kb
Host smart-be459ca3-cc5b-4e27-bbda-402eddda2e4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641415527 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1641415527
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.154916719
Short name T773
Test name
Test status
Simulation time 80863753 ps
CPU time 1.03 seconds
Started Mar 10 12:21:40 PM PDT 24
Finished Mar 10 12:21:41 PM PDT 24
Peak memory 202668 kb
Host smart-05a13787-1efb-437b-961b-3fb663de637a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154916719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.154916719
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.571597216
Short name T64
Test name
Test status
Simulation time 31919700 ps
CPU time 0.64 seconds
Started Mar 10 12:21:40 PM PDT 24
Finished Mar 10 12:21:40 PM PDT 24
Peak memory 201940 kb
Host smart-ddf7417b-6471-4c12-ac81-5f10155dae4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=571597216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.571597216
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1159519702
Short name T171
Test name
Test status
Simulation time 73265890 ps
CPU time 1.04 seconds
Started Mar 10 12:21:44 PM PDT 24
Finished Mar 10 12:21:45 PM PDT 24
Peak memory 202512 kb
Host smart-710b39d6-0d49-400c-b326-ef162dbddbbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159519702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.1159519702
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.630868739
Short name T161
Test name
Test status
Simulation time 235413778 ps
CPU time 2.69 seconds
Started Mar 10 12:21:40 PM PDT 24
Finished Mar 10 12:21:43 PM PDT 24
Peak memory 202604 kb
Host smart-17b4b81b-33b6-4bca-a52c-2334526547f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=630868739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.630868739
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1419210233
Short name T235
Test name
Test status
Simulation time 319957831 ps
CPU time 4.37 seconds
Started Mar 10 12:24:11 PM PDT 24
Finished Mar 10 12:24:15 PM PDT 24
Peak memory 202416 kb
Host smart-18d47f18-a9a5-40a6-97d2-b6ca559ca2b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1419210233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1419210233
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1621254488
Short name T82
Test name
Test status
Simulation time 45268305 ps
CPU time 1.33 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:22 PM PDT 24
Peak memory 210184 kb
Host smart-5bf0bf1e-e4ac-4138-af65-39e8503b394e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621254488 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.1621254488
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3562880153
Short name T720
Test name
Test status
Simulation time 39056807 ps
CPU time 0.79 seconds
Started Mar 10 12:21:42 PM PDT 24
Finished Mar 10 12:21:43 PM PDT 24
Peak memory 202276 kb
Host smart-44dda13b-f8d1-47db-9666-f3f747a604dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562880153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3562880153
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2266981507
Short name T232
Test name
Test status
Simulation time 22735030 ps
CPU time 0.67 seconds
Started Mar 10 12:23:54 PM PDT 24
Finished Mar 10 12:23:56 PM PDT 24
Peak memory 200900 kb
Host smart-91002e0a-e3ad-4308-b706-c73c1e68546d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2266981507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2266981507
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.561899967
Short name T748
Test name
Test status
Simulation time 123886143 ps
CPU time 1.54 seconds
Started Mar 10 12:24:09 PM PDT 24
Finished Mar 10 12:24:11 PM PDT 24
Peak memory 202468 kb
Host smart-32fbaf5b-2bfc-44d8-af2e-71a897950465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561899967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_cs
r_outstanding.561899967
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3420811142
Short name T214
Test name
Test status
Simulation time 56331112 ps
CPU time 1.63 seconds
Started Mar 10 12:23:55 PM PDT 24
Finished Mar 10 12:23:57 PM PDT 24
Peak memory 202296 kb
Host smart-ebedfe23-4e4b-4620-a581-a08ab4b4d692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3420811142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3420811142
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.548868612
Short name T759
Test name
Test status
Simulation time 105300923 ps
CPU time 1.53 seconds
Started Mar 10 12:24:31 PM PDT 24
Finished Mar 10 12:24:33 PM PDT 24
Peak memory 213260 kb
Host smart-cda81b5c-d03a-49cf-b02e-9fba8a8fdd69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548868612 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.548868612
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3346439799
Short name T778
Test name
Test status
Simulation time 70662861 ps
CPU time 0.99 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:21 PM PDT 24
Peak memory 202476 kb
Host smart-b5f955e2-7e1f-4736-a4cd-ce01e89cead5
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346439799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3346439799
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3911606319
Short name T799
Test name
Test status
Simulation time 27804857 ps
CPU time 0.64 seconds
Started Mar 10 12:23:58 PM PDT 24
Finished Mar 10 12:23:59 PM PDT 24
Peak memory 201672 kb
Host smart-2da3f9b4-54c9-4a53-9697-a5bc2b2f9542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3911606319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3911606319
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4039344675
Short name T726
Test name
Test status
Simulation time 87155667 ps
CPU time 1.08 seconds
Started Mar 10 12:21:52 PM PDT 24
Finished Mar 10 12:21:54 PM PDT 24
Peak memory 202540 kb
Host smart-aa7972e1-6e8b-4b2b-af2a-5283cd9bc398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039344675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.4039344675
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3266372814
Short name T218
Test name
Test status
Simulation time 268108092 ps
CPU time 2.93 seconds
Started Mar 10 12:23:20 PM PDT 24
Finished Mar 10 12:23:23 PM PDT 24
Peak memory 202472 kb
Host smart-ce4f83d5-f93e-4a57-bbe6-af9a780e4af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3266372814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3266372814
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2755620301
Short name T299
Test name
Test status
Simulation time 8370694914 ps
CPU time 9.46 seconds
Started Mar 10 01:56:04 PM PDT 24
Finished Mar 10 01:56:14 PM PDT 24
Peak memory 202520 kb
Host smart-828a6055-0ae1-4bb7-8b92-7efe1caf0418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27556
20301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2755620301
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.587774495
Short name T191
Test name
Test status
Simulation time 78181770 ps
CPU time 2.11 seconds
Started Mar 10 01:56:03 PM PDT 24
Finished Mar 10 01:56:05 PM PDT 24
Peak memory 202548 kb
Host smart-42b0ca45-047f-4083-a864-a9f28983c6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58777
4495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.587774495
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2678318115
Short name T432
Test name
Test status
Simulation time 8406581462 ps
CPU time 8.21 seconds
Started Mar 10 01:56:06 PM PDT 24
Finished Mar 10 01:56:14 PM PDT 24
Peak memory 202532 kb
Host smart-d440dec5-e8b5-45df-8905-5a17115ab4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26783
18115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2678318115
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1105647611
Short name T642
Test name
Test status
Simulation time 8410806593 ps
CPU time 9.3 seconds
Started Mar 10 01:56:05 PM PDT 24
Finished Mar 10 01:56:15 PM PDT 24
Peak memory 202480 kb
Host smart-bcf408df-bfe8-4997-ac33-441cf5b1d22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11056
47611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1105647611
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3741894776
Short name T545
Test name
Test status
Simulation time 8368979330 ps
CPU time 8.63 seconds
Started Mar 10 01:56:08 PM PDT 24
Finished Mar 10 01:56:16 PM PDT 24
Peak memory 202604 kb
Host smart-c3ea3f35-35cc-418d-ba23-f237b4780020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37418
94776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3741894776
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.4034273585
Short name T18
Test name
Test status
Simulation time 8371018394 ps
CPU time 9.69 seconds
Started Mar 10 01:56:08 PM PDT 24
Finished Mar 10 01:56:18 PM PDT 24
Peak memory 202576 kb
Host smart-bf44de6d-dc88-4bc5-81bf-af782cae259b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40342
73585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.4034273585
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1107738787
Short name T443
Test name
Test status
Simulation time 8400606297 ps
CPU time 7.9 seconds
Started Mar 10 01:56:04 PM PDT 24
Finished Mar 10 01:56:12 PM PDT 24
Peak memory 202576 kb
Host smart-1237b18c-e70b-42ed-ab60-590b18090a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11077
38787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1107738787
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3269802694
Short name T362
Test name
Test status
Simulation time 24157759 ps
CPU time 0.64 seconds
Started Mar 10 01:56:04 PM PDT 24
Finished Mar 10 01:56:05 PM PDT 24
Peak memory 202520 kb
Host smart-495b5f47-947a-44bb-94c6-d8bf89902b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32698
02694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3269802694
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2415202981
Short name T136
Test name
Test status
Simulation time 8385308736 ps
CPU time 7.12 seconds
Started Mar 10 01:56:06 PM PDT 24
Finished Mar 10 01:56:13 PM PDT 24
Peak memory 202532 kb
Host smart-f4333c65-84eb-41b8-bbbb-25ba1fdbabdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24152
02981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2415202981
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3080793154
Short name T349
Test name
Test status
Simulation time 8389960462 ps
CPU time 7.26 seconds
Started Mar 10 01:56:06 PM PDT 24
Finished Mar 10 01:56:13 PM PDT 24
Peak memory 202524 kb
Host smart-090a9771-ddbd-4c60-833d-0de422421ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30807
93154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3080793154
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.824077813
Short name T610
Test name
Test status
Simulation time 8357695917 ps
CPU time 8.44 seconds
Started Mar 10 01:56:03 PM PDT 24
Finished Mar 10 01:56:12 PM PDT 24
Peak memory 202564 kb
Host smart-bb44be63-7b22-4248-ac2d-9014e4d92b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82407
7813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.824077813
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1014762018
Short name T484
Test name
Test status
Simulation time 8476646349 ps
CPU time 9.17 seconds
Started Mar 10 01:56:03 PM PDT 24
Finished Mar 10 01:56:13 PM PDT 24
Peak memory 202624 kb
Host smart-1de01bab-2ede-4f2d-9303-203643556839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10147
62018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1014762018
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.4277389478
Short name T406
Test name
Test status
Simulation time 8371278325 ps
CPU time 7.37 seconds
Started Mar 10 01:56:09 PM PDT 24
Finished Mar 10 01:56:16 PM PDT 24
Peak memory 202508 kb
Host smart-89d41230-9eae-4714-87e9-0a19bf711305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42773
89478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.4277389478
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1795849510
Short name T48
Test name
Test status
Simulation time 164135549 ps
CPU time 1.89 seconds
Started Mar 10 01:56:12 PM PDT 24
Finished Mar 10 01:56:14 PM PDT 24
Peak memory 202556 kb
Host smart-b95822b0-93bb-4456-a98e-67357b71fd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17958
49510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1795849510
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.32312894
Short name T117
Test name
Test status
Simulation time 8458242171 ps
CPU time 7.53 seconds
Started Mar 10 01:56:07 PM PDT 24
Finished Mar 10 01:56:15 PM PDT 24
Peak memory 202576 kb
Host smart-8bad1dca-e3a5-4c7d-9664-f81d320ce30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32312
894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.32312894
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2005642874
Short name T414
Test name
Test status
Simulation time 8404990105 ps
CPU time 7.62 seconds
Started Mar 10 01:56:11 PM PDT 24
Finished Mar 10 01:56:20 PM PDT 24
Peak memory 202560 kb
Host smart-d6453135-50d7-452c-af18-3d33fde1ab34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20056
42874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2005642874
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.674924275
Short name T650
Test name
Test status
Simulation time 8360209847 ps
CPU time 7.32 seconds
Started Mar 10 01:56:08 PM PDT 24
Finished Mar 10 01:56:15 PM PDT 24
Peak memory 202560 kb
Host smart-120cd630-e23c-4623-9605-56ad177459e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67492
4275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.674924275
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.918157831
Short name T102
Test name
Test status
Simulation time 8418526431 ps
CPU time 7.84 seconds
Started Mar 10 01:56:12 PM PDT 24
Finished Mar 10 01:56:21 PM PDT 24
Peak memory 202540 kb
Host smart-fb890915-d262-4a3a-b531-20d4c6aa5ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91815
7831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.918157831
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3895602711
Short name T199
Test name
Test status
Simulation time 8398788779 ps
CPU time 7.33 seconds
Started Mar 10 01:56:11 PM PDT 24
Finished Mar 10 01:56:19 PM PDT 24
Peak memory 202456 kb
Host smart-9eb9a3ab-ce43-4088-89e6-a691ebecdbf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38956
02711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3895602711
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3595929613
Short name T337
Test name
Test status
Simulation time 8366023697 ps
CPU time 8.55 seconds
Started Mar 10 01:56:08 PM PDT 24
Finished Mar 10 01:56:16 PM PDT 24
Peak memory 202484 kb
Host smart-b13c0c49-e093-4f96-a800-fe426f6df701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35959
29613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3595929613
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3418580894
Short name T646
Test name
Test status
Simulation time 27454524 ps
CPU time 0.6 seconds
Started Mar 10 01:56:09 PM PDT 24
Finished Mar 10 01:56:10 PM PDT 24
Peak memory 202536 kb
Host smart-75caeb74-5fb0-4279-a99b-4db545f3c4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34185
80894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3418580894
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.210287739
Short name T501
Test name
Test status
Simulation time 8405316112 ps
CPU time 8.16 seconds
Started Mar 10 01:56:07 PM PDT 24
Finished Mar 10 01:56:15 PM PDT 24
Peak memory 202548 kb
Host smart-6f623498-4b85-48d3-baf6-90019d592489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21028
7739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.210287739
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1013991256
Short name T267
Test name
Test status
Simulation time 8373033357 ps
CPU time 7.83 seconds
Started Mar 10 01:56:11 PM PDT 24
Finished Mar 10 01:56:20 PM PDT 24
Peak memory 202480 kb
Host smart-d13d8f5f-4b88-43b6-b798-a74060406f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139
91256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1013991256
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3187739912
Short name T68
Test name
Test status
Simulation time 91307730 ps
CPU time 0.87 seconds
Started Mar 10 01:56:07 PM PDT 24
Finished Mar 10 01:56:08 PM PDT 24
Peak memory 217444 kb
Host smart-cad6450a-859e-45d6-89d0-ec130386ac02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3187739912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3187739912
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3316238013
Short name T419
Test name
Test status
Simulation time 8359523522 ps
CPU time 7.02 seconds
Started Mar 10 01:56:10 PM PDT 24
Finished Mar 10 01:56:17 PM PDT 24
Peak memory 202540 kb
Host smart-afb2bc63-a6a4-4cac-bc84-e890bc828c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33162
38013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3316238013
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2138273228
Short name T711
Test name
Test status
Simulation time 8471881228 ps
CPU time 7.62 seconds
Started Mar 10 01:56:10 PM PDT 24
Finished Mar 10 01:56:18 PM PDT 24
Peak memory 202580 kb
Host smart-cc408ba7-1093-4906-ab63-744f8c4d7689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21382
73228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2138273228
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3087835385
Short name T376
Test name
Test status
Simulation time 8367415464 ps
CPU time 7.43 seconds
Started Mar 10 01:56:36 PM PDT 24
Finished Mar 10 01:56:43 PM PDT 24
Peak memory 202496 kb
Host smart-74711b4c-738e-42b2-b040-b92dd19d2d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30878
35385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3087835385
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2058662256
Short name T577
Test name
Test status
Simulation time 167636698 ps
CPU time 1.57 seconds
Started Mar 10 01:56:33 PM PDT 24
Finished Mar 10 01:56:35 PM PDT 24
Peak memory 202576 kb
Host smart-9a83a903-97ee-4eec-818c-47d49aacf860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20586
62256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2058662256
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2094963321
Short name T591
Test name
Test status
Simulation time 8407681815 ps
CPU time 8.03 seconds
Started Mar 10 01:56:34 PM PDT 24
Finished Mar 10 01:56:42 PM PDT 24
Peak memory 202572 kb
Host smart-08c66a5e-7e7b-4c41-9615-809dcc9d9cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20949
63321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2094963321
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1244872856
Short name T630
Test name
Test status
Simulation time 8403810593 ps
CPU time 8.77 seconds
Started Mar 10 01:56:33 PM PDT 24
Finished Mar 10 01:56:42 PM PDT 24
Peak memory 202580 kb
Host smart-65a66aee-5e17-48df-a775-8b42390d351c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448
72856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1244872856
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1952319569
Short name T380
Test name
Test status
Simulation time 8366642303 ps
CPU time 7.8 seconds
Started Mar 10 01:56:39 PM PDT 24
Finished Mar 10 01:56:48 PM PDT 24
Peak memory 202576 kb
Host smart-c3ac42dd-4580-4220-830f-a61f26d58c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19523
19569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1952319569
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1697635391
Short name T353
Test name
Test status
Simulation time 8395164038 ps
CPU time 7.36 seconds
Started Mar 10 01:56:38 PM PDT 24
Finished Mar 10 01:56:46 PM PDT 24
Peak memory 202552 kb
Host smart-8d9cec27-3eb1-41eb-ac99-7a5624cbd5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16976
35391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1697635391
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1569500537
Short name T73
Test name
Test status
Simulation time 8387952577 ps
CPU time 7.76 seconds
Started Mar 10 01:56:37 PM PDT 24
Finished Mar 10 01:56:45 PM PDT 24
Peak memory 202576 kb
Host smart-68889730-0cd9-48d2-b71e-80b84a8d813a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15695
00537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1569500537
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2355565006
Short name T24
Test name
Test status
Simulation time 26863645 ps
CPU time 0.64 seconds
Started Mar 10 01:56:38 PM PDT 24
Finished Mar 10 01:56:40 PM PDT 24
Peak memory 202528 kb
Host smart-ea5b38e4-6b81-47cf-a01b-74b1ae171032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23555
65006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2355565006
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.559107337
Short name T491
Test name
Test status
Simulation time 8389804663 ps
CPU time 7.26 seconds
Started Mar 10 01:56:38 PM PDT 24
Finished Mar 10 01:56:45 PM PDT 24
Peak memory 202576 kb
Host smart-3286fab4-ce46-4409-bcb2-f4dd3e44daec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55910
7337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.559107337
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2442299848
Short name T468
Test name
Test status
Simulation time 8363724198 ps
CPU time 7.74 seconds
Started Mar 10 01:56:38 PM PDT 24
Finished Mar 10 01:56:47 PM PDT 24
Peak memory 202568 kb
Host smart-6b6847f8-cc4c-4a46-9f94-84f833084e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24422
99848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2442299848
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3117563700
Short name T37
Test name
Test status
Simulation time 8375387981 ps
CPU time 7.73 seconds
Started Mar 10 01:56:39 PM PDT 24
Finished Mar 10 01:56:47 PM PDT 24
Peak memory 202496 kb
Host smart-dd87cc60-721c-4345-b3ec-ae2452c1f4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31175
63700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3117563700
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.328665099
Short name T330
Test name
Test status
Simulation time 68850752 ps
CPU time 1.78 seconds
Started Mar 10 01:56:41 PM PDT 24
Finished Mar 10 01:56:43 PM PDT 24
Peak memory 202580 kb
Host smart-4838c315-fbbe-4b24-917e-65b56fcac556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32866
5099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.328665099
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.622962804
Short name T373
Test name
Test status
Simulation time 8410218540 ps
CPU time 7.54 seconds
Started Mar 10 01:56:38 PM PDT 24
Finished Mar 10 01:56:46 PM PDT 24
Peak memory 202516 kb
Host smart-cc539da1-58a5-4fcf-a54d-532e72d0f0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62296
2804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.622962804
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1210793251
Short name T546
Test name
Test status
Simulation time 8409653320 ps
CPU time 8.23 seconds
Started Mar 10 01:56:39 PM PDT 24
Finished Mar 10 01:56:48 PM PDT 24
Peak memory 202564 kb
Host smart-3e65c90b-c1c1-418a-bdf9-bfbce22e3c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
93251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1210793251
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3370357080
Short name T339
Test name
Test status
Simulation time 8366509413 ps
CPU time 7.15 seconds
Started Mar 10 01:56:43 PM PDT 24
Finished Mar 10 01:56:51 PM PDT 24
Peak memory 202536 kb
Host smart-baf464d3-10fc-42e4-b1f3-e7d4bda3909f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
57080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3370357080
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.622876038
Short name T426
Test name
Test status
Simulation time 8390215106 ps
CPU time 7.95 seconds
Started Mar 10 01:56:39 PM PDT 24
Finished Mar 10 01:56:48 PM PDT 24
Peak memory 202556 kb
Host smart-822d3466-9165-4c38-af16-9234f0ee8aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62287
6038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.622876038
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3075648619
Short name T624
Test name
Test status
Simulation time 8384204051 ps
CPU time 7.56 seconds
Started Mar 10 01:56:41 PM PDT 24
Finished Mar 10 01:56:49 PM PDT 24
Peak memory 202536 kb
Host smart-eecda99a-1fae-4d0e-a998-bb48ce9ed649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30756
48619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3075648619
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1726220261
Short name T494
Test name
Test status
Simulation time 27086736 ps
CPU time 0.65 seconds
Started Mar 10 01:56:44 PM PDT 24
Finished Mar 10 01:56:45 PM PDT 24
Peak memory 202536 kb
Host smart-350bd67f-59cc-44b6-81b2-fe98a0069a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17262
20261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1726220261
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.4129890326
Short name T666
Test name
Test status
Simulation time 8391733362 ps
CPU time 9.85 seconds
Started Mar 10 01:56:47 PM PDT 24
Finished Mar 10 01:56:57 PM PDT 24
Peak memory 202476 kb
Host smart-193eaa47-addf-4b05-8649-a971fbb39648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41298
90326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.4129890326
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.1518236
Short name T664
Test name
Test status
Simulation time 8378762938 ps
CPU time 7.13 seconds
Started Mar 10 01:56:39 PM PDT 24
Finished Mar 10 01:56:47 PM PDT 24
Peak memory 202468 kb
Host smart-84bfe466-a401-4fda-8d6f-2a1ec6e1f8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15182
36 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.1518236
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2675528344
Short name T470
Test name
Test status
Simulation time 8360506962 ps
CPU time 7.61 seconds
Started Mar 10 01:56:44 PM PDT 24
Finished Mar 10 01:56:51 PM PDT 24
Peak memory 202484 kb
Host smart-ab99aa4f-b912-414e-89d6-a97e8a62e463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26755
28344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2675528344
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3564642054
Short name T679
Test name
Test status
Simulation time 8369702836 ps
CPU time 7.83 seconds
Started Mar 10 01:56:50 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202560 kb
Host smart-3639c933-74b1-46e8-8844-0c694dea4d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35646
42054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3564642054
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3819196012
Short name T594
Test name
Test status
Simulation time 50369655 ps
CPU time 1.51 seconds
Started Mar 10 01:56:44 PM PDT 24
Finished Mar 10 01:56:46 PM PDT 24
Peak memory 202572 kb
Host smart-869041cc-c559-4f08-bafe-5c397e6df0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38191
96012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3819196012
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3512304531
Short name T248
Test name
Test status
Simulation time 8407740790 ps
CPU time 7.88 seconds
Started Mar 10 01:56:46 PM PDT 24
Finished Mar 10 01:56:54 PM PDT 24
Peak memory 202588 kb
Host smart-ad38292b-5f4b-4825-b872-eb26da7cbc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35123
04531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3512304531
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2898920717
Short name T482
Test name
Test status
Simulation time 8368930186 ps
CPU time 7.92 seconds
Started Mar 10 01:56:46 PM PDT 24
Finished Mar 10 01:56:54 PM PDT 24
Peak memory 202588 kb
Host smart-05240467-8d71-41a0-880a-aafae2fac834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28989
20717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2898920717
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1041972127
Short name T527
Test name
Test status
Simulation time 8369730806 ps
CPU time 7.23 seconds
Started Mar 10 01:56:46 PM PDT 24
Finished Mar 10 01:56:53 PM PDT 24
Peak memory 202560 kb
Host smart-37621061-c969-42b0-8eb8-8f79267e2434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10419
72127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1041972127
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.366964314
Short name T5
Test name
Test status
Simulation time 8386196220 ps
CPU time 7.64 seconds
Started Mar 10 01:56:45 PM PDT 24
Finished Mar 10 01:56:53 PM PDT 24
Peak memory 202496 kb
Host smart-b986c178-3036-44ce-a54d-5d11ff6bc5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36696
4314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.366964314
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.719559691
Short name T702
Test name
Test status
Simulation time 25005894 ps
CPU time 0.63 seconds
Started Mar 10 01:56:44 PM PDT 24
Finished Mar 10 01:56:45 PM PDT 24
Peak memory 202492 kb
Host smart-17ea7dff-cec7-4988-9577-87991c79c70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71955
9691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.719559691
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.748213172
Short name T600
Test name
Test status
Simulation time 8381723181 ps
CPU time 8.24 seconds
Started Mar 10 01:56:45 PM PDT 24
Finished Mar 10 01:56:53 PM PDT 24
Peak memory 202552 kb
Host smart-0ea3d2d2-a21a-4dee-964b-365069e8acb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74821
3172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.748213172
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.662168305
Short name T507
Test name
Test status
Simulation time 8395713822 ps
CPU time 7.73 seconds
Started Mar 10 01:56:46 PM PDT 24
Finished Mar 10 01:56:54 PM PDT 24
Peak memory 202536 kb
Host smart-0fbc32a6-27d4-416f-87cb-325f79d99ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66216
8305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.662168305
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2663937392
Short name T558
Test name
Test status
Simulation time 8362133617 ps
CPU time 7.05 seconds
Started Mar 10 01:56:45 PM PDT 24
Finished Mar 10 01:56:53 PM PDT 24
Peak memory 202540 kb
Host smart-e694c95c-6cec-497e-a55f-886e7a4ffc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26639
37392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2663937392
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3161643880
Short name T439
Test name
Test status
Simulation time 8475141000 ps
CPU time 7.24 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:57:00 PM PDT 24
Peak memory 202604 kb
Host smart-de751e4a-273d-4aed-94b6-e2bbf0b5f9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31616
43880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3161643880
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1310184697
Short name T495
Test name
Test status
Simulation time 8372809646 ps
CPU time 8.28 seconds
Started Mar 10 01:56:49 PM PDT 24
Finished Mar 10 01:56:58 PM PDT 24
Peak memory 202536 kb
Host smart-27bef26e-f257-4fc0-8c7a-6c645f21e407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13101
84697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1310184697
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2139614875
Short name T286
Test name
Test status
Simulation time 236293535 ps
CPU time 2.06 seconds
Started Mar 10 01:56:50 PM PDT 24
Finished Mar 10 01:56:52 PM PDT 24
Peak memory 202540 kb
Host smart-b2699acb-d7da-474d-b3e8-26c4439fa4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21396
14875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2139614875
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2526093351
Short name T26
Test name
Test status
Simulation time 8420217858 ps
CPU time 7.74 seconds
Started Mar 10 01:56:50 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202548 kb
Host smart-31815f01-7076-4080-a4a3-6371cb0d4808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25260
93351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2526093351
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3550331961
Short name T268
Test name
Test status
Simulation time 8410023221 ps
CPU time 9.55 seconds
Started Mar 10 01:56:49 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202580 kb
Host smart-7bdad45f-38e4-4af0-a521-a1eed59e9680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35503
31961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3550331961
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.471282639
Short name T319
Test name
Test status
Simulation time 8363618282 ps
CPU time 7.17 seconds
Started Mar 10 01:56:51 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202604 kb
Host smart-feb2bfdf-f994-4177-bc45-d16d8f5768e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47128
2639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.471282639
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2076500569
Short name T281
Test name
Test status
Simulation time 8385960778 ps
CPU time 8.1 seconds
Started Mar 10 01:56:50 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202444 kb
Host smart-900dc518-cd62-4b3c-8c8e-8ce9d3b7231c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20765
00569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2076500569
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1725207966
Short name T633
Test name
Test status
Simulation time 8401325862 ps
CPU time 7.61 seconds
Started Mar 10 01:56:48 PM PDT 24
Finished Mar 10 01:56:56 PM PDT 24
Peak memory 202556 kb
Host smart-99479d21-fc11-414a-864c-cad7bdc997c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17252
07966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1725207966
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.18015104
Short name T509
Test name
Test status
Simulation time 30991092 ps
CPU time 0.65 seconds
Started Mar 10 01:56:51 PM PDT 24
Finished Mar 10 01:56:52 PM PDT 24
Peak memory 202480 kb
Host smart-0b5bf932-c097-4399-a1a8-6bb25843e5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18015
104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.18015104
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.760120116
Short name T208
Test name
Test status
Simulation time 8408908283 ps
CPU time 8.32 seconds
Started Mar 10 01:56:50 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202564 kb
Host smart-119f56f6-8ca2-43cb-937d-af3d2dc49f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76012
0116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.760120116
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.4241968695
Short name T201
Test name
Test status
Simulation time 8387497619 ps
CPU time 7.75 seconds
Started Mar 10 01:56:49 PM PDT 24
Finished Mar 10 01:56:58 PM PDT 24
Peak memory 202588 kb
Host smart-616dce13-5925-4025-8bf9-cdfcf70425a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42419
68695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.4241968695
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.278858114
Short name T348
Test name
Test status
Simulation time 8359787770 ps
CPU time 7.88 seconds
Started Mar 10 01:56:49 PM PDT 24
Finished Mar 10 01:56:58 PM PDT 24
Peak memory 202564 kb
Host smart-c5fe0406-60e5-481d-afa7-81353dc0d4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
8114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.278858114
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2957511075
Short name T601
Test name
Test status
Simulation time 8370025227 ps
CPU time 7.19 seconds
Started Mar 10 01:56:50 PM PDT 24
Finished Mar 10 01:56:57 PM PDT 24
Peak memory 202592 kb
Host smart-5dd7de96-a771-4bc8-aa9e-efad811695cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29575
11075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2957511075
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2339008128
Short name T524
Test name
Test status
Simulation time 85202960 ps
CPU time 1.17 seconds
Started Mar 10 01:56:48 PM PDT 24
Finished Mar 10 01:56:50 PM PDT 24
Peak memory 202548 kb
Host smart-7cc1fe2e-5ec7-46f8-ba00-eae08f00e01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23390
08128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2339008128
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2316549407
Short name T331
Test name
Test status
Simulation time 8432636755 ps
CPU time 7.85 seconds
Started Mar 10 01:56:51 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202576 kb
Host smart-176f36e6-73bf-4537-8f52-8bff959cc282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23165
49407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2316549407
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4142310345
Short name T605
Test name
Test status
Simulation time 8403150963 ps
CPU time 7.58 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202496 kb
Host smart-185cf109-7981-491c-99bc-8fc8189fa9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41423
10345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4142310345
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2821895271
Short name T276
Test name
Test status
Simulation time 8366768330 ps
CPU time 9.36 seconds
Started Mar 10 01:56:48 PM PDT 24
Finished Mar 10 01:56:58 PM PDT 24
Peak memory 202588 kb
Host smart-d187de17-6d8a-4023-908e-b2bb021e46a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28218
95271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2821895271
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.4103185948
Short name T293
Test name
Test status
Simulation time 8398933621 ps
CPU time 9.79 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:57:03 PM PDT 24
Peak memory 202512 kb
Host smart-4fab939c-6a20-415e-9057-334fe7fc46d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41031
85948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4103185948
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3041006048
Short name T279
Test name
Test status
Simulation time 8387442251 ps
CPU time 7.68 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202560 kb
Host smart-f8d4f3b1-b926-4337-9495-4d7494de1afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30410
06048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3041006048
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1688828803
Short name T434
Test name
Test status
Simulation time 31605075 ps
CPU time 0.66 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:56:54 PM PDT 24
Peak memory 202504 kb
Host smart-2ec3bb7f-b95e-426e-a480-7ab8742f55a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16888
28803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1688828803
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.265289635
Short name T526
Test name
Test status
Simulation time 8421960063 ps
CPU time 8.73 seconds
Started Mar 10 01:56:49 PM PDT 24
Finished Mar 10 01:56:58 PM PDT 24
Peak memory 202564 kb
Host smart-486413c6-94a9-4965-91c1-0701b4853d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26528
9635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.265289635
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1082479043
Short name T45
Test name
Test status
Simulation time 8408242130 ps
CPU time 9.3 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202548 kb
Host smart-1c5eb01f-fc70-465e-8afe-21cb7a778861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10824
79043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1082479043
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2840155270
Short name T536
Test name
Test status
Simulation time 8360781346 ps
CPU time 9.26 seconds
Started Mar 10 01:56:50 PM PDT 24
Finished Mar 10 01:57:00 PM PDT 24
Peak memory 202556 kb
Host smart-3fe253f1-3fcf-43c9-8506-7d99d4e0695f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
55270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2840155270
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3144138617
Short name T626
Test name
Test status
Simulation time 8372426820 ps
CPU time 7.7 seconds
Started Mar 10 01:56:50 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202568 kb
Host smart-59d33bc1-bfb2-4f00-bf9a-d3e85d6e67a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31441
38617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3144138617
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1215867144
Short name T659
Test name
Test status
Simulation time 113617927 ps
CPU time 1.14 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:56:55 PM PDT 24
Peak memory 202524 kb
Host smart-614d8341-415c-4ac5-8931-b94781288402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12158
67144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1215867144
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1225721163
Short name T115
Test name
Test status
Simulation time 8390562051 ps
CPU time 8.18 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202532 kb
Host smart-693319bd-e1f8-4cb1-b4d9-a136a6233b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12257
21163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1225721163
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.786923985
Short name T480
Test name
Test status
Simulation time 8401609281 ps
CPU time 7.38 seconds
Started Mar 10 01:56:51 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202596 kb
Host smart-306dd1ef-0718-4439-91bb-8c7a4c813358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78692
3985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.786923985
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1157777974
Short name T79
Test name
Test status
Simulation time 8361359943 ps
CPU time 8.02 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202560 kb
Host smart-bed9ee25-f205-4f4a-86ea-dfcd1204bd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577
77974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1157777974
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2066170988
Short name T430
Test name
Test status
Simulation time 8372660450 ps
CPU time 7.62 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:57:00 PM PDT 24
Peak memory 202588 kb
Host smart-f65851eb-9c16-4bed-b208-d01f73f8af6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20661
70988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2066170988
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.77116858
Short name T580
Test name
Test status
Simulation time 8392028105 ps
CPU time 7.51 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:57:00 PM PDT 24
Peak memory 202476 kb
Host smart-aadc32c4-9040-4043-a7e3-e8f742d536e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77116
858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.77116858
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.315275281
Short name T302
Test name
Test status
Simulation time 24364066 ps
CPU time 0.67 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:56:53 PM PDT 24
Peak memory 202512 kb
Host smart-abec590e-5b30-4769-a2fb-5e087781ce0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31527
5281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.315275281
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.896040235
Short name T121
Test name
Test status
Simulation time 8403665018 ps
CPU time 7.82 seconds
Started Mar 10 01:56:58 PM PDT 24
Finished Mar 10 01:57:06 PM PDT 24
Peak memory 202472 kb
Host smart-c6dc5198-a1d8-4e89-a2e3-e805a030e951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89604
0235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.896040235
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3048818706
Short name T371
Test name
Test status
Simulation time 8406980679 ps
CPU time 7.24 seconds
Started Mar 10 01:56:56 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202544 kb
Host smart-88d1d04d-123f-4a6d-b9c5-109204c91cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
18706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3048818706
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2847424874
Short name T357
Test name
Test status
Simulation time 8363364791 ps
CPU time 7.85 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:57:01 PM PDT 24
Peak memory 202588 kb
Host smart-d59cb214-89c6-4cd3-b881-3b0d2d9ba702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28474
24874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2847424874
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3855171360
Short name T156
Test name
Test status
Simulation time 8470773712 ps
CPU time 7.85 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202528 kb
Host smart-cff67bbc-ef63-40b8-b844-50382811d241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
71360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3855171360
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1669330563
Short name T469
Test name
Test status
Simulation time 8369743652 ps
CPU time 7.82 seconds
Started Mar 10 01:56:55 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202572 kb
Host smart-26f28c7d-a01e-4c94-a62a-d53df2ba1641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16693
30563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1669330563
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4051798247
Short name T206
Test name
Test status
Simulation time 237522916 ps
CPU time 2.01 seconds
Started Mar 10 01:56:56 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202580 kb
Host smart-2b346c60-00ea-423c-a1a8-aeef825b1d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40517
98247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4051798247
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3086923909
Short name T333
Test name
Test status
Simulation time 8446986455 ps
CPU time 9.31 seconds
Started Mar 10 01:56:54 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202480 kb
Host smart-77f46b86-01dc-4a96-9ca0-4be59344c4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30869
23909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3086923909
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.674831058
Short name T683
Test name
Test status
Simulation time 8410993914 ps
CPU time 7.25 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:01 PM PDT 24
Peak memory 202548 kb
Host smart-8b2cb6ea-ab3c-4c18-b8b5-5e6ebf39834a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67483
1058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.674831058
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1187076925
Short name T384
Test name
Test status
Simulation time 8367905708 ps
CPU time 7.43 seconds
Started Mar 10 01:56:56 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202544 kb
Host smart-e488c294-26ed-43d2-8a82-5c82be2f03ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11870
76925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1187076925
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2091581713
Short name T110
Test name
Test status
Simulation time 8403730424 ps
CPU time 9.45 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202596 kb
Host smart-ac46a85c-ce3f-4576-b338-700efe20fbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
81713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2091581713
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.453227330
Short name T712
Test name
Test status
Simulation time 8390812753 ps
CPU time 8.58 seconds
Started Mar 10 01:56:52 PM PDT 24
Finished Mar 10 01:57:01 PM PDT 24
Peak memory 202548 kb
Host smart-83546ea7-c76b-42e7-b137-7f2df6aa4aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45322
7330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.453227330
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2871496749
Short name T416
Test name
Test status
Simulation time 8395964914 ps
CPU time 7.62 seconds
Started Mar 10 01:56:53 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202568 kb
Host smart-0aae86af-91b0-476e-9211-de684014811f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28714
96749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2871496749
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3368146312
Short name T500
Test name
Test status
Simulation time 32346153 ps
CPU time 0.71 seconds
Started Mar 10 01:56:58 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202504 kb
Host smart-231bcce4-e6df-4e9a-947d-06f17b94a2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33681
46312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3368146312
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.819355694
Short name T489
Test name
Test status
Simulation time 8371049493 ps
CPU time 8.98 seconds
Started Mar 10 01:56:55 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202564 kb
Host smart-dd86f751-ce96-4183-9b78-f9c75f48eb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81935
5694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.819355694
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3944061743
Short name T608
Test name
Test status
Simulation time 8358988556 ps
CPU time 7.58 seconds
Started Mar 10 01:56:51 PM PDT 24
Finished Mar 10 01:56:59 PM PDT 24
Peak memory 202600 kb
Host smart-950c303f-e9fb-4aac-8b6c-2f038e19082d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39440
61743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3944061743
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3532627633
Short name T496
Test name
Test status
Simulation time 8369283263 ps
CPU time 8.34 seconds
Started Mar 10 01:56:54 PM PDT 24
Finished Mar 10 01:57:02 PM PDT 24
Peak memory 202568 kb
Host smart-febe93e2-fc64-4c24-80f8-b31fdcaa0bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35326
27633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3532627633
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2954997053
Short name T193
Test name
Test status
Simulation time 70739427 ps
CPU time 2.02 seconds
Started Mar 10 01:56:55 PM PDT 24
Finished Mar 10 01:56:58 PM PDT 24
Peak memory 202560 kb
Host smart-fdd1812d-a906-4f0a-8070-0163deec4c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29549
97053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2954997053
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1253033888
Short name T358
Test name
Test status
Simulation time 8399130218 ps
CPU time 7.44 seconds
Started Mar 10 01:56:56 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202576 kb
Host smart-333ff20b-5092-4f33-8972-b5ab0b4100eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12530
33888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1253033888
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2473638615
Short name T448
Test name
Test status
Simulation time 8409376711 ps
CPU time 9.78 seconds
Started Mar 10 01:56:55 PM PDT 24
Finished Mar 10 01:57:05 PM PDT 24
Peak memory 202560 kb
Host smart-d617f08c-3f80-40f5-82d3-19ce6256668a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24736
38615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2473638615
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.873564578
Short name T446
Test name
Test status
Simulation time 8363233583 ps
CPU time 7.74 seconds
Started Mar 10 01:56:57 PM PDT 24
Finished Mar 10 01:57:05 PM PDT 24
Peak memory 202540 kb
Host smart-e1012920-3d71-466c-ac43-cd580c3d2c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87356
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.873564578
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4079296307
Short name T701
Test name
Test status
Simulation time 8431410025 ps
CPU time 9.77 seconds
Started Mar 10 01:56:54 PM PDT 24
Finished Mar 10 01:57:05 PM PDT 24
Peak memory 202584 kb
Host smart-321852bd-6e47-4d5b-9ca2-49763b340766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40792
96307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4079296307
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3262371257
Short name T692
Test name
Test status
Simulation time 8395227981 ps
CPU time 7.3 seconds
Started Mar 10 01:56:55 PM PDT 24
Finished Mar 10 01:57:03 PM PDT 24
Peak memory 202508 kb
Host smart-6b4a7371-7004-4ece-9d32-25689ca74400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32623
71257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3262371257
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1510239883
Short name T244
Test name
Test status
Simulation time 8384785697 ps
CPU time 8.31 seconds
Started Mar 10 01:56:54 PM PDT 24
Finished Mar 10 01:57:03 PM PDT 24
Peak memory 202540 kb
Host smart-b06bf96d-5e24-4b74-8d22-5c648c86d59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15102
39883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1510239883
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3045215900
Short name T627
Test name
Test status
Simulation time 23377429 ps
CPU time 0.64 seconds
Started Mar 10 01:56:59 PM PDT 24
Finished Mar 10 01:57:00 PM PDT 24
Peak memory 202468 kb
Host smart-f6c805b6-774e-41ba-bd2a-a24f0b448409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30452
15900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3045215900
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.756570874
Short name T677
Test name
Test status
Simulation time 8435734733 ps
CPU time 7.72 seconds
Started Mar 10 01:56:56 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202576 kb
Host smart-cbf2b6fb-464f-4e30-9615-aeb3bdd34415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75657
0874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.756570874
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.1124078495
Short name T693
Test name
Test status
Simulation time 8390724066 ps
CPU time 7.78 seconds
Started Mar 10 01:56:55 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202468 kb
Host smart-92077132-ffa3-4e9c-9006-4aa5bf146df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240
78495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.1124078495
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3097713758
Short name T499
Test name
Test status
Simulation time 8354783402 ps
CPU time 9.16 seconds
Started Mar 10 01:57:00 PM PDT 24
Finished Mar 10 01:57:09 PM PDT 24
Peak memory 202496 kb
Host smart-7c8ce77e-5883-4237-84c7-96ea3a14e569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30977
13758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3097713758
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3120893071
Short name T259
Test name
Test status
Simulation time 8369717572 ps
CPU time 7.14 seconds
Started Mar 10 01:56:59 PM PDT 24
Finished Mar 10 01:57:06 PM PDT 24
Peak memory 202604 kb
Host smart-95ac5cb1-6573-4568-83a3-0ad3a6e5225a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31208
93071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3120893071
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.864375039
Short name T46
Test name
Test status
Simulation time 56029439 ps
CPU time 1.64 seconds
Started Mar 10 01:56:59 PM PDT 24
Finished Mar 10 01:57:01 PM PDT 24
Peak memory 202636 kb
Host smart-22a0a0b3-a34b-46b5-9e81-d23e10271d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86437
5039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.864375039
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.4289368162
Short name T593
Test name
Test status
Simulation time 8372062149 ps
CPU time 9.29 seconds
Started Mar 10 01:56:59 PM PDT 24
Finished Mar 10 01:57:08 PM PDT 24
Peak memory 202520 kb
Host smart-2470d7bb-8b25-4999-9bf4-89b73a6fa6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42893
68162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.4289368162
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2139613660
Short name T596
Test name
Test status
Simulation time 8406310973 ps
CPU time 8.44 seconds
Started Mar 10 01:56:59 PM PDT 24
Finished Mar 10 01:57:08 PM PDT 24
Peak memory 202596 kb
Host smart-9b27cacc-c1eb-4841-8d21-7d1522a3b9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21396
13660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2139613660
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1499572794
Short name T291
Test name
Test status
Simulation time 8360067013 ps
CPU time 7.42 seconds
Started Mar 10 01:56:58 PM PDT 24
Finished Mar 10 01:57:06 PM PDT 24
Peak memory 202556 kb
Host smart-c55e5b0b-8596-4f61-a5c2-5426e2413301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14995
72794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1499572794
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.2712008512
Short name T305
Test name
Test status
Simulation time 8375970359 ps
CPU time 9.86 seconds
Started Mar 10 01:56:58 PM PDT 24
Finished Mar 10 01:57:09 PM PDT 24
Peak memory 202560 kb
Host smart-e6f710f9-f02b-4f2b-b19b-21cc02bad7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27120
08512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2712008512
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2705488418
Short name T345
Test name
Test status
Simulation time 8378022541 ps
CPU time 7.37 seconds
Started Mar 10 01:56:58 PM PDT 24
Finished Mar 10 01:57:05 PM PDT 24
Peak memory 202548 kb
Host smart-9e8f463e-68e1-47c7-8471-839c8f71dc09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
88418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2705488418
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3454882563
Short name T466
Test name
Test status
Simulation time 24180432 ps
CPU time 0.64 seconds
Started Mar 10 01:57:02 PM PDT 24
Finished Mar 10 01:57:03 PM PDT 24
Peak memory 202520 kb
Host smart-bde7f7ac-a145-499c-abb7-fe8257291fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34548
82563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3454882563
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2803558190
Short name T437
Test name
Test status
Simulation time 8439340753 ps
CPU time 7.96 seconds
Started Mar 10 01:56:59 PM PDT 24
Finished Mar 10 01:57:07 PM PDT 24
Peak memory 202520 kb
Host smart-dda33a98-3366-4a6e-bc6a-a354e5931802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28035
58190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2803558190
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.2194435548
Short name T640
Test name
Test status
Simulation time 8381538733 ps
CPU time 7.13 seconds
Started Mar 10 01:56:59 PM PDT 24
Finished Mar 10 01:57:07 PM PDT 24
Peak memory 202556 kb
Host smart-fe45baa1-98ad-486d-b73e-868e850adb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21944
35548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.2194435548
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1625350262
Short name T247
Test name
Test status
Simulation time 8356514592 ps
CPU time 7.6 seconds
Started Mar 10 01:56:57 PM PDT 24
Finished Mar 10 01:57:06 PM PDT 24
Peak memory 202600 kb
Host smart-dd6d452c-4423-4495-86ca-d894b52a1f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16253
50262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1625350262
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2342407010
Short name T616
Test name
Test status
Simulation time 8369994342 ps
CPU time 7.13 seconds
Started Mar 10 01:57:10 PM PDT 24
Finished Mar 10 01:57:17 PM PDT 24
Peak memory 202572 kb
Host smart-a6505259-087f-43fb-8929-c79aa389b5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424
07010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2342407010
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2075280557
Short name T401
Test name
Test status
Simulation time 65040560 ps
CPU time 1.85 seconds
Started Mar 10 01:57:02 PM PDT 24
Finished Mar 10 01:57:04 PM PDT 24
Peak memory 202636 kb
Host smart-3ce41207-1074-460a-b9e7-25db335d43dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20752
80557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2075280557
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2335712087
Short name T662
Test name
Test status
Simulation time 8455793197 ps
CPU time 7.75 seconds
Started Mar 10 01:57:08 PM PDT 24
Finished Mar 10 01:57:16 PM PDT 24
Peak memory 202476 kb
Host smart-94c2e1df-0497-4e2b-bb74-cf91f6cd83e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23357
12087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2335712087
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1928646668
Short name T369
Test name
Test status
Simulation time 8406948742 ps
CPU time 8.22 seconds
Started Mar 10 01:57:10 PM PDT 24
Finished Mar 10 01:57:18 PM PDT 24
Peak memory 202588 kb
Host smart-b5e27f93-44ad-45f8-94a0-9148b88ec567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19286
46668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1928646668
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3056848200
Short name T663
Test name
Test status
Simulation time 8369062661 ps
CPU time 7.74 seconds
Started Mar 10 01:57:02 PM PDT 24
Finished Mar 10 01:57:09 PM PDT 24
Peak memory 202520 kb
Host smart-36a0d552-3f22-43b2-bfd1-f840fe883e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30568
48200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3056848200
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.557224542
Short name T94
Test name
Test status
Simulation time 8427869491 ps
CPU time 9.85 seconds
Started Mar 10 01:57:05 PM PDT 24
Finished Mar 10 01:57:15 PM PDT 24
Peak memory 202556 kb
Host smart-07815879-737c-4e86-b4d7-0dc43919dcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55722
4542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.557224542
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.557037461
Short name T383
Test name
Test status
Simulation time 8362801676 ps
CPU time 8.39 seconds
Started Mar 10 01:57:03 PM PDT 24
Finished Mar 10 01:57:11 PM PDT 24
Peak memory 202560 kb
Host smart-6a181b0a-8ce8-40c8-9014-31a66be9a9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55703
7461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.557037461
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.174188455
Short name T313
Test name
Test status
Simulation time 8393791271 ps
CPU time 8.9 seconds
Started Mar 10 01:57:06 PM PDT 24
Finished Mar 10 01:57:15 PM PDT 24
Peak memory 202560 kb
Host smart-d40e4e1b-4dc7-4ebd-bf98-14969ba35546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17418
8455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.174188455
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.362988712
Short name T423
Test name
Test status
Simulation time 25560547 ps
CPU time 0.66 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:10 PM PDT 24
Peak memory 202508 kb
Host smart-dca50759-b871-4d1b-bea5-a55a5e9fdaa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36298
8712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.362988712
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1042933785
Short name T566
Test name
Test status
Simulation time 8372463846 ps
CPU time 7.03 seconds
Started Mar 10 01:57:03 PM PDT 24
Finished Mar 10 01:57:10 PM PDT 24
Peak memory 202512 kb
Host smart-7aa00903-029e-45f9-9249-23cf9edf0ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10429
33785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1042933785
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.2604257151
Short name T541
Test name
Test status
Simulation time 8400310496 ps
CPU time 8.76 seconds
Started Mar 10 01:57:07 PM PDT 24
Finished Mar 10 01:57:15 PM PDT 24
Peak memory 202456 kb
Host smart-e41bf4ad-ba25-4977-8428-7f34ea2a9c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26042
57151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.2604257151
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2951876623
Short name T535
Test name
Test status
Simulation time 8355473226 ps
CPU time 7.65 seconds
Started Mar 10 01:57:04 PM PDT 24
Finished Mar 10 01:57:11 PM PDT 24
Peak memory 202524 kb
Host smart-163772fb-0247-4871-aebe-f11e7e022326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29518
76623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2951876623
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1104264804
Short name T144
Test name
Test status
Simulation time 8479484668 ps
CPU time 8.86 seconds
Started Mar 10 01:57:06 PM PDT 24
Finished Mar 10 01:57:15 PM PDT 24
Peak memory 202632 kb
Host smart-575463ee-02dc-42a2-8518-0480942d7f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042
64804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1104264804
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1192678937
Short name T407
Test name
Test status
Simulation time 8368779022 ps
CPU time 8.9 seconds
Started Mar 10 01:56:07 PM PDT 24
Finished Mar 10 01:56:16 PM PDT 24
Peak memory 202588 kb
Host smart-bb582da1-02af-4cdb-9d87-565e2e170ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11926
78937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1192678937
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2210369193
Short name T415
Test name
Test status
Simulation time 92585815 ps
CPU time 1.24 seconds
Started Mar 10 01:56:09 PM PDT 24
Finished Mar 10 01:56:10 PM PDT 24
Peak memory 202544 kb
Host smart-e768947f-f811-468a-a3fa-a7ab39a6ba12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22103
69193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2210369193
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.859801612
Short name T420
Test name
Test status
Simulation time 8414166137 ps
CPU time 7.77 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:24 PM PDT 24
Peak memory 202576 kb
Host smart-e2cd95c9-4bc0-4d05-b420-92e8a0670a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85980
1612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.859801612
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2297363886
Short name T529
Test name
Test status
Simulation time 8404865801 ps
CPU time 8.36 seconds
Started Mar 10 01:56:11 PM PDT 24
Finished Mar 10 01:56:20 PM PDT 24
Peak memory 202560 kb
Host smart-316f8005-ef9c-45d8-a542-2d83dd5b62eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973
63886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2297363886
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.691806758
Short name T417
Test name
Test status
Simulation time 8363079470 ps
CPU time 7.08 seconds
Started Mar 10 01:56:13 PM PDT 24
Finished Mar 10 01:56:21 PM PDT 24
Peak memory 202524 kb
Host smart-feb2263c-96a6-4732-9311-4bdf8ed8fac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69180
6758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.691806758
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3478451176
Short name T477
Test name
Test status
Simulation time 8380423455 ps
CPU time 7.44 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:24 PM PDT 24
Peak memory 202572 kb
Host smart-cf86ee4a-cb9b-454e-907e-0652ee9cc343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34784
51176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3478451176
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.175872228
Short name T634
Test name
Test status
Simulation time 8369177691 ps
CPU time 7.67 seconds
Started Mar 10 01:56:07 PM PDT 24
Finished Mar 10 01:56:15 PM PDT 24
Peak memory 202604 kb
Host smart-544ea2bd-ab3f-45f6-b092-87624449757a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17587
2228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.175872228
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.190071333
Short name T31
Test name
Test status
Simulation time 28169080 ps
CPU time 0.62 seconds
Started Mar 10 01:56:14 PM PDT 24
Finished Mar 10 01:56:15 PM PDT 24
Peak memory 202532 kb
Host smart-0f9acfbb-be82-4079-8892-470f3708b79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19007
1333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.190071333
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.175321172
Short name T280
Test name
Test status
Simulation time 8378489204 ps
CPU time 7.28 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:24 PM PDT 24
Peak memory 202428 kb
Host smart-01a57be7-231a-4f82-995a-656f85fd50fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17532
1172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.175321172
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3323175825
Short name T249
Test name
Test status
Simulation time 8373665160 ps
CPU time 7.95 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:24 PM PDT 24
Peak memory 202564 kb
Host smart-b6e9eda2-5865-4a83-8b0e-a5db5fb6e27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33231
75825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3323175825
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3224326917
Short name T53
Test name
Test status
Simulation time 159984627 ps
CPU time 1.03 seconds
Started Mar 10 01:56:12 PM PDT 24
Finished Mar 10 01:56:14 PM PDT 24
Peak memory 218488 kb
Host smart-a3adba6a-6f69-4b06-b7f2-7ca74c8defcc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3224326917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3224326917
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.4009920478
Short name T347
Test name
Test status
Simulation time 8360703023 ps
CPU time 7.29 seconds
Started Mar 10 01:56:13 PM PDT 24
Finished Mar 10 01:56:21 PM PDT 24
Peak memory 202576 kb
Host smart-e2b139ce-eb46-42f0-a43c-ce9835d35732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
20478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.4009920478
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.586629617
Short name T125
Test name
Test status
Simulation time 8468945901 ps
CPU time 7.54 seconds
Started Mar 10 01:56:11 PM PDT 24
Finished Mar 10 01:56:19 PM PDT 24
Peak memory 202508 kb
Host smart-d061b96c-43a7-4625-bb89-0d0bdcb95655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58662
9617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.586629617
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3007787073
Short name T253
Test name
Test status
Simulation time 8375191324 ps
CPU time 7.81 seconds
Started Mar 10 01:57:08 PM PDT 24
Finished Mar 10 01:57:16 PM PDT 24
Peak memory 202476 kb
Host smart-34b48e36-6689-44c9-9c14-312cfefcd20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30077
87073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3007787073
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3755350307
Short name T202
Test name
Test status
Simulation time 200302578 ps
CPU time 2.07 seconds
Started Mar 10 01:57:08 PM PDT 24
Finished Mar 10 01:57:10 PM PDT 24
Peak memory 202424 kb
Host smart-d70cbb26-6bed-4f8f-b05d-2dcb5da0379c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37553
50307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3755350307
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.455054362
Short name T510
Test name
Test status
Simulation time 8406797705 ps
CPU time 7.23 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:16 PM PDT 24
Peak memory 202428 kb
Host smart-8972d0ac-93e3-4277-8476-2a57b5045eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45505
4362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.455054362
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1037684401
Short name T424
Test name
Test status
Simulation time 8408703116 ps
CPU time 7.62 seconds
Started Mar 10 01:57:06 PM PDT 24
Finished Mar 10 01:57:13 PM PDT 24
Peak memory 202536 kb
Host smart-7930881b-2958-402e-af7b-5c137316cd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10376
84401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1037684401
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1415409742
Short name T262
Test name
Test status
Simulation time 8365855781 ps
CPU time 7.99 seconds
Started Mar 10 01:57:02 PM PDT 24
Finished Mar 10 01:57:11 PM PDT 24
Peak memory 202576 kb
Host smart-f88c8d44-6e23-4926-bee0-9dffebddaa2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154
09742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1415409742
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3859689725
Short name T705
Test name
Test status
Simulation time 8414052509 ps
CPU time 7.92 seconds
Started Mar 10 01:57:02 PM PDT 24
Finished Mar 10 01:57:10 PM PDT 24
Peak memory 202560 kb
Host smart-b63c8778-2f58-42a7-afcf-f6fcb042c7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38596
89725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3859689725
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3497472237
Short name T344
Test name
Test status
Simulation time 8402625899 ps
CPU time 7.51 seconds
Started Mar 10 01:57:08 PM PDT 24
Finished Mar 10 01:57:15 PM PDT 24
Peak memory 202476 kb
Host smart-d71be044-f0c1-41e0-87c7-0866d67dd773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34974
72237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3497472237
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.609884630
Short name T290
Test name
Test status
Simulation time 8364418576 ps
CPU time 8.53 seconds
Started Mar 10 01:57:03 PM PDT 24
Finished Mar 10 01:57:12 PM PDT 24
Peak memory 202500 kb
Host smart-8fcf0ff5-7abe-49af-bc69-efee399173f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60988
4630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.609884630
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1304492401
Short name T629
Test name
Test status
Simulation time 28094830 ps
CPU time 0.65 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:09 PM PDT 24
Peak memory 202516 kb
Host smart-ffbe4538-a695-4d34-a8d4-7ae2afdaf476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13044
92401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1304492401
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.4085098738
Short name T505
Test name
Test status
Simulation time 8403405569 ps
CPU time 8.22 seconds
Started Mar 10 01:57:03 PM PDT 24
Finished Mar 10 01:57:12 PM PDT 24
Peak memory 202496 kb
Host smart-3310091f-1f88-49e0-a2a7-a225cb3fd6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850
98738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.4085098738
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.103271168
Short name T638
Test name
Test status
Simulation time 8384155836 ps
CPU time 7.08 seconds
Started Mar 10 01:57:10 PM PDT 24
Finished Mar 10 01:57:17 PM PDT 24
Peak memory 202560 kb
Host smart-59ad4fff-e7ef-44db-bd2a-ec333ebc7357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10327
1168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.103271168
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2849205584
Short name T435
Test name
Test status
Simulation time 8362517616 ps
CPU time 8.03 seconds
Started Mar 10 01:57:07 PM PDT 24
Finished Mar 10 01:57:15 PM PDT 24
Peak memory 202568 kb
Host smart-88484c11-f9f8-4036-b5e9-f73458d0012f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28492
05584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2849205584
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1234779908
Short name T149
Test name
Test status
Simulation time 8474960007 ps
CPU time 8.1 seconds
Started Mar 10 01:57:04 PM PDT 24
Finished Mar 10 01:57:12 PM PDT 24
Peak memory 202552 kb
Host smart-15145600-ba78-4c5a-95d2-c41fc92244bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12347
79908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1234779908
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.479284957
Short name T655
Test name
Test status
Simulation time 8370564072 ps
CPU time 7.57 seconds
Started Mar 10 01:57:08 PM PDT 24
Finished Mar 10 01:57:16 PM PDT 24
Peak memory 202568 kb
Host smart-504b6767-d6ca-4039-a843-e58e9636c781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47928
4957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.479284957
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1001560950
Short name T578
Test name
Test status
Simulation time 133837906 ps
CPU time 1.4 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:10 PM PDT 24
Peak memory 202540 kb
Host smart-a4d73fb5-d3ce-4efd-8bc1-a948e3406cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10015
60950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1001560950
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2237850143
Short name T570
Test name
Test status
Simulation time 8371544271 ps
CPU time 7.08 seconds
Started Mar 10 01:57:11 PM PDT 24
Finished Mar 10 01:57:19 PM PDT 24
Peak memory 202572 kb
Host smart-547b04fb-889b-4a72-873e-f0d214a5d1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22378
50143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2237850143
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2257085868
Short name T341
Test name
Test status
Simulation time 8411230061 ps
CPU time 7.25 seconds
Started Mar 10 01:57:08 PM PDT 24
Finished Mar 10 01:57:16 PM PDT 24
Peak memory 202604 kb
Host smart-83643491-8bf0-4fa3-b536-2458cfa3476a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22570
85868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2257085868
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1087777177
Short name T304
Test name
Test status
Simulation time 8363600480 ps
CPU time 7.02 seconds
Started Mar 10 01:57:06 PM PDT 24
Finished Mar 10 01:57:13 PM PDT 24
Peak memory 202472 kb
Host smart-45f5f28b-ce10-421e-bdf4-ec3525b2e694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10877
77177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1087777177
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3953432257
Short name T107
Test name
Test status
Simulation time 8447531062 ps
CPU time 8.6 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:18 PM PDT 24
Peak memory 202556 kb
Host smart-f6768890-d6f8-4d0d-836a-b7b6c966f4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
32257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3953432257
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2797775658
Short name T301
Test name
Test status
Simulation time 8370865340 ps
CPU time 7.42 seconds
Started Mar 10 01:57:06 PM PDT 24
Finished Mar 10 01:57:14 PM PDT 24
Peak memory 202572 kb
Host smart-f44d8548-39de-4821-b6b6-1f31e5f7398c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27977
75658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2797775658
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.438420167
Short name T418
Test name
Test status
Simulation time 8404721927 ps
CPU time 7.63 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202548 kb
Host smart-ce6b0295-c5a0-4d37-88e0-eeccd18ab4a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43842
0167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.438420167
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.269029530
Short name T707
Test name
Test status
Simulation time 31823723 ps
CPU time 0.64 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:09 PM PDT 24
Peak memory 202528 kb
Host smart-4ed2ae17-e8d8-4a4e-8f25-b5164c7621a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26902
9530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.269029530
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.4267817097
Short name T129
Test name
Test status
Simulation time 8399393654 ps
CPU time 8.56 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:18 PM PDT 24
Peak memory 202480 kb
Host smart-3b0f8b57-4727-4d28-8eb5-24ef71b096c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42678
17097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.4267817097
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.3087669730
Short name T697
Test name
Test status
Simulation time 8387348349 ps
CPU time 8.31 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:18 PM PDT 24
Peak memory 202468 kb
Host smart-d1985e5b-b8be-4467-819d-002af758c636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876
69730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.3087669730
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1709398897
Short name T460
Test name
Test status
Simulation time 8362065605 ps
CPU time 7.97 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202576 kb
Host smart-33dd5155-abd6-4d12-a6c3-97a924eee5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
98897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1709398897
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3027917966
Short name T145
Test name
Test status
Simulation time 8478511659 ps
CPU time 8.8 seconds
Started Mar 10 01:57:08 PM PDT 24
Finished Mar 10 01:57:17 PM PDT 24
Peak memory 202612 kb
Host smart-79550e1d-e278-41be-a59a-9db6ef0fecd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30279
17966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3027917966
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3242152027
Short name T359
Test name
Test status
Simulation time 8366618549 ps
CPU time 7.89 seconds
Started Mar 10 01:57:06 PM PDT 24
Finished Mar 10 01:57:14 PM PDT 24
Peak memory 202552 kb
Host smart-0a56b2d8-b2db-405c-87d8-af329699bb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32421
52027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3242152027
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2332471075
Short name T497
Test name
Test status
Simulation time 8457529486 ps
CPU time 8.31 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202512 kb
Host smart-01d06480-2fa7-4165-a8ac-b6520c2f853c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23324
71075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2332471075
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.394718524
Short name T451
Test name
Test status
Simulation time 8403801284 ps
CPU time 7.13 seconds
Started Mar 10 01:57:11 PM PDT 24
Finished Mar 10 01:57:18 PM PDT 24
Peak memory 202552 kb
Host smart-8c0e02b0-afa2-4039-b168-f13e6aa3f72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39471
8524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.394718524
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3097271838
Short name T246
Test name
Test status
Simulation time 8361174103 ps
CPU time 9.65 seconds
Started Mar 10 01:57:13 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 202556 kb
Host smart-88cab26e-d8ae-4ad7-b96b-7e58395dc5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30972
71838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3097271838
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.4213586264
Short name T86
Test name
Test status
Simulation time 8396149379 ps
CPU time 7.86 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202560 kb
Host smart-27316d5d-07a6-4d6d-aa50-473a0f1d3313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
86264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.4213586264
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.449392095
Short name T429
Test name
Test status
Simulation time 8404922261 ps
CPU time 7.6 seconds
Started Mar 10 01:57:14 PM PDT 24
Finished Mar 10 01:57:22 PM PDT 24
Peak memory 202556 kb
Host smart-ad7f9624-92e1-4aad-a8e3-f1f9fe92b69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44939
2095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.449392095
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3053232879
Short name T517
Test name
Test status
Simulation time 22401130 ps
CPU time 0.62 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:13 PM PDT 24
Peak memory 202488 kb
Host smart-f362cd02-6d4e-4869-ab85-d5bd96c8b3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
32879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3053232879
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.956290038
Short name T122
Test name
Test status
Simulation time 8420871036 ps
CPU time 8.1 seconds
Started Mar 10 01:57:15 PM PDT 24
Finished Mar 10 01:57:24 PM PDT 24
Peak memory 202556 kb
Host smart-cb591bad-8f0d-48d3-bb48-11b55ec30560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95629
0038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.956290038
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2619031635
Short name T685
Test name
Test status
Simulation time 8377155698 ps
CPU time 6.99 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:19 PM PDT 24
Peak memory 202520 kb
Host smart-e6d8642d-fe3b-4ec8-8529-edf5b661c32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26190
31635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2619031635
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2848270019
Short name T12
Test name
Test status
Simulation time 8359152406 ps
CPU time 7.33 seconds
Started Mar 10 01:57:13 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202576 kb
Host smart-2ab9492d-bda8-41b2-a967-e267a918a777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28482
70019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2848270019
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.924171637
Short name T159
Test name
Test status
Simulation time 8472285754 ps
CPU time 8.72 seconds
Started Mar 10 01:57:09 PM PDT 24
Finished Mar 10 01:57:18 PM PDT 24
Peak memory 202512 kb
Host smart-fffa9624-9d74-496c-9110-2af96c2e8ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92417
1637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.924171637
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.493957287
Short name T251
Test name
Test status
Simulation time 8366943928 ps
CPU time 7.95 seconds
Started Mar 10 01:57:14 PM PDT 24
Finished Mar 10 01:57:22 PM PDT 24
Peak memory 202520 kb
Host smart-faabc462-d0cc-423c-ab79-907a4454413a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49395
7287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.493957287
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3654926647
Short name T364
Test name
Test status
Simulation time 188785589 ps
CPU time 2.07 seconds
Started Mar 10 01:57:14 PM PDT 24
Finished Mar 10 01:57:16 PM PDT 24
Peak memory 202204 kb
Host smart-84b51947-e513-491c-9b6b-67bcba82dc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36549
26647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3654926647
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.436576380
Short name T133
Test name
Test status
Simulation time 8384548570 ps
CPU time 7.79 seconds
Started Mar 10 01:57:13 PM PDT 24
Finished Mar 10 01:57:21 PM PDT 24
Peak memory 202516 kb
Host smart-be211c4d-78f6-47a0-8e58-afe04bbb8486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43657
6380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.436576380
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2813022942
Short name T320
Test name
Test status
Simulation time 8405356812 ps
CPU time 8.83 seconds
Started Mar 10 01:57:13 PM PDT 24
Finished Mar 10 01:57:22 PM PDT 24
Peak memory 202580 kb
Host smart-4877f26e-bc66-4d31-af6a-f462079fa8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28130
22942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2813022942
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.4214799234
Short name T667
Test name
Test status
Simulation time 8363929796 ps
CPU time 7.42 seconds
Started Mar 10 01:57:11 PM PDT 24
Finished Mar 10 01:57:19 PM PDT 24
Peak memory 202560 kb
Host smart-4a468b42-4522-423a-840f-22ab702996c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42147
99234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.4214799234
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3605749820
Short name T438
Test name
Test status
Simulation time 8425056897 ps
CPU time 7.79 seconds
Started Mar 10 01:57:14 PM PDT 24
Finished Mar 10 01:57:22 PM PDT 24
Peak memory 202200 kb
Host smart-96dbf754-c82f-42f7-8534-3402a7eefc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36057
49820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3605749820
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2232216507
Short name T514
Test name
Test status
Simulation time 8389983307 ps
CPU time 7.74 seconds
Started Mar 10 01:57:14 PM PDT 24
Finished Mar 10 01:57:22 PM PDT 24
Peak memory 202520 kb
Host smart-f4a34607-7df3-4546-9715-6edbe14474c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322
16507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2232216507
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1982481429
Short name T427
Test name
Test status
Simulation time 8370448768 ps
CPU time 7.41 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202580 kb
Host smart-988578ad-a6b8-469a-b7ee-6fae16ca05d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19824
81429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1982481429
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1990677589
Short name T29
Test name
Test status
Simulation time 23606308 ps
CPU time 0.63 seconds
Started Mar 10 01:57:11 PM PDT 24
Finished Mar 10 01:57:11 PM PDT 24
Peak memory 202520 kb
Host smart-30bb2d04-b602-4e6f-a6a4-878692f89fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19906
77589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1990677589
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.965387587
Short name T288
Test name
Test status
Simulation time 8426241788 ps
CPU time 9.16 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:22 PM PDT 24
Peak memory 202460 kb
Host smart-be0206fc-6eb2-4054-a120-b489545404cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96538
7587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.965387587
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3792673768
Short name T562
Test name
Test status
Simulation time 8397613682 ps
CPU time 7.78 seconds
Started Mar 10 01:57:12 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202576 kb
Host smart-6584cbb2-7da2-41ad-b914-ef8d6fd88c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37926
73768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3792673768
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.736453382
Short name T387
Test name
Test status
Simulation time 8357413608 ps
CPU time 8.55 seconds
Started Mar 10 01:57:15 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 202480 kb
Host smart-ad2b46fd-ace3-4465-8087-e3ff9cf58c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73645
3382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.736453382
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1287055513
Short name T41
Test name
Test status
Simulation time 8364550513 ps
CPU time 9.41 seconds
Started Mar 10 01:57:17 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 202588 kb
Host smart-ae41cea0-e7d5-420d-b0f4-2596242d1f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12870
55513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1287055513
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2676771216
Short name T332
Test name
Test status
Simulation time 163104937 ps
CPU time 1.87 seconds
Started Mar 10 01:57:16 PM PDT 24
Finished Mar 10 01:57:18 PM PDT 24
Peak memory 202576 kb
Host smart-d85dea62-e951-440b-a71c-5a19e477e240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26767
71216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2676771216
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.4192772297
Short name T413
Test name
Test status
Simulation time 8413348684 ps
CPU time 7.01 seconds
Started Mar 10 01:57:17 PM PDT 24
Finished Mar 10 01:57:24 PM PDT 24
Peak memory 202572 kb
Host smart-d0f3d09e-915d-4775-866f-7dfa839a2c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41927
72297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.4192772297
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2881160489
Short name T575
Test name
Test status
Simulation time 8409720645 ps
CPU time 7.18 seconds
Started Mar 10 01:57:15 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 202600 kb
Host smart-0fe71bdd-e588-4d53-91c8-e92931746e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28811
60489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2881160489
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3224921063
Short name T260
Test name
Test status
Simulation time 8367955088 ps
CPU time 7.82 seconds
Started Mar 10 01:57:16 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 202588 kb
Host smart-a87ee56b-3935-46c1-bce6-f08c72c3aefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32249
21063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3224921063
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.189054754
Short name T303
Test name
Test status
Simulation time 8371876275 ps
CPU time 9.47 seconds
Started Mar 10 01:57:16 PM PDT 24
Finished Mar 10 01:57:25 PM PDT 24
Peak memory 202536 kb
Host smart-ee0f9719-dfb6-4400-958e-c32febd77d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18905
4754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.189054754
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1148739692
Short name T657
Test name
Test status
Simulation time 8380060230 ps
CPU time 7.71 seconds
Started Mar 10 01:57:15 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 202564 kb
Host smart-c2323b47-89bc-4b72-a061-354761f64be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11487
39692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1148739692
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.287718725
Short name T599
Test name
Test status
Simulation time 31291538 ps
CPU time 0.64 seconds
Started Mar 10 01:57:18 PM PDT 24
Finished Mar 10 01:57:19 PM PDT 24
Peak memory 202492 kb
Host smart-2ab85b81-02be-4aaf-97e7-6785216dd7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28771
8725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.287718725
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1893213108
Short name T462
Test name
Test status
Simulation time 8410538379 ps
CPU time 7.11 seconds
Started Mar 10 01:57:23 PM PDT 24
Finished Mar 10 01:57:31 PM PDT 24
Peak memory 202476 kb
Host smart-d1649a9c-e65a-4e82-af21-dc36886b7bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18932
13108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1893213108
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2989730303
Short name T3
Test name
Test status
Simulation time 8369269645 ps
CPU time 8.02 seconds
Started Mar 10 01:57:19 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 202524 kb
Host smart-dc1f3be8-d670-44d1-a7ca-8cf7287a5418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29897
30303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2989730303
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2927411731
Short name T479
Test name
Test status
Simulation time 8358651503 ps
CPU time 7.56 seconds
Started Mar 10 01:57:18 PM PDT 24
Finished Mar 10 01:57:25 PM PDT 24
Peak memory 202568 kb
Host smart-5321a8a8-ce6d-4695-96de-77f19b68d3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29274
11731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2927411731
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1085690398
Short name T155
Test name
Test status
Simulation time 8474201308 ps
CPU time 8.74 seconds
Started Mar 10 01:57:14 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 202620 kb
Host smart-7d00b6cc-bb96-4e94-a1f6-581877ccd36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10856
90398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1085690398
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2807044873
Short name T612
Test name
Test status
Simulation time 8368765149 ps
CPU time 7.31 seconds
Started Mar 10 01:57:17 PM PDT 24
Finished Mar 10 01:57:24 PM PDT 24
Peak memory 202568 kb
Host smart-ab5f66b1-1acd-49f4-8c01-67324472f135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28070
44873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2807044873
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2980944342
Short name T614
Test name
Test status
Simulation time 183304886 ps
CPU time 1.62 seconds
Started Mar 10 01:57:18 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202504 kb
Host smart-de8873f1-f2ac-42b7-91d1-ca0348cb6958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29809
44342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2980944342
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1970135675
Short name T390
Test name
Test status
Simulation time 8440088085 ps
CPU time 9.42 seconds
Started Mar 10 01:57:23 PM PDT 24
Finished Mar 10 01:57:33 PM PDT 24
Peak memory 202432 kb
Host smart-a3d19e0c-a9a2-448d-9381-0452d757b827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19701
35675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1970135675
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2222776770
Short name T569
Test name
Test status
Simulation time 8404148224 ps
CPU time 7.08 seconds
Started Mar 10 01:57:15 PM PDT 24
Finished Mar 10 01:57:22 PM PDT 24
Peak memory 202556 kb
Host smart-0bc61dc1-2a34-4936-b839-d5fbda8386d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22227
76770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2222776770
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.53518414
Short name T410
Test name
Test status
Simulation time 8364504764 ps
CPU time 7.98 seconds
Started Mar 10 01:57:23 PM PDT 24
Finished Mar 10 01:57:32 PM PDT 24
Peak memory 202420 kb
Host smart-fce3fb78-cabb-4c1a-b966-6a2bb2e178dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53518
414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.53518414
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.4008524277
Short name T474
Test name
Test status
Simulation time 8375631065 ps
CPU time 9.05 seconds
Started Mar 10 01:57:18 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 202572 kb
Host smart-7c1fd778-fcd3-4fc0-a6bc-445219e98441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40085
24277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.4008524277
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1347885416
Short name T654
Test name
Test status
Simulation time 8395509788 ps
CPU time 7.12 seconds
Started Mar 10 01:57:19 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 202500 kb
Host smart-9a6347e6-2299-4e21-8d27-2c8b1f18058e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13478
85416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1347885416
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.536565074
Short name T402
Test name
Test status
Simulation time 30754340 ps
CPU time 0.61 seconds
Started Mar 10 01:57:19 PM PDT 24
Finished Mar 10 01:57:20 PM PDT 24
Peak memory 202532 kb
Host smart-b0b04c64-489d-48e7-92c7-43b6ecd9c622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53656
5074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.536565074
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1341801586
Short name T604
Test name
Test status
Simulation time 8415751006 ps
CPU time 8.09 seconds
Started Mar 10 01:57:20 PM PDT 24
Finished Mar 10 01:57:29 PM PDT 24
Peak memory 202496 kb
Host smart-cddcc16a-60b8-4f78-8dc1-16e1d4ff4359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13418
01586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1341801586
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.2797943061
Short name T389
Test name
Test status
Simulation time 8376010260 ps
CPU time 6.95 seconds
Started Mar 10 01:57:20 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 202564 kb
Host smart-8007b659-4120-4fc5-b7fe-b0804d1293c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27979
43061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.2797943061
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.2153482339
Short name T714
Test name
Test status
Simulation time 8359106515 ps
CPU time 8.07 seconds
Started Mar 10 01:57:21 PM PDT 24
Finished Mar 10 01:57:29 PM PDT 24
Peak memory 202472 kb
Host smart-a430c6dc-e063-4cf5-9a34-11ffa4148d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21534
82339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.2153482339
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2116974474
Short name T433
Test name
Test status
Simulation time 8476160371 ps
CPU time 8.1 seconds
Started Mar 10 01:57:20 PM PDT 24
Finished Mar 10 01:57:28 PM PDT 24
Peak memory 202556 kb
Host smart-f64cfb31-781f-4da3-9189-bc238943ba7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21169
74474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2116974474
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1461107109
Short name T528
Test name
Test status
Simulation time 8373901973 ps
CPU time 10.03 seconds
Started Mar 10 01:57:21 PM PDT 24
Finished Mar 10 01:57:31 PM PDT 24
Peak memory 202576 kb
Host smart-a186c360-eeed-4304-97b9-1abb92185871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14611
07109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1461107109
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.4011450372
Short name T207
Test name
Test status
Simulation time 257451227 ps
CPU time 2.3 seconds
Started Mar 10 01:57:21 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 202564 kb
Host smart-f1cfefee-dd6c-41b5-af17-e49a3fa137f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40114
50372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.4011450372
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3897344971
Short name T120
Test name
Test status
Simulation time 8381967667 ps
CPU time 8.72 seconds
Started Mar 10 01:57:21 PM PDT 24
Finished Mar 10 01:57:30 PM PDT 24
Peak memory 202576 kb
Host smart-64c5d7e7-fcd6-4a73-a41f-5071cf0d888f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38973
44971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3897344971
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3358956614
Short name T686
Test name
Test status
Simulation time 8406370079 ps
CPU time 7.23 seconds
Started Mar 10 01:57:23 PM PDT 24
Finished Mar 10 01:57:30 PM PDT 24
Peak memory 202576 kb
Host smart-26254854-e198-49ed-8804-b4c0465e78ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33589
56614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3358956614
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3935128380
Short name T486
Test name
Test status
Simulation time 8362893633 ps
CPU time 7.67 seconds
Started Mar 10 01:57:21 PM PDT 24
Finished Mar 10 01:57:29 PM PDT 24
Peak memory 202520 kb
Host smart-a1851332-6beb-4863-926e-a4e7dfdfa1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39351
28380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3935128380
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.851364362
Short name T105
Test name
Test status
Simulation time 8451924778 ps
CPU time 8.25 seconds
Started Mar 10 01:57:19 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 202572 kb
Host smart-1acfff76-fbf1-4b4c-86c7-05d4138dd153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85136
4362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.851364362
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.282104940
Short name T311
Test name
Test status
Simulation time 8371188306 ps
CPU time 8.87 seconds
Started Mar 10 01:57:21 PM PDT 24
Finished Mar 10 01:57:30 PM PDT 24
Peak memory 202552 kb
Host smart-ead5c2c7-0693-4654-9b0d-5c36a222651c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28210
4940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.282104940
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2607221504
Short name T321
Test name
Test status
Simulation time 8399471231 ps
CPU time 7.13 seconds
Started Mar 10 01:57:21 PM PDT 24
Finished Mar 10 01:57:28 PM PDT 24
Peak memory 202484 kb
Host smart-5c2caaf7-e6bc-4cc6-aa57-0a5609a8d339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26072
21504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2607221504
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1379650020
Short name T561
Test name
Test status
Simulation time 31758810 ps
CPU time 0.63 seconds
Started Mar 10 01:57:22 PM PDT 24
Finished Mar 10 01:57:23 PM PDT 24
Peak memory 202500 kb
Host smart-4f4cb00e-1e78-4132-87f6-5b94b06479af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13796
50020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1379650020
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2150037333
Short name T126
Test name
Test status
Simulation time 8380906952 ps
CPU time 7.25 seconds
Started Mar 10 01:57:19 PM PDT 24
Finished Mar 10 01:57:26 PM PDT 24
Peak memory 202532 kb
Host smart-7929731b-8413-47ba-a9e2-84bdf2a62829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21500
37333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2150037333
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.2460822003
Short name T513
Test name
Test status
Simulation time 8383097775 ps
CPU time 7.21 seconds
Started Mar 10 01:57:23 PM PDT 24
Finished Mar 10 01:57:30 PM PDT 24
Peak memory 202576 kb
Host smart-b0c226d1-ba15-4b46-aed5-1e50df5e2076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24608
22003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.2460822003
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1139121201
Short name T447
Test name
Test status
Simulation time 8359927634 ps
CPU time 7.85 seconds
Started Mar 10 01:57:20 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 202568 kb
Host smart-11e68314-0666-4d3c-915b-568e037ba6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11391
21201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1139121201
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.487091570
Short name T590
Test name
Test status
Simulation time 8474259211 ps
CPU time 9.74 seconds
Started Mar 10 01:57:19 PM PDT 24
Finished Mar 10 01:57:29 PM PDT 24
Peak memory 202596 kb
Host smart-79e7e463-7bb5-4afd-a711-2e7fb58bd4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48709
1570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.487091570
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2848846983
Short name T411
Test name
Test status
Simulation time 8369667294 ps
CPU time 7.42 seconds
Started Mar 10 01:57:21 PM PDT 24
Finished Mar 10 01:57:29 PM PDT 24
Peak memory 202568 kb
Host smart-978c411e-c48c-4ea7-8dc9-d483ff3efdf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28488
46983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2848846983
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1205532004
Short name T696
Test name
Test status
Simulation time 306546020 ps
CPU time 2.47 seconds
Started Mar 10 01:57:24 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 202588 kb
Host smart-92a34e69-ffbc-460a-9829-2f7fa6e39665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12055
32004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1205532004
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2425290234
Short name T124
Test name
Test status
Simulation time 8431280062 ps
CPU time 7.27 seconds
Started Mar 10 01:57:20 PM PDT 24
Finished Mar 10 01:57:28 PM PDT 24
Peak memory 202652 kb
Host smart-d0986ecb-0510-4f89-bb9a-d0373901f46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24252
90234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2425290234
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2791764590
Short name T278
Test name
Test status
Simulation time 8409604914 ps
CPU time 7.59 seconds
Started Mar 10 01:57:24 PM PDT 24
Finished Mar 10 01:57:32 PM PDT 24
Peak memory 202580 kb
Host smart-9a6e4d10-f554-4252-9157-2354631bf806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27917
64590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2791764590
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1170883896
Short name T704
Test name
Test status
Simulation time 8364427389 ps
CPU time 7.65 seconds
Started Mar 10 01:57:24 PM PDT 24
Finished Mar 10 01:57:32 PM PDT 24
Peak memory 202580 kb
Host smart-054ca895-1317-45c6-812d-2065a3aa84a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11708
83896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1170883896
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2333377157
Short name T404
Test name
Test status
Simulation time 8403288182 ps
CPU time 7.16 seconds
Started Mar 10 01:57:27 PM PDT 24
Finished Mar 10 01:57:34 PM PDT 24
Peak memory 202588 kb
Host smart-5dac9be5-3e6c-487f-aa3b-f7014420beb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23333
77157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2333377157
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.1797625041
Short name T393
Test name
Test status
Simulation time 8390906513 ps
CPU time 7.38 seconds
Started Mar 10 01:57:26 PM PDT 24
Finished Mar 10 01:57:33 PM PDT 24
Peak memory 202548 kb
Host smart-2002622a-47f2-4235-9bea-490bb9c400bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17976
25041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.1797625041
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2914773939
Short name T352
Test name
Test status
Simulation time 26281271 ps
CPU time 0.66 seconds
Started Mar 10 01:57:25 PM PDT 24
Finished Mar 10 01:57:26 PM PDT 24
Peak memory 202492 kb
Host smart-b4df513c-bb0c-4333-8602-41e20ad23645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29147
73939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2914773939
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.4090588496
Short name T636
Test name
Test status
Simulation time 8407114216 ps
CPU time 7.57 seconds
Started Mar 10 01:57:24 PM PDT 24
Finished Mar 10 01:57:33 PM PDT 24
Peak memory 202564 kb
Host smart-edab25a6-2d65-4d99-9dbf-d1de37f75182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40905
88496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.4090588496
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.1512168761
Short name T335
Test name
Test status
Simulation time 8381660147 ps
CPU time 8 seconds
Started Mar 10 01:57:26 PM PDT 24
Finished Mar 10 01:57:35 PM PDT 24
Peak memory 202576 kb
Host smart-63043c1f-4756-4d1b-a9ce-5ad754463bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15121
68761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.1512168761
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.4056718542
Short name T400
Test name
Test status
Simulation time 8361448763 ps
CPU time 7.3 seconds
Started Mar 10 01:57:24 PM PDT 24
Finished Mar 10 01:57:33 PM PDT 24
Peak memory 202584 kb
Host smart-c1c44f7a-fb50-483e-a2fc-19ca862249e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40567
18542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.4056718542
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.459168505
Short name T43
Test name
Test status
Simulation time 8475238291 ps
CPU time 7.72 seconds
Started Mar 10 01:57:23 PM PDT 24
Finished Mar 10 01:57:30 PM PDT 24
Peak memory 202604 kb
Host smart-85580e03-42be-4f40-bdc1-284b46fb6de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45916
8505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.459168505
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.952948433
Short name T618
Test name
Test status
Simulation time 8365060223 ps
CPU time 7.32 seconds
Started Mar 10 01:57:24 PM PDT 24
Finished Mar 10 01:57:33 PM PDT 24
Peak memory 202572 kb
Host smart-cb08484d-924b-4932-b275-c7d998f5d49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95294
8433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.952948433
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.649274834
Short name T77
Test name
Test status
Simulation time 69168554 ps
CPU time 1.94 seconds
Started Mar 10 01:57:32 PM PDT 24
Finished Mar 10 01:57:34 PM PDT 24
Peak memory 202548 kb
Host smart-7c45e148-52a7-40ac-acfc-4a1c794dd1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64927
4834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.649274834
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3240044273
Short name T394
Test name
Test status
Simulation time 8379905500 ps
CPU time 7.28 seconds
Started Mar 10 01:57:33 PM PDT 24
Finished Mar 10 01:57:40 PM PDT 24
Peak memory 202560 kb
Host smart-7350d358-c229-49e5-9f64-5dbee9d3a4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32400
44273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3240044273
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2648756617
Short name T568
Test name
Test status
Simulation time 8405109791 ps
CPU time 7.33 seconds
Started Mar 10 01:57:30 PM PDT 24
Finished Mar 10 01:57:37 PM PDT 24
Peak memory 202556 kb
Host smart-1474ece0-8d2a-491c-b280-3cf2093a63e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26487
56617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2648756617
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2129695541
Short name T709
Test name
Test status
Simulation time 8365939668 ps
CPU time 9.81 seconds
Started Mar 10 01:57:30 PM PDT 24
Finished Mar 10 01:57:40 PM PDT 24
Peak memory 202484 kb
Host smart-5a677b31-1c3e-41c9-a882-2526346fed7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21296
95541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2129695541
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1922018813
Short name T28
Test name
Test status
Simulation time 8430194853 ps
CPU time 7.36 seconds
Started Mar 10 01:57:31 PM PDT 24
Finished Mar 10 01:57:39 PM PDT 24
Peak memory 202588 kb
Host smart-c683a318-ee8e-4d3a-9f3d-d3e9dc0f6ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19220
18813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1922018813
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1166131313
Short name T493
Test name
Test status
Simulation time 8377690723 ps
CPU time 9 seconds
Started Mar 10 01:57:31 PM PDT 24
Finished Mar 10 01:57:40 PM PDT 24
Peak memory 202560 kb
Host smart-50157f2e-74b9-4472-9905-8dbc9ed59d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11661
31313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1166131313
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2769665313
Short name T192
Test name
Test status
Simulation time 8399906270 ps
CPU time 9.75 seconds
Started Mar 10 01:57:29 PM PDT 24
Finished Mar 10 01:57:39 PM PDT 24
Peak memory 202472 kb
Host smart-252db13a-26bb-47a0-96f8-b4f27f4bcba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27696
65313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2769665313
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3417439713
Short name T703
Test name
Test status
Simulation time 29505291 ps
CPU time 0.63 seconds
Started Mar 10 01:57:30 PM PDT 24
Finished Mar 10 01:57:31 PM PDT 24
Peak memory 202488 kb
Host smart-a7483590-6f9b-47bd-9eef-ac23f03b9387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34174
39713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3417439713
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.4195762398
Short name T131
Test name
Test status
Simulation time 8422219615 ps
CPU time 7.73 seconds
Started Mar 10 01:57:30 PM PDT 24
Finished Mar 10 01:57:38 PM PDT 24
Peak memory 202540 kb
Host smart-2b547afc-c2cb-4487-8e24-b07eccd49ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41957
62398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.4195762398
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2241563400
Short name T273
Test name
Test status
Simulation time 8392311471 ps
CPU time 9.16 seconds
Started Mar 10 01:57:39 PM PDT 24
Finished Mar 10 01:57:49 PM PDT 24
Peak memory 202536 kb
Host smart-bff7407f-edde-4648-9042-8dba7ee21372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22415
63400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2241563400
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3823829736
Short name T391
Test name
Test status
Simulation time 8359038584 ps
CPU time 7.31 seconds
Started Mar 10 01:57:31 PM PDT 24
Finished Mar 10 01:57:38 PM PDT 24
Peak memory 202604 kb
Host smart-24ca0951-9e7f-4b1a-9221-c456c2c51833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38238
29736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3823829736
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.4270702905
Short name T38
Test name
Test status
Simulation time 8476536910 ps
CPU time 7.97 seconds
Started Mar 10 01:57:26 PM PDT 24
Finished Mar 10 01:57:35 PM PDT 24
Peak memory 202604 kb
Host smart-35a843f5-4ff0-4f74-a0f9-9ec2c6847d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42707
02905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.4270702905
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2310123047
Short name T671
Test name
Test status
Simulation time 8369775074 ps
CPU time 7.28 seconds
Started Mar 10 01:57:31 PM PDT 24
Finished Mar 10 01:57:38 PM PDT 24
Peak memory 202480 kb
Host smart-af9335dc-64d7-49fe-bf02-2d23b2f76724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23101
23047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2310123047
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3135708270
Short name T372
Test name
Test status
Simulation time 114655335 ps
CPU time 1.47 seconds
Started Mar 10 01:57:29 PM PDT 24
Finished Mar 10 01:57:31 PM PDT 24
Peak memory 202636 kb
Host smart-2c1c9b3f-a549-48a2-90e3-fcdbb49b70fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
08270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3135708270
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3956277172
Short name T116
Test name
Test status
Simulation time 8429373527 ps
CPU time 7.68 seconds
Started Mar 10 01:57:31 PM PDT 24
Finished Mar 10 01:57:39 PM PDT 24
Peak memory 202556 kb
Host smart-b13e7f67-ca2f-451c-97ea-385ee47a866f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39562
77172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3956277172
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.4264251557
Short name T472
Test name
Test status
Simulation time 8404621580 ps
CPU time 8.7 seconds
Started Mar 10 01:57:28 PM PDT 24
Finished Mar 10 01:57:37 PM PDT 24
Peak memory 202576 kb
Host smart-feadeb7a-af9f-4c1c-8c91-e74e9e005625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642
51557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.4264251557
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3681902665
Short name T277
Test name
Test status
Simulation time 8368636366 ps
CPU time 9.54 seconds
Started Mar 10 01:57:32 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202588 kb
Host smart-dfd54856-77af-4767-83a1-c79f53be50b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36819
02665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3681902665
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2705068158
Short name T326
Test name
Test status
Simulation time 8368625010 ps
CPU time 7.18 seconds
Started Mar 10 01:57:38 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202508 kb
Host smart-8a6d9182-f9b0-4e9d-ad4f-de02365bbda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27050
68158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2705068158
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3890415685
Short name T396
Test name
Test status
Simulation time 8373201821 ps
CPU time 8.64 seconds
Started Mar 10 01:57:32 PM PDT 24
Finished Mar 10 01:57:41 PM PDT 24
Peak memory 202588 kb
Host smart-8637f8d7-0f94-4bd8-8d9e-be47ec01f014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38904
15685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3890415685
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.4089028369
Short name T615
Test name
Test status
Simulation time 24093149 ps
CPU time 0.64 seconds
Started Mar 10 01:57:37 PM PDT 24
Finished Mar 10 01:57:37 PM PDT 24
Peak memory 202404 kb
Host smart-50d3f1a8-ed19-4966-b071-f7fb5619812d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40890
28369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.4089028369
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2088614240
Short name T565
Test name
Test status
Simulation time 8397804102 ps
CPU time 7.84 seconds
Started Mar 10 01:57:32 PM PDT 24
Finished Mar 10 01:57:40 PM PDT 24
Peak memory 202536 kb
Host smart-ddb48e5a-2ada-486f-9eaa-df18d8134e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20886
14240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2088614240
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1673285944
Short name T487
Test name
Test status
Simulation time 8403294174 ps
CPU time 8.47 seconds
Started Mar 10 01:57:32 PM PDT 24
Finished Mar 10 01:57:41 PM PDT 24
Peak memory 202564 kb
Host smart-6e17751c-4a18-4952-bde8-012775b4776d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16732
85944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1673285944
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.349857413
Short name T456
Test name
Test status
Simulation time 8358407045 ps
CPU time 8.33 seconds
Started Mar 10 01:57:30 PM PDT 24
Finished Mar 10 01:57:39 PM PDT 24
Peak memory 202576 kb
Host smart-5bb7a0b8-dcd7-43ee-9da8-8ff785aad2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34985
7413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.349857413
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2335949999
Short name T150
Test name
Test status
Simulation time 8476268763 ps
CPU time 7.15 seconds
Started Mar 10 01:57:28 PM PDT 24
Finished Mar 10 01:57:36 PM PDT 24
Peak memory 202580 kb
Host smart-435a56ee-dd50-4a43-b853-a92fd6ca7827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23359
49999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2335949999
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.131989873
Short name T680
Test name
Test status
Simulation time 8368168597 ps
CPU time 7.18 seconds
Started Mar 10 01:56:15 PM PDT 24
Finished Mar 10 01:56:23 PM PDT 24
Peak memory 202480 kb
Host smart-03f7a5bc-e780-478a-ae38-050d5f694490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13198
9873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.131989873
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2427347380
Short name T265
Test name
Test status
Simulation time 146700059 ps
CPU time 1.39 seconds
Started Mar 10 01:56:13 PM PDT 24
Finished Mar 10 01:56:15 PM PDT 24
Peak memory 202444 kb
Host smart-336a1651-c262-4219-a7f1-4b3bde0815d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24273
47380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2427347380
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1534049057
Short name T269
Test name
Test status
Simulation time 8397263837 ps
CPU time 8.85 seconds
Started Mar 10 01:56:18 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202576 kb
Host smart-efbcb477-fded-4594-8718-88002d100312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15340
49057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1534049057
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3266201037
Short name T365
Test name
Test status
Simulation time 8403033386 ps
CPU time 8.01 seconds
Started Mar 10 01:56:14 PM PDT 24
Finished Mar 10 01:56:22 PM PDT 24
Peak memory 202536 kb
Host smart-48333b18-e73c-4cd6-84bb-d76f65745ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
01037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3266201037
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2553683972
Short name T553
Test name
Test status
Simulation time 8363688313 ps
CPU time 7.61 seconds
Started Mar 10 01:56:15 PM PDT 24
Finished Mar 10 01:56:23 PM PDT 24
Peak memory 202588 kb
Host smart-25e4038e-7305-4cc3-b0d6-f10217068bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25536
83972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2553683972
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3914854853
Short name T340
Test name
Test status
Simulation time 8450787271 ps
CPU time 7.67 seconds
Started Mar 10 01:56:15 PM PDT 24
Finished Mar 10 01:56:23 PM PDT 24
Peak memory 202508 kb
Host smart-571a6e17-2cd3-4d90-b32a-378c43a3e47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
54853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3914854853
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2449041508
Short name T336
Test name
Test status
Simulation time 8401376007 ps
CPU time 8.13 seconds
Started Mar 10 01:56:18 PM PDT 24
Finished Mar 10 01:56:26 PM PDT 24
Peak memory 202428 kb
Host smart-91b17434-6358-4b6a-a19f-6d84b08df07c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24490
41508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2449041508
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.72224219
Short name T386
Test name
Test status
Simulation time 8378941969 ps
CPU time 7.74 seconds
Started Mar 10 01:56:13 PM PDT 24
Finished Mar 10 01:56:21 PM PDT 24
Peak memory 202524 kb
Host smart-59b7501f-4903-4454-a742-2a811b778497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72224
219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.72224219
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2457742208
Short name T651
Test name
Test status
Simulation time 30412966 ps
CPU time 0.62 seconds
Started Mar 10 01:56:13 PM PDT 24
Finished Mar 10 01:56:15 PM PDT 24
Peak memory 202492 kb
Host smart-f5b608bf-8df4-42f9-afd7-2a730551ca14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24577
42208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2457742208
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3692681089
Short name T473
Test name
Test status
Simulation time 8410604627 ps
CPU time 7.86 seconds
Started Mar 10 01:56:13 PM PDT 24
Finished Mar 10 01:56:22 PM PDT 24
Peak memory 202544 kb
Host smart-6bca417d-9e4b-4626-a8f1-da1e0e956ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36926
81089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3692681089
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3152706241
Short name T492
Test name
Test status
Simulation time 8382579012 ps
CPU time 8.51 seconds
Started Mar 10 01:56:24 PM PDT 24
Finished Mar 10 01:56:34 PM PDT 24
Peak memory 202368 kb
Host smart-fb0cf529-6603-4c09-b1fc-e092517e5a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31527
06241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3152706241
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3212441462
Short name T69
Test name
Test status
Simulation time 94975943 ps
CPU time 0.9 seconds
Started Mar 10 01:56:23 PM PDT 24
Finished Mar 10 01:56:26 PM PDT 24
Peak memory 217376 kb
Host smart-e21b0de5-44c2-452f-879b-faa6e9be05f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3212441462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3212441462
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1666500980
Short name T658
Test name
Test status
Simulation time 8359802930 ps
CPU time 7.67 seconds
Started Mar 10 01:56:24 PM PDT 24
Finished Mar 10 01:56:32 PM PDT 24
Peak memory 202456 kb
Host smart-0745eb2b-ba89-4372-8980-d8e98d23a6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16665
00980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1666500980
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2025080519
Short name T623
Test name
Test status
Simulation time 8469155834 ps
CPU time 7.51 seconds
Started Mar 10 01:56:18 PM PDT 24
Finished Mar 10 01:56:26 PM PDT 24
Peak memory 202484 kb
Host smart-57b1d7df-0a37-4770-9658-6c703edd272f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20250
80519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2025080519
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2110009776
Short name T307
Test name
Test status
Simulation time 8366398793 ps
CPU time 7.64 seconds
Started Mar 10 01:57:37 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202568 kb
Host smart-3e81d985-bfde-4d2d-a641-b1b7ec4d39ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21100
09776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2110009776
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.987800344
Short name T542
Test name
Test status
Simulation time 44124273 ps
CPU time 1.33 seconds
Started Mar 10 01:57:38 PM PDT 24
Finished Mar 10 01:57:39 PM PDT 24
Peak memory 202580 kb
Host smart-9c3e7a43-7a90-4ac2-a072-e2f57d4063b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98780
0344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.987800344
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2660458836
Short name T113
Test name
Test status
Simulation time 8395421800 ps
CPU time 7.83 seconds
Started Mar 10 01:57:38 PM PDT 24
Finished Mar 10 01:57:46 PM PDT 24
Peak memory 202556 kb
Host smart-de914a0b-e2bf-4fc9-b400-c7a459939e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26604
58836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2660458836
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1629606026
Short name T621
Test name
Test status
Simulation time 8407934724 ps
CPU time 7.8 seconds
Started Mar 10 01:57:34 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202520 kb
Host smart-bc6ec072-c8fa-49f5-89b4-996260f870af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16296
06026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1629606026
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2965924904
Short name T399
Test name
Test status
Simulation time 8361811900 ps
CPU time 7.84 seconds
Started Mar 10 01:57:34 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202580 kb
Host smart-e5c1a9f2-8ee7-4fa1-bd12-24f2ba17d555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29659
24904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2965924904
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2904432117
Short name T533
Test name
Test status
Simulation time 8407359132 ps
CPU time 9.62 seconds
Started Mar 10 01:57:32 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202564 kb
Host smart-edb2ea7d-260e-46f7-adb3-e9f86d20b1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29044
32117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2904432117
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3905219841
Short name T611
Test name
Test status
Simulation time 8380124796 ps
CPU time 8.3 seconds
Started Mar 10 01:57:34 PM PDT 24
Finished Mar 10 01:57:43 PM PDT 24
Peak memory 202560 kb
Host smart-43576390-b814-471f-ae2a-e923772978f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39052
19841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3905219841
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2850779970
Short name T324
Test name
Test status
Simulation time 8408588856 ps
CPU time 7.84 seconds
Started Mar 10 01:57:35 PM PDT 24
Finished Mar 10 01:57:43 PM PDT 24
Peak memory 202588 kb
Host smart-3a292589-39dd-4b4a-b29a-a13a59fcc782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28507
79970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2850779970
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2381152617
Short name T632
Test name
Test status
Simulation time 28567384 ps
CPU time 0.65 seconds
Started Mar 10 01:57:36 PM PDT 24
Finished Mar 10 01:57:37 PM PDT 24
Peak memory 202412 kb
Host smart-36ecd33e-d344-486a-a65d-070d40e3c23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23811
52617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2381152617
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1354604870
Short name T2
Test name
Test status
Simulation time 8460649415 ps
CPU time 7.66 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:48 PM PDT 24
Peak memory 202548 kb
Host smart-6ea8b24a-2b01-410e-9915-d52bbfcd9f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13546
04870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1354604870
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2538568063
Short name T356
Test name
Test status
Simulation time 8394803039 ps
CPU time 7.23 seconds
Started Mar 10 01:57:33 PM PDT 24
Finished Mar 10 01:57:40 PM PDT 24
Peak memory 202552 kb
Host smart-84f9caf9-5429-4cdd-b2c9-26b5ba2bf63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25385
68063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2538568063
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1710952795
Short name T515
Test name
Test status
Simulation time 8361893430 ps
CPU time 7.34 seconds
Started Mar 10 01:57:34 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202564 kb
Host smart-273df67f-5167-4d15-8a0e-da59ca469ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17109
52795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1710952795
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1560928114
Short name T142
Test name
Test status
Simulation time 8473581050 ps
CPU time 8.5 seconds
Started Mar 10 01:57:38 PM PDT 24
Finished Mar 10 01:57:46 PM PDT 24
Peak memory 202632 kb
Host smart-3a40e59a-5682-4738-b938-1b753fcbe260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15609
28114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1560928114
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1345252894
Short name T309
Test name
Test status
Simulation time 8368604879 ps
CPU time 7.17 seconds
Started Mar 10 01:57:36 PM PDT 24
Finished Mar 10 01:57:43 PM PDT 24
Peak memory 202564 kb
Host smart-85095539-d3bb-4874-8805-decedcac238d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
52894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1345252894
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2697426820
Short name T354
Test name
Test status
Simulation time 141809891 ps
CPU time 1.68 seconds
Started Mar 10 01:57:34 PM PDT 24
Finished Mar 10 01:57:36 PM PDT 24
Peak memory 202548 kb
Host smart-8d1ef93f-e5b8-4fd5-814d-4a96ac40338f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26974
26820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2697426820
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1690762977
Short name T490
Test name
Test status
Simulation time 8406126954 ps
CPU time 8 seconds
Started Mar 10 01:57:38 PM PDT 24
Finished Mar 10 01:57:46 PM PDT 24
Peak memory 202584 kb
Host smart-7f42436d-6f07-49c6-b689-4bd5b16bc687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16907
62977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1690762977
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1192877369
Short name T312
Test name
Test status
Simulation time 8365959516 ps
CPU time 9.44 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:50 PM PDT 24
Peak memory 202576 kb
Host smart-db7bb908-1103-4e48-b8ff-ed027e32242e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
77369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1192877369
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2614778830
Short name T475
Test name
Test status
Simulation time 8415450784 ps
CPU time 7.35 seconds
Started Mar 10 01:57:35 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202556 kb
Host smart-2e4ec280-bf42-47b5-8320-3a70312c5a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26147
78830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2614778830
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.314370824
Short name T449
Test name
Test status
Simulation time 8371230798 ps
CPU time 7.63 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:48 PM PDT 24
Peak memory 202548 kb
Host smart-d8ad4f08-7d27-4715-aa3b-f49a4469d6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31437
0824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.314370824
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.310487982
Short name T511
Test name
Test status
Simulation time 8392047844 ps
CPU time 7.12 seconds
Started Mar 10 01:57:37 PM PDT 24
Finished Mar 10 01:57:44 PM PDT 24
Peak memory 202480 kb
Host smart-7475a6bd-4266-47bd-bf8a-656c22804d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048
7982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.310487982
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.453766709
Short name T187
Test name
Test status
Simulation time 25315650 ps
CPU time 0.6 seconds
Started Mar 10 01:57:35 PM PDT 24
Finished Mar 10 01:57:35 PM PDT 24
Peak memory 202408 kb
Host smart-a73ead8a-7b72-4c66-9d10-c5d15738786b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45376
6709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.453766709
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2979181163
Short name T713
Test name
Test status
Simulation time 8386557364 ps
CPU time 7.56 seconds
Started Mar 10 01:57:37 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202572 kb
Host smart-7b5397c5-188c-460b-bb1a-f5b6370213a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29791
81163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2979181163
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.4152535707
Short name T17
Test name
Test status
Simulation time 8407010433 ps
CPU time 7.71 seconds
Started Mar 10 01:57:37 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202584 kb
Host smart-282e33fa-e705-47f9-9eae-c4a8fbd68d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525
35707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.4152535707
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1599921420
Short name T16
Test name
Test status
Simulation time 8359450448 ps
CPU time 7.47 seconds
Started Mar 10 01:57:38 PM PDT 24
Finished Mar 10 01:57:46 PM PDT 24
Peak memory 202536 kb
Host smart-ce8419c1-c27d-49a0-ba75-95d0dc5820f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15999
21420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1599921420
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1997248979
Short name T699
Test name
Test status
Simulation time 8367962333 ps
CPU time 7.71 seconds
Started Mar 10 01:57:35 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202588 kb
Host smart-217c1b37-b9f1-4325-8c60-c64c51b16889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19972
48979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1997248979
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2741290894
Short name T34
Test name
Test status
Simulation time 218661032 ps
CPU time 1.86 seconds
Started Mar 10 01:57:32 PM PDT 24
Finished Mar 10 01:57:34 PM PDT 24
Peak memory 202544 kb
Host smart-240e6f29-4243-4d00-a3b3-4baaee86a0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27412
90894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2741290894
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2126598656
Short name T272
Test name
Test status
Simulation time 8372726280 ps
CPU time 7.39 seconds
Started Mar 10 01:57:39 PM PDT 24
Finished Mar 10 01:57:47 PM PDT 24
Peak memory 202480 kb
Host smart-ec375204-c135-478e-b611-ca68c64d2ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21265
98656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2126598656
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2543912487
Short name T647
Test name
Test status
Simulation time 8406781860 ps
CPU time 8.53 seconds
Started Mar 10 01:57:33 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202616 kb
Host smart-d3c0cd93-8a84-42fa-b14b-8ae868fc6111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25439
12487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2543912487
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1124947641
Short name T710
Test name
Test status
Simulation time 8362232126 ps
CPU time 8.5 seconds
Started Mar 10 01:57:36 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202596 kb
Host smart-bfac0cdc-7f00-4d22-a60c-1d5c5646d25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11249
47641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1124947641
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1721264443
Short name T13
Test name
Test status
Simulation time 8393922142 ps
CPU time 8.21 seconds
Started Mar 10 01:57:36 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202492 kb
Host smart-83d92a69-d732-4273-9a37-930278ef91ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17212
64443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1721264443
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3424292227
Short name T422
Test name
Test status
Simulation time 8376691366 ps
CPU time 8.95 seconds
Started Mar 10 01:57:35 PM PDT 24
Finished Mar 10 01:57:44 PM PDT 24
Peak memory 202564 kb
Host smart-2463a67e-5267-48a4-846b-fed1444707ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34242
92227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3424292227
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3493117864
Short name T242
Test name
Test status
Simulation time 8399612454 ps
CPU time 7.54 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:52 PM PDT 24
Peak memory 202556 kb
Host smart-e17c0b25-aec4-4509-97a6-155a56404069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34931
17864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3493117864
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3245419331
Short name T314
Test name
Test status
Simulation time 25975756 ps
CPU time 0.65 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202496 kb
Host smart-9652f6bd-5cbe-463d-8b97-952b16b14fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32454
19331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3245419331
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.546835165
Short name T498
Test name
Test status
Simulation time 8415372213 ps
CPU time 7.59 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:47 PM PDT 24
Peak memory 202540 kb
Host smart-03a96d8e-c716-44f0-9bcc-2305dc04d2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54683
5165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.546835165
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.949576705
Short name T296
Test name
Test status
Simulation time 8396111658 ps
CPU time 8.06 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:49 PM PDT 24
Peak memory 202604 kb
Host smart-81ac241c-7b97-4c99-aaef-0b54708d88cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94957
6705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.949576705
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3497086164
Short name T342
Test name
Test status
Simulation time 8358835782 ps
CPU time 7.03 seconds
Started Mar 10 01:57:39 PM PDT 24
Finished Mar 10 01:57:46 PM PDT 24
Peak memory 202576 kb
Host smart-a4a1c9f7-060a-4466-a505-06c175e723de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34970
86164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3497086164
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.228600071
Short name T653
Test name
Test status
Simulation time 8477051155 ps
CPU time 7.29 seconds
Started Mar 10 01:57:34 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202616 kb
Host smart-af93d47c-1a83-454a-94d3-4b4b3ce8fdb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22860
0071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.228600071
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2662709711
Short name T669
Test name
Test status
Simulation time 8372240671 ps
CPU time 7.21 seconds
Started Mar 10 01:57:42 PM PDT 24
Finished Mar 10 01:57:49 PM PDT 24
Peak memory 202512 kb
Host smart-7aca09e5-4867-4d91-a3ba-72ab19abb1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26627
09711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2662709711
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.4038257674
Short name T551
Test name
Test status
Simulation time 36106895 ps
CPU time 1.04 seconds
Started Mar 10 01:57:38 PM PDT 24
Finished Mar 10 01:57:39 PM PDT 24
Peak memory 202648 kb
Host smart-c8b7d9d6-e290-492c-88e2-f82a1b3fad5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40382
57674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.4038257674
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.949462430
Short name T597
Test name
Test status
Simulation time 8398197763 ps
CPU time 9.17 seconds
Started Mar 10 01:57:39 PM PDT 24
Finished Mar 10 01:57:49 PM PDT 24
Peak memory 202568 kb
Host smart-14608606-7109-4c18-a36f-cc5307f17c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94946
2430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.949462430
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1896501147
Short name T503
Test name
Test status
Simulation time 8407120130 ps
CPU time 7.84 seconds
Started Mar 10 01:57:42 PM PDT 24
Finished Mar 10 01:57:50 PM PDT 24
Peak memory 202588 kb
Host smart-8ec34179-b610-4ef1-9a58-32ebbb585e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18965
01147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1896501147
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1568860025
Short name T459
Test name
Test status
Simulation time 8368638093 ps
CPU time 9.25 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:50 PM PDT 24
Peak memory 202468 kb
Host smart-0a370faf-beaf-4ab0-9bcb-26f8e1edb26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
60025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1568860025
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3411617371
Short name T88
Test name
Test status
Simulation time 8399877725 ps
CPU time 7.13 seconds
Started Mar 10 01:57:38 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202572 kb
Host smart-49b0ad93-7ef9-4e33-9f16-cb3a8f0d5ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34116
17371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3411617371
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.409267879
Short name T698
Test name
Test status
Simulation time 8398387872 ps
CPU time 7.47 seconds
Started Mar 10 01:57:42 PM PDT 24
Finished Mar 10 01:57:49 PM PDT 24
Peak memory 202560 kb
Host smart-19868aa9-5c64-4fc2-baa0-ab16a7c019aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40926
7879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.409267879
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3120038349
Short name T236
Test name
Test status
Simulation time 8409372897 ps
CPU time 7.5 seconds
Started Mar 10 01:57:52 PM PDT 24
Finished Mar 10 01:58:01 PM PDT 24
Peak memory 202496 kb
Host smart-47cd325f-6eb5-48cc-b850-1fe06ebcaa40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200
38349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3120038349
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3842925448
Short name T367
Test name
Test status
Simulation time 29892222 ps
CPU time 0.63 seconds
Started Mar 10 01:57:42 PM PDT 24
Finished Mar 10 01:57:42 PM PDT 24
Peak memory 202516 kb
Host smart-a623358f-82df-47da-96bf-6ac5541774d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38429
25448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3842925448
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.4073361810
Short name T607
Test name
Test status
Simulation time 8432088613 ps
CPU time 7.1 seconds
Started Mar 10 01:57:39 PM PDT 24
Finished Mar 10 01:57:46 PM PDT 24
Peak memory 202460 kb
Host smart-2a3cdc55-3eb9-4b12-b279-2ed93a3b550e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40733
61810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.4073361810
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.343398937
Short name T619
Test name
Test status
Simulation time 8362214105 ps
CPU time 7.34 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:48 PM PDT 24
Peak memory 202468 kb
Host smart-459ae67a-7a98-4119-8912-fa4dbbc17fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34339
8937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.343398937
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1240988930
Short name T325
Test name
Test status
Simulation time 8361988667 ps
CPU time 7.48 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:47 PM PDT 24
Peak memory 202540 kb
Host smart-0ce0c87f-00ee-4141-b289-49f3e4f47cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12409
88930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1240988930
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3440296803
Short name T40
Test name
Test status
Simulation time 8469201615 ps
CPU time 9.31 seconds
Started Mar 10 01:57:41 PM PDT 24
Finished Mar 10 01:57:51 PM PDT 24
Peak memory 202628 kb
Host smart-2c7a1b44-df39-4c4e-9660-0247427698a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34402
96803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3440296803
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2087762929
Short name T673
Test name
Test status
Simulation time 8371231198 ps
CPU time 8.07 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:48 PM PDT 24
Peak memory 202548 kb
Host smart-23b0fb2e-a9da-46da-bdd0-e6e55750de66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877
62929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2087762929
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.4129420615
Short name T70
Test name
Test status
Simulation time 235286523 ps
CPU time 1.86 seconds
Started Mar 10 01:57:39 PM PDT 24
Finished Mar 10 01:57:41 PM PDT 24
Peak memory 202620 kb
Host smart-d6e3baa0-cfa6-46f2-adc5-097badd9c57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41294
20615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.4129420615
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.325201315
Short name T128
Test name
Test status
Simulation time 8401610230 ps
CPU time 7.8 seconds
Started Mar 10 01:57:41 PM PDT 24
Finished Mar 10 01:57:49 PM PDT 24
Peak memory 202520 kb
Host smart-0fd293d4-4060-4810-8e18-ebc3a4d983d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32520
1315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.325201315
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1053387762
Short name T238
Test name
Test status
Simulation time 8409080709 ps
CPU time 7.54 seconds
Started Mar 10 01:57:45 PM PDT 24
Finished Mar 10 01:57:53 PM PDT 24
Peak memory 202588 kb
Host smart-df8a63f7-da85-4069-96ce-3f3f38d67ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10533
87762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1053387762
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.989777754
Short name T329
Test name
Test status
Simulation time 8364428934 ps
CPU time 8.98 seconds
Started Mar 10 01:57:42 PM PDT 24
Finished Mar 10 01:57:51 PM PDT 24
Peak memory 202560 kb
Host smart-041dd552-dada-4c63-b86c-27e94881f2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98977
7754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.989777754
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2530937541
Short name T204
Test name
Test status
Simulation time 8411024814 ps
CPU time 7.66 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:48 PM PDT 24
Peak memory 202536 kb
Host smart-fd92e2f8-99ae-4f9d-93f8-ef6e76e69f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25309
37541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2530937541
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.845808461
Short name T370
Test name
Test status
Simulation time 8373330602 ps
CPU time 10.1 seconds
Started Mar 10 01:57:42 PM PDT 24
Finished Mar 10 01:57:52 PM PDT 24
Peak memory 202560 kb
Host smart-414b8c52-a3c5-4552-990f-f64b14649203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84580
8461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.845808461
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3521827349
Short name T688
Test name
Test status
Simulation time 8379759750 ps
CPU time 7.13 seconds
Started Mar 10 01:57:40 PM PDT 24
Finished Mar 10 01:57:48 PM PDT 24
Peak memory 202556 kb
Host smart-c774143e-b395-43c3-8629-629a9cbed0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35218
27349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3521827349
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3876219445
Short name T555
Test name
Test status
Simulation time 20273571 ps
CPU time 0.66 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:45 PM PDT 24
Peak memory 202508 kb
Host smart-7db04d46-6993-490a-b793-5bb44de50d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38762
19445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3876219445
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1800064458
Short name T444
Test name
Test status
Simulation time 8452368983 ps
CPU time 8.65 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:53 PM PDT 24
Peak memory 202528 kb
Host smart-3cf4bd9a-4e55-4630-88f9-5c9e95f86710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18000
64458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1800064458
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.693456155
Short name T523
Test name
Test status
Simulation time 8379002508 ps
CPU time 8.09 seconds
Started Mar 10 01:57:49 PM PDT 24
Finished Mar 10 01:57:57 PM PDT 24
Peak memory 202572 kb
Host smart-0542520e-9a93-4466-be92-09f779c47400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69345
6155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.693456155
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1189026111
Short name T556
Test name
Test status
Simulation time 8363504595 ps
CPU time 9.76 seconds
Started Mar 10 01:57:45 PM PDT 24
Finished Mar 10 01:57:55 PM PDT 24
Peak memory 202496 kb
Host smart-7e92102d-652a-4103-b3ca-0106f1db8863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
26111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1189026111
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2358056063
Short name T516
Test name
Test status
Simulation time 8472422897 ps
CPU time 7.52 seconds
Started Mar 10 01:57:46 PM PDT 24
Finished Mar 10 01:57:54 PM PDT 24
Peak memory 202604 kb
Host smart-2a14ecc9-bd23-4b9f-9139-43d579496123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23580
56063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2358056063
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1712262437
Short name T183
Test name
Test status
Simulation time 8372973382 ps
CPU time 9.7 seconds
Started Mar 10 01:57:54 PM PDT 24
Finished Mar 10 01:58:05 PM PDT 24
Peak memory 202536 kb
Host smart-c0f68670-5df7-42d3-b91d-d42ad1ca003c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17122
62437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1712262437
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.954326280
Short name T531
Test name
Test status
Simulation time 38639664 ps
CPU time 1.05 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:46 PM PDT 24
Peak memory 202540 kb
Host smart-68a9dbd0-6fca-4f74-8923-5db206c38564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95432
6280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.954326280
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1955195179
Short name T405
Test name
Test status
Simulation time 8401935860 ps
CPU time 7.53 seconds
Started Mar 10 01:57:46 PM PDT 24
Finished Mar 10 01:57:54 PM PDT 24
Peak memory 202576 kb
Host smart-4fdd03f9-b9d4-4802-8ee7-6dc2db5b961e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19551
95179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1955195179
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.86824722
Short name T196
Test name
Test status
Simulation time 8410858743 ps
CPU time 7.45 seconds
Started Mar 10 01:57:59 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202480 kb
Host smart-b63101b2-e125-43af-85aa-48ee7b497237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86824
722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.86824722
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.317839167
Short name T287
Test name
Test status
Simulation time 8362485627 ps
CPU time 7.92 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:52 PM PDT 24
Peak memory 202596 kb
Host smart-9ddd4116-d967-4f93-98ee-45306ebf7cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31783
9167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.317839167
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.501074316
Short name T481
Test name
Test status
Simulation time 8405664921 ps
CPU time 7.39 seconds
Started Mar 10 01:57:46 PM PDT 24
Finished Mar 10 01:57:54 PM PDT 24
Peak memory 202536 kb
Host smart-90dc2c55-20b5-47c9-92d8-e7f63b533956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50107
4316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.501074316
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.550794195
Short name T520
Test name
Test status
Simulation time 8393643555 ps
CPU time 7.1 seconds
Started Mar 10 01:57:53 PM PDT 24
Finished Mar 10 01:58:01 PM PDT 24
Peak memory 202544 kb
Host smart-6e41cf45-0251-4bbd-ba5e-0ce99af75a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55079
4195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.550794195
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.4180260290
Short name T316
Test name
Test status
Simulation time 8395926218 ps
CPU time 7.52 seconds
Started Mar 10 01:57:54 PM PDT 24
Finished Mar 10 01:58:03 PM PDT 24
Peak memory 202552 kb
Host smart-376f7f31-2f21-410c-9b7e-7f6c813a10c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41802
60290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.4180260290
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.4235233168
Short name T672
Test name
Test status
Simulation time 31359697 ps
CPU time 0.64 seconds
Started Mar 10 01:57:58 PM PDT 24
Finished Mar 10 01:57:59 PM PDT 24
Peak memory 202492 kb
Host smart-d8077912-2fba-4773-84fd-2264db963a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
33168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.4235233168
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2178945980
Short name T576
Test name
Test status
Simulation time 8378182816 ps
CPU time 9.52 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:54 PM PDT 24
Peak memory 202576 kb
Host smart-c667c32d-3d01-43a3-abc3-b3dc75cf5815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21789
45980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2178945980
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.768356217
Short name T455
Test name
Test status
Simulation time 8396154244 ps
CPU time 7.5 seconds
Started Mar 10 01:57:45 PM PDT 24
Finished Mar 10 01:57:53 PM PDT 24
Peak memory 202544 kb
Host smart-f28d0f89-1c39-4eb3-9d30-57f6670e2bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76835
6217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.768356217
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1511876716
Short name T572
Test name
Test status
Simulation time 8362588695 ps
CPU time 7.57 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202544 kb
Host smart-4382b19f-9ad3-4b68-bc13-1217d72755ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15118
76716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1511876716
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.419560311
Short name T140
Test name
Test status
Simulation time 8481709904 ps
CPU time 8.08 seconds
Started Mar 10 01:57:49 PM PDT 24
Finished Mar 10 01:57:58 PM PDT 24
Peak memory 202552 kb
Host smart-c5f86bed-735f-40d5-a3f6-58bd882594d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41956
0311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.419560311
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2486532386
Short name T35
Test name
Test status
Simulation time 8368825389 ps
CPU time 7.75 seconds
Started Mar 10 01:57:52 PM PDT 24
Finished Mar 10 01:58:01 PM PDT 24
Peak memory 202592 kb
Host smart-ed9a8aa4-fc85-4450-8ddb-3511b582823d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24865
32386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2486532386
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3677056408
Short name T567
Test name
Test status
Simulation time 8409766523 ps
CPU time 7.87 seconds
Started Mar 10 01:57:51 PM PDT 24
Finished Mar 10 01:58:00 PM PDT 24
Peak memory 202496 kb
Host smart-6b5eec0a-0c9b-42a9-b2b1-43c65f6a292c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36770
56408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3677056408
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2274963193
Short name T571
Test name
Test status
Simulation time 8364824444 ps
CPU time 7.64 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:52 PM PDT 24
Peak memory 202556 kb
Host smart-3c439f03-d076-4a98-be39-96b90211c21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
63193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2274963193
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2726142738
Short name T609
Test name
Test status
Simulation time 8407460027 ps
CPU time 7.1 seconds
Started Mar 10 01:57:54 PM PDT 24
Finished Mar 10 01:58:03 PM PDT 24
Peak memory 202536 kb
Host smart-9c3025aa-416e-46be-ac21-d26c4e94b581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27261
42738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2726142738
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.3003092528
Short name T504
Test name
Test status
Simulation time 8406497200 ps
CPU time 7.45 seconds
Started Mar 10 01:57:45 PM PDT 24
Finished Mar 10 01:57:53 PM PDT 24
Peak memory 202536 kb
Host smart-9d02a873-48cc-4401-85c1-681a8fc6a3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30030
92528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3003092528
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1415934651
Short name T263
Test name
Test status
Simulation time 8378503127 ps
CPU time 7.06 seconds
Started Mar 10 01:57:43 PM PDT 24
Finished Mar 10 01:57:51 PM PDT 24
Peak memory 202548 kb
Host smart-00104640-c225-4448-8110-86b7a225e01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14159
34651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1415934651
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1187426089
Short name T670
Test name
Test status
Simulation time 24590873 ps
CPU time 0.63 seconds
Started Mar 10 01:57:57 PM PDT 24
Finished Mar 10 01:57:59 PM PDT 24
Peak memory 202456 kb
Host smart-54d2d53d-7717-469b-bf59-c9fa3c7cc81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11874
26089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1187426089
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3838012113
Short name T584
Test name
Test status
Simulation time 8450863179 ps
CPU time 7.86 seconds
Started Mar 10 01:57:50 PM PDT 24
Finished Mar 10 01:57:59 PM PDT 24
Peak memory 202520 kb
Host smart-a84e6161-3f8c-411f-b8c5-236531dc5db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38380
12113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3838012113
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2641394163
Short name T465
Test name
Test status
Simulation time 8382947586 ps
CPU time 7.14 seconds
Started Mar 10 01:57:46 PM PDT 24
Finished Mar 10 01:57:53 PM PDT 24
Peak memory 202520 kb
Host smart-7370035a-cd81-4321-9993-6034ab7a1120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
94163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2641394163
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1583868630
Short name T463
Test name
Test status
Simulation time 8358002351 ps
CPU time 7.59 seconds
Started Mar 10 01:57:52 PM PDT 24
Finished Mar 10 01:58:01 PM PDT 24
Peak memory 202604 kb
Host smart-4c9ccc2d-1b01-42b7-bd56-084e245d5325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15838
68630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1583868630
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.827964169
Short name T652
Test name
Test status
Simulation time 8480646002 ps
CPU time 9.83 seconds
Started Mar 10 01:57:44 PM PDT 24
Finished Mar 10 01:57:55 PM PDT 24
Peak memory 202624 kb
Host smart-74c1b998-38be-4efe-a231-d392a1cc329f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82796
4169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.827964169
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2499142908
Short name T550
Test name
Test status
Simulation time 8366956603 ps
CPU time 7.72 seconds
Started Mar 10 01:57:53 PM PDT 24
Finished Mar 10 01:58:03 PM PDT 24
Peak memory 202536 kb
Host smart-bd5f3499-6a3f-4870-aa49-c26d73202b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24991
42908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2499142908
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2698912396
Short name T203
Test name
Test status
Simulation time 195854681 ps
CPU time 2.16 seconds
Started Mar 10 01:57:52 PM PDT 24
Finished Mar 10 01:57:55 PM PDT 24
Peak memory 202588 kb
Host smart-c4692085-5d52-40a3-a972-eaf0bbb7491a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26989
12396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2698912396
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.4019051290
Short name T118
Test name
Test status
Simulation time 8433959310 ps
CPU time 7.78 seconds
Started Mar 10 01:57:47 PM PDT 24
Finished Mar 10 01:57:55 PM PDT 24
Peak memory 202568 kb
Host smart-e7c99eb1-c49c-4dd4-b819-ea40c785b45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40190
51290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.4019051290
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2188729767
Short name T643
Test name
Test status
Simulation time 8407003638 ps
CPU time 8.83 seconds
Started Mar 10 01:57:57 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202568 kb
Host smart-9738587d-7e40-40c4-9eae-bcb0dd7b3049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21887
29767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2188729767
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2800501816
Short name T506
Test name
Test status
Simulation time 8367655527 ps
CPU time 7.09 seconds
Started Mar 10 01:57:49 PM PDT 24
Finished Mar 10 01:57:56 PM PDT 24
Peak memory 202588 kb
Host smart-727ee9ae-055c-4d55-a488-0f1cb1d7f6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28005
01816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2800501816
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2316078767
Short name T100
Test name
Test status
Simulation time 8392394729 ps
CPU time 7.38 seconds
Started Mar 10 01:57:53 PM PDT 24
Finished Mar 10 01:58:01 PM PDT 24
Peak memory 202572 kb
Host smart-f532b518-0d5c-4869-8434-39a5e9c92e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23160
78767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2316078767
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.4193247638
Short name T71
Test name
Test status
Simulation time 8372653578 ps
CPU time 7.27 seconds
Started Mar 10 01:57:50 PM PDT 24
Finished Mar 10 01:57:57 PM PDT 24
Peak memory 202528 kb
Host smart-a6e8ce82-6874-4670-a44a-b5803f66b71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
47638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.4193247638
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.150282786
Short name T388
Test name
Test status
Simulation time 8392980033 ps
CPU time 9.05 seconds
Started Mar 10 01:57:56 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202564 kb
Host smart-17607eec-add4-4f52-a0fe-e4e594f550e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15028
2786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.150282786
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2382659508
Short name T327
Test name
Test status
Simulation time 8423411131 ps
CPU time 7.89 seconds
Started Mar 10 01:57:53 PM PDT 24
Finished Mar 10 01:58:02 PM PDT 24
Peak memory 202576 kb
Host smart-5672a37b-a0d5-4433-a847-0821097e7843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23826
59508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2382659508
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.3082917146
Short name T574
Test name
Test status
Simulation time 8381932079 ps
CPU time 7.48 seconds
Started Mar 10 01:57:59 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202500 kb
Host smart-672fe909-bb5f-4ce0-bfd8-0bf67b6561cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30829
17146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.3082917146
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3805043474
Short name T381
Test name
Test status
Simulation time 8355652643 ps
CPU time 9.67 seconds
Started Mar 10 01:57:56 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202548 kb
Host smart-a6fabb4c-7edd-4ecf-8fc1-ad5a54876a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050
43474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3805043474
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1520288400
Short name T151
Test name
Test status
Simulation time 8472381573 ps
CPU time 8.45 seconds
Started Mar 10 01:57:54 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202532 kb
Host smart-01a544c3-1bf6-4462-8c96-6f43736025e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15202
88400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1520288400
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.311043678
Short name T44
Test name
Test status
Simulation time 8370145986 ps
CPU time 7.58 seconds
Started Mar 10 01:57:57 PM PDT 24
Finished Mar 10 01:58:06 PM PDT 24
Peak memory 202516 kb
Host smart-52c47d34-6261-4b67-9448-54541675997d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31104
3678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.311043678
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2085661038
Short name T559
Test name
Test status
Simulation time 130756621 ps
CPU time 1.61 seconds
Started Mar 10 01:58:07 PM PDT 24
Finished Mar 10 01:58:09 PM PDT 24
Peak memory 202532 kb
Host smart-da123ed9-6236-4237-9e32-80e003d72002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20856
61038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2085661038
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1386702618
Short name T403
Test name
Test status
Simulation time 8400785608 ps
CPU time 9.48 seconds
Started Mar 10 01:57:53 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202560 kb
Host smart-3846bbd8-2671-498c-a95c-e5d98e013511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13867
02618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1386702618
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.31719348
Short name T300
Test name
Test status
Simulation time 8407555535 ps
CPU time 8.04 seconds
Started Mar 10 01:57:59 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202524 kb
Host smart-eaccbb16-39ab-4af2-80c9-501fbf802551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31719
348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.31719348
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1761368615
Short name T275
Test name
Test status
Simulation time 8362851649 ps
CPU time 7.5 seconds
Started Mar 10 01:58:00 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202484 kb
Host smart-a97548d1-7fcb-445d-a7a6-8fbb1d03a793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17613
68615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1761368615
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1217071143
Short name T90
Test name
Test status
Simulation time 8423722277 ps
CPU time 7.7 seconds
Started Mar 10 01:57:59 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202480 kb
Host smart-04a8fff0-f0e7-4072-bdc1-dd4987a8a8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12170
71143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1217071143
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1828418272
Short name T549
Test name
Test status
Simulation time 8405035042 ps
CPU time 8.2 seconds
Started Mar 10 01:57:54 PM PDT 24
Finished Mar 10 01:58:03 PM PDT 24
Peak memory 202532 kb
Host smart-e60ef34a-3cca-4d9e-a6f5-d60c065405d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
18272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1828418272
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1925319291
Short name T385
Test name
Test status
Simulation time 8372792671 ps
CPU time 7.51 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202576 kb
Host smart-a78ab4f7-fd41-46ec-8e0d-55d018873043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19253
19291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1925319291
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3022982136
Short name T660
Test name
Test status
Simulation time 28817564 ps
CPU time 0.67 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:57:57 PM PDT 24
Peak memory 202464 kb
Host smart-0bd3b1ad-0853-44eb-9b3c-0a15dfbae45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30229
82136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3022982136
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3878583019
Short name T135
Test name
Test status
Simulation time 8440385866 ps
CPU time 7.23 seconds
Started Mar 10 01:57:53 PM PDT 24
Finished Mar 10 01:58:01 PM PDT 24
Peak memory 202552 kb
Host smart-115f1177-5492-46d9-bb85-b5403e5f5f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38785
83019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3878583019
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3259439557
Short name T243
Test name
Test status
Simulation time 8366072885 ps
CPU time 9.45 seconds
Started Mar 10 01:57:56 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202604 kb
Host smart-f3c3e1e4-5373-4993-bf60-873ca64162e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32594
39557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3259439557
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2779224853
Short name T452
Test name
Test status
Simulation time 8359271604 ps
CPU time 8.34 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:58:05 PM PDT 24
Peak memory 202560 kb
Host smart-b13caefb-2b3f-4914-b3af-bd9abd01694b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27792
24853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2779224853
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3588014434
Short name T134
Test name
Test status
Simulation time 8476783924 ps
CPU time 7.26 seconds
Started Mar 10 01:57:53 PM PDT 24
Finished Mar 10 01:58:01 PM PDT 24
Peak memory 202612 kb
Host smart-825b456b-0b55-407b-a425-277381292cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35880
14434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3588014434
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2278948205
Short name T261
Test name
Test status
Simulation time 8370038135 ps
CPU time 7.34 seconds
Started Mar 10 01:57:57 PM PDT 24
Finished Mar 10 01:58:06 PM PDT 24
Peak memory 202572 kb
Host smart-84bddd94-ac44-4871-8a3a-5ed2f8df0528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22789
48205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2278948205
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.518194525
Short name T197
Test name
Test status
Simulation time 194392781 ps
CPU time 1.95 seconds
Started Mar 10 01:57:56 PM PDT 24
Finished Mar 10 01:58:00 PM PDT 24
Peak memory 202628 kb
Host smart-b43789b4-a08f-4855-90c2-9bb97b588f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51819
4525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.518194525
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3414498826
Short name T85
Test name
Test status
Simulation time 8429514238 ps
CPU time 7.87 seconds
Started Mar 10 01:58:09 PM PDT 24
Finished Mar 10 01:58:18 PM PDT 24
Peak memory 202556 kb
Host smart-eb28f6d6-435b-46d3-96ea-cc93bd461003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34144
98826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3414498826
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1138023175
Short name T284
Test name
Test status
Simulation time 8406392062 ps
CPU time 7.5 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202560 kb
Host smart-b4a5e28b-d9ba-4a48-9d52-f53682eb4d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11380
23175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1138023175
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2903752919
Short name T292
Test name
Test status
Simulation time 8367828765 ps
CPU time 8.47 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:58:05 PM PDT 24
Peak memory 202596 kb
Host smart-4e143e69-00c5-47a3-8b08-2e455aa31f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29037
52919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2903752919
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3537095563
Short name T317
Test name
Test status
Simulation time 8454928287 ps
CPU time 7.81 seconds
Started Mar 10 01:58:18 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202576 kb
Host smart-55c730a2-d1ea-4cb8-99d2-43ebbcf8daae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35370
95563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3537095563
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.4158158145
Short name T690
Test name
Test status
Simulation time 8372578507 ps
CPU time 7.91 seconds
Started Mar 10 01:58:06 PM PDT 24
Finished Mar 10 01:58:14 PM PDT 24
Peak memory 202592 kb
Host smart-8207a95e-5874-4097-920d-a52cebe76b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41581
58145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.4158158145
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.4055046132
Short name T374
Test name
Test status
Simulation time 8393477739 ps
CPU time 7.5 seconds
Started Mar 10 01:57:52 PM PDT 24
Finished Mar 10 01:58:00 PM PDT 24
Peak memory 202588 kb
Host smart-4ac3b833-152b-4c40-b0fb-ca3f93e14054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40550
46132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.4055046132
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3595534040
Short name T328
Test name
Test status
Simulation time 34529835 ps
CPU time 0.64 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:57:57 PM PDT 24
Peak memory 202536 kb
Host smart-fc663522-c15e-405c-b20f-740e2dcb254e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35955
34040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3595534040
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2119687702
Short name T639
Test name
Test status
Simulation time 8412285508 ps
CPU time 7.33 seconds
Started Mar 10 01:57:56 PM PDT 24
Finished Mar 10 01:58:05 PM PDT 24
Peak memory 202520 kb
Host smart-6d3a2eb3-6d71-40e8-aa77-d95c686ee469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21196
87702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2119687702
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.474950559
Short name T675
Test name
Test status
Simulation time 8370732608 ps
CPU time 8.31 seconds
Started Mar 10 01:57:53 PM PDT 24
Finished Mar 10 01:58:02 PM PDT 24
Peak memory 202576 kb
Host smart-077b5ea7-144c-4e31-b44a-d799be4b1040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47495
0559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.474950559
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3748737021
Short name T271
Test name
Test status
Simulation time 8356565098 ps
CPU time 8.13 seconds
Started Mar 10 01:57:54 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202536 kb
Host smart-eb52f308-b17c-4bde-a195-07b2e61adf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37487
37021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3748737021
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3547832357
Short name T674
Test name
Test status
Simulation time 8475539385 ps
CPU time 9.84 seconds
Started Mar 10 01:57:56 PM PDT 24
Finished Mar 10 01:58:08 PM PDT 24
Peak memory 202588 kb
Host smart-caa3802b-a409-40a1-9f95-13ae1315da74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35478
32357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3547832357
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3898023869
Short name T76
Test name
Test status
Simulation time 8365881052 ps
CPU time 8.01 seconds
Started Mar 10 01:56:24 PM PDT 24
Finished Mar 10 01:56:33 PM PDT 24
Peak memory 202476 kb
Host smart-bd64817f-9c7c-404a-9375-8aefefbd0945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38980
23869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3898023869
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1418664190
Short name T375
Test name
Test status
Simulation time 8432109786 ps
CPU time 8.34 seconds
Started Mar 10 01:56:19 PM PDT 24
Finished Mar 10 01:56:28 PM PDT 24
Peak memory 202576 kb
Host smart-7f0719dd-058f-4a6a-b133-a6b065de7e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14186
64190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1418664190
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.49249547
Short name T297
Test name
Test status
Simulation time 8409279348 ps
CPU time 8.72 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:26 PM PDT 24
Peak memory 202520 kb
Host smart-324ee68a-a71a-46c1-81dd-cd9d66e1fa41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49249
547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.49249547
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1495089096
Short name T351
Test name
Test status
Simulation time 8370226528 ps
CPU time 8.7 seconds
Started Mar 10 01:56:17 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202468 kb
Host smart-ae1ed968-c072-49f6-a2a2-9997bb9e9210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14950
89096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1495089096
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.50016832
Short name T98
Test name
Test status
Simulation time 8401146524 ps
CPU time 7.37 seconds
Started Mar 10 01:56:18 PM PDT 24
Finished Mar 10 01:56:26 PM PDT 24
Peak memory 202560 kb
Host smart-6cba8606-3073-4cd4-bd94-6c7569c9ac66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50016
832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.50016832
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1390935546
Short name T346
Test name
Test status
Simulation time 8395582986 ps
CPU time 9.39 seconds
Started Mar 10 01:56:18 PM PDT 24
Finished Mar 10 01:56:28 PM PDT 24
Peak memory 202572 kb
Host smart-fe9a410a-ded9-493d-a86f-02e945d28fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13909
35546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1390935546
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1736943513
Short name T412
Test name
Test status
Simulation time 8365951158 ps
CPU time 9.05 seconds
Started Mar 10 01:56:18 PM PDT 24
Finished Mar 10 01:56:28 PM PDT 24
Peak memory 202588 kb
Host smart-76c70072-9f97-4dd8-8980-b048f54d80be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17369
43513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1736943513
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.852126941
Short name T543
Test name
Test status
Simulation time 27137468 ps
CPU time 0.65 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:18 PM PDT 24
Peak memory 202480 kb
Host smart-6a52fdc1-5cc4-4cde-95ac-edca876781b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85212
6941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.852126941
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2529416154
Short name T440
Test name
Test status
Simulation time 8389780603 ps
CPU time 8.31 seconds
Started Mar 10 01:56:18 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202532 kb
Host smart-f56caec5-e167-4d70-9e87-6701650f746f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25294
16154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2529416154
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.1290860184
Short name T194
Test name
Test status
Simulation time 8378642715 ps
CPU time 7.87 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:25 PM PDT 24
Peak memory 202576 kb
Host smart-1d3fc91b-0424-42bb-99a7-b76faeadd506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12908
60184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.1290860184
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2113325422
Short name T54
Test name
Test status
Simulation time 159570750 ps
CPU time 0.95 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:18 PM PDT 24
Peak memory 217544 kb
Host smart-292384ee-c914-46eb-8ea1-028d007b176b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2113325422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2113325422
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2818594243
Short name T585
Test name
Test status
Simulation time 8363986405 ps
CPU time 8.01 seconds
Started Mar 10 01:56:18 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202520 kb
Host smart-771f2c01-aa25-4eb6-a873-00213100e4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28185
94243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2818594243
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3214807963
Short name T425
Test name
Test status
Simulation time 8481164457 ps
CPU time 7.38 seconds
Started Mar 10 01:56:12 PM PDT 24
Finished Mar 10 01:56:20 PM PDT 24
Peak memory 202580 kb
Host smart-5c221cbc-b821-4002-ae6c-a999e3a6250e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32148
07963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3214807963
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2608530304
Short name T573
Test name
Test status
Simulation time 8367190922 ps
CPU time 8.18 seconds
Started Mar 10 01:57:56 PM PDT 24
Finished Mar 10 01:58:06 PM PDT 24
Peak memory 202536 kb
Host smart-e63da499-dd3a-431a-9a29-fe0b5b16afc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26085
30304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2608530304
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.320824695
Short name T240
Test name
Test status
Simulation time 36696304 ps
CPU time 1.01 seconds
Started Mar 10 01:57:54 PM PDT 24
Finished Mar 10 01:57:57 PM PDT 24
Peak memory 202624 kb
Host smart-9671bca2-bc8d-4b17-bded-f3b470c33881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32082
4695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.320824695
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.4181814081
Short name T132
Test name
Test status
Simulation time 8449763357 ps
CPU time 8.96 seconds
Started Mar 10 01:58:20 PM PDT 24
Finished Mar 10 01:58:30 PM PDT 24
Peak memory 202520 kb
Host smart-16a5e836-9ea1-4f9b-8945-a3043f59821e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41818
14081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.4181814081
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.873059011
Short name T695
Test name
Test status
Simulation time 8405657135 ps
CPU time 8.03 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:09 PM PDT 24
Peak memory 202560 kb
Host smart-dd7ea55f-d718-48db-8f96-357ee04ff667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87305
9011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.873059011
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2448921996
Short name T588
Test name
Test status
Simulation time 8364910084 ps
CPU time 7.59 seconds
Started Mar 10 01:58:00 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202524 kb
Host smart-980b780a-4eb6-4550-899d-aed4ba0e83c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24489
21996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2448921996
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2181986645
Short name T97
Test name
Test status
Simulation time 8408594411 ps
CPU time 7.59 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:09 PM PDT 24
Peak memory 202476 kb
Host smart-0b0c56f1-709c-47fc-b1d4-37d4884d769d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21819
86645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2181986645
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3746667509
Short name T310
Test name
Test status
Simulation time 8376570084 ps
CPU time 7.79 seconds
Started Mar 10 01:57:56 PM PDT 24
Finished Mar 10 01:58:06 PM PDT 24
Peak memory 202576 kb
Host smart-fc794e66-9a9d-4b6e-8bd4-cead938a9c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37466
67509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3746667509
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.147365362
Short name T282
Test name
Test status
Simulation time 8399126344 ps
CPU time 7.62 seconds
Started Mar 10 01:58:11 PM PDT 24
Finished Mar 10 01:58:18 PM PDT 24
Peak memory 202576 kb
Host smart-6168b5b8-d365-46d9-bfcf-9bf791d4037b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
5362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.147365362
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1168156417
Short name T554
Test name
Test status
Simulation time 29461704 ps
CPU time 0.68 seconds
Started Mar 10 01:58:17 PM PDT 24
Finished Mar 10 01:58:18 PM PDT 24
Peak memory 202412 kb
Host smart-df1cb51b-850d-41d9-b090-05e909a84697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11681
56417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1168156417
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.860467096
Short name T519
Test name
Test status
Simulation time 8373151163 ps
CPU time 7.45 seconds
Started Mar 10 01:57:59 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202576 kb
Host smart-21147a60-bdd7-47ca-992b-a734e83913f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86046
7096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.860467096
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1356035220
Short name T453
Test name
Test status
Simulation time 8356513165 ps
CPU time 6.95 seconds
Started Mar 10 01:57:57 PM PDT 24
Finished Mar 10 01:58:05 PM PDT 24
Peak memory 202560 kb
Host smart-9410fe88-78ce-46a1-afab-d4d5708054e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
35220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1356035220
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.543651796
Short name T148
Test name
Test status
Simulation time 8482713143 ps
CPU time 7.78 seconds
Started Mar 10 01:57:57 PM PDT 24
Finished Mar 10 01:58:06 PM PDT 24
Peak memory 202588 kb
Host smart-028f20ed-780d-4d50-bc49-6885bb31b001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54365
1796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.543651796
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1476930715
Short name T42
Test name
Test status
Simulation time 8372435909 ps
CPU time 8.58 seconds
Started Mar 10 01:58:16 PM PDT 24
Finished Mar 10 01:58:24 PM PDT 24
Peak memory 202532 kb
Host smart-b5f93135-e946-4e04-9b29-aaac96ac7c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14769
30715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1476930715
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.259131089
Short name T237
Test name
Test status
Simulation time 45948721 ps
CPU time 1.22 seconds
Started Mar 10 01:58:12 PM PDT 24
Finished Mar 10 01:58:14 PM PDT 24
Peak memory 202568 kb
Host smart-c4b28bd2-62b8-4200-b20f-6768efb8cf09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25913
1089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.259131089
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2286500317
Short name T436
Test name
Test status
Simulation time 8436255879 ps
CPU time 7.26 seconds
Started Mar 10 01:58:19 PM PDT 24
Finished Mar 10 01:58:27 PM PDT 24
Peak memory 202576 kb
Host smart-d87a0ae4-462c-4d0f-be3d-d0398bde5973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
00317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2286500317
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3089677988
Short name T534
Test name
Test status
Simulation time 8404840466 ps
CPU time 7.06 seconds
Started Mar 10 01:58:02 PM PDT 24
Finished Mar 10 01:58:09 PM PDT 24
Peak memory 202456 kb
Host smart-76859f5b-2443-4c24-89d0-f5e4f9d2aa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30896
77988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3089677988
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2823920603
Short name T502
Test name
Test status
Simulation time 8361987423 ps
CPU time 8.04 seconds
Started Mar 10 01:58:12 PM PDT 24
Finished Mar 10 01:58:20 PM PDT 24
Peak memory 202568 kb
Host smart-e2725600-48f3-422f-8c35-5b9e2c74f799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239
20603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2823920603
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3259243749
Short name T108
Test name
Test status
Simulation time 8450122557 ps
CPU time 8.4 seconds
Started Mar 10 01:57:58 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202560 kb
Host smart-753ef652-9fba-467d-9d41-1c5adb7e93f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32592
43749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3259243749
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.422182705
Short name T603
Test name
Test status
Simulation time 8365764596 ps
CPU time 7.23 seconds
Started Mar 10 01:57:59 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202520 kb
Host smart-73da0d89-087a-45a7-9092-6c670f14bdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218
2705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.422182705
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3861081239
Short name T461
Test name
Test status
Simulation time 8372444122 ps
CPU time 8.46 seconds
Started Mar 10 01:58:12 PM PDT 24
Finished Mar 10 01:58:21 PM PDT 24
Peak memory 202564 kb
Host smart-a5324602-245d-419e-ab88-697e0f91de68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38610
81239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3861081239
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.367095414
Short name T200
Test name
Test status
Simulation time 24104801 ps
CPU time 0.63 seconds
Started Mar 10 01:58:14 PM PDT 24
Finished Mar 10 01:58:15 PM PDT 24
Peak memory 202500 kb
Host smart-3cd669c2-b2e7-4b7b-8401-7b4099d0c661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36709
5414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.367095414
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1188812961
Short name T112
Test name
Test status
Simulation time 8400879956 ps
CPU time 7.28 seconds
Started Mar 10 01:57:59 PM PDT 24
Finished Mar 10 01:58:07 PM PDT 24
Peak memory 202520 kb
Host smart-f968831a-a273-4615-945a-ee9409f3c548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
12961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1188812961
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2087352378
Short name T47
Test name
Test status
Simulation time 8370089078 ps
CPU time 8.15 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:09 PM PDT 24
Peak memory 202504 kb
Host smart-f2f8bd1e-68a3-4faa-b549-1037f95c1ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20873
52378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2087352378
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1104706475
Short name T625
Test name
Test status
Simulation time 8357650158 ps
CPU time 7.19 seconds
Started Mar 10 01:58:17 PM PDT 24
Finished Mar 10 01:58:24 PM PDT 24
Peak memory 202520 kb
Host smart-59668bdb-5791-4369-9189-21260a33a388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11047
06475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1104706475
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1970355824
Short name T143
Test name
Test status
Simulation time 8477412675 ps
CPU time 7.77 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202616 kb
Host smart-f41decc2-ced7-412f-ab13-3946f6e23726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19703
55824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1970355824
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3616767354
Short name T258
Test name
Test status
Simulation time 8368779028 ps
CPU time 9.12 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:11 PM PDT 24
Peak memory 202476 kb
Host smart-fe3cf899-f063-49a3-8cd5-4cce6025aa68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36167
67354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3616767354
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3470598102
Short name T557
Test name
Test status
Simulation time 58098102 ps
CPU time 1.71 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:03 PM PDT 24
Peak memory 202564 kb
Host smart-270d7ba7-e99c-471b-a85e-ff18282b2016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34705
98102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3470598102
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2611887282
Short name T581
Test name
Test status
Simulation time 8419505070 ps
CPU time 7.72 seconds
Started Mar 10 01:57:55 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202444 kb
Host smart-8793a6c8-2d5f-46df-bdc9-9c2377970258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
87282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2611887282
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.609014105
Short name T587
Test name
Test status
Simulation time 8410850484 ps
CPU time 8.22 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:10 PM PDT 24
Peak memory 202504 kb
Host smart-3c2d0bdb-78ca-4593-bfa2-d94156487611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60901
4105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.609014105
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1826866915
Short name T245
Test name
Test status
Simulation time 8363992456 ps
CPU time 7.67 seconds
Started Mar 10 01:58:22 PM PDT 24
Finished Mar 10 01:58:31 PM PDT 24
Peak memory 202472 kb
Host smart-91c417d3-1937-429c-8451-d01c5161084d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18268
66915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1826866915
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3353409448
Short name T398
Test name
Test status
Simulation time 8432500869 ps
CPU time 7.76 seconds
Started Mar 10 01:58:00 PM PDT 24
Finished Mar 10 01:58:08 PM PDT 24
Peak memory 202588 kb
Host smart-61e99ee3-c96f-4eaa-89ed-4bd26c71167d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33534
09448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3353409448
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.888482806
Short name T343
Test name
Test status
Simulation time 8375197991 ps
CPU time 7.51 seconds
Started Mar 10 01:58:04 PM PDT 24
Finished Mar 10 01:58:12 PM PDT 24
Peak memory 202560 kb
Host smart-f0c2e522-992d-4e00-9a63-1e79e31ed022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88848
2806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.888482806
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3530956330
Short name T8
Test name
Test status
Simulation time 8382846293 ps
CPU time 7.75 seconds
Started Mar 10 01:58:16 PM PDT 24
Finished Mar 10 01:58:23 PM PDT 24
Peak memory 202556 kb
Host smart-85e97d42-2d8d-4706-acbd-7ce7e9ef79ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35309
56330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3530956330
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2761943524
Short name T708
Test name
Test status
Simulation time 22940979 ps
CPU time 0.63 seconds
Started Mar 10 01:58:11 PM PDT 24
Finished Mar 10 01:58:12 PM PDT 24
Peak memory 202448 kb
Host smart-671a4ff0-dadd-4e6f-8392-6617bb750831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27619
43524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2761943524
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1418240741
Short name T130
Test name
Test status
Simulation time 8388047339 ps
CPU time 7.58 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:09 PM PDT 24
Peak memory 202512 kb
Host smart-ac6d9143-57b6-4442-9214-d8cc5d884b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14182
40741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1418240741
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.3104321532
Short name T1
Test name
Test status
Simulation time 8391204075 ps
CPU time 8.4 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:10 PM PDT 24
Peak memory 202540 kb
Host smart-ec8a621d-1811-4c56-b457-8d1afeb4611e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31043
21532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.3104321532
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1772735723
Short name T395
Test name
Test status
Simulation time 8359642058 ps
CPU time 9.67 seconds
Started Mar 10 01:58:12 PM PDT 24
Finished Mar 10 01:58:22 PM PDT 24
Peak memory 202556 kb
Host smart-f1ffcdd0-c2c3-4cef-b54b-e478f91c0aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17727
35723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1772735723
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2809894565
Short name T250
Test name
Test status
Simulation time 8365192789 ps
CPU time 7.98 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:10 PM PDT 24
Peak memory 202572 kb
Host smart-d38c46aa-1002-4da7-9f4a-1dedf5f55f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28098
94565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2809894565
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3251208019
Short name T682
Test name
Test status
Simulation time 42893243 ps
CPU time 1.12 seconds
Started Mar 10 01:58:03 PM PDT 24
Finished Mar 10 01:58:04 PM PDT 24
Peak memory 202448 kb
Host smart-222d1dc8-55df-4ea4-ba66-547ebe3ef532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32512
08019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3251208019
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3788772801
Short name T681
Test name
Test status
Simulation time 8396835671 ps
CPU time 7.78 seconds
Started Mar 10 01:58:00 PM PDT 24
Finished Mar 10 01:58:08 PM PDT 24
Peak memory 202548 kb
Host smart-8b8198dc-15e2-4d57-88dc-09c132c96d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37887
72801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3788772801
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2511488764
Short name T648
Test name
Test status
Simulation time 8405871816 ps
CPU time 10.08 seconds
Started Mar 10 01:58:06 PM PDT 24
Finished Mar 10 01:58:16 PM PDT 24
Peak memory 202576 kb
Host smart-7342e369-4e17-4c10-a6ce-5841e02aabf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
88764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2511488764
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1363722474
Short name T628
Test name
Test status
Simulation time 8368162373 ps
CPU time 7.44 seconds
Started Mar 10 01:58:07 PM PDT 24
Finished Mar 10 01:58:15 PM PDT 24
Peak memory 202560 kb
Host smart-2209beec-57cd-4d1f-b569-1c1b06686b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13637
22474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1363722474
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.935467160
Short name T285
Test name
Test status
Simulation time 8391079127 ps
CPU time 8.75 seconds
Started Mar 10 01:58:01 PM PDT 24
Finished Mar 10 01:58:10 PM PDT 24
Peak memory 202560 kb
Host smart-6ca07e1e-536e-4cd6-9de4-1028d082185d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93546
7160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.935467160
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3282431083
Short name T539
Test name
Test status
Simulation time 8381876164 ps
CPU time 8.99 seconds
Started Mar 10 01:58:12 PM PDT 24
Finished Mar 10 01:58:21 PM PDT 24
Peak memory 202572 kb
Host smart-80fc2ec8-b6fb-4027-8c86-5ef1eec0c3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824
31083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3282431083
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.598179415
Short name T22
Test name
Test status
Simulation time 8439736032 ps
CPU time 9.38 seconds
Started Mar 10 01:58:03 PM PDT 24
Finished Mar 10 01:58:13 PM PDT 24
Peak memory 202428 kb
Host smart-1c06d12d-f96a-4719-be5b-9e9cbbe2867a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59817
9415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.598179415
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.2257061783
Short name T378
Test name
Test status
Simulation time 8390962244 ps
CPU time 7.82 seconds
Started Mar 10 01:58:13 PM PDT 24
Finished Mar 10 01:58:21 PM PDT 24
Peak memory 202576 kb
Host smart-acca16d9-8525-45bb-97aa-51829cdd275c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22570
61783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.2257061783
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2114948728
Short name T441
Test name
Test status
Simulation time 8358797189 ps
CPU time 7.74 seconds
Started Mar 10 01:58:14 PM PDT 24
Finished Mar 10 01:58:22 PM PDT 24
Peak memory 202468 kb
Host smart-3a29b9b7-a3fd-42e1-a5e4-902e142f39f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21149
48728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2114948728
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.431173945
Short name T450
Test name
Test status
Simulation time 8369950396 ps
CPU time 7.94 seconds
Started Mar 10 01:58:18 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202556 kb
Host smart-1bbd03b4-f606-4fbd-afb4-5b99d6b2e250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43117
3945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.431173945
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4004461484
Short name T75
Test name
Test status
Simulation time 305598501 ps
CPU time 2.33 seconds
Started Mar 10 01:58:15 PM PDT 24
Finished Mar 10 01:58:17 PM PDT 24
Peak memory 202628 kb
Host smart-133fae84-1508-4589-963d-2f70e617a9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40044
61484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4004461484
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.854231454
Short name T464
Test name
Test status
Simulation time 8437672764 ps
CPU time 7.47 seconds
Started Mar 10 01:58:08 PM PDT 24
Finished Mar 10 01:58:16 PM PDT 24
Peak memory 202576 kb
Host smart-5c788ebb-3219-4f05-b638-9cb45d5dcaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85423
1454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.854231454
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1366060829
Short name T318
Test name
Test status
Simulation time 8411539690 ps
CPU time 7.82 seconds
Started Mar 10 01:58:11 PM PDT 24
Finished Mar 10 01:58:19 PM PDT 24
Peak memory 202576 kb
Host smart-9f1b50ae-dff8-441b-b0a7-d61ceac24aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13660
60829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1366060829
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.904345769
Short name T315
Test name
Test status
Simulation time 8360472346 ps
CPU time 8.69 seconds
Started Mar 10 01:58:17 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202572 kb
Host smart-3d16abc1-5124-4f71-8de4-4d5aec807474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90434
5769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.904345769
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3353446229
Short name T111
Test name
Test status
Simulation time 8392840265 ps
CPU time 7.09 seconds
Started Mar 10 01:58:10 PM PDT 24
Finished Mar 10 01:58:17 PM PDT 24
Peak memory 202512 kb
Host smart-6f8c3557-3882-411b-9775-996b71b10642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33534
46229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3353446229
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1308708773
Short name T19
Test name
Test status
Simulation time 8375570739 ps
CPU time 7.89 seconds
Started Mar 10 01:58:12 PM PDT 24
Finished Mar 10 01:58:20 PM PDT 24
Peak memory 202508 kb
Host smart-08dcfdd7-1f9b-412e-91b7-b0d80666c8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13087
08773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1308708773
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1605765125
Short name T308
Test name
Test status
Simulation time 8407810524 ps
CPU time 7.41 seconds
Started Mar 10 01:58:04 PM PDT 24
Finished Mar 10 01:58:11 PM PDT 24
Peak memory 202596 kb
Host smart-298eca1e-ddee-4b2c-86ac-0cbac17717b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16057
65125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1605765125
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.38784124
Short name T649
Test name
Test status
Simulation time 25140780 ps
CPU time 0.63 seconds
Started Mar 10 01:58:07 PM PDT 24
Finished Mar 10 01:58:08 PM PDT 24
Peak memory 202400 kb
Host smart-03638428-367b-49ba-accf-d7b7b6a96bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38784
124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.38784124
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1721004588
Short name T518
Test name
Test status
Simulation time 8437755786 ps
CPU time 9.34 seconds
Started Mar 10 01:58:05 PM PDT 24
Finished Mar 10 01:58:14 PM PDT 24
Peak memory 202520 kb
Host smart-756dac36-b82a-41aa-92e2-77e90695bfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17210
04588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1721004588
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3554109829
Short name T544
Test name
Test status
Simulation time 8397298259 ps
CPU time 7.33 seconds
Started Mar 10 01:58:06 PM PDT 24
Finished Mar 10 01:58:13 PM PDT 24
Peak memory 202604 kb
Host smart-e0ed31b4-0d45-433a-a33d-17a3592b436c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35541
09829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3554109829
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2089545873
Short name T458
Test name
Test status
Simulation time 8356076747 ps
CPU time 7.08 seconds
Started Mar 10 01:58:16 PM PDT 24
Finished Mar 10 01:58:23 PM PDT 24
Peak memory 202568 kb
Host smart-f5e0da5f-3a4f-43fa-a979-36b96a3c2356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895
45873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2089545873
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.4097797543
Short name T620
Test name
Test status
Simulation time 8475996212 ps
CPU time 7.36 seconds
Started Mar 10 01:58:03 PM PDT 24
Finished Mar 10 01:58:11 PM PDT 24
Peak memory 202616 kb
Host smart-065772c4-a311-48fc-8a42-8645287943f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40977
97543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4097797543
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1673610747
Short name T10
Test name
Test status
Simulation time 8367945053 ps
CPU time 7.38 seconds
Started Mar 10 01:58:11 PM PDT 24
Finished Mar 10 01:58:18 PM PDT 24
Peak memory 202480 kb
Host smart-741fd59c-f026-4ace-b4b6-1cf2fe02ad8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
10747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1673610747
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3525429699
Short name T189
Test name
Test status
Simulation time 194219250 ps
CPU time 1.71 seconds
Started Mar 10 01:58:15 PM PDT 24
Finished Mar 10 01:58:17 PM PDT 24
Peak memory 202572 kb
Host smart-e033133d-5850-441a-a905-167955947e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35254
29699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3525429699
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2529631343
Short name T668
Test name
Test status
Simulation time 8400818102 ps
CPU time 7.49 seconds
Started Mar 10 01:58:05 PM PDT 24
Finished Mar 10 01:58:13 PM PDT 24
Peak memory 202560 kb
Host smart-22b54bf8-410a-4478-9347-5379b25ba2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25296
31343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2529631343
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1730496204
Short name T382
Test name
Test status
Simulation time 8408388292 ps
CPU time 7.52 seconds
Started Mar 10 01:58:05 PM PDT 24
Finished Mar 10 01:58:13 PM PDT 24
Peak memory 202604 kb
Host smart-c69ea83a-4327-4740-9af0-e59557e2691e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17304
96204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1730496204
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2399034959
Short name T241
Test name
Test status
Simulation time 8363583279 ps
CPU time 6.99 seconds
Started Mar 10 01:58:15 PM PDT 24
Finished Mar 10 01:58:22 PM PDT 24
Peak memory 202576 kb
Host smart-baef5557-bbac-4bde-95db-e0f24427c6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
34959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2399034959
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2596149233
Short name T89
Test name
Test status
Simulation time 8437898607 ps
CPU time 7.25 seconds
Started Mar 10 01:58:14 PM PDT 24
Finished Mar 10 01:58:21 PM PDT 24
Peak memory 202532 kb
Host smart-1541628a-0799-4ff2-8a85-094b5df2a525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25961
49233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2596149233
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.742108925
Short name T355
Test name
Test status
Simulation time 8408067632 ps
CPU time 7.55 seconds
Started Mar 10 01:58:16 PM PDT 24
Finished Mar 10 01:58:24 PM PDT 24
Peak memory 202496 kb
Host smart-9769b383-98a5-4c01-9825-f3c4f1b6d03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74210
8925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.742108925
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3857343505
Short name T485
Test name
Test status
Simulation time 8373674776 ps
CPU time 7.1 seconds
Started Mar 10 01:58:07 PM PDT 24
Finished Mar 10 01:58:14 PM PDT 24
Peak memory 202472 kb
Host smart-c3d05989-89fc-4bd6-a236-a245a73b2450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38573
43505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3857343505
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1782043324
Short name T32
Test name
Test status
Simulation time 28262184 ps
CPU time 0.6 seconds
Started Mar 10 01:58:19 PM PDT 24
Finished Mar 10 01:58:20 PM PDT 24
Peak memory 202436 kb
Host smart-3559478b-d2c5-4f65-8c68-f9c0ddfa6226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17820
43324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1782043324
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.711296427
Short name T195
Test name
Test status
Simulation time 8387668073 ps
CPU time 7.81 seconds
Started Mar 10 01:58:11 PM PDT 24
Finished Mar 10 01:58:19 PM PDT 24
Peak memory 202556 kb
Host smart-fdb43798-5cf4-4afd-a752-95c92a94aa32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71129
6427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.711296427
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.295708835
Short name T478
Test name
Test status
Simulation time 8394574813 ps
CPU time 7.8 seconds
Started Mar 10 01:58:09 PM PDT 24
Finished Mar 10 01:58:17 PM PDT 24
Peak memory 202552 kb
Host smart-30693b21-741d-45b4-bd1f-a9dc9f4af8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29570
8835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.295708835
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2202842100
Short name T471
Test name
Test status
Simulation time 8357494054 ps
CPU time 7.65 seconds
Started Mar 10 01:58:25 PM PDT 24
Finished Mar 10 01:58:33 PM PDT 24
Peak memory 202600 kb
Host smart-42fc60f1-a0d2-4cc5-9673-423f80a9f9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22028
42100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2202842100
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3272001747
Short name T583
Test name
Test status
Simulation time 8480268682 ps
CPU time 8.11 seconds
Started Mar 10 01:58:06 PM PDT 24
Finished Mar 10 01:58:14 PM PDT 24
Peak memory 202604 kb
Host smart-3bc60210-46ee-4fcf-9eed-050ddb81e4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32720
01747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3272001747
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.4052869542
Short name T190
Test name
Test status
Simulation time 8367600412 ps
CPU time 9.26 seconds
Started Mar 10 01:58:16 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202576 kb
Host smart-f2bcad0f-0c50-4e67-93f6-29679d188838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40528
69542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.4052869542
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.708975446
Short name T691
Test name
Test status
Simulation time 61860962 ps
CPU time 1.68 seconds
Started Mar 10 01:58:16 PM PDT 24
Finished Mar 10 01:58:18 PM PDT 24
Peak memory 202520 kb
Host smart-6ab9bfde-ffa8-4340-8f84-f699b14359e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70897
5446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.708975446
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2372059976
Short name T408
Test name
Test status
Simulation time 8395217069 ps
CPU time 8.34 seconds
Started Mar 10 01:58:10 PM PDT 24
Finished Mar 10 01:58:18 PM PDT 24
Peak memory 202564 kb
Host smart-4970a773-a5e3-4c3e-a929-dbb2b99298bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23720
59976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2372059976
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2143468391
Short name T467
Test name
Test status
Simulation time 8410799651 ps
CPU time 7.71 seconds
Started Mar 10 01:58:10 PM PDT 24
Finished Mar 10 01:58:18 PM PDT 24
Peak memory 202564 kb
Host smart-00d67eab-0736-47e1-a42a-cb9ce6dc732f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
68391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2143468391
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2707511291
Short name T239
Test name
Test status
Simulation time 8365468499 ps
CPU time 8.6 seconds
Started Mar 10 01:58:18 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202524 kb
Host smart-fd6a6bf2-1507-4066-8ac6-9a0c0b990e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27075
11291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2707511291
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.2643292648
Short name T595
Test name
Test status
Simulation time 8398073615 ps
CPU time 7.22 seconds
Started Mar 10 01:58:16 PM PDT 24
Finished Mar 10 01:58:24 PM PDT 24
Peak memory 202572 kb
Host smart-e45d7221-33a2-479c-a539-b968638f5a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26432
92648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2643292648
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1691008211
Short name T538
Test name
Test status
Simulation time 8390140093 ps
CPU time 7.79 seconds
Started Mar 10 01:58:09 PM PDT 24
Finished Mar 10 01:58:17 PM PDT 24
Peak memory 202512 kb
Host smart-7947916a-d2b6-4adb-b0b3-bb3104168aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
08211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1691008211
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.989647453
Short name T645
Test name
Test status
Simulation time 8385202969 ps
CPU time 7.31 seconds
Started Mar 10 01:58:20 PM PDT 24
Finished Mar 10 01:58:27 PM PDT 24
Peak memory 202504 kb
Host smart-a2a51265-aa60-4ac0-a3a0-fe43873c6fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98964
7453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.989647453
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.369094101
Short name T512
Test name
Test status
Simulation time 28334845 ps
CPU time 0.69 seconds
Started Mar 10 01:58:19 PM PDT 24
Finished Mar 10 01:58:20 PM PDT 24
Peak memory 202480 kb
Host smart-9036b063-ce32-4fd6-9800-29ad809890b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36909
4101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.369094101
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.998756735
Short name T294
Test name
Test status
Simulation time 8376793870 ps
CPU time 7.48 seconds
Started Mar 10 01:58:08 PM PDT 24
Finished Mar 10 01:58:16 PM PDT 24
Peak memory 202552 kb
Host smart-c0d592d2-2bd6-4fd1-9df1-63e6fdb75565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99875
6735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.998756735
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1972682668
Short name T379
Test name
Test status
Simulation time 8398476665 ps
CPU time 8.03 seconds
Started Mar 10 01:58:18 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202576 kb
Host smart-68508415-1890-4f65-b819-563442c58211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19726
82668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1972682668
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.46309452
Short name T552
Test name
Test status
Simulation time 8362493281 ps
CPU time 8.63 seconds
Started Mar 10 01:58:26 PM PDT 24
Finished Mar 10 01:58:35 PM PDT 24
Peak memory 202576 kb
Host smart-4d0c9899-e933-4f7a-a6a4-e1443070aa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46309
452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.46309452
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3590832218
Short name T154
Test name
Test status
Simulation time 8473467928 ps
CPU time 9.6 seconds
Started Mar 10 01:58:16 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202580 kb
Host smart-2f0056b2-9254-4af6-82ba-20466fd347de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35908
32218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3590832218
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.281113661
Short name T476
Test name
Test status
Simulation time 8373266267 ps
CPU time 9.6 seconds
Started Mar 10 01:58:21 PM PDT 24
Finished Mar 10 01:58:32 PM PDT 24
Peak memory 202572 kb
Host smart-ce545ab7-63dc-491b-9371-a4bb14919119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28111
3661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.281113661
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1522570339
Short name T641
Test name
Test status
Simulation time 79422993 ps
CPU time 1.11 seconds
Started Mar 10 01:58:18 PM PDT 24
Finished Mar 10 01:58:20 PM PDT 24
Peak memory 202620 kb
Host smart-c31dfdf9-9e56-49f1-8410-c6f36a881ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15225
70339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1522570339
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.605075024
Short name T560
Test name
Test status
Simulation time 8402772067 ps
CPU time 7.21 seconds
Started Mar 10 01:58:17 PM PDT 24
Finished Mar 10 01:58:24 PM PDT 24
Peak memory 202556 kb
Host smart-4b765558-2e1b-469e-ab45-7fc5899c3a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60507
5024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.605075024
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2798409297
Short name T338
Test name
Test status
Simulation time 8365351439 ps
CPU time 6.99 seconds
Started Mar 10 01:58:18 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202576 kb
Host smart-5a9d0a88-35e9-4653-a371-77412dc0a6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27984
09297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2798409297
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1105139667
Short name T363
Test name
Test status
Simulation time 8373982392 ps
CPU time 7.63 seconds
Started Mar 10 01:58:18 PM PDT 24
Finished Mar 10 01:58:25 PM PDT 24
Peak memory 202588 kb
Host smart-d19dfb87-189b-4bd2-95c8-fce5c1467e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11051
39667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1105139667
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3913841547
Short name T323
Test name
Test status
Simulation time 8388094231 ps
CPU time 8.58 seconds
Started Mar 10 01:58:27 PM PDT 24
Finished Mar 10 01:58:36 PM PDT 24
Peak memory 202588 kb
Host smart-59f9ec58-bdc6-471a-b5d7-f35ca7b33a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39138
41547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3913841547
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1672095778
Short name T454
Test name
Test status
Simulation time 28773756 ps
CPU time 0.6 seconds
Started Mar 10 01:58:25 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202532 kb
Host smart-593050dc-6151-4df0-a14b-fd776f2f6133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16720
95778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1672095778
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3371352459
Short name T409
Test name
Test status
Simulation time 8424169292 ps
CPU time 8.66 seconds
Started Mar 10 01:58:15 PM PDT 24
Finished Mar 10 01:58:24 PM PDT 24
Peak memory 202544 kb
Host smart-eba1cf86-2ddf-4f39-8ae1-2836497bdde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
52459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3371352459
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1662473710
Short name T678
Test name
Test status
Simulation time 8371350563 ps
CPU time 7.6 seconds
Started Mar 10 01:58:25 PM PDT 24
Finished Mar 10 01:58:33 PM PDT 24
Peak memory 202600 kb
Host smart-32aa78f7-ef72-4589-a831-50cf50f5db1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16624
73710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1662473710
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1210551519
Short name T656
Test name
Test status
Simulation time 8360064425 ps
CPU time 8.9 seconds
Started Mar 10 01:58:17 PM PDT 24
Finished Mar 10 01:58:26 PM PDT 24
Peak memory 202588 kb
Host smart-02654308-eb7d-4531-b65f-6bc40ab1ddf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12105
51519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1210551519
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2207260625
Short name T139
Test name
Test status
Simulation time 8471833181 ps
CPU time 8.07 seconds
Started Mar 10 01:58:19 PM PDT 24
Finished Mar 10 01:58:28 PM PDT 24
Peak memory 202564 kb
Host smart-dd9a54f8-bfc0-4355-b0bb-10d7e5c74c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22072
60625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2207260625
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.131399870
Short name T537
Test name
Test status
Simulation time 8366431203 ps
CPU time 7.94 seconds
Started Mar 10 01:58:19 PM PDT 24
Finished Mar 10 01:58:27 PM PDT 24
Peak memory 202512 kb
Host smart-9e90d76b-99b0-45e9-bedf-556d4fc80e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13139
9870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.131399870
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3515857756
Short name T548
Test name
Test status
Simulation time 134241616 ps
CPU time 1.59 seconds
Started Mar 10 01:58:25 PM PDT 24
Finished Mar 10 01:58:27 PM PDT 24
Peak memory 202532 kb
Host smart-01401a9f-5a09-4252-9d78-df6554b5f9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35158
57756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3515857756
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3400920264
Short name T706
Test name
Test status
Simulation time 8388981069 ps
CPU time 7.76 seconds
Started Mar 10 01:58:25 PM PDT 24
Finished Mar 10 01:58:33 PM PDT 24
Peak memory 202572 kb
Host smart-e3b6bccf-112e-4fab-adc4-1764a82d26ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34009
20264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3400920264
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3115449255
Short name T622
Test name
Test status
Simulation time 8404319576 ps
CPU time 8.03 seconds
Started Mar 10 01:58:22 PM PDT 24
Finished Mar 10 01:58:31 PM PDT 24
Peak memory 202468 kb
Host smart-bbb11c44-c882-4f7d-88b7-64bcf0a38887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31154
49255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3115449255
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1943054044
Short name T522
Test name
Test status
Simulation time 8366057044 ps
CPU time 6.95 seconds
Started Mar 10 01:58:25 PM PDT 24
Finished Mar 10 01:58:32 PM PDT 24
Peak memory 202604 kb
Host smart-46f35d5f-ba63-495b-b9e0-7e4f23b9ebbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19430
54044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1943054044
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.511717587
Short name T483
Test name
Test status
Simulation time 8461506399 ps
CPU time 7.9 seconds
Started Mar 10 01:58:25 PM PDT 24
Finished Mar 10 01:58:33 PM PDT 24
Peak memory 202572 kb
Host smart-c471d388-b471-4a15-8125-36c45c1924a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51171
7587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.511717587
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.367087691
Short name T532
Test name
Test status
Simulation time 8378021914 ps
CPU time 7.5 seconds
Started Mar 10 01:58:21 PM PDT 24
Finished Mar 10 01:58:30 PM PDT 24
Peak memory 202576 kb
Host smart-04daf932-6d57-4de8-8eee-f6bd8f704cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36708
7691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.367087691
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2006548067
Short name T266
Test name
Test status
Simulation time 8389328045 ps
CPU time 7.04 seconds
Started Mar 10 01:58:27 PM PDT 24
Finished Mar 10 01:58:34 PM PDT 24
Peak memory 202632 kb
Host smart-e5695383-19ee-4913-a898-f316e88e8c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20065
48067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2006548067
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1384449872
Short name T421
Test name
Test status
Simulation time 27139830 ps
CPU time 0.65 seconds
Started Mar 10 01:58:30 PM PDT 24
Finished Mar 10 01:58:30 PM PDT 24
Peak memory 202520 kb
Host smart-c385c1b5-d837-485b-940c-bb1bdd1b8292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13844
49872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1384449872
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.26378259
Short name T127
Test name
Test status
Simulation time 8406748236 ps
CPU time 7.58 seconds
Started Mar 10 01:58:14 PM PDT 24
Finished Mar 10 01:58:22 PM PDT 24
Peak memory 202520 kb
Host smart-1820c5aa-5e08-4683-a006-2da79fbab157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26378
259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.26378259
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3023097506
Short name T676
Test name
Test status
Simulation time 8395227006 ps
CPU time 7.47 seconds
Started Mar 10 01:58:24 PM PDT 24
Finished Mar 10 01:58:31 PM PDT 24
Peak memory 202600 kb
Host smart-10f47334-4bcf-4bc7-a32a-4a8c4046894f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30230
97506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3023097506
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3863408258
Short name T39
Test name
Test status
Simulation time 8473734167 ps
CPU time 8.97 seconds
Started Mar 10 01:58:25 PM PDT 24
Finished Mar 10 01:58:34 PM PDT 24
Peak memory 202512 kb
Host smart-b70fd2a5-32f5-41ce-a086-1cd4bb32cb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
08258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3863408258
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4203734671
Short name T306
Test name
Test status
Simulation time 8368764705 ps
CPU time 7.86 seconds
Started Mar 10 01:58:26 PM PDT 24
Finished Mar 10 01:58:34 PM PDT 24
Peak memory 202584 kb
Host smart-a4b3f24b-1ec3-44e0-bc8b-187758aa6c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42037
34671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4203734671
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2394332904
Short name T205
Test name
Test status
Simulation time 128766814 ps
CPU time 1.29 seconds
Started Mar 10 01:58:20 PM PDT 24
Finished Mar 10 01:58:21 PM PDT 24
Peak memory 202568 kb
Host smart-b9535713-2a2f-4a45-9a36-60fe099f27e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23943
32904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2394332904
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3930095430
Short name T661
Test name
Test status
Simulation time 8375721988 ps
CPU time 7.41 seconds
Started Mar 10 01:58:21 PM PDT 24
Finished Mar 10 01:58:29 PM PDT 24
Peak memory 202560 kb
Host smart-6a4af20d-cc2c-4be5-846f-35576dbcd6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39300
95430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3930095430
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2866005898
Short name T665
Test name
Test status
Simulation time 8408978048 ps
CPU time 7.96 seconds
Started Mar 10 01:58:20 PM PDT 24
Finished Mar 10 01:58:29 PM PDT 24
Peak memory 202580 kb
Host smart-b89c49b0-8add-499d-a48a-01d22aac5f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28660
05898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2866005898
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3609807011
Short name T613
Test name
Test status
Simulation time 8366031702 ps
CPU time 8.66 seconds
Started Mar 10 01:58:30 PM PDT 24
Finished Mar 10 01:58:39 PM PDT 24
Peak memory 202560 kb
Host smart-8492ac10-a40c-456a-960d-b14db53c4240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
07011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3609807011
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3441513209
Short name T20
Test name
Test status
Simulation time 8384929706 ps
CPU time 8.34 seconds
Started Mar 10 01:58:23 PM PDT 24
Finished Mar 10 01:58:32 PM PDT 24
Peak memory 202508 kb
Host smart-bfd6cc86-5203-4406-8e68-4b18233507c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34415
13209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3441513209
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1369404737
Short name T256
Test name
Test status
Simulation time 8370360088 ps
CPU time 7.62 seconds
Started Mar 10 01:58:22 PM PDT 24
Finished Mar 10 01:58:31 PM PDT 24
Peak memory 202548 kb
Host smart-fe7a7064-9098-48fd-a524-43a5d90afe68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13694
04737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1369404737
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2545714668
Short name T547
Test name
Test status
Simulation time 30331887 ps
CPU time 0.66 seconds
Started Mar 10 01:58:21 PM PDT 24
Finished Mar 10 01:58:23 PM PDT 24
Peak memory 202520 kb
Host smart-fbe87d54-7afc-4ca8-bfd3-da2f06109273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25457
14668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2545714668
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3922356396
Short name T397
Test name
Test status
Simulation time 8408737891 ps
CPU time 9.49 seconds
Started Mar 10 01:58:18 PM PDT 24
Finished Mar 10 01:58:28 PM PDT 24
Peak memory 202588 kb
Host smart-4aa25781-0093-48d3-bfce-73c686fa9186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39223
56396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3922356396
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1551493232
Short name T255
Test name
Test status
Simulation time 8356297887 ps
CPU time 7.41 seconds
Started Mar 10 01:58:20 PM PDT 24
Finished Mar 10 01:58:28 PM PDT 24
Peak memory 202588 kb
Host smart-5a77f842-ccb8-4fb9-a75d-af17bed4f83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15514
93232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1551493232
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.4262520345
Short name T445
Test name
Test status
Simulation time 8369637355 ps
CPU time 8.55 seconds
Started Mar 10 01:56:17 PM PDT 24
Finished Mar 10 01:56:26 PM PDT 24
Peak memory 202536 kb
Host smart-9241ca9b-6934-4aea-98ac-daa56f4cdf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42625
20345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.4262520345
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3394923019
Short name T78
Test name
Test status
Simulation time 59983577 ps
CPU time 1.75 seconds
Started Mar 10 01:56:17 PM PDT 24
Finished Mar 10 01:56:19 PM PDT 24
Peak memory 202624 kb
Host smart-cc743d5c-978b-4fd6-8c50-2d4f8f8b9fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33949
23019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3394923019
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3331965732
Short name T631
Test name
Test status
Simulation time 8395538682 ps
CPU time 9.05 seconds
Started Mar 10 01:56:17 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202556 kb
Host smart-741d6069-66fb-462b-a236-1668f16984e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33319
65732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3331965732
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2086846754
Short name T508
Test name
Test status
Simulation time 8410028773 ps
CPU time 7.5 seconds
Started Mar 10 01:56:19 PM PDT 24
Finished Mar 10 01:56:26 PM PDT 24
Peak memory 202604 kb
Host smart-fbeb8de2-6839-4fbb-bf92-6abd7bf254e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20868
46754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2086846754
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2308298962
Short name T530
Test name
Test status
Simulation time 8363929365 ps
CPU time 7.62 seconds
Started Mar 10 01:56:19 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202548 kb
Host smart-daf1674d-3b2d-4ec2-b2b2-78e75dc514bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23082
98962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2308298962
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3483651784
Short name T103
Test name
Test status
Simulation time 8399952066 ps
CPU time 8.15 seconds
Started Mar 10 01:56:16 PM PDT 24
Finished Mar 10 01:56:25 PM PDT 24
Peak memory 202592 kb
Host smart-20e7a82d-ec30-43da-9d82-24f8808def02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
51784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3483651784
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2891812863
Short name T350
Test name
Test status
Simulation time 8403116802 ps
CPU time 7.45 seconds
Started Mar 10 01:56:17 PM PDT 24
Finished Mar 10 01:56:25 PM PDT 24
Peak memory 202496 kb
Host smart-9434b6df-4cd2-4a94-8285-4f31c1be0cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28918
12863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2891812863
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.123377503
Short name T361
Test name
Test status
Simulation time 8391049168 ps
CPU time 8.88 seconds
Started Mar 10 01:56:19 PM PDT 24
Finished Mar 10 01:56:28 PM PDT 24
Peak memory 202604 kb
Host smart-b10eb968-87f8-4d81-ad57-f59593bbd511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12337
7503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.123377503
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.4283423597
Short name T687
Test name
Test status
Simulation time 27129093 ps
CPU time 0.65 seconds
Started Mar 10 01:56:25 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202396 kb
Host smart-9ee01ca8-d594-4ca5-97ee-69806de8ac87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42834
23597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.4283423597
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3854363310
Short name T21
Test name
Test status
Simulation time 8443040122 ps
CPU time 7.75 seconds
Started Mar 10 01:56:26 PM PDT 24
Finished Mar 10 01:56:35 PM PDT 24
Peak memory 202520 kb
Host smart-4e78df3c-5cfa-4b3a-b7ac-647ffd043869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38543
63310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3854363310
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.4198979502
Short name T289
Test name
Test status
Simulation time 8392971722 ps
CPU time 8.34 seconds
Started Mar 10 01:56:24 PM PDT 24
Finished Mar 10 01:56:34 PM PDT 24
Peak memory 202540 kb
Host smart-584d63de-34f1-4ac4-bcef-4373ddcfa67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41989
79502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.4198979502
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.2191064283
Short name T606
Test name
Test status
Simulation time 8364173814 ps
CPU time 7.31 seconds
Started Mar 10 01:56:23 PM PDT 24
Finished Mar 10 01:56:32 PM PDT 24
Peak memory 202576 kb
Host smart-6caa3830-2ed1-4d46-a29a-40cc5ecfc8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21910
64283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.2191064283
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2182921613
Short name T540
Test name
Test status
Simulation time 8477552625 ps
CPU time 7.16 seconds
Started Mar 10 01:56:14 PM PDT 24
Finished Mar 10 01:56:22 PM PDT 24
Peak memory 202608 kb
Host smart-5ad8739f-b0ae-4aa8-bb17-8ff69c9619cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21829
21613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2182921613
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.879734514
Short name T368
Test name
Test status
Simulation time 8370829217 ps
CPU time 8.25 seconds
Started Mar 10 01:56:24 PM PDT 24
Finished Mar 10 01:56:34 PM PDT 24
Peak memory 202520 kb
Host smart-c63de88c-e1fd-4ead-985a-e83c704d2018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87973
4514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.879734514
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.4231037172
Short name T298
Test name
Test status
Simulation time 111516336 ps
CPU time 1.16 seconds
Started Mar 10 01:56:25 PM PDT 24
Finished Mar 10 01:56:28 PM PDT 24
Peak memory 202628 kb
Host smart-7460330b-28ac-41ff-9392-49d9b22508f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42310
37172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.4231037172
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.860376675
Short name T377
Test name
Test status
Simulation time 8404176564 ps
CPU time 7.27 seconds
Started Mar 10 01:56:24 PM PDT 24
Finished Mar 10 01:56:32 PM PDT 24
Peak memory 202540 kb
Host smart-2ae5716f-7ca5-40bd-9c48-a1d0a2d4cab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86037
6675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.860376675
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3146330579
Short name T563
Test name
Test status
Simulation time 8405516703 ps
CPU time 8.46 seconds
Started Mar 10 01:56:26 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202524 kb
Host smart-414de8c9-3331-4d97-a594-e0882df6cc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31463
30579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3146330579
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2492182868
Short name T252
Test name
Test status
Simulation time 8362854357 ps
CPU time 8.99 seconds
Started Mar 10 01:56:25 PM PDT 24
Finished Mar 10 01:56:35 PM PDT 24
Peak memory 202548 kb
Host smart-4a1e94d6-0331-43d0-959e-9e2b479459bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24921
82868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2492182868
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.113614401
Short name T93
Test name
Test status
Simulation time 8425298092 ps
CPU time 7.37 seconds
Started Mar 10 01:56:23 PM PDT 24
Finished Mar 10 01:56:32 PM PDT 24
Peak memory 202516 kb
Host smart-8fabdc11-c301-4551-a543-8ccd7db132fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
4401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.113614401
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3864920685
Short name T283
Test name
Test status
Simulation time 8383467480 ps
CPU time 7.01 seconds
Started Mar 10 01:56:23 PM PDT 24
Finished Mar 10 01:56:32 PM PDT 24
Peak memory 202592 kb
Host smart-32b68625-dfca-4f3c-a3f3-88b2daba69d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649
20685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3864920685
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.930309729
Short name T694
Test name
Test status
Simulation time 8374407271 ps
CPU time 7.53 seconds
Started Mar 10 01:56:27 PM PDT 24
Finished Mar 10 01:56:35 PM PDT 24
Peak memory 202556 kb
Host smart-578fd221-35e6-4d0e-89b1-5da8dbb562d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93030
9729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.930309729
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1286927100
Short name T589
Test name
Test status
Simulation time 31885185 ps
CPU time 0.66 seconds
Started Mar 10 01:56:25 PM PDT 24
Finished Mar 10 01:56:27 PM PDT 24
Peak memory 202480 kb
Host smart-1b5a55ac-7958-4b99-86be-2d24b5541b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
27100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1286927100
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1226607886
Short name T274
Test name
Test status
Simulation time 8416916389 ps
CPU time 8.21 seconds
Started Mar 10 01:56:27 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202568 kb
Host smart-0132fd16-6006-417d-9ae3-ac9fc6147734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12266
07886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1226607886
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.629779887
Short name T644
Test name
Test status
Simulation time 8367722362 ps
CPU time 7.52 seconds
Started Mar 10 01:56:26 PM PDT 24
Finished Mar 10 01:56:34 PM PDT 24
Peak memory 202556 kb
Host smart-9251db41-b76c-4c3d-bfb0-30ae808a7f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62977
9887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.629779887
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1303352784
Short name T457
Test name
Test status
Simulation time 8359845746 ps
CPU time 9.19 seconds
Started Mar 10 01:56:26 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202464 kb
Host smart-72fdf5b3-3984-4263-a71b-eeabb8e3494b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13033
52784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1303352784
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.191276814
Short name T137
Test name
Test status
Simulation time 8478196723 ps
CPU time 7.58 seconds
Started Mar 10 01:56:25 PM PDT 24
Finished Mar 10 01:56:33 PM PDT 24
Peak memory 202632 kb
Host smart-18024bbf-e45c-4d38-b444-2eb1373ddda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19127
6814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.191276814
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2712959236
Short name T322
Test name
Test status
Simulation time 8370364681 ps
CPU time 8.86 seconds
Started Mar 10 01:56:26 PM PDT 24
Finished Mar 10 01:56:35 PM PDT 24
Peak memory 202588 kb
Host smart-58b12425-72a6-4f23-8c3c-4a496ab12b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27129
59236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2712959236
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.866607637
Short name T72
Test name
Test status
Simulation time 163247007 ps
CPU time 1.92 seconds
Started Mar 10 01:56:27 PM PDT 24
Finished Mar 10 01:56:30 PM PDT 24
Peak memory 202588 kb
Host smart-ee1490fb-759c-45e7-9371-07f9109f9aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86660
7637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.866607637
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2598379812
Short name T123
Test name
Test status
Simulation time 8428155988 ps
CPU time 7.97 seconds
Started Mar 10 01:56:26 PM PDT 24
Finished Mar 10 01:56:34 PM PDT 24
Peak memory 202544 kb
Host smart-876edbc0-300c-46e5-8410-00a87e6c2e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
79812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2598379812
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1358601230
Short name T257
Test name
Test status
Simulation time 8411189521 ps
CPU time 8.4 seconds
Started Mar 10 01:56:24 PM PDT 24
Finished Mar 10 01:56:33 PM PDT 24
Peak memory 202592 kb
Host smart-9c18f0a5-d729-4716-af8e-4992bda92a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13586
01230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1358601230
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1441522356
Short name T602
Test name
Test status
Simulation time 8360931623 ps
CPU time 9.31 seconds
Started Mar 10 01:56:25 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202576 kb
Host smart-26736324-fa0c-4dc7-a331-be41b8afa21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14415
22356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1441522356
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3301248987
Short name T442
Test name
Test status
Simulation time 8403201567 ps
CPU time 8.94 seconds
Started Mar 10 01:56:26 PM PDT 24
Finished Mar 10 01:56:37 PM PDT 24
Peak memory 202536 kb
Host smart-be776c39-7292-46a0-98d9-37826c74c4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33012
48987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3301248987
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4037990887
Short name T689
Test name
Test status
Simulation time 8385208194 ps
CPU time 7.67 seconds
Started Mar 10 01:56:27 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202568 kb
Host smart-ebf02ead-8621-4cc4-b4ae-67e72445f38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40379
90887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4037990887
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.920976281
Short name T586
Test name
Test status
Simulation time 8396393343 ps
CPU time 9.46 seconds
Started Mar 10 01:56:25 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202556 kb
Host smart-bfec4eae-c927-473c-9c1f-dbb97d8105ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92097
6281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.920976281
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1671328802
Short name T23
Test name
Test status
Simulation time 26602740 ps
CPU time 0.68 seconds
Started Mar 10 01:56:31 PM PDT 24
Finished Mar 10 01:56:32 PM PDT 24
Peak memory 202536 kb
Host smart-658c4870-8012-4923-a04c-e2b0ef7c4340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
28802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1671328802
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2627808052
Short name T264
Test name
Test status
Simulation time 8403775552 ps
CPU time 8.19 seconds
Started Mar 10 01:56:29 PM PDT 24
Finished Mar 10 01:56:37 PM PDT 24
Peak memory 202600 kb
Host smart-2b86ba95-d268-4c8d-95dc-647df110fe76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26278
08052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2627808052
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1033266802
Short name T579
Test name
Test status
Simulation time 8357038892 ps
CPU time 7.88 seconds
Started Mar 10 01:56:30 PM PDT 24
Finished Mar 10 01:56:39 PM PDT 24
Peak memory 202560 kb
Host smart-bda574a3-69b4-4dd9-bb69-c692eedd0170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10332
66802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1033266802
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.477702440
Short name T147
Test name
Test status
Simulation time 8473912422 ps
CPU time 8.16 seconds
Started Mar 10 01:56:26 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202576 kb
Host smart-8f5036f7-f035-417b-83ab-2f5d464f88b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47770
2440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.477702440
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1671329967
Short name T366
Test name
Test status
Simulation time 8374753361 ps
CPU time 7.54 seconds
Started Mar 10 01:56:30 PM PDT 24
Finished Mar 10 01:56:37 PM PDT 24
Peak memory 202576 kb
Host smart-f8e1a519-ebca-44ab-bd2b-946326e495da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
29967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1671329967
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2795515288
Short name T186
Test name
Test status
Simulation time 73017501 ps
CPU time 1.99 seconds
Started Mar 10 01:56:29 PM PDT 24
Finished Mar 10 01:56:31 PM PDT 24
Peak memory 202572 kb
Host smart-b4558252-df1c-40a7-bde4-de241acdfa39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
15288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2795515288
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.718134999
Short name T360
Test name
Test status
Simulation time 8457203966 ps
CPU time 7.31 seconds
Started Mar 10 01:56:28 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202488 kb
Host smart-8458d751-f910-4a6a-8d53-ec379d66b0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71813
4999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.718134999
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.89821500
Short name T431
Test name
Test status
Simulation time 8412036305 ps
CPU time 8.11 seconds
Started Mar 10 01:56:30 PM PDT 24
Finished Mar 10 01:56:38 PM PDT 24
Peak memory 202464 kb
Host smart-a2adffc9-5d22-4b33-a033-100fe550eaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89821
500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.89821500
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1590662148
Short name T6
Test name
Test status
Simulation time 8368534187 ps
CPU time 8.17 seconds
Started Mar 10 01:56:32 PM PDT 24
Finished Mar 10 01:56:40 PM PDT 24
Peak memory 202588 kb
Host smart-f6986cf4-76f3-4629-bf75-402f8f5140ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15906
62148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1590662148
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3800446202
Short name T598
Test name
Test status
Simulation time 8418162861 ps
CPU time 7.63 seconds
Started Mar 10 01:56:31 PM PDT 24
Finished Mar 10 01:56:38 PM PDT 24
Peak memory 202560 kb
Host smart-c2e60fe1-c658-43dd-bfec-d7263f706c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38004
46202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3800446202
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3119299548
Short name T521
Test name
Test status
Simulation time 8369130864 ps
CPU time 8.21 seconds
Started Mar 10 01:56:32 PM PDT 24
Finished Mar 10 01:56:40 PM PDT 24
Peak memory 202508 kb
Host smart-796e8e6d-23ca-47ad-ace1-4c6bf57df454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31192
99548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3119299548
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1149556439
Short name T74
Test name
Test status
Simulation time 8370702439 ps
CPU time 9.94 seconds
Started Mar 10 01:56:30 PM PDT 24
Finished Mar 10 01:56:41 PM PDT 24
Peak memory 202564 kb
Host smart-897d9c62-5545-44bb-81fb-f92b3e91cf11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11495
56439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1149556439
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1761120435
Short name T488
Test name
Test status
Simulation time 22667504 ps
CPU time 0.64 seconds
Started Mar 10 01:56:30 PM PDT 24
Finished Mar 10 01:56:31 PM PDT 24
Peak memory 202508 kb
Host smart-3b1ab929-ebc3-4ccd-82f7-3d098328699a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17611
20435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1761120435
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2238531687
Short name T114
Test name
Test status
Simulation time 8439892719 ps
CPU time 7.84 seconds
Started Mar 10 01:56:32 PM PDT 24
Finished Mar 10 01:56:40 PM PDT 24
Peak memory 202548 kb
Host smart-4cd39789-87e1-47b1-a025-f2247ca3851b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22385
31687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2238531687
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2934883319
Short name T525
Test name
Test status
Simulation time 8387459247 ps
CPU time 8.24 seconds
Started Mar 10 01:56:32 PM PDT 24
Finished Mar 10 01:56:40 PM PDT 24
Peak memory 202536 kb
Host smart-9551d926-d5a7-4bec-b475-803673b50538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29348
83319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2934883319
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.75518351
Short name T254
Test name
Test status
Simulation time 8362871090 ps
CPU time 7.36 seconds
Started Mar 10 01:56:32 PM PDT 24
Finished Mar 10 01:56:40 PM PDT 24
Peak memory 202556 kb
Host smart-f794638d-281e-42d4-ae38-6cdbbb02c5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75518
351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.75518351
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1391637662
Short name T157
Test name
Test status
Simulation time 8475978805 ps
CPU time 7.82 seconds
Started Mar 10 01:56:29 PM PDT 24
Finished Mar 10 01:56:37 PM PDT 24
Peak memory 202656 kb
Host smart-8b8d7ab7-7ea8-46ef-bd5f-b0ad4f9d7ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13916
37662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1391637662
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1304525741
Short name T334
Test name
Test status
Simulation time 8371147548 ps
CPU time 8.24 seconds
Started Mar 10 01:56:37 PM PDT 24
Finished Mar 10 01:56:45 PM PDT 24
Peak memory 202576 kb
Host smart-9ece2a5b-f9a2-4d81-9c40-de7e9fd0f713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13045
25741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1304525741
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.607278036
Short name T564
Test name
Test status
Simulation time 235648119 ps
CPU time 2 seconds
Started Mar 10 01:56:34 PM PDT 24
Finished Mar 10 01:56:36 PM PDT 24
Peak memory 202572 kb
Host smart-76586d00-b207-4937-85d2-87fca62f729f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60727
8036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.607278036
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3441427225
Short name T637
Test name
Test status
Simulation time 8371814159 ps
CPU time 7.61 seconds
Started Mar 10 01:56:37 PM PDT 24
Finished Mar 10 01:56:44 PM PDT 24
Peak memory 202560 kb
Host smart-92c1bc2d-5cd9-4f20-8c92-6dbce6cf1797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34414
27225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3441427225
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.4277403793
Short name T582
Test name
Test status
Simulation time 8404649927 ps
CPU time 8.61 seconds
Started Mar 10 01:56:45 PM PDT 24
Finished Mar 10 01:56:53 PM PDT 24
Peak memory 202480 kb
Host smart-d38903eb-228d-4298-a050-2af240c374fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42774
03793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.4277403793
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1210351032
Short name T295
Test name
Test status
Simulation time 8365304378 ps
CPU time 8.41 seconds
Started Mar 10 01:56:35 PM PDT 24
Finished Mar 10 01:56:43 PM PDT 24
Peak memory 202576 kb
Host smart-7d9fa36b-b84d-44e6-88ef-e290c2df066f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12103
51032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1210351032
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1994204239
Short name T92
Test name
Test status
Simulation time 8456173771 ps
CPU time 7.56 seconds
Started Mar 10 01:56:35 PM PDT 24
Finished Mar 10 01:56:42 PM PDT 24
Peak memory 202588 kb
Host smart-79d1de44-4040-4a00-86ce-3d88a8c06e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19942
04239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1994204239
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2856455752
Short name T700
Test name
Test status
Simulation time 8384656839 ps
CPU time 7.34 seconds
Started Mar 10 01:56:33 PM PDT 24
Finished Mar 10 01:56:41 PM PDT 24
Peak memory 202572 kb
Host smart-59a84021-5c1a-42a8-b32e-2c588e819e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28564
55752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2856455752
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4142677228
Short name T617
Test name
Test status
Simulation time 8376630144 ps
CPU time 7.82 seconds
Started Mar 10 01:56:36 PM PDT 24
Finished Mar 10 01:56:44 PM PDT 24
Peak memory 202556 kb
Host smart-eb7912b3-18be-4041-a17d-4def0e0c92b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41426
77228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4142677228
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1894579568
Short name T392
Test name
Test status
Simulation time 25086952 ps
CPU time 0.64 seconds
Started Mar 10 01:56:38 PM PDT 24
Finished Mar 10 01:56:39 PM PDT 24
Peak memory 202436 kb
Host smart-5aa9a84e-b9ae-45c2-8a9e-90603cffe4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18945
79568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1894579568
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1185266876
Short name T684
Test name
Test status
Simulation time 8446571653 ps
CPU time 7.19 seconds
Started Mar 10 01:56:35 PM PDT 24
Finished Mar 10 01:56:42 PM PDT 24
Peak memory 202552 kb
Host smart-0c082152-c74b-43ac-a7b8-e93d07bf29d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11852
66876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1185266876
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1793764234
Short name T428
Test name
Test status
Simulation time 8366635040 ps
CPU time 9.91 seconds
Started Mar 10 01:56:37 PM PDT 24
Finished Mar 10 01:56:47 PM PDT 24
Peak memory 202560 kb
Host smart-a83c3b58-53d3-4ec6-b887-84a45ac9bc65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937
64234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1793764234
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1891250482
Short name T270
Test name
Test status
Simulation time 8359043297 ps
CPU time 8.66 seconds
Started Mar 10 01:56:34 PM PDT 24
Finished Mar 10 01:56:43 PM PDT 24
Peak memory 202572 kb
Host smart-babd5ed9-1e87-4069-b335-a7398436aa95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18912
50482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1891250482
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1519735887
Short name T592
Test name
Test status
Simulation time 8477626003 ps
CPU time 7.72 seconds
Started Mar 10 01:56:33 PM PDT 24
Finished Mar 10 01:56:41 PM PDT 24
Peak memory 202616 kb
Host smart-ebae7a34-8586-4581-8abf-32105dc60970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15197
35887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1519735887
Directory /workspace/9.usbdev_smoke/latest
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