Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2255	1		T1	2		T2	3		T3	4
all_values[1]	2255	1		T1	2		T2	3		T3	4
all_values[2]	2255	1		T1	2		T2	3		T3	4
all_values[3]	2255	1		T1	2		T2	3		T3	4
all_values[4]	2255	1		T1	2		T2	3		T3	4
all_values[5]	2255	1		T1	2		T2	3		T3	4
all_values[6]	2255	1		T1	2		T2	3		T3	4
all_values[7]	2255	1		T1	2		T2	3		T3	4
all_values[8]	2255	1		T1	2		T2	3		T3	4
all_values[9]	2255	1		T1	2		T2	3		T3	4
all_values[10]	2255	1		T1	2		T2	3		T3	4
all_values[11]	2255	1		T1	2		T2	3		T3	4
all_values[12]	2255	1		T1	2		T2	3		T3	4
all_values[13]	2255	1		T1	2		T2	3		T3	4
all_values[14]	2255	1		T1	2		T2	3		T3	4
all_values[15]	2255	1		T1	2		T2	3		T3	4
all_values[16]	2255	1		T1	2		T2	3		T3	4
all_values[17]	2255	1		T1	2		T2	3		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	37446	1		T1	36		T2	54		T3	72
auto[1]	3144	1		T6	2		T7	2		T10	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36209	1		T1	36		T2	54		T3	72
auto[1]	4381	1		T54	127		T55	117		T56	125

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1741	1		T1	2		T2	3		T3	4
all_values[0]	auto[0]	auto[1]	129	1		T54	4		T55	4		T56	3
all_values[0]	auto[1]	auto[0]	278	1		T6	2		T7	2		T12	2
all_values[0]	auto[1]	auto[1]	107	1		T54	4		T55	2		T56	4
all_values[1]	auto[0]	auto[0]	1719	1		T1	2		T2	3		T3	4
all_values[1]	auto[0]	auto[1]	97	1		T54	2		T55	2		T56	5
all_values[1]	auto[1]	auto[0]	293	1		T10	3		T20	3		T21	3
all_values[1]	auto[1]	auto[1]	146	1		T54	6		T55	6		T56	3
all_values[2]	auto[0]	auto[0]	1986	1		T1	2		T2	3		T3	4
all_values[2]	auto[0]	auto[1]	130	1		T54	1		T55	1		T56	3
all_values[2]	auto[1]	auto[0]	20	1		T54	1		T56	1		T57	1
all_values[2]	auto[1]	auto[1]	119	1		T54	5		T55	7		T56	4
all_values[3]	auto[0]	auto[0]	1991	1		T1	2		T2	3		T3	4
all_values[3]	auto[0]	auto[1]	125	1		T54	2		T56	4		T57	2
all_values[3]	auto[1]	auto[0]	21	1		T55	3		T207	4		T208	1
all_values[3]	auto[1]	auto[1]	118	1		T54	6		T55	3		T56	3
all_values[4]	auto[0]	auto[0]	1997	1		T1	2		T2	3		T3	4
all_values[4]	auto[0]	auto[1]	113	1		T54	1		T55	6		T56	5
all_values[4]	auto[1]	auto[0]	21	1		T54	1		T56	1		T57	1
all_values[4]	auto[1]	auto[1]	124	1		T54	4		T55	2		T56	2
all_values[5]	auto[0]	auto[0]	1990	1		T1	2		T2	3		T3	4
all_values[5]	auto[0]	auto[1]	117	1		T54	1		T55	2		T56	5
all_values[5]	auto[1]	auto[0]	22	1		T54	1		T55	2		T56	1
all_values[5]	auto[1]	auto[1]	126	1		T54	3		T55	3		T56	2
all_values[6]	auto[0]	auto[0]	1988	1		T1	2		T2	3		T3	4
all_values[6]	auto[0]	auto[1]	102	1		T54	3		T55	2		T56	5
all_values[6]	auto[1]	auto[0]	27	1		T56	1		T209	4		T203	1
all_values[6]	auto[1]	auto[1]	138	1		T54	5		T55	6		T56	1
all_values[7]	auto[0]	auto[0]	1985	1		T1	2		T2	3		T3	4
all_values[7]	auto[0]	auto[1]	103	1		T54	3		T55	6		T56	2
all_values[7]	auto[1]	auto[0]	24	1		T55	1		T56	1		T203	1
all_values[7]	auto[1]	auto[1]	143	1		T54	5		T55	1		T56	5
all_values[8]	auto[0]	auto[0]	2007	1		T1	2		T2	3		T3	4
all_values[8]	auto[0]	auto[1]	106	1		T54	4		T55	3		T56	1
all_values[8]	auto[1]	auto[0]	20	1		T57	1		T209	1		T203	1
all_values[8]	auto[1]	auto[1]	122	1		T54	3		T55	4		T56	6
all_values[9]	auto[0]	auto[0]	1998	1		T1	2		T2	3		T3	4
all_values[9]	auto[0]	auto[1]	141	1		T54	6		T55	1		T56	5
all_values[9]	auto[1]	auto[0]	16	1		T55	1		T210	1		T211	1
all_values[9]	auto[1]	auto[1]	100	1		T54	1		T55	4		T56	3
all_values[10]	auto[0]	auto[0]	1985	1		T1	2		T2	3		T3	4
all_values[10]	auto[0]	auto[1]	111	1		T54	4		T55	4		T56	4
all_values[10]	auto[1]	auto[0]	22	1		T209	5		T203	1		T211	1
all_values[10]	auto[1]	auto[1]	137	1		T54	4		T55	4		T56	3
all_values[11]	auto[0]	auto[0]	1987	1		T1	2		T2	3		T3	4
all_values[11]	auto[0]	auto[1]	121	1		T55	6		T56	7		T57	3
all_values[11]	auto[1]	auto[0]	9	1		T54	1		T212	1		T213	1
all_values[11]	auto[1]	auto[1]	138	1		T54	6		T55	1		T56	1
all_values[12]	auto[0]	auto[0]	1987	1		T1	2		T2	3		T3	4
all_values[12]	auto[0]	auto[1]	135	1		T54	2		T55	4		T56	2
all_values[12]	auto[1]	auto[0]	19	1		T55	1		T57	1		T203	1
all_values[12]	auto[1]	auto[1]	114	1		T54	5		T55	2		T56	6
all_values[13]	auto[0]	auto[0]	1990	1		T1	2		T2	3		T3	4
all_values[13]	auto[0]	auto[1]	106	1		T54	4		T55	6		T56	4
all_values[13]	auto[1]	auto[0]	28	1		T54	1		T57	1		T213	2
all_values[13]	auto[1]	auto[1]	131	1		T54	3		T55	1		T56	2
all_values[14]	auto[0]	auto[0]	1980	1		T1	2		T2	3		T3	4
all_values[14]	auto[0]	auto[1]	151	1		T54	2		T55	3		T56	4
all_values[14]	auto[1]	auto[0]	23	1		T54	1		T55	1		T210	2
all_values[14]	auto[1]	auto[1]	101	1		T54	5		T55	4		T56	4
all_values[15]	auto[0]	auto[0]	1986	1		T1	2		T2	3		T3	4
all_values[15]	auto[0]	auto[1]	124	1		T54	3		T55	1		T56	3
all_values[15]	auto[1]	auto[0]	24	1		T55	1		T56	1		T57	1
all_values[15]	auto[1]	auto[1]	121	1		T54	5		T55	5		T56	2
all_values[16]	auto[0]	auto[0]	1989	1		T1	2		T2	3		T3	4
all_values[16]	auto[0]	auto[1]	99	1		T54	5		T55	2		T56	4
all_values[16]	auto[1]	auto[0]	27	1		T55	2		T56	3		T210	3
all_values[16]	auto[1]	auto[1]	140	1		T54	2		T55	4		T56	1
all_values[17]	auto[0]	auto[0]	1986	1		T1	2		T2	3		T3	4
all_values[17]	auto[0]	auto[1]	144	1		T54	6		T55	4		T56	7
all_values[17]	auto[1]	auto[0]	23	1		T55	2		T56	1		T57	1
all_values[17]	auto[1]	auto[1]	102	1		T54	2		T55	1		T57	1