Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2255	1		T1	2		T2	3		T3	4
all_pins[1]	2255	1		T1	2		T2	3		T3	4
all_pins[2]	2255	1		T1	2		T2	3		T3	4
all_pins[3]	2255	1		T1	2		T2	3		T3	4
all_pins[4]	2255	1		T1	2		T2	3		T3	4
all_pins[5]	2255	1		T1	2		T2	3		T3	4
all_pins[6]	2255	1		T1	2		T2	3		T3	4
all_pins[7]	2255	1		T1	2		T2	3		T3	4
all_pins[8]	2255	1		T1	2		T2	3		T3	4
all_pins[9]	2255	1		T1	2		T2	3		T3	4
all_pins[10]	2255	1		T1	2		T2	3		T3	4
all_pins[11]	2255	1		T1	2		T2	3		T3	4
all_pins[12]	2255	1		T1	2		T2	3		T3	4
all_pins[13]	2255	1		T1	2		T2	3		T3	4
all_pins[14]	2255	1		T1	2		T2	3		T3	4
all_pins[15]	2255	1		T1	2		T2	3		T3	4
all_pins[16]	2255	1		T1	2		T2	3		T3	4
all_pins[17]	2255	1		T1	2		T2	3		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	39469	1		T1	36		T2	54		T3	72
values[0x1]	1121	1		T10	1		T20	1		T21	1
transitions[0x0=>0x1]	858	1		T10	1		T20	1		T21	1
transitions[0x1=>0x0]	869	1		T10	1		T20	1		T21	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2209	1		T1	2		T2	3		T3	4
all_pins[0]	values[0x1]	46	1		T54	1		T55	2		T56	2
all_pins[0]	transitions[0x0=>0x1]	37	1		T54	1		T55	2		T56	1
all_pins[0]	transitions[0x1=>0x0]	149	1		T10	1		T20	1		T21	1
all_pins[1]	values[0x0]	2097	1		T1	2		T2	3		T3	4
all_pins[1]	values[0x1]	158	1		T10	1		T20	1		T21	1
all_pins[1]	transitions[0x0=>0x1]	139	1		T10	1		T20	1		T21	1
all_pins[1]	transitions[0x1=>0x0]	46	1		T54	3		T210	2		T203	4
all_pins[2]	values[0x0]	2190	1		T1	2		T2	3		T3	4
all_pins[2]	values[0x1]	65	1		T54	4		T55	1		T56	2
all_pins[2]	transitions[0x0=>0x1]	43	1		T54	1		T55	1		T56	2
all_pins[2]	transitions[0x1=>0x0]	37	1		T55	2		T56	1		T203	2
all_pins[3]	values[0x0]	2196	1		T1	2		T2	3		T3	4
all_pins[3]	values[0x1]	59	1		T54	3		T55	2		T56	1
all_pins[3]	transitions[0x0=>0x1]	39	1		T54	1		T55	2		T56	1
all_pins[3]	transitions[0x1=>0x0]	45	1		T54	1		T56	2		T210	2
all_pins[4]	values[0x0]	2190	1		T1	2		T2	3		T3	4
all_pins[4]	values[0x1]	65	1		T54	3		T56	2		T210	3
all_pins[4]	transitions[0x0=>0x1]	48	1		T54	1		T56	2		T210	3
all_pins[4]	transitions[0x1=>0x0]	39	1		T56	2		T57	3		T209	1
all_pins[5]	values[0x0]	2199	1		T1	2		T2	3		T3	4
all_pins[5]	values[0x1]	56	1		T54	2		T56	2		T57	3
all_pins[5]	transitions[0x0=>0x1]	39	1		T56	2		T209	1		T203	4
all_pins[5]	transitions[0x1=>0x0]	43	1		T54	2		T55	5		T210	2
all_pins[6]	values[0x0]	2195	1		T1	2		T2	3		T3	4
all_pins[6]	values[0x1]	60	1		T54	4		T55	5		T57	3
all_pins[6]	transitions[0x0=>0x1]	50	1		T54	4		T55	5		T57	2
all_pins[6]	transitions[0x1=>0x0]	44	1		T56	3		T210	2		T209	1
all_pins[7]	values[0x0]	2201	1		T1	2		T2	3		T3	4
all_pins[7]	values[0x1]	54	1		T56	3		T57	1		T210	3
all_pins[7]	transitions[0x0=>0x1]	42	1		T56	2		T57	1		T209	1
all_pins[7]	transitions[0x1=>0x0]	36	1		T54	1		T55	3		T56	1
all_pins[8]	values[0x0]	2207	1		T1	2		T2	3		T3	4
all_pins[8]	values[0x1]	48	1		T54	1		T55	3		T56	2
all_pins[8]	transitions[0x0=>0x1]	43	1		T54	1		T55	3		T56	2
all_pins[8]	transitions[0x1=>0x0]	35	1		T54	1		T55	2		T56	1
all_pins[9]	values[0x0]	2215	1		T1	2		T2	3		T3	4
all_pins[9]	values[0x1]	40	1		T54	1		T55	2		T56	1
all_pins[9]	transitions[0x0=>0x1]	30	1		T54	1		T55	2		T56	1
all_pins[9]	transitions[0x1=>0x0]	61	1		T54	2		T55	3		T56	2
all_pins[10]	values[0x0]	2184	1		T1	2		T2	3		T3	4
all_pins[10]	values[0x1]	71	1		T54	2		T55	3		T56	2
all_pins[10]	transitions[0x0=>0x1]	50	1		T54	1		T55	2		T56	2
all_pins[10]	transitions[0x1=>0x0]	45	1		T54	4		T56	1		T210	4
all_pins[11]	values[0x0]	2189	1		T1	2		T2	3		T3	4
all_pins[11]	values[0x1]	66	1		T54	5		T55	1		T56	1
all_pins[11]	transitions[0x0=>0x1]	55	1		T54	3		T55	1		T210	4
all_pins[11]	transitions[0x1=>0x0]	35	1		T54	1		T56	2		T57	3
all_pins[12]	values[0x0]	2209	1		T1	2		T2	3		T3	4
all_pins[12]	values[0x1]	46	1		T54	3		T56	3		T57	3
all_pins[12]	transitions[0x0=>0x1]	24	1		T54	2		T56	2		T57	1
all_pins[12]	transitions[0x1=>0x0]	44	1		T54	1		T55	1		T210	4
all_pins[13]	values[0x0]	2189	1		T1	2		T2	3		T3	4
all_pins[13]	values[0x1]	66	1		T54	2		T55	1		T56	1
all_pins[13]	transitions[0x0=>0x1]	52	1		T54	1		T55	1		T56	1
all_pins[13]	transitions[0x1=>0x0]	32	1		T54	2		T56	3		T210	1
all_pins[14]	values[0x0]	2209	1		T1	2		T2	3		T3	4
all_pins[14]	values[0x1]	46	1		T54	3		T56	3		T210	1
all_pins[14]	transitions[0x0=>0x1]	36	1		T54	2		T56	3		T210	1
all_pins[14]	transitions[0x1=>0x0]	58	1		T54	1		T55	3		T56	2
all_pins[15]	values[0x0]	2187	1		T1	2		T2	3		T3	4
all_pins[15]	values[0x1]	68	1		T54	2		T55	3		T56	2
all_pins[15]	transitions[0x0=>0x1]	52	1		T54	2		T55	1		T56	2
all_pins[15]	transitions[0x1=>0x0]	46	1		T54	2		T210	2		T209	1
all_pins[16]	values[0x0]	2193	1		T1	2		T2	3		T3	4
all_pins[16]	values[0x1]	62	1		T54	2		T55	2		T210	2
all_pins[16]	transitions[0x0=>0x1]	53	1		T54	1		T55	2		T210	2
all_pins[16]	transitions[0x1=>0x0]	36	1		T55	1		T57	1		T210	2
all_pins[17]	values[0x0]	2210	1		T1	2		T2	3		T3	4
all_pins[17]	values[0x1]	45	1		T54	1		T55	1		T57	1
all_pins[17]	transitions[0x0=>0x1]	26	1		T54	1		T57	1		T210	2
all_pins[17]	transitions[0x1=>0x0]	38	1		T54	1		T55	1		T56	2