Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	245	1		T54	7		T55	7		T56	7
all_values[1]	245	1		T54	7		T55	7		T56	7
all_values[2]	245	1		T54	7		T55	7		T56	7
all_values[3]	245	1		T54	7		T55	7		T56	7
all_values[4]	245	1		T54	7		T55	7		T56	7
all_values[5]	245	1		T54	7		T55	7		T56	7
all_values[6]	245	1		T54	7		T55	7		T56	7
all_values[7]	245	1		T54	7		T55	7		T56	7
all_values[8]	245	1		T54	7		T55	7		T56	7
all_values[9]	245	1		T54	7		T55	7		T56	7
all_values[10]	245	1		T54	7		T55	7		T56	7
all_values[11]	245	1		T54	7		T55	7		T56	7
all_values[12]	245	1		T54	7		T55	7		T56	7
all_values[13]	245	1		T54	7		T55	7		T56	7
all_values[14]	245	1		T54	7		T55	7		T56	7
all_values[15]	245	1		T54	7		T55	7		T56	7
all_values[16]	245	1		T54	7		T55	7		T56	7
all_values[17]	245	1		T54	7		T55	7		T56	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2336	1		T54	69		T55	52		T56	72
auto[1]	2074	1		T54	57		T55	74		T56	54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	734	1		T54	17		T55	27		T56	19
auto[1]	3676	1		T54	109		T55	99		T56	107

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2565	1		T54	70		T55	76		T56	69
auto[1]	1845	1		T54	56		T55	50		T56	57

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	27	1		T56	1		T210	1		T209	1
all_values[0]	auto[0]	auto[0]	auto[1]	52	1		T54	2		T55	1		T210	1
all_values[0]	auto[0]	auto[1]	auto[0]	21	1		T55	2		T57	4		T207	1
all_values[0]	auto[0]	auto[1]	auto[1]	47	1		T54	1		T55	1		T56	1
all_values[0]	auto[1]	auto[0]	auto[1]	60	1		T54	4		T55	1		T56	4
all_values[0]	auto[1]	auto[1]	auto[1]	38	1		T55	2		T56	1		T209	1
all_values[1]	auto[0]	auto[0]	auto[0]	22	1		T209	2		T203	1		T213	1
all_values[1]	auto[0]	auto[0]	auto[1]	51	1		T54	2		T55	1		T56	2
all_values[1]	auto[0]	auto[1]	auto[0]	18	1		T207	1		T213	3		T211	2
all_values[1]	auto[0]	auto[1]	auto[1]	59	1		T54	3		T55	3		T210	4
all_values[1]	auto[1]	auto[0]	auto[1]	36	1		T54	1		T55	1		T56	1
all_values[1]	auto[1]	auto[1]	auto[1]	59	1		T54	1		T55	2		T56	4
all_values[2]	auto[0]	auto[0]	auto[0]	22	1		T54	1		T210	1		T209	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1		T55	1		T57	1		T210	2
all_values[2]	auto[0]	auto[1]	auto[0]	14	1		T54	1		T56	1		T57	1
all_values[2]	auto[0]	auto[1]	auto[1]	51	1		T54	1		T55	4		T56	2
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T54	1		T55	1		T56	3
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T54	3		T55	1		T56	1
all_values[3]	auto[0]	auto[0]	auto[0]	25	1		T55	1		T56	1		T209	1
all_values[3]	auto[0]	auto[0]	auto[1]	60	1		T56	1		T210	2		T209	1
all_values[3]	auto[0]	auto[1]	auto[0]	15	1		T55	4		T207	2		T208	1
all_values[3]	auto[0]	auto[1]	auto[1]	42	1		T54	2		T55	1		T56	1
all_values[3]	auto[1]	auto[0]	auto[1]	55	1		T54	4		T56	2		T57	2
all_values[3]	auto[1]	auto[1]	auto[1]	48	1		T54	1		T55	1		T56	2
all_values[4]	auto[0]	auto[0]	auto[0]	29	1		T54	1		T57	3		T209	2
all_values[4]	auto[0]	auto[0]	auto[1]	40	1		T54	1		T55	2		T56	1
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T54	2		T56	1		T57	1
all_values[4]	auto[0]	auto[1]	auto[1]	51	1		T54	2		T55	1		T210	3
all_values[4]	auto[1]	auto[0]	auto[1]	61	1		T54	1		T55	3		T56	2
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T55	1		T56	3		T210	2
all_values[5]	auto[0]	auto[0]	auto[0]	24	1		T54	3		T55	1		T210	3
all_values[5]	auto[0]	auto[0]	auto[1]	47	1		T56	3		T209	1		T203	3
all_values[5]	auto[0]	auto[1]	auto[0]	18	1		T54	1		T55	2		T56	1
all_values[5]	auto[0]	auto[1]	auto[1]	49	1		T54	1		T55	2		T56	2
all_values[5]	auto[1]	auto[0]	auto[1]	63	1		T54	2		T55	2		T56	1
all_values[5]	auto[1]	auto[1]	auto[1]	44	1		T57	2		T210	1		T209	2
all_values[6]	auto[0]	auto[0]	auto[0]	25	1		T56	1		T209	2		T203	1
all_values[6]	auto[0]	auto[0]	auto[1]	36	1		T54	1		T56	2		T210	1
all_values[6]	auto[0]	auto[1]	auto[0]	19	1		T56	1		T209	2		T211	1
all_values[6]	auto[0]	auto[1]	auto[1]	64	1		T54	2		T55	3		T57	2
all_values[6]	auto[1]	auto[0]	auto[1]	53	1		T54	4		T55	1		T56	1
all_values[6]	auto[1]	auto[1]	auto[1]	48	1		T55	3		T56	2		T57	2
all_values[7]	auto[0]	auto[0]	auto[0]	19	1		T203	1		T207	1		T212	1
all_values[7]	auto[0]	auto[0]	auto[1]	46	1		T54	2		T55	5		T56	1
all_values[7]	auto[0]	auto[1]	auto[0]	20	1		T55	1		T56	1		T203	1
all_values[7]	auto[0]	auto[1]	auto[1]	66	1		T54	4		T56	1		T57	2
all_values[7]	auto[1]	auto[0]	auto[1]	50	1		T54	1		T55	1		T56	2
all_values[7]	auto[1]	auto[1]	auto[1]	44	1		T56	2		T57	1		T210	1
all_values[8]	auto[0]	auto[0]	auto[0]	40	1		T54	1		T55	1		T56	1
all_values[8]	auto[0]	auto[0]	auto[1]	42	1		T54	2		T55	1		T57	1
all_values[8]	auto[0]	auto[1]	auto[0]	14	1		T57	1		T209	2		T205	1
all_values[8]	auto[0]	auto[1]	auto[1]	57	1		T54	1		T55	1		T56	3
all_values[8]	auto[1]	auto[0]	auto[1]	50	1		T54	1		T55	1		T56	2
all_values[8]	auto[1]	auto[1]	auto[1]	42	1		T54	2		T55	3		T56	1
all_values[9]	auto[0]	auto[0]	auto[0]	32	1		T54	1		T55	2		T210	1
all_values[9]	auto[0]	auto[0]	auto[1]	67	1		T54	2		T56	3		T57	2
all_values[9]	auto[0]	auto[1]	auto[0]	11	1		T55	1		T211	1		T214	2
all_values[9]	auto[0]	auto[1]	auto[1]	40	1		T54	1		T55	2		T56	1
all_values[9]	auto[1]	auto[0]	auto[1]	53	1		T54	2		T57	1		T210	1
all_values[9]	auto[1]	auto[1]	auto[1]	42	1		T54	1		T55	2		T56	3
all_values[10]	auto[0]	auto[0]	auto[0]	21	1		T56	1		T210	1		T203	1
all_values[10]	auto[0]	auto[0]	auto[1]	48	1		T54	2		T55	1		T56	3
all_values[10]	auto[0]	auto[1]	auto[0]	16	1		T209	4		T211	1		T214	1
all_values[10]	auto[0]	auto[1]	auto[1]	53	1		T54	3		T55	1		T56	1
all_values[10]	auto[1]	auto[0]	auto[1]	52	1		T54	1		T55	2		T56	2
all_values[10]	auto[1]	auto[1]	auto[1]	55	1		T54	1		T55	3		T203	2
all_values[11]	auto[0]	auto[0]	auto[0]	20	1		T54	1		T55	1		T57	2
all_values[11]	auto[0]	auto[0]	auto[1]	45	1		T55	2		T56	3		T57	1
all_values[11]	auto[0]	auto[1]	auto[0]	7	1		T54	1		T212	1		T213	1
all_values[11]	auto[0]	auto[1]	auto[1]	58	1		T54	3		T56	1		T210	1
all_values[11]	auto[1]	auto[0]	auto[1]	64	1		T55	3		T56	3		T57	1
all_values[11]	auto[1]	auto[1]	auto[1]	51	1		T54	2		T55	1		T210	3
all_values[12]	auto[0]	auto[0]	auto[0]	21	1		T54	1		T55	1		T209	1
all_values[12]	auto[0]	auto[0]	auto[1]	54	1		T54	1		T55	2		T210	2
all_values[12]	auto[0]	auto[1]	auto[0]	16	1		T55	1		T57	1		T213	1
all_values[12]	auto[0]	auto[1]	auto[1]	45	1		T54	1		T55	1		T56	3
all_values[12]	auto[1]	auto[0]	auto[1]	63	1		T54	1		T56	3		T210	3
all_values[12]	auto[1]	auto[1]	auto[1]	46	1		T54	3		T55	2		T56	1
all_values[13]	auto[0]	auto[0]	auto[0]	29	1		T54	1		T55	1		T56	2
all_values[13]	auto[0]	auto[0]	auto[1]	44	1		T54	2		T55	3		T56	1
all_values[13]	auto[0]	auto[1]	auto[0]	17	1		T57	1		T213	2		T211	2
all_values[13]	auto[0]	auto[1]	auto[1]	58	1		T55	1		T56	2		T57	1
all_values[13]	auto[1]	auto[0]	auto[1]	60	1		T55	2		T56	2		T210	2
all_values[13]	auto[1]	auto[1]	auto[1]	37	1		T54	4		T57	1		T210	1
all_values[14]	auto[0]	auto[0]	auto[0]	17	1		T54	1		T210	1		T203	1
all_values[14]	auto[0]	auto[0]	auto[1]	57	1		T56	2		T57	2		T210	1
all_values[14]	auto[0]	auto[1]	auto[0]	17	1		T55	1		T210	2		T212	1
all_values[14]	auto[0]	auto[1]	auto[1]	47	1		T54	1		T55	3		T56	2
all_values[14]	auto[1]	auto[0]	auto[1]	69	1		T54	3		T55	2		T56	3
all_values[14]	auto[1]	auto[1]	auto[1]	38	1		T54	2		T55	1		T57	1
all_values[15]	auto[0]	auto[0]	auto[0]	23	1		T55	1		T56	3		T57	1
all_values[15]	auto[0]	auto[0]	auto[1]	58	1		T54	3		T56	1		T57	1
all_values[15]	auto[0]	auto[1]	auto[0]	15	1		T55	1		T57	1		T212	1
all_values[15]	auto[0]	auto[1]	auto[1]	49	1		T54	1		T55	2		T56	1
all_values[15]	auto[1]	auto[0]	auto[1]	55	1		T54	2		T57	1		T210	2
all_values[15]	auto[1]	auto[1]	auto[1]	45	1		T54	1		T55	3		T56	2
all_values[16]	auto[0]	auto[0]	auto[0]	20	1		T54	1		T210	3		T215	1
all_values[16]	auto[0]	auto[0]	auto[1]	39	1		T54	2		T56	2		T57	1
all_values[16]	auto[0]	auto[1]	auto[0]	25	1		T55	2		T56	3		T210	2
all_values[16]	auto[0]	auto[1]	auto[1]	55	1		T55	3		T57	1		T210	1
all_values[16]	auto[1]	auto[0]	auto[1]	48	1		T54	2		T55	1		T57	1
all_values[16]	auto[1]	auto[1]	auto[1]	58	1		T54	2		T55	1		T56	2
all_values[17]	auto[0]	auto[0]	auto[0]	18	1		T55	1		T210	1		T213	1
all_values[17]	auto[0]	auto[0]	auto[1]	59	1		T54	3		T55	1		T56	4
all_values[17]	auto[0]	auto[1]	auto[0]	20	1		T55	2		T56	1		T57	1
all_values[17]	auto[0]	auto[1]	auto[1]	45	1		T54	1		T210	3		T203	1
all_values[17]	auto[1]	auto[0]	auto[1]	55	1		T54	2		T55	1		T56	2
all_values[17]	auto[1]	auto[1]	auto[1]	48	1		T54	1		T55	2		T57	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal