Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2254	1		T1	5		T2	2		T3	4
all_values[1]	2254	1		T1	5		T2	2		T3	4
all_values[2]	2254	1		T1	5		T2	2		T3	4
all_values[3]	2254	1		T1	5		T2	2		T3	4
all_values[4]	2254	1		T1	5		T2	2		T3	4
all_values[5]	2254	1		T1	5		T2	2		T3	4
all_values[6]	2254	1		T1	5		T2	2		T3	4
all_values[7]	2254	1		T1	5		T2	2		T3	4
all_values[8]	2254	1		T1	5		T2	2		T3	4
all_values[9]	2254	1		T1	5		T2	2		T3	4
all_values[10]	2254	1		T1	5		T2	2		T3	4
all_values[11]	2254	1		T1	5		T2	2		T3	4
all_values[12]	2254	1		T1	5		T2	2		T3	4
all_values[13]	2254	1		T1	5		T2	2		T3	4
all_values[14]	2254	1		T1	5		T2	2		T3	4
all_values[15]	2254	1		T1	5		T2	2		T3	4
all_values[16]	2254	1		T1	5		T2	2		T3	4
all_values[17]	2254	1		T1	5		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38501	1		T1	87		T2	36		T3	70
auto[1]	2071	1		T1	3		T3	2		T8	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	38053	1		T1	90		T2	36		T3	72
auto[1]	2519	1		T59	79		T60	119		T61	76

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1852	1		T1	5		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	61	1		T59	4		T60	2		T63	3
all_values[0]	auto[1]	auto[0]	259	1		T3	2		T11	3		T12	3
all_values[0]	auto[1]	auto[1]	82	1		T59	1		T60	5		T61	5
all_values[1]	auto[0]	auto[0]	1828	1		T1	2		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	56	1		T59	1		T60	3		T61	5
all_values[1]	auto[1]	auto[0]	295	1		T1	3		T8	3		T9	3
all_values[1]	auto[1]	auto[1]	75	1		T59	4		T60	4		T63	4
all_values[2]	auto[0]	auto[0]	2113	1		T1	5		T2	2		T3	4
all_values[2]	auto[0]	auto[1]	75	1		T60	6		T61	2		T63	1
all_values[2]	auto[1]	auto[0]	12	1		T242	1		T243	3		T244	1
all_values[2]	auto[1]	auto[1]	54	1		T59	4		T60	2		T61	3
all_values[3]	auto[0]	auto[0]	2100	1		T1	5		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	66	1		T59	3		T60	2		T238	4
all_values[3]	auto[1]	auto[0]	23	1		T59	1		T62	2		T242	4
all_values[3]	auto[1]	auto[1]	65	1		T59	1		T60	6		T61	5
all_values[4]	auto[0]	auto[0]	2089	1		T1	5		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	84	1		T59	4		T60	1		T61	3
all_values[4]	auto[1]	auto[0]	12	1		T242	1		T245	2		T246	4
all_values[4]	auto[1]	auto[1]	69	1		T59	1		T60	6		T61	2
all_values[5]	auto[0]	auto[0]	2105	1		T1	5		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	46	1		T60	1		T61	1		T63	1
all_values[5]	auto[1]	auto[0]	18	1		T60	1		T243	3		T245	1
all_values[5]	auto[1]	auto[1]	85	1		T60	5		T61	4		T63	4
all_values[6]	auto[0]	auto[0]	2103	1		T1	5		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	53	1		T59	4		T61	1		T242	4
all_values[6]	auto[1]	auto[0]	18	1		T60	6		T239	1		T247	1
all_values[6]	auto[1]	auto[1]	80	1		T59	1		T61	3		T63	5
all_values[7]	auto[0]	auto[0]	2102	1		T1	5		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	69	1		T59	2		T60	5		T61	3
all_values[7]	auto[1]	auto[0]	11	1		T243	2		T245	1		T247	3
all_values[7]	auto[1]	auto[1]	72	1		T59	3		T60	3		T61	2
all_values[8]	auto[0]	auto[0]	2096	1		T1	5		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	80	1		T59	4		T60	1		T61	4
all_values[8]	auto[1]	auto[0]	16	1		T61	1		T62	1		T238	1
all_values[8]	auto[1]	auto[1]	62	1		T59	1		T60	5		T242	2
all_values[9]	auto[0]	auto[0]	2102	1		T1	5		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	55	1		T60	2		T61	1		T63	1
all_values[9]	auto[1]	auto[0]	18	1		T59	1		T242	1		T243	2
all_values[9]	auto[1]	auto[1]	79	1		T59	4		T60	5		T61	4
all_values[10]	auto[0]	auto[0]	2100	1		T1	5		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	74	1		T59	3		T60	5		T63	1
all_values[10]	auto[1]	auto[0]	15	1		T60	3		T61	4		T63	1
all_values[10]	auto[1]	auto[1]	65	1		T59	2		T63	3		T62	5
all_values[11]	auto[0]	auto[0]	2092	1		T1	5		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	80	1		T59	2		T60	6		T63	5
all_values[11]	auto[1]	auto[0]	13	1		T61	1		T242	1		T243	1
all_values[11]	auto[1]	auto[1]	69	1		T59	3		T60	2		T61	3
all_values[12]	auto[0]	auto[0]	2097	1		T1	5		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	74	1		T59	4		T60	1		T61	2
all_values[12]	auto[1]	auto[0]	19	1		T238	1		T245	3		T239	2
all_values[12]	auto[1]	auto[1]	64	1		T59	1		T60	7		T61	3
all_values[13]	auto[0]	auto[0]	2099	1		T1	5		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	78	1		T59	4		T60	2		T63	1
all_values[13]	auto[1]	auto[0]	17	1		T60	1		T61	5		T243	1
all_values[13]	auto[1]	auto[1]	60	1		T59	1		T60	4		T63	4
all_values[14]	auto[0]	auto[0]	2101	1		T1	5		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	78	1		T60	5		T61	4		T63	2
all_values[14]	auto[1]	auto[0]	16	1		T59	1		T60	2		T62	4
all_values[14]	auto[1]	auto[1]	59	1		T59	3		T60	1		T61	1
all_values[15]	auto[0]	auto[0]	2090	1		T1	5		T2	2		T3	4
all_values[15]	auto[0]	auto[1]	72	1		T59	1		T60	4		T61	1
all_values[15]	auto[1]	auto[0]	6	1		T248	1		T249	5		-	-
all_values[15]	auto[1]	auto[1]	86	1		T59	4		T60	4		T61	4
all_values[16]	auto[0]	auto[0]	2098	1		T1	5		T2	2		T3	4
all_values[16]	auto[0]	auto[1]	64	1		T59	3		T60	3		T61	2
all_values[16]	auto[1]	auto[0]	15	1		T59	1		T60	1		T239	1
all_values[16]	auto[1]	auto[1]	77	1		T59	1		T60	4		T61	3
all_values[17]	auto[0]	auto[0]	2096	1		T1	5		T2	2		T3	4
all_values[17]	auto[0]	auto[1]	73	1		T59	5		T60	2		T62	3
all_values[17]	auto[1]	auto[0]	7	1		T247	1		T250	1		T246	1
all_values[17]	auto[1]	auto[1]	78	1		T60	5		T61	5		T242	4