Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.54 96.36 88.61 97.17 46.88 94.18 97.36 92.25


Total test records in report: 801
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T771 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.353079128 Mar 14 01:09:22 PM PDT 24 Mar 14 01:09:25 PM PDT 24 55659262 ps
T772 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3039400576 Mar 14 01:09:20 PM PDT 24 Mar 14 01:09:22 PM PDT 24 45380433 ps
T773 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1450846503 Mar 14 01:09:33 PM PDT 24 Mar 14 01:09:37 PM PDT 24 94142823 ps
T250 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2317156186 Mar 14 01:10:15 PM PDT 24 Mar 14 01:10:15 PM PDT 24 24051059 ps
T229 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3882299383 Mar 14 01:09:09 PM PDT 24 Mar 14 01:09:10 PM PDT 24 46475839 ps
T234 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3997518662 Mar 14 01:09:34 PM PDT 24 Mar 14 01:09:36 PM PDT 24 148278140 ps
T196 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.850409740 Mar 14 01:09:19 PM PDT 24 Mar 14 01:09:23 PM PDT 24 371464988 ps
T246 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2307368449 Mar 14 01:09:46 PM PDT 24 Mar 14 01:09:47 PM PDT 24 21576036 ps
T183 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.711610817 Mar 14 01:09:35 PM PDT 24 Mar 14 01:09:36 PM PDT 24 71491643 ps
T240 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1154756739 Mar 14 01:09:35 PM PDT 24 Mar 14 01:09:38 PM PDT 24 224195050 ps
T774 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2314013101 Mar 14 01:09:34 PM PDT 24 Mar 14 01:09:36 PM PDT 24 68743074 ps
T775 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2616282986 Mar 14 01:09:11 PM PDT 24 Mar 14 01:09:12 PM PDT 24 42008083 ps
T776 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1270394676 Mar 14 01:09:22 PM PDT 24 Mar 14 01:09:24 PM PDT 24 71642947 ps
T251 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1530518200 Mar 14 01:10:11 PM PDT 24 Mar 14 01:10:12 PM PDT 24 23059541 ps
T248 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3506240431 Mar 14 01:09:36 PM PDT 24 Mar 14 01:09:37 PM PDT 24 27672160 ps
T235 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2167015901 Mar 14 01:09:21 PM PDT 24 Mar 14 01:09:23 PM PDT 24 92344248 ps
T777 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1647720838 Mar 14 01:09:44 PM PDT 24 Mar 14 01:09:46 PM PDT 24 54277492 ps
T778 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1244420582 Mar 14 01:09:22 PM PDT 24 Mar 14 01:09:24 PM PDT 24 26273047 ps
T779 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3015861779 Mar 14 01:09:32 PM PDT 24 Mar 14 01:09:35 PM PDT 24 97275438 ps
T780 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.469503711 Mar 14 01:09:07 PM PDT 24 Mar 14 01:09:11 PM PDT 24 153771295 ps
T236 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4051984676 Mar 14 01:09:43 PM PDT 24 Mar 14 01:09:46 PM PDT 24 130817428 ps
T253 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.939423481 Mar 14 01:10:09 PM PDT 24 Mar 14 01:10:10 PM PDT 24 24881543 ps
T781 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.793508641 Mar 14 01:09:32 PM PDT 24 Mar 14 01:09:34 PM PDT 24 24258385 ps
T782 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1591622021 Mar 14 01:09:09 PM PDT 24 Mar 14 01:09:13 PM PDT 24 224772786 ps
T783 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3236114058 Mar 14 01:09:10 PM PDT 24 Mar 14 01:09:12 PM PDT 24 57313734 ps
T784 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1048973901 Mar 14 01:09:48 PM PDT 24 Mar 14 01:09:49 PM PDT 24 23534760 ps
T785 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1044189265 Mar 14 01:09:47 PM PDT 24 Mar 14 01:09:48 PM PDT 24 37965646 ps
T786 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2801840467 Mar 14 01:09:46 PM PDT 24 Mar 14 01:09:47 PM PDT 24 27036064 ps
T787 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2069242355 Mar 14 01:09:21 PM PDT 24 Mar 14 01:09:23 PM PDT 24 175228893 ps
T237 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.631964301 Mar 14 01:09:37 PM PDT 24 Mar 14 01:09:39 PM PDT 24 147784721 ps
T788 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3792974920 Mar 14 01:09:46 PM PDT 24 Mar 14 01:09:48 PM PDT 24 65892341 ps
T789 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.436175455 Mar 14 01:10:10 PM PDT 24 Mar 14 01:10:11 PM PDT 24 31577651 ps
T790 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.96489240 Mar 14 01:09:32 PM PDT 24 Mar 14 01:09:35 PM PDT 24 113008335 ps
T791 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.325538793 Mar 14 01:09:46 PM PDT 24 Mar 14 01:09:49 PM PDT 24 242568735 ps
T197 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2359217322 Mar 14 01:09:08 PM PDT 24 Mar 14 01:09:10 PM PDT 24 179693782 ps
T792 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3207534077 Mar 14 01:09:10 PM PDT 24 Mar 14 01:09:16 PM PDT 24 195418951 ps
T793 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3930893188 Mar 14 01:10:14 PM PDT 24 Mar 14 01:10:15 PM PDT 24 25564243 ps
T181 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2976687230 Mar 14 01:09:09 PM PDT 24 Mar 14 01:09:11 PM PDT 24 59586937 ps
T241 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.275944869 Mar 14 01:09:19 PM PDT 24 Mar 14 01:09:21 PM PDT 24 154172038 ps
T794 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3986076352 Mar 14 01:09:18 PM PDT 24 Mar 14 01:09:22 PM PDT 24 248675682 ps
T795 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1379270336 Mar 14 01:09:21 PM PDT 24 Mar 14 01:09:23 PM PDT 24 62088537 ps
T249 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.425372809 Mar 14 01:09:22 PM PDT 24 Mar 14 01:09:22 PM PDT 24 27562664 ps
T796 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2336057762 Mar 14 01:09:32 PM PDT 24 Mar 14 01:09:35 PM PDT 24 71412804 ps
T797 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1721593923 Mar 14 01:10:13 PM PDT 24 Mar 14 01:10:14 PM PDT 24 25865340 ps
T798 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.67059370 Mar 14 01:09:46 PM PDT 24 Mar 14 01:09:47 PM PDT 24 28061253 ps
T254 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3558930523 Mar 14 01:10:11 PM PDT 24 Mar 14 01:10:12 PM PDT 24 23779068 ps
T54 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2777915548 Mar 14 01:09:23 PM PDT 24 Mar 14 01:09:24 PM PDT 24 37914926 ps
T799 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2823365165 Mar 14 01:09:47 PM PDT 24 Mar 14 01:09:47 PM PDT 24 20073509 ps
T800 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3341381398 Mar 14 01:09:08 PM PDT 24 Mar 14 01:09:14 PM PDT 24 199804569 ps
T198 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3480048697 Mar 14 01:09:20 PM PDT 24 Mar 14 01:09:25 PM PDT 24 195127934 ps
T801 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2179563426 Mar 14 01:09:38 PM PDT 24 Mar 14 01:09:41 PM PDT 24 188612710 ps

Test location /workspace/coverage/default/9.usbdev_smoke.1240997117
Short name T3
Test name
Test status
Simulation time 8473831401 ps
CPU time 8.22 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:49 PM PDT 24
Peak memory 202568 kb
Host smart-e2871bed-5983-4608-bcb7-0e6cac9de341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12409
97117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1240997117
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1015850953
Short name T6
Test name
Test status
Simulation time 216315489 ps
CPU time 2.26 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202736 kb
Host smart-d542b322-0e2a-4151-9872-420b4895f5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10158
50953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1015850953
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2602561934
Short name T60
Test name
Test status
Simulation time 18528497 ps
CPU time 0.7 seconds
Started Mar 14 01:09:34 PM PDT 24
Finished Mar 14 01:09:35 PM PDT 24
Peak memory 202404 kb
Host smart-f4fbac1e-a733-4efc-acc9-05b5b989876e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2602561934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2602561934
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3262901928
Short name T55
Test name
Test status
Simulation time 142991926 ps
CPU time 1.8 seconds
Started Mar 14 01:09:20 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 214312 kb
Host smart-a66b47e4-f8b2-4897-b423-a14098083c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262901928 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.3262901928
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3568126652
Short name T243
Test name
Test status
Simulation time 21869158 ps
CPU time 0.66 seconds
Started Mar 14 01:09:07 PM PDT 24
Finished Mar 14 01:09:08 PM PDT 24
Peak memory 202420 kb
Host smart-8a9358ed-0303-4181-8549-a3c6e770c5e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3568126652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3568126652
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2459187960
Short name T50
Test name
Test status
Simulation time 165084807 ps
CPU time 1.08 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:28 PM PDT 24
Peak memory 218832 kb
Host smart-f9e50ee9-186f-4044-96e3-4e8ca04df2ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2459187960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2459187960
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2306624719
Short name T172
Test name
Test status
Simulation time 8357502057 ps
CPU time 7.27 seconds
Started Mar 14 01:31:04 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202508 kb
Host smart-f5869b10-8819-45fd-bff1-471660c4e506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23066
24719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2306624719
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2338567033
Short name T93
Test name
Test status
Simulation time 8425961075 ps
CPU time 7.67 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:15 PM PDT 24
Peak memory 202508 kb
Host smart-2e06941b-813e-4beb-99c9-a73764bfb974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23385
67033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2338567033
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1159951647
Short name T32
Test name
Test status
Simulation time 31045263 ps
CPU time 0.64 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:29 PM PDT 24
Peak memory 202440 kb
Host smart-8007b672-5ea3-4852-8d77-4671dd110fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11599
51647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1159951647
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3865365873
Short name T52
Test name
Test status
Simulation time 36836324 ps
CPU time 0.82 seconds
Started Mar 14 01:09:20 PM PDT 24
Finished Mar 14 01:09:21 PM PDT 24
Peak memory 202736 kb
Host smart-ea1a51d0-8f77-40e1-ac1f-ac9b641cc116
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865365873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3865365873
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.466378163
Short name T20
Test name
Test status
Simulation time 8391495166 ps
CPU time 8.61 seconds
Started Mar 14 01:32:13 PM PDT 24
Finished Mar 14 01:32:22 PM PDT 24
Peak memory 202524 kb
Host smart-16a677fc-0700-41f6-a4c4-8897a62f489b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46637
8163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.466378163
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.939423481
Short name T253
Test name
Test status
Simulation time 24881543 ps
CPU time 0.61 seconds
Started Mar 14 01:10:09 PM PDT 24
Finished Mar 14 01:10:10 PM PDT 24
Peak memory 202352 kb
Host smart-813ab105-18c4-43d8-8cef-618591ce96b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=939423481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.939423481
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1919179266
Short name T1
Test name
Test status
Simulation time 8376044438 ps
CPU time 7.61 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:37 PM PDT 24
Peak memory 202572 kb
Host smart-1f966292-be44-4e1b-b72c-860144303007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19191
79266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1919179266
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_smoke.4246370153
Short name T148
Test name
Test status
Simulation time 8475876309 ps
CPU time 7.83 seconds
Started Mar 14 01:30:50 PM PDT 24
Finished Mar 14 01:30:57 PM PDT 24
Peak memory 202540 kb
Host smart-e915aed1-99d7-4e33-afd2-698d6d7b8e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42463
70153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.4246370153
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2307368449
Short name T246
Test name
Test status
Simulation time 21576036 ps
CPU time 0.64 seconds
Started Mar 14 01:09:46 PM PDT 24
Finished Mar 14 01:09:47 PM PDT 24
Peak memory 202364 kb
Host smart-6f840802-f842-448f-9a2a-0d800ebbad43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2307368449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2307368449
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_smoke.4212366497
Short name T15
Test name
Test status
Simulation time 8480533644 ps
CPU time 8.13 seconds
Started Mar 14 01:31:07 PM PDT 24
Finished Mar 14 01:31:15 PM PDT 24
Peak memory 202580 kb
Host smart-823b3bad-ec56-43f7-924a-33c2c2be9938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42123
66497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.4212366497
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3414758907
Short name T474
Test name
Test status
Simulation time 8479395861 ps
CPU time 8.88 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202620 kb
Host smart-cfb76761-1367-4918-8ccd-7bd7ff0ea349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34147
58907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3414758907
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3860472244
Short name T142
Test name
Test status
Simulation time 8473798012 ps
CPU time 8.78 seconds
Started Mar 14 01:31:36 PM PDT 24
Finished Mar 14 01:31:45 PM PDT 24
Peak memory 202468 kb
Host smart-b403c871-d910-48e8-b88b-925b61972ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38604
72244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3860472244
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3837839249
Short name T134
Test name
Test status
Simulation time 8476019982 ps
CPU time 8.11 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202412 kb
Host smart-60a027bb-5c44-430e-8ef0-cbd1c9cca5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38378
39249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3837839249
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3749118570
Short name T39
Test name
Test status
Simulation time 8476315843 ps
CPU time 8.29 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202604 kb
Host smart-d5004497-2a73-41c0-97ab-523450db5a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37491
18570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3749118570
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3701506274
Short name T44
Test name
Test status
Simulation time 8473015956 ps
CPU time 9.24 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:29 PM PDT 24
Peak memory 202536 kb
Host smart-d5e69834-4ec4-4739-8a54-aa8453268d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37015
06274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3701506274
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.89348694
Short name T77
Test name
Test status
Simulation time 8452935380 ps
CPU time 8.58 seconds
Started Mar 14 01:32:22 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202544 kb
Host smart-0967ae2e-0664-4b76-9f9e-906c28f37ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89348
694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.89348694
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3792218456
Short name T418
Test name
Test status
Simulation time 8392222658 ps
CPU time 8.44 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:14 PM PDT 24
Peak memory 202552 kb
Host smart-d2d1047d-850c-4ace-a265-57d2026d6c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37922
18456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3792218456
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.46156867
Short name T47
Test name
Test status
Simulation time 174042402 ps
CPU time 2.57 seconds
Started Mar 14 01:09:08 PM PDT 24
Finished Mar 14 01:09:11 PM PDT 24
Peak memory 202984 kb
Host smart-518eb210-a6a8-4174-a5c5-c93beeb03633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=46156867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.46156867
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.142057397
Short name T252
Test name
Test status
Simulation time 22616833 ps
CPU time 0.64 seconds
Started Mar 14 01:10:12 PM PDT 24
Finished Mar 14 01:10:13 PM PDT 24
Peak memory 202312 kb
Host smart-7330e742-3999-4662-b3c4-8c50054065a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=142057397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.142057397
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4106774107
Short name T180
Test name
Test status
Simulation time 55660046 ps
CPU time 1.38 seconds
Started Mar 14 01:09:50 PM PDT 24
Finished Mar 14 01:09:52 PM PDT 24
Peak memory 202964 kb
Host smart-c6bd8a28-e0f4-4801-b928-c395089961cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106774107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.4106774107
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.425372809
Short name T249
Test name
Test status
Simulation time 27562664 ps
CPU time 0.63 seconds
Started Mar 14 01:09:22 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 202320 kb
Host smart-36c467d6-6eac-40d3-9056-30c32e982445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=425372809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.425372809
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3480048697
Short name T198
Test name
Test status
Simulation time 195127934 ps
CPU time 4.49 seconds
Started Mar 14 01:09:20 PM PDT 24
Finished Mar 14 01:09:25 PM PDT 24
Peak memory 202860 kb
Host smart-6c0d65ee-b4ab-4374-a196-a7c2197923b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480048697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3480048697
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1549219746
Short name T145
Test name
Test status
Simulation time 8472973396 ps
CPU time 7.74 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202616 kb
Host smart-eb7cd784-47d0-4838-9d2c-18628ff64818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
19746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1549219746
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1450846503
Short name T773
Test name
Test status
Simulation time 94142823 ps
CPU time 2.88 seconds
Started Mar 14 01:09:33 PM PDT 24
Finished Mar 14 01:09:37 PM PDT 24
Peak memory 202956 kb
Host smart-dfce9338-835b-40f4-a45e-f92c118530ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1450846503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1450846503
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2777915548
Short name T54
Test name
Test status
Simulation time 37914926 ps
CPU time 0.85 seconds
Started Mar 14 01:09:23 PM PDT 24
Finished Mar 14 01:09:24 PM PDT 24
Peak memory 202724 kb
Host smart-a08a2e30-a37e-4188-8d0d-80242ec291de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777915548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2777915548
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2497840454
Short name T25
Test name
Test status
Simulation time 31254448 ps
CPU time 0.65 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:31:53 PM PDT 24
Peak memory 202240 kb
Host smart-98ef135d-1aac-426a-97a2-241f73d6fe9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24978
40454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2497840454
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1118313275
Short name T306
Test name
Test status
Simulation time 8356532738 ps
CPU time 7.72 seconds
Started Mar 14 01:30:15 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202464 kb
Host smart-933ea39b-0463-4a06-abb1-88917f7c280b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11183
13275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1118313275
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1697702374
Short name T136
Test name
Test status
Simulation time 8471793315 ps
CPU time 8.27 seconds
Started Mar 14 01:30:50 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 202536 kb
Host smart-410c92c9-8cb7-4f39-b92c-bbb53d396031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16977
02374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1697702374
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3390717403
Short name T151
Test name
Test status
Simulation time 8473281581 ps
CPU time 7.61 seconds
Started Mar 14 01:30:17 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 202556 kb
Host smart-2543f671-6108-4d78-9f57-3e2c88fb75f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33907
17403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3390717403
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2089159955
Short name T114
Test name
Test status
Simulation time 8469703074 ps
CPU time 7.31 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:52 PM PDT 24
Peak memory 202616 kb
Host smart-644570a0-bf4f-4530-9aea-b016d8607f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20891
59955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2089159955
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2976687230
Short name T181
Test name
Test status
Simulation time 59586937 ps
CPU time 1.4 seconds
Started Mar 14 01:09:09 PM PDT 24
Finished Mar 14 01:09:11 PM PDT 24
Peak memory 202940 kb
Host smart-3bad5a89-2658-4287-9366-2209375af75e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976687230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.2976687230
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.466060094
Short name T96
Test name
Test status
Simulation time 8431566312 ps
CPU time 7.51 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:30:21 PM PDT 24
Peak memory 202580 kb
Host smart-3f9c3c1b-aa78-46b2-9da3-95f0be88d7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46606
0094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.466060094
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.4150437868
Short name T746
Test name
Test status
Simulation time 8421259331 ps
CPU time 7.16 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 202548 kb
Host smart-1b856a7a-470a-4578-9410-b80291292b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41504
37868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.4150437868
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2979147773
Short name T87
Test name
Test status
Simulation time 8403659628 ps
CPU time 8.12 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202568 kb
Host smart-d3ce7cd8-21df-47ae-ae4a-564b9cbb81f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29791
47773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2979147773
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1183570581
Short name T105
Test name
Test status
Simulation time 8441617731 ps
CPU time 7.58 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:12 PM PDT 24
Peak memory 202472 kb
Host smart-8c692c3c-4de9-4e41-976f-f03fbcd5a737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11835
70581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1183570581
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3085341493
Short name T79
Test name
Test status
Simulation time 8411729240 ps
CPU time 7.68 seconds
Started Mar 14 01:31:02 PM PDT 24
Finished Mar 14 01:31:10 PM PDT 24
Peak memory 202544 kb
Host smart-b7da4791-3832-4b61-8732-a1d840c4e68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30853
41493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3085341493
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2132250304
Short name T83
Test name
Test status
Simulation time 8432177280 ps
CPU time 7.66 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202548 kb
Host smart-e9146cd6-63aa-4f6d-ae2e-ff58be7f2069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21322
50304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2132250304
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.4206581846
Short name T650
Test name
Test status
Simulation time 8425791950 ps
CPU time 7.83 seconds
Started Mar 14 01:31:17 PM PDT 24
Finished Mar 14 01:31:25 PM PDT 24
Peak memory 202468 kb
Host smart-6da85e2a-f4fd-493a-b41a-78ab64a943df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42065
81846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.4206581846
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2244050595
Short name T171
Test name
Test status
Simulation time 8358094738 ps
CPU time 7.3 seconds
Started Mar 14 01:31:19 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202576 kb
Host smart-919b7152-dc32-4e7e-a0a7-3bd92c5c6873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22440
50595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2244050595
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3732442356
Short name T99
Test name
Test status
Simulation time 8428809144 ps
CPU time 7.14 seconds
Started Mar 14 01:31:53 PM PDT 24
Finished Mar 14 01:32:01 PM PDT 24
Peak memory 202580 kb
Host smart-02f66b5c-3a29-4a89-b3c5-fe52d8efea9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37324
42356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3732442356
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3465885336
Short name T107
Test name
Test status
Simulation time 8414901724 ps
CPU time 7.43 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:02 PM PDT 24
Peak memory 202384 kb
Host smart-bf815929-0c33-423d-a10b-6518f67e52cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34658
85336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3465885336
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.303766944
Short name T18
Test name
Test status
Simulation time 8441372223 ps
CPU time 8.78 seconds
Started Mar 14 01:32:12 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 202564 kb
Host smart-13bddd9d-8aa4-4f81-a2d3-4b0af0ea82a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30376
6944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.303766944
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1210406631
Short name T102
Test name
Test status
Simulation time 8394096916 ps
CPU time 8.96 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:37 PM PDT 24
Peak memory 202516 kb
Host smart-ffa39abb-3974-4bba-8496-5a3e497c73ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12104
06631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1210406631
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2477715147
Short name T58
Test name
Test status
Simulation time 174954708 ps
CPU time 2.17 seconds
Started Mar 14 01:09:11 PM PDT 24
Finished Mar 14 01:09:13 PM PDT 24
Peak memory 202900 kb
Host smart-40869782-156b-4d12-a605-c73a6796a596
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477715147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2477715147
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3341381398
Short name T800
Test name
Test status
Simulation time 199804569 ps
CPU time 4.61 seconds
Started Mar 14 01:09:08 PM PDT 24
Finished Mar 14 01:09:14 PM PDT 24
Peak memory 202856 kb
Host smart-46dd75ff-e04a-43a3-84ef-127f16a29194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341381398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3341381398
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2616282986
Short name T775
Test name
Test status
Simulation time 42008083 ps
CPU time 0.75 seconds
Started Mar 14 01:09:11 PM PDT 24
Finished Mar 14 01:09:12 PM PDT 24
Peak memory 202792 kb
Host smart-25d253a5-f245-4983-a243-3031996f10ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616282986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2616282986
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2019013635
Short name T195
Test name
Test status
Simulation time 40413372 ps
CPU time 1.45 seconds
Started Mar 14 01:09:08 PM PDT 24
Finished Mar 14 01:09:10 PM PDT 24
Peak memory 202924 kb
Host smart-cc76d20c-927b-45c8-a9f7-f7a8a06179f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2019013635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2019013635
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1959306695
Short name T763
Test name
Test status
Simulation time 250903681 ps
CPU time 2.47 seconds
Started Mar 14 01:09:09 PM PDT 24
Finished Mar 14 01:09:12 PM PDT 24
Peak memory 202924 kb
Host smart-905f7962-9c9e-4996-970d-dc139319dc27
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1959306695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1959306695
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.610076662
Short name T76
Test name
Test status
Simulation time 77623742 ps
CPU time 2.04 seconds
Started Mar 14 01:09:05 PM PDT 24
Finished Mar 14 01:09:07 PM PDT 24
Peak memory 202940 kb
Host smart-9fbb1d3e-c75c-4234-8d04-aa2027ccc5f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610076662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.610076662
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.631221931
Short name T53
Test name
Test status
Simulation time 27965607 ps
CPU time 0.73 seconds
Started Mar 14 01:09:07 PM PDT 24
Finished Mar 14 01:09:08 PM PDT 24
Peak memory 202732 kb
Host smart-3e6daeb6-06a2-410d-bed1-555a02382a43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631221931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.631221931
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.580404736
Short name T74
Test name
Test status
Simulation time 77254962 ps
CPU time 1.17 seconds
Started Mar 14 01:09:06 PM PDT 24
Finished Mar 14 01:09:07 PM PDT 24
Peak memory 211236 kb
Host smart-a7046a8e-6723-4754-8e59-114b148cce6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580404736 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.580404736
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2749910389
Short name T73
Test name
Test status
Simulation time 50831073 ps
CPU time 0.88 seconds
Started Mar 14 01:09:07 PM PDT 24
Finished Mar 14 01:09:08 PM PDT 24
Peak memory 202752 kb
Host smart-ecc5fa1b-7256-4625-895e-ab9cc5caaafd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749910389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2749910389
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2738784361
Short name T247
Test name
Test status
Simulation time 19553862 ps
CPU time 0.65 seconds
Started Mar 14 01:09:08 PM PDT 24
Finished Mar 14 01:09:09 PM PDT 24
Peak memory 202448 kb
Host smart-5f17ee8c-2c53-4a0c-826b-dc36b55ef3c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2738784361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2738784361
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2325086578
Short name T194
Test name
Test status
Simulation time 149944664 ps
CPU time 2.31 seconds
Started Mar 14 01:09:10 PM PDT 24
Finished Mar 14 01:09:12 PM PDT 24
Peak memory 202960 kb
Host smart-86b4f502-9f86-4251-873e-c00a9306e4a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2325086578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2325086578
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.469503711
Short name T780
Test name
Test status
Simulation time 153771295 ps
CPU time 3.99 seconds
Started Mar 14 01:09:07 PM PDT 24
Finished Mar 14 01:09:11 PM PDT 24
Peak memory 202840 kb
Host smart-7ae26b8e-c18c-46cc-bef3-2e48d86ec92e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=469503711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.469503711
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1364558740
Short name T232
Test name
Test status
Simulation time 85379541 ps
CPU time 1.14 seconds
Started Mar 14 01:09:06 PM PDT 24
Finished Mar 14 01:09:08 PM PDT 24
Peak memory 202864 kb
Host smart-d0d32da7-8c12-4fdb-981b-4b0358bacad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364558740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c
sr_outstanding.1364558740
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3236114058
Short name T783
Test name
Test status
Simulation time 57313734 ps
CPU time 1.73 seconds
Started Mar 14 01:09:10 PM PDT 24
Finished Mar 14 01:09:12 PM PDT 24
Peak memory 202988 kb
Host smart-5d49855a-25a8-47a1-a464-06871ebb1a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3236114058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3236114058
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3599479690
Short name T766
Test name
Test status
Simulation time 70114729 ps
CPU time 1.29 seconds
Started Mar 14 01:09:36 PM PDT 24
Finished Mar 14 01:09:37 PM PDT 24
Peak memory 212224 kb
Host smart-145c2cdb-2627-493d-a94f-2e599718e8b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599479690 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.3599479690
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2336057762
Short name T796
Test name
Test status
Simulation time 71412804 ps
CPU time 1.07 seconds
Started Mar 14 01:09:32 PM PDT 24
Finished Mar 14 01:09:35 PM PDT 24
Peak memory 202948 kb
Host smart-e068ebe9-2f19-4cc1-9edd-ecedebbd5726
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336057762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.2336057762
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2660154609
Short name T200
Test name
Test status
Simulation time 119469073 ps
CPU time 1.45 seconds
Started Mar 14 01:09:36 PM PDT 24
Finished Mar 14 01:09:37 PM PDT 24
Peak memory 202968 kb
Host smart-25eba63b-fc64-4564-a60c-e065df474ac3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660154609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.2660154609
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3015861779
Short name T779
Test name
Test status
Simulation time 97275438 ps
CPU time 1.52 seconds
Started Mar 14 01:09:32 PM PDT 24
Finished Mar 14 01:09:35 PM PDT 24
Peak memory 202996 kb
Host smart-c3e7f09f-d4d6-464f-8523-1b5f345a9bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3015861779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3015861779
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3997518662
Short name T234
Test name
Test status
Simulation time 148278140 ps
CPU time 1.66 seconds
Started Mar 14 01:09:34 PM PDT 24
Finished Mar 14 01:09:36 PM PDT 24
Peak memory 211188 kb
Host smart-8d1280fa-7bb3-4e1e-81f7-b5f11f384b1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997518662 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.3997518662
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.96489240
Short name T790
Test name
Test status
Simulation time 113008335 ps
CPU time 1.4 seconds
Started Mar 14 01:09:32 PM PDT 24
Finished Mar 14 01:09:35 PM PDT 24
Peak memory 203036 kb
Host smart-b9d36805-6b2d-43ce-91ef-f15024341760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96489240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_cs
r_outstanding.96489240
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1814332431
Short name T46
Test name
Test status
Simulation time 191725209 ps
CPU time 2.23 seconds
Started Mar 14 01:09:34 PM PDT 24
Finished Mar 14 01:09:37 PM PDT 24
Peak memory 203044 kb
Host smart-e209c5f7-5bd8-4fd6-b44c-f45b75899018
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1814332431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1814332431
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.631964301
Short name T237
Test name
Test status
Simulation time 147784721 ps
CPU time 1.94 seconds
Started Mar 14 01:09:37 PM PDT 24
Finished Mar 14 01:09:39 PM PDT 24
Peak memory 211220 kb
Host smart-3a8cd1f7-d915-451c-bec0-66742fde8128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631964301 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.631964301
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4051984676
Short name T236
Test name
Test status
Simulation time 130817428 ps
CPU time 1.48 seconds
Started Mar 14 01:09:43 PM PDT 24
Finished Mar 14 01:09:46 PM PDT 24
Peak memory 203020 kb
Host smart-5323d8c2-2df0-4b5d-b0ab-5d563b806017
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051984676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.4051984676
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2202968914
Short name T227
Test name
Test status
Simulation time 185130037 ps
CPU time 2.37 seconds
Started Mar 14 01:09:36 PM PDT 24
Finished Mar 14 01:09:39 PM PDT 24
Peak memory 203012 kb
Host smart-2eb87532-0508-43e8-b3c2-67bca9050845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2202968914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2202968914
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.793508641
Short name T781
Test name
Test status
Simulation time 24258385 ps
CPU time 0.64 seconds
Started Mar 14 01:09:32 PM PDT 24
Finished Mar 14 01:09:34 PM PDT 24
Peak memory 202388 kb
Host smart-ce8f5552-35c3-4b3a-9a9c-91843817789a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=793508641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.793508641
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2733676333
Short name T191
Test name
Test status
Simulation time 104335208 ps
CPU time 1.32 seconds
Started Mar 14 01:09:33 PM PDT 24
Finished Mar 14 01:09:35 PM PDT 24
Peak memory 202872 kb
Host smart-dc62e504-1298-4262-920b-581ecf8819f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733676333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.2733676333
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1154756739
Short name T240
Test name
Test status
Simulation time 224195050 ps
CPU time 2.64 seconds
Started Mar 14 01:09:35 PM PDT 24
Finished Mar 14 01:09:38 PM PDT 24
Peak memory 202940 kb
Host smart-bbf01b7d-ae49-4556-b6b9-2580299dc94c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1154756739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1154756739
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3514985948
Short name T56
Test name
Test status
Simulation time 73958129 ps
CPU time 1.33 seconds
Started Mar 14 01:09:35 PM PDT 24
Finished Mar 14 01:09:36 PM PDT 24
Peak memory 212368 kb
Host smart-2afa3f11-05a7-4fee-b1fd-9a0295aaccc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514985948 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.3514985948
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1647720838
Short name T777
Test name
Test status
Simulation time 54277492 ps
CPU time 1.5 seconds
Started Mar 14 01:09:44 PM PDT 24
Finished Mar 14 01:09:46 PM PDT 24
Peak memory 203020 kb
Host smart-2d994a5e-a89c-4096-88cc-208027ec1edc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647720838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.1647720838
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2179563426
Short name T801
Test name
Test status
Simulation time 188612710 ps
CPU time 2.15 seconds
Started Mar 14 01:09:38 PM PDT 24
Finished Mar 14 01:09:41 PM PDT 24
Peak memory 202936 kb
Host smart-9d58d9dd-5ca0-4de4-8c48-642b9161d64f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2179563426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2179563426
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2314013101
Short name T774
Test name
Test status
Simulation time 68743074 ps
CPU time 1.19 seconds
Started Mar 14 01:09:34 PM PDT 24
Finished Mar 14 01:09:36 PM PDT 24
Peak memory 211224 kb
Host smart-72751b21-be87-42d9-883a-3c5a16e2fb94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314013101 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2314013101
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3506240431
Short name T248
Test name
Test status
Simulation time 27672160 ps
CPU time 0.68 seconds
Started Mar 14 01:09:36 PM PDT 24
Finished Mar 14 01:09:37 PM PDT 24
Peak memory 202392 kb
Host smart-2f443e81-9cae-417b-8f54-140760a795e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3506240431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3506240431
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.711610817
Short name T183
Test name
Test status
Simulation time 71491643 ps
CPU time 1.03 seconds
Started Mar 14 01:09:35 PM PDT 24
Finished Mar 14 01:09:36 PM PDT 24
Peak memory 202968 kb
Host smart-a6f80e86-4f8e-46bf-8efb-4e126ab50496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711610817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_c
sr_outstanding.711610817
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1033930120
Short name T185
Test name
Test status
Simulation time 223216647 ps
CPU time 3.06 seconds
Started Mar 14 01:09:33 PM PDT 24
Finished Mar 14 01:09:37 PM PDT 24
Peak memory 202944 kb
Host smart-aab167b5-6f86-4f92-b946-80f85bcd9572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1033930120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1033930120
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1663548813
Short name T770
Test name
Test status
Simulation time 58100782 ps
CPU time 1.79 seconds
Started Mar 14 01:09:47 PM PDT 24
Finished Mar 14 01:09:49 PM PDT 24
Peak memory 211224 kb
Host smart-bb0850d5-a1f1-4140-bfb9-d9a57163092d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663548813 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.1663548813
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1044189265
Short name T785
Test name
Test status
Simulation time 37965646 ps
CPU time 0.76 seconds
Started Mar 14 01:09:47 PM PDT 24
Finished Mar 14 01:09:48 PM PDT 24
Peak memory 202672 kb
Host smart-d4b19021-425e-4482-91e3-4bf6e1bb74c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044189265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1044189265
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1829619316
Short name T187
Test name
Test status
Simulation time 206868507 ps
CPU time 2.36 seconds
Started Mar 14 01:09:50 PM PDT 24
Finished Mar 14 01:09:53 PM PDT 24
Peak memory 203044 kb
Host smart-d218b80a-09a4-4ca4-afcf-5d42bf1cabad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1829619316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1829619316
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.793806492
Short name T769
Test name
Test status
Simulation time 121628085 ps
CPU time 1.75 seconds
Started Mar 14 01:09:47 PM PDT 24
Finished Mar 14 01:09:49 PM PDT 24
Peak memory 214156 kb
Host smart-880caf7f-39ea-4b6c-a936-142ace0dddec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793806492 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.793806492
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1010799053
Short name T57
Test name
Test status
Simulation time 74894831 ps
CPU time 1.06 seconds
Started Mar 14 01:09:46 PM PDT 24
Finished Mar 14 01:09:47 PM PDT 24
Peak memory 202848 kb
Host smart-2d809f84-a2ae-4d2c-ae4a-22ba7e8d0bff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010799053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.1010799053
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.325538793
Short name T791
Test name
Test status
Simulation time 242568735 ps
CPU time 3.13 seconds
Started Mar 14 01:09:46 PM PDT 24
Finished Mar 14 01:09:49 PM PDT 24
Peak memory 202952 kb
Host smart-7948879a-41a2-4149-9027-56cfa57824ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=325538793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.325538793
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3792974920
Short name T788
Test name
Test status
Simulation time 65892341 ps
CPU time 1.87 seconds
Started Mar 14 01:09:46 PM PDT 24
Finished Mar 14 01:09:48 PM PDT 24
Peak memory 211160 kb
Host smart-c1364a61-7a16-4554-9ceb-f9ca205de70b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792974920 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3792974920
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2330656382
Short name T238
Test name
Test status
Simulation time 30411572 ps
CPU time 0.64 seconds
Started Mar 14 01:09:46 PM PDT 24
Finished Mar 14 01:09:47 PM PDT 24
Peak memory 202296 kb
Host smart-66eaeb9b-8eb6-4e86-848b-5aa6fc83b26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2330656382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2330656382
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3515693658
Short name T184
Test name
Test status
Simulation time 263404232 ps
CPU time 2.92 seconds
Started Mar 14 01:09:47 PM PDT 24
Finished Mar 14 01:09:50 PM PDT 24
Peak memory 202956 kb
Host smart-6add6175-6b77-4870-9cdf-1ac4ff1c7ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3515693658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3515693658
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2359217322
Short name T197
Test name
Test status
Simulation time 179693782 ps
CPU time 2.11 seconds
Started Mar 14 01:09:08 PM PDT 24
Finished Mar 14 01:09:10 PM PDT 24
Peak memory 202868 kb
Host smart-e2e6aec0-df17-45d0-a3f9-a025ffde7633
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359217322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2359217322
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3207534077
Short name T792
Test name
Test status
Simulation time 195418951 ps
CPU time 4.88 seconds
Started Mar 14 01:09:10 PM PDT 24
Finished Mar 14 01:09:16 PM PDT 24
Peak memory 202936 kb
Host smart-3ecd1b86-c4a9-4b26-9505-7a77a4127abe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207534077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3207534077
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3882299383
Short name T229
Test name
Test status
Simulation time 46475839 ps
CPU time 0.88 seconds
Started Mar 14 01:09:09 PM PDT 24
Finished Mar 14 01:09:10 PM PDT 24
Peak memory 202736 kb
Host smart-7312a2c0-53e1-44f0-a56e-c23ffa6900e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882299383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3882299383
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1683378352
Short name T190
Test name
Test status
Simulation time 84795136 ps
CPU time 1.43 seconds
Started Mar 14 01:09:06 PM PDT 24
Finished Mar 14 01:09:08 PM PDT 24
Peak memory 202976 kb
Host smart-413bc075-6319-4c40-a260-748f4eac384b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1683378352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1683378352
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.772683423
Short name T765
Test name
Test status
Simulation time 83307013 ps
CPU time 2.21 seconds
Started Mar 14 01:09:10 PM PDT 24
Finished Mar 14 01:09:12 PM PDT 24
Peak memory 202852 kb
Host smart-d6656d1d-50f6-4def-8733-bc19ef783131
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=772683423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.772683423
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2466100487
Short name T201
Test name
Test status
Simulation time 59649443 ps
CPU time 1.43 seconds
Started Mar 14 01:09:09 PM PDT 24
Finished Mar 14 01:09:11 PM PDT 24
Peak memory 202880 kb
Host smart-a91bcc6f-0b8a-4768-9916-a057b2553e56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466100487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.2466100487
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1591622021
Short name T782
Test name
Test status
Simulation time 224772786 ps
CPU time 3.06 seconds
Started Mar 14 01:09:09 PM PDT 24
Finished Mar 14 01:09:13 PM PDT 24
Peak memory 203008 kb
Host smart-c32e133c-8440-4607-a00c-666572227c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1591622021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1591622021
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1048973901
Short name T784
Test name
Test status
Simulation time 23534760 ps
CPU time 0.64 seconds
Started Mar 14 01:09:48 PM PDT 24
Finished Mar 14 01:09:49 PM PDT 24
Peak memory 202408 kb
Host smart-c9897ea8-2b3c-4aa7-a50e-7e3380b19c65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1048973901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1048973901
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2801840467
Short name T786
Test name
Test status
Simulation time 27036064 ps
CPU time 0.66 seconds
Started Mar 14 01:09:46 PM PDT 24
Finished Mar 14 01:09:47 PM PDT 24
Peak memory 202340 kb
Host smart-9c212811-72e3-4e65-a81a-a826b71abcba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2801840467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2801840467
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2823365165
Short name T799
Test name
Test status
Simulation time 20073509 ps
CPU time 0.66 seconds
Started Mar 14 01:09:47 PM PDT 24
Finished Mar 14 01:09:47 PM PDT 24
Peak memory 202396 kb
Host smart-fcfe12f1-e050-44ac-9ad0-07016ec991a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2823365165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2823365165
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3426336535
Short name T245
Test name
Test status
Simulation time 20674529 ps
CPU time 0.62 seconds
Started Mar 14 01:09:46 PM PDT 24
Finished Mar 14 01:09:47 PM PDT 24
Peak memory 202480 kb
Host smart-cb1dc067-f98f-4399-bf26-89facfe1eac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3426336535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3426336535
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.67059370
Short name T798
Test name
Test status
Simulation time 28061253 ps
CPU time 0.66 seconds
Started Mar 14 01:09:46 PM PDT 24
Finished Mar 14 01:09:47 PM PDT 24
Peak memory 202316 kb
Host smart-b8bf85c3-fa55-4709-a206-98819919c8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=67059370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.67059370
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1796038964
Short name T242
Test name
Test status
Simulation time 25773633 ps
CPU time 0.67 seconds
Started Mar 14 01:10:14 PM PDT 24
Finished Mar 14 01:10:15 PM PDT 24
Peak memory 202324 kb
Host smart-771cbc60-2e3c-4a46-9a37-98e49a2b8d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1796038964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1796038964
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.380282152
Short name T61
Test name
Test status
Simulation time 19271306 ps
CPU time 0.62 seconds
Started Mar 14 01:10:12 PM PDT 24
Finished Mar 14 01:10:13 PM PDT 24
Peak memory 202404 kb
Host smart-9fcfbe1d-cc56-4537-b046-aca8e3945568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=380282152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.380282152
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1172501761
Short name T63
Test name
Test status
Simulation time 19888383 ps
CPU time 0.63 seconds
Started Mar 14 01:10:14 PM PDT 24
Finished Mar 14 01:10:15 PM PDT 24
Peak memory 202420 kb
Host smart-6626aaa4-b4c4-4db6-927f-bf8d7118432e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1172501761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1172501761
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2069242355
Short name T787
Test name
Test status
Simulation time 175228893 ps
CPU time 2.07 seconds
Started Mar 14 01:09:21 PM PDT 24
Finished Mar 14 01:09:23 PM PDT 24
Peak memory 202956 kb
Host smart-b83b0fc7-ef58-4d10-b950-f6f3722796d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069242355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2069242355
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1270394676
Short name T776
Test name
Test status
Simulation time 71642947 ps
CPU time 2.32 seconds
Started Mar 14 01:09:22 PM PDT 24
Finished Mar 14 01:09:24 PM PDT 24
Peak memory 211176 kb
Host smart-b5a79319-9b50-47e4-99e3-7de883bf2252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270394676 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.1270394676
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1187757290
Short name T193
Test name
Test status
Simulation time 62283996 ps
CPU time 1.06 seconds
Started Mar 14 01:09:20 PM PDT 24
Finished Mar 14 01:09:21 PM PDT 24
Peak memory 202884 kb
Host smart-222ce101-d435-4548-9163-5edce584ac94
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187757290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1187757290
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.750974562
Short name T189
Test name
Test status
Simulation time 46340185 ps
CPU time 1.32 seconds
Started Mar 14 01:09:20 PM PDT 24
Finished Mar 14 01:09:21 PM PDT 24
Peak memory 202868 kb
Host smart-8d5568a0-2319-499c-89f3-8e835c6ca3b2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=750974562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.750974562
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.728000538
Short name T768
Test name
Test status
Simulation time 355702724 ps
CPU time 2.68 seconds
Started Mar 14 01:09:10 PM PDT 24
Finished Mar 14 01:09:13 PM PDT 24
Peak memory 202936 kb
Host smart-adaf8bd4-af4c-4be5-a837-a8a194ff813a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=728000538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.728000538
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.844302259
Short name T48
Test name
Test status
Simulation time 167452642 ps
CPU time 2.04 seconds
Started Mar 14 01:09:10 PM PDT 24
Finished Mar 14 01:09:12 PM PDT 24
Peak memory 202912 kb
Host smart-283a7f72-9086-4532-99f7-db6ef799122c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=844302259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.844302259
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3930893188
Short name T793
Test name
Test status
Simulation time 25564243 ps
CPU time 0.63 seconds
Started Mar 14 01:10:14 PM PDT 24
Finished Mar 14 01:10:15 PM PDT 24
Peak memory 202360 kb
Host smart-a9ff4c6a-80b7-4e52-907e-0a9580eee497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3930893188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3930893188
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2861575889
Short name T62
Test name
Test status
Simulation time 23074524 ps
CPU time 0.66 seconds
Started Mar 14 01:10:16 PM PDT 24
Finished Mar 14 01:10:17 PM PDT 24
Peak memory 202412 kb
Host smart-4087f035-d070-4a23-9687-1d5cbb4a64bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2861575889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2861575889
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3558930523
Short name T254
Test name
Test status
Simulation time 23779068 ps
CPU time 0.62 seconds
Started Mar 14 01:10:11 PM PDT 24
Finished Mar 14 01:10:12 PM PDT 24
Peak memory 202364 kb
Host smart-57c66d7e-35de-4108-b408-f6cf781dd7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3558930523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3558930523
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.436175455
Short name T789
Test name
Test status
Simulation time 31577651 ps
CPU time 0.66 seconds
Started Mar 14 01:10:10 PM PDT 24
Finished Mar 14 01:10:11 PM PDT 24
Peak memory 202344 kb
Host smart-b5bbac63-ca16-4d81-9f40-42a2ddf3c713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=436175455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.436175455
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2317156186
Short name T250
Test name
Test status
Simulation time 24051059 ps
CPU time 0.63 seconds
Started Mar 14 01:10:15 PM PDT 24
Finished Mar 14 01:10:15 PM PDT 24
Peak memory 202480 kb
Host smart-3a67181a-2d7e-4f11-88fe-e34b80912080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2317156186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2317156186
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.850409740
Short name T196
Test name
Test status
Simulation time 371464988 ps
CPU time 3.6 seconds
Started Mar 14 01:09:19 PM PDT 24
Finished Mar 14 01:09:23 PM PDT 24
Peak memory 202932 kb
Host smart-c1d7bd04-1774-4418-bf92-4a90c3bf94ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850409740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.850409740
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.284897098
Short name T192
Test name
Test status
Simulation time 198492684 ps
CPU time 4.73 seconds
Started Mar 14 01:09:21 PM PDT 24
Finished Mar 14 01:09:26 PM PDT 24
Peak memory 202920 kb
Host smart-558b98ad-cfa5-4157-86e3-7baf259505fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284897098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.284897098
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3725955851
Short name T188
Test name
Test status
Simulation time 44469175 ps
CPU time 1.28 seconds
Started Mar 14 01:09:19 PM PDT 24
Finished Mar 14 01:09:21 PM PDT 24
Peak memory 202980 kb
Host smart-49bfbb45-2abf-4e9a-986e-153e2365bbf6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3725955851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3725955851
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.336706250
Short name T764
Test name
Test status
Simulation time 149780145 ps
CPU time 3.97 seconds
Started Mar 14 01:09:21 PM PDT 24
Finished Mar 14 01:09:25 PM PDT 24
Peak memory 202924 kb
Host smart-a2844224-178c-4db2-b3aa-b94f8a5443ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=336706250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.336706250
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1379270336
Short name T795
Test name
Test status
Simulation time 62088537 ps
CPU time 1.03 seconds
Started Mar 14 01:09:21 PM PDT 24
Finished Mar 14 01:09:23 PM PDT 24
Peak memory 202988 kb
Host smart-454683b1-8d77-4876-9f69-af06d6060a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379270336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.1379270336
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3039400576
Short name T772
Test name
Test status
Simulation time 45380433 ps
CPU time 1.49 seconds
Started Mar 14 01:09:20 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 202880 kb
Host smart-7910e04f-8b22-43cd-86d2-d11dd44862e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3039400576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3039400576
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1530518200
Short name T251
Test name
Test status
Simulation time 23059541 ps
CPU time 0.65 seconds
Started Mar 14 01:10:11 PM PDT 24
Finished Mar 14 01:10:12 PM PDT 24
Peak memory 202492 kb
Host smart-379bff5b-32a4-4df5-b590-bf5bb409b64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1530518200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1530518200
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1721593923
Short name T797
Test name
Test status
Simulation time 25865340 ps
CPU time 0.64 seconds
Started Mar 14 01:10:13 PM PDT 24
Finished Mar 14 01:10:14 PM PDT 24
Peak memory 202336 kb
Host smart-ddb202e9-0239-4abf-92dc-0310ebccb19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1721593923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1721593923
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1455950897
Short name T59
Test name
Test status
Simulation time 22708774 ps
CPU time 0.65 seconds
Started Mar 14 01:10:13 PM PDT 24
Finished Mar 14 01:10:13 PM PDT 24
Peak memory 202436 kb
Host smart-9aa11a8a-8047-47bb-9322-9296212c0f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1455950897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1455950897
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2167015901
Short name T235
Test name
Test status
Simulation time 92344248 ps
CPU time 1.12 seconds
Started Mar 14 01:09:21 PM PDT 24
Finished Mar 14 01:09:23 PM PDT 24
Peak memory 202960 kb
Host smart-0ee57de5-2898-4dd5-bc4d-9987aadf7514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167015901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.2167015901
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1606817155
Short name T225
Test name
Test status
Simulation time 56702724 ps
CPU time 1.5 seconds
Started Mar 14 01:09:20 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 202908 kb
Host smart-d70b7b40-0093-4efa-980c-3c6c4141f2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606817155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1606817155
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1244420582
Short name T778
Test name
Test status
Simulation time 26273047 ps
CPU time 0.8 seconds
Started Mar 14 01:09:22 PM PDT 24
Finished Mar 14 01:09:24 PM PDT 24
Peak memory 202696 kb
Host smart-b59ba0cc-d600-4e7d-b6d6-fde152a05e3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244420582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1244420582
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2108869506
Short name T226
Test name
Test status
Simulation time 244778212 ps
CPU time 2.69 seconds
Started Mar 14 01:09:23 PM PDT 24
Finished Mar 14 01:09:26 PM PDT 24
Peak memory 203012 kb
Host smart-4349795c-5171-495d-a496-35cb5635a65a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2108869506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2108869506
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.275944869
Short name T241
Test name
Test status
Simulation time 154172038 ps
CPU time 1.85 seconds
Started Mar 14 01:09:19 PM PDT 24
Finished Mar 14 01:09:21 PM PDT 24
Peak memory 211212 kb
Host smart-5c1a2638-4868-43b0-ba8c-78b24141f364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275944869 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.275944869
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1731048033
Short name T75
Test name
Test status
Simulation time 45219124 ps
CPU time 0.82 seconds
Started Mar 14 01:09:22 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 202744 kb
Host smart-eed4c26a-ee86-488c-b90e-1249ea945e76
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731048033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1731048033
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.238867097
Short name T239
Test name
Test status
Simulation time 24281358 ps
CPU time 0.67 seconds
Started Mar 14 01:09:23 PM PDT 24
Finished Mar 14 01:09:24 PM PDT 24
Peak memory 202408 kb
Host smart-e707b424-587f-4bb6-ac71-15d0efeedfc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=238867097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.238867097
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1944455202
Short name T199
Test name
Test status
Simulation time 68867974 ps
CPU time 1.53 seconds
Started Mar 14 01:09:22 PM PDT 24
Finished Mar 14 01:09:25 PM PDT 24
Peak memory 202936 kb
Host smart-734395e5-f07c-4c12-99d0-e0f223a197b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944455202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.1944455202
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.353079128
Short name T771
Test name
Test status
Simulation time 55659262 ps
CPU time 1.76 seconds
Started Mar 14 01:09:22 PM PDT 24
Finished Mar 14 01:09:25 PM PDT 24
Peak memory 202900 kb
Host smart-f325dfba-2d8a-4d9f-a0fc-2f2ce5975c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=353079128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.353079128
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1851497463
Short name T244
Test name
Test status
Simulation time 23157917 ps
CPU time 0.62 seconds
Started Mar 14 01:09:21 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 202416 kb
Host smart-bcbae866-34be-4b44-aa67-3c8a4eac2d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1851497463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1851497463
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3453580394
Short name T767
Test name
Test status
Simulation time 50247822 ps
CPU time 1.53 seconds
Started Mar 14 01:09:21 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 203016 kb
Host smart-bf30ceb4-3691-413f-be21-a3a3ac3a03fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3453580394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3453580394
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2050885973
Short name T186
Test name
Test status
Simulation time 67491033 ps
CPU time 2.14 seconds
Started Mar 14 01:09:19 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 211228 kb
Host smart-dc846965-e9e9-4ec0-8a8b-e7ec63b6ebf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050885973 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2050885973
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2503378644
Short name T233
Test name
Test status
Simulation time 152345250 ps
CPU time 1.6 seconds
Started Mar 14 01:09:24 PM PDT 24
Finished Mar 14 01:09:25 PM PDT 24
Peak memory 203032 kb
Host smart-23138f85-d976-4f54-b1f7-4a81ba287640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503378644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c
sr_outstanding.2503378644
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3986076352
Short name T794
Test name
Test status
Simulation time 248675682 ps
CPU time 2.82 seconds
Started Mar 14 01:09:18 PM PDT 24
Finished Mar 14 01:09:22 PM PDT 24
Peak memory 202920 kb
Host smart-523ebe95-da0c-4ecd-8a5c-97cbb5052329
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3986076352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3986076352
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2523585532
Short name T354
Test name
Test status
Simulation time 8370288619 ps
CPU time 7.29 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 202548 kb
Host smart-ca076236-8a48-4249-a231-e51f3170c3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25235
85532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2523585532
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3255481338
Short name T515
Test name
Test status
Simulation time 125776888 ps
CPU time 1.2 seconds
Started Mar 14 01:30:15 PM PDT 24
Finished Mar 14 01:30:16 PM PDT 24
Peak memory 202628 kb
Host smart-23cd3b58-5258-48d5-a530-b792cfdd04a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32554
81338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3255481338
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1411627356
Short name T176
Test name
Test status
Simulation time 8359969101 ps
CPU time 8.89 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:23 PM PDT 24
Peak memory 202508 kb
Host smart-af432b83-8d2a-454e-bca3-f5b254b2c645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14116
27356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1411627356
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2568041794
Short name T610
Test name
Test status
Simulation time 8425645623 ps
CPU time 9.44 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:36 PM PDT 24
Peak memory 202524 kb
Host smart-dc460522-4f1d-47b2-b66e-76f71286530b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25680
41794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2568041794
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.663628940
Short name T745
Test name
Test status
Simulation time 8411379110 ps
CPU time 8.14 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:23 PM PDT 24
Peak memory 202536 kb
Host smart-3d4f1ddc-9cc9-4330-b53e-a8ad35caf4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66362
8940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.663628940
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3847310529
Short name T321
Test name
Test status
Simulation time 8361155313 ps
CPU time 9.51 seconds
Started Mar 14 01:30:17 PM PDT 24
Finished Mar 14 01:30:27 PM PDT 24
Peak memory 202584 kb
Host smart-e9494e01-8668-4aa1-bce4-747ab216e5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38473
10529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3847310529
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.32993969
Short name T264
Test name
Test status
Simulation time 8364763609 ps
CPU time 7.09 seconds
Started Mar 14 01:30:18 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 202520 kb
Host smart-f8fcf8ce-a2dc-4a31-ba6b-b40a56b87b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32993
969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.32993969
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1582466673
Short name T520
Test name
Test status
Simulation time 8384502167 ps
CPU time 7.06 seconds
Started Mar 14 01:30:19 PM PDT 24
Finished Mar 14 01:30:26 PM PDT 24
Peak memory 202540 kb
Host smart-fbd5c1e9-7806-4ef4-89d5-e3754551afc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15824
66673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1582466673
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.3772958153
Short name T575
Test name
Test status
Simulation time 27776595 ps
CPU time 0.66 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:26 PM PDT 24
Peak memory 202432 kb
Host smart-b0b4a43b-11dd-4834-abcc-793b699ca091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37729
58153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.3772958153
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3645943079
Short name T339
Test name
Test status
Simulation time 8383747976 ps
CPU time 7.67 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 202524 kb
Host smart-f3615f6e-7953-43d4-b38d-df68484883cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
43079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3645943079
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3441277175
Short name T479
Test name
Test status
Simulation time 8375988241 ps
CPU time 8.65 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202496 kb
Host smart-47cec465-b0f1-41c1-bc0a-7d5edb61a3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34412
77175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3441277175
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1163613362
Short name T64
Test name
Test status
Simulation time 100458515 ps
CPU time 0.91 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:30:14 PM PDT 24
Peak memory 217736 kb
Host smart-54f6a790-ba0d-4c32-828f-c8042497c8a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1163613362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1163613362
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1780263157
Short name T388
Test name
Test status
Simulation time 8371453633 ps
CPU time 7.64 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202512 kb
Host smart-cd0da02e-3c3b-4302-8e42-c2e9a95b8ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17802
63157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1780263157
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2568420668
Short name T590
Test name
Test status
Simulation time 138879303 ps
CPU time 1.68 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:16 PM PDT 24
Peak memory 202712 kb
Host smart-409daf60-868b-4548-a8c8-7555837a7daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25684
20668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2568420668
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3118610862
Short name T313
Test name
Test status
Simulation time 8357959021 ps
CPU time 7.29 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 202520 kb
Host smart-42a12bd2-796b-43c6-8b8e-faf6cc202013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31186
10862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3118610862
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1469865536
Short name T622
Test name
Test status
Simulation time 8391681855 ps
CPU time 8.11 seconds
Started Mar 14 01:30:16 PM PDT 24
Finished Mar 14 01:30:24 PM PDT 24
Peak memory 202520 kb
Host smart-dd455cea-5afd-436b-9d6f-3a7d2395170e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14698
65536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1469865536
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4269995816
Short name T342
Test name
Test status
Simulation time 8406115871 ps
CPU time 7.35 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:30:21 PM PDT 24
Peak memory 202548 kb
Host smart-6f17e673-4ddb-49b5-ae2a-21fd00f1ee34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42699
95816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4269995816
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.225099579
Short name T328
Test name
Test status
Simulation time 8366455537 ps
CPU time 8.52 seconds
Started Mar 14 01:30:19 PM PDT 24
Finished Mar 14 01:30:27 PM PDT 24
Peak memory 202564 kb
Host smart-bacfa68b-81c7-48ac-b828-e60d35d88fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22509
9579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.225099579
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.1805880962
Short name T436
Test name
Test status
Simulation time 8402004045 ps
CPU time 7.25 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202536 kb
Host smart-88a11be8-c0b0-4fd6-9dca-8443183927af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18058
80962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.1805880962
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.214418837
Short name T309
Test name
Test status
Simulation time 8379839216 ps
CPU time 7.29 seconds
Started Mar 14 01:30:15 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202596 kb
Host smart-c167fa60-3913-4993-ace0-1d5ca2245455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21441
8837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.214418837
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.904787754
Short name T586
Test name
Test status
Simulation time 22674504 ps
CPU time 0.63 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:27 PM PDT 24
Peak memory 202456 kb
Host smart-fc4287b0-82a7-434d-8ed7-8440f891b2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90478
7754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.904787754
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1428865750
Short name T729
Test name
Test status
Simulation time 8432098556 ps
CPU time 7.5 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:36 PM PDT 24
Peak memory 202544 kb
Host smart-21ceefc9-10e8-4657-a9e3-67a240e6a374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14288
65750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1428865750
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1183872458
Short name T256
Test name
Test status
Simulation time 8387313706 ps
CPU time 7.16 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:34 PM PDT 24
Peak memory 202524 kb
Host smart-5fed69a6-1a7b-44b3-8e96-53c58aaacb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11838
72458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1183872458
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1135161330
Short name T65
Test name
Test status
Simulation time 178378820 ps
CPU time 0.97 seconds
Started Mar 14 01:30:16 PM PDT 24
Finished Mar 14 01:30:17 PM PDT 24
Peak memory 217712 kb
Host smart-21d958e2-f271-4ac7-a76c-6bbd6b0c8161
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1135161330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1135161330
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1853060022
Short name T432
Test name
Test status
Simulation time 8357904608 ps
CPU time 8.58 seconds
Started Mar 14 01:30:16 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 202608 kb
Host smart-da784cb7-a751-454a-bd5d-083580d1a1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18530
60022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1853060022
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.275178250
Short name T140
Test name
Test status
Simulation time 8476447531 ps
CPU time 8.88 seconds
Started Mar 14 01:30:15 PM PDT 24
Finished Mar 14 01:30:24 PM PDT 24
Peak memory 202556 kb
Host smart-f1ca37e3-e829-4747-ab68-ca793b12651a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27517
8250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.275178250
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1932036478
Short name T43
Test name
Test status
Simulation time 8373106028 ps
CPU time 8.87 seconds
Started Mar 14 01:30:49 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 202576 kb
Host smart-eb4552a9-ec4d-43f7-80bc-4f99ede0eb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19320
36478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1932036478
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.4256527000
Short name T207
Test name
Test status
Simulation time 145707416 ps
CPU time 1.41 seconds
Started Mar 14 01:30:52 PM PDT 24
Finished Mar 14 01:30:54 PM PDT 24
Peak memory 202680 kb
Host smart-d9c44263-ff29-4682-ad05-d2f43e01d1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42565
27000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.4256527000
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2225257037
Short name T178
Test name
Test status
Simulation time 8358380566 ps
CPU time 7.93 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202548 kb
Host smart-b5515ce1-3aca-4d05-aa97-8261076f1fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22252
57037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2225257037
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.975930085
Short name T434
Test name
Test status
Simulation time 8381058822 ps
CPU time 9.46 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:13 PM PDT 24
Peak memory 202524 kb
Host smart-3a3b2e75-da87-4195-9426-a6639c5a6329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97593
0085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.975930085
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2194115955
Short name T70
Test name
Test status
Simulation time 8403863530 ps
CPU time 7.44 seconds
Started Mar 14 01:30:51 PM PDT 24
Finished Mar 14 01:30:59 PM PDT 24
Peak memory 202584 kb
Host smart-5e5409c3-ebc2-4512-a4c4-076354c88d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21941
15955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2194115955
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3205556745
Short name T329
Test name
Test status
Simulation time 8364203491 ps
CPU time 7.9 seconds
Started Mar 14 01:30:48 PM PDT 24
Finished Mar 14 01:30:56 PM PDT 24
Peak memory 202416 kb
Host smart-14d91fdf-2a31-4682-8d50-34e33b35a307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32055
56745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3205556745
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2345812920
Short name T755
Test name
Test status
Simulation time 8414059527 ps
CPU time 7.91 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202576 kb
Host smart-55005923-cc43-49a9-99f0-0c45dbf39e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23458
12920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2345812920
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4107578076
Short name T648
Test name
Test status
Simulation time 8404573206 ps
CPU time 8.22 seconds
Started Mar 14 01:30:52 PM PDT 24
Finished Mar 14 01:31:01 PM PDT 24
Peak memory 202548 kb
Host smart-db664af6-e99e-409b-9429-bfb6f2f54b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41075
78076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4107578076
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2519876047
Short name T546
Test name
Test status
Simulation time 8401487158 ps
CPU time 7.14 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:10 PM PDT 24
Peak memory 202576 kb
Host smart-1b68a0da-5615-4df2-9f50-1447c49bb1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25198
76047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2519876047
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2206869996
Short name T545
Test name
Test status
Simulation time 33322565 ps
CPU time 0.65 seconds
Started Mar 14 01:30:51 PM PDT 24
Finished Mar 14 01:30:51 PM PDT 24
Peak memory 202464 kb
Host smart-d3c1707b-f4d6-436d-8bf6-de129032086e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22068
69996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2206869996
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3487781317
Short name T123
Test name
Test status
Simulation time 8415183624 ps
CPU time 8.03 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202572 kb
Host smart-3b8b86c9-2214-457e-b4da-18bfeeac8600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
81317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3487781317
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.1547366491
Short name T467
Test name
Test status
Simulation time 8407212206 ps
CPU time 7.37 seconds
Started Mar 14 01:30:49 PM PDT 24
Finished Mar 14 01:30:56 PM PDT 24
Peak memory 202536 kb
Host smart-7870bde7-fc9e-413c-8b80-6ecb6a929410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15473
66491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.1547366491
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1113939930
Short name T536
Test name
Test status
Simulation time 8357286453 ps
CPU time 7.25 seconds
Started Mar 14 01:30:47 PM PDT 24
Finished Mar 14 01:30:54 PM PDT 24
Peak memory 202596 kb
Host smart-8f74955f-7436-41e2-a0b8-30a6f6eb92c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11139
39930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1113939930
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.303191111
Short name T441
Test name
Test status
Simulation time 8367854224 ps
CPU time 8.13 seconds
Started Mar 14 01:30:52 PM PDT 24
Finished Mar 14 01:31:00 PM PDT 24
Peak memory 202552 kb
Host smart-6c0ddfaa-1958-423b-a901-e664b3be24a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30319
1111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.303191111
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.55565324
Short name T470
Test name
Test status
Simulation time 192366584 ps
CPU time 2.01 seconds
Started Mar 14 01:30:48 PM PDT 24
Finished Mar 14 01:30:51 PM PDT 24
Peak memory 202952 kb
Host smart-6fcecf99-f0f6-4f23-86d2-6761a7c4c4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55565
324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.55565324
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1696464277
Short name T158
Test name
Test status
Simulation time 8359781791 ps
CPU time 7.6 seconds
Started Mar 14 01:30:51 PM PDT 24
Finished Mar 14 01:30:59 PM PDT 24
Peak memory 202548 kb
Host smart-3f1c3fc2-c488-41fe-b18c-14936e1c645d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16964
64277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1696464277
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3840976440
Short name T628
Test name
Test status
Simulation time 8430076444 ps
CPU time 7.97 seconds
Started Mar 14 01:30:50 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 202548 kb
Host smart-f7e6e4e2-806b-44c4-b4b8-7c668d6a3188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38409
76440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3840976440
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.134886498
Short name T417
Test name
Test status
Simulation time 8403665528 ps
CPU time 7.59 seconds
Started Mar 14 01:30:52 PM PDT 24
Finished Mar 14 01:30:59 PM PDT 24
Peak memory 202568 kb
Host smart-1d9dee42-b764-4253-80db-2c3ee08ba891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13488
6498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.134886498
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3655125170
Short name T350
Test name
Test status
Simulation time 8361672410 ps
CPU time 7.55 seconds
Started Mar 14 01:30:51 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 202584 kb
Host smart-3438c6a4-0700-45ad-97ee-b90afbfa0270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36551
25170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3655125170
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1624505672
Short name T431
Test name
Test status
Simulation time 8389847372 ps
CPU time 7.05 seconds
Started Mar 14 01:30:52 PM PDT 24
Finished Mar 14 01:31:00 PM PDT 24
Peak memory 202512 kb
Host smart-792bcc32-bc3b-479b-83ca-606588d70c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16245
05672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1624505672
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4233331535
Short name T298
Test name
Test status
Simulation time 8394652896 ps
CPU time 8.01 seconds
Started Mar 14 01:30:49 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 202620 kb
Host smart-141cc279-d9a1-4e68-89b3-3efd9f004fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42333
31535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4233331535
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2738065753
Short name T561
Test name
Test status
Simulation time 26285324 ps
CPU time 0.63 seconds
Started Mar 14 01:30:53 PM PDT 24
Finished Mar 14 01:30:54 PM PDT 24
Peak memory 202480 kb
Host smart-42e08ce5-a834-4404-886b-d4e2d166c0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27380
65753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2738065753
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1952846103
Short name T455
Test name
Test status
Simulation time 8423696219 ps
CPU time 7.91 seconds
Started Mar 14 01:30:51 PM PDT 24
Finished Mar 14 01:30:59 PM PDT 24
Peak memory 202524 kb
Host smart-26ca1aea-9707-45dd-a192-d7927eb20bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
46103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1952846103
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3775640970
Short name T280
Test name
Test status
Simulation time 8381448268 ps
CPU time 7.19 seconds
Started Mar 14 01:30:53 PM PDT 24
Finished Mar 14 01:31:01 PM PDT 24
Peak memory 202504 kb
Host smart-ec53a6cd-a0bc-4731-97b9-33b6d7275a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37756
40970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3775640970
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.86255933
Short name T547
Test name
Test status
Simulation time 8359744900 ps
CPU time 8.7 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202572 kb
Host smart-78cb0140-4935-4a27-b707-38ccea8c0748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86255
933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.86255933
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2595282338
Short name T630
Test name
Test status
Simulation time 8366732296 ps
CPU time 9.49 seconds
Started Mar 14 01:30:47 PM PDT 24
Finished Mar 14 01:30:57 PM PDT 24
Peak memory 202384 kb
Host smart-388b0501-2a50-48d5-b803-b4381cde20e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25952
82338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2595282338
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2210786454
Short name T386
Test name
Test status
Simulation time 67438419 ps
CPU time 1.93 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:07 PM PDT 24
Peak memory 202740 kb
Host smart-7fb3de71-9229-47a2-9729-9a1294667726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22107
86454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2210786454
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2909392018
Short name T9
Test name
Test status
Simulation time 8412407224 ps
CPU time 7.48 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:12 PM PDT 24
Peak memory 202548 kb
Host smart-7417ff7c-5175-4977-bb26-58a36a124e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29093
92018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2909392018
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1063053176
Short name T609
Test name
Test status
Simulation time 8410793548 ps
CPU time 7.69 seconds
Started Mar 14 01:31:02 PM PDT 24
Finished Mar 14 01:31:10 PM PDT 24
Peak memory 202512 kb
Host smart-5fd73c9f-9c72-4ebd-8408-d4a191b71b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10630
53176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1063053176
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3497333667
Short name T673
Test name
Test status
Simulation time 8362609261 ps
CPU time 7.4 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:12 PM PDT 24
Peak memory 202540 kb
Host smart-1832023b-4e11-4c4d-953a-35b93d7777e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34973
33667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3497333667
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1547571807
Short name T588
Test name
Test status
Simulation time 8392772463 ps
CPU time 7.56 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:13 PM PDT 24
Peak memory 202532 kb
Host smart-1eb5d256-3903-4654-8680-a84a12ea500c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
71807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1547571807
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1172094182
Short name T714
Test name
Test status
Simulation time 8381399323 ps
CPU time 7.56 seconds
Started Mar 14 01:31:04 PM PDT 24
Finished Mar 14 01:31:12 PM PDT 24
Peak memory 202516 kb
Host smart-ef67051f-b431-4c31-92d9-3c672a2ca55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11720
94182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1172094182
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.301287577
Short name T736
Test name
Test status
Simulation time 24097738 ps
CPU time 0.65 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:06 PM PDT 24
Peak memory 202484 kb
Host smart-589509e8-096d-4603-9405-1ce15bb3ec26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30128
7577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.301287577
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.2988111722
Short name T663
Test name
Test status
Simulation time 8372872989 ps
CPU time 8.16 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202600 kb
Host smart-3ead439e-7ecb-41b4-b1d2-25d456084d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
11722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.2988111722
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3086530815
Short name T491
Test name
Test status
Simulation time 8359268670 ps
CPU time 7.72 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202464 kb
Host smart-63918aab-ae72-40a3-b204-e1a69261cf6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865
30815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3086530815
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2066610274
Short name T42
Test name
Test status
Simulation time 8478939318 ps
CPU time 8.08 seconds
Started Mar 14 01:30:53 PM PDT 24
Finished Mar 14 01:31:01 PM PDT 24
Peak memory 202500 kb
Host smart-2f20ad50-74bd-4b8f-a746-ce5aeac80a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
10274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2066610274
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.4118071261
Short name T531
Test name
Test status
Simulation time 8366207749 ps
CPU time 8.44 seconds
Started Mar 14 01:31:02 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202596 kb
Host smart-d02c3760-b819-43ef-889c-f3fd8254a54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41180
71261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.4118071261
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3522827464
Short name T439
Test name
Test status
Simulation time 48745163 ps
CPU time 1.58 seconds
Started Mar 14 01:31:02 PM PDT 24
Finished Mar 14 01:31:04 PM PDT 24
Peak memory 202604 kb
Host smart-ab18674c-0175-4482-b044-833e7c0de309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35228
27464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3522827464
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.4108960819
Short name T160
Test name
Test status
Simulation time 8356857069 ps
CPU time 9.6 seconds
Started Mar 14 01:31:07 PM PDT 24
Finished Mar 14 01:31:17 PM PDT 24
Peak memory 202524 kb
Host smart-7176d364-8ad2-4119-bd77-adbf8cc9ea37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
60819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.4108960819
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2957340785
Short name T581
Test name
Test status
Simulation time 8432118519 ps
CPU time 7.97 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:13 PM PDT 24
Peak memory 202512 kb
Host smart-c47cc7cb-0599-4119-877e-eb374d2dbb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573
40785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2957340785
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2238128529
Short name T459
Test name
Test status
Simulation time 8405498344 ps
CPU time 9.05 seconds
Started Mar 14 01:31:06 PM PDT 24
Finished Mar 14 01:31:15 PM PDT 24
Peak memory 202544 kb
Host smart-7b50e40a-9787-4c4f-aaef-fa68f1771288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22381
28529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2238128529
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3556176915
Short name T255
Test name
Test status
Simulation time 8365379738 ps
CPU time 8.82 seconds
Started Mar 14 01:31:05 PM PDT 24
Finished Mar 14 01:31:14 PM PDT 24
Peak memory 202512 kb
Host smart-1dd3554d-fa79-44ed-96f2-d48736394d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35561
76915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3556176915
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3208163363
Short name T267
Test name
Test status
Simulation time 8396532703 ps
CPU time 10.2 seconds
Started Mar 14 01:31:01 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202532 kb
Host smart-57ac36d5-8fb9-4ae2-bf97-800767276c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32081
63363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3208163363
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3550177839
Short name T276
Test name
Test status
Simulation time 8372884234 ps
CPU time 8.92 seconds
Started Mar 14 01:31:04 PM PDT 24
Finished Mar 14 01:31:13 PM PDT 24
Peak memory 202620 kb
Host smart-cb53c166-262b-4bbb-acdb-7a6a37217bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35501
77839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3550177839
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.69844565
Short name T699
Test name
Test status
Simulation time 27141458 ps
CPU time 0.64 seconds
Started Mar 14 01:31:02 PM PDT 24
Finished Mar 14 01:31:03 PM PDT 24
Peak memory 202492 kb
Host smart-c4cdb8b7-2a9f-4024-8c39-4186c36db089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69844
565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.69844565
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.287433392
Short name T563
Test name
Test status
Simulation time 8390645473 ps
CPU time 7.13 seconds
Started Mar 14 01:31:03 PM PDT 24
Finished Mar 14 01:31:10 PM PDT 24
Peak memory 202528 kb
Host smart-79a12326-4c68-4786-8481-1091ea90b7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28743
3392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.287433392
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.4222366086
Short name T619
Test name
Test status
Simulation time 8378843197 ps
CPU time 7.68 seconds
Started Mar 14 01:31:11 PM PDT 24
Finished Mar 14 01:31:19 PM PDT 24
Peak memory 202504 kb
Host smart-593a5e33-3274-45bb-b2d4-2cc4eef659f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42223
66086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.4222366086
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4209669126
Short name T713
Test name
Test status
Simulation time 8360805941 ps
CPU time 7.34 seconds
Started Mar 14 01:31:02 PM PDT 24
Finished Mar 14 01:31:09 PM PDT 24
Peak memory 202572 kb
Host smart-108debf6-b1a8-4ebe-8c6e-a9c6eb1e1b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
69126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4209669126
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.33783310
Short name T733
Test name
Test status
Simulation time 8372024476 ps
CPU time 7.71 seconds
Started Mar 14 01:31:04 PM PDT 24
Finished Mar 14 01:31:12 PM PDT 24
Peak memory 202580 kb
Host smart-346b6465-5d00-4534-a820-144ad047539b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33783
310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.33783310
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1667596246
Short name T344
Test name
Test status
Simulation time 49999956 ps
CPU time 1.44 seconds
Started Mar 14 01:31:06 PM PDT 24
Finished Mar 14 01:31:07 PM PDT 24
Peak memory 202676 kb
Host smart-7b8a07e0-14ba-4b7a-8262-f8e38e4b6853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16675
96246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1667596246
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3210191959
Short name T453
Test name
Test status
Simulation time 8362662246 ps
CPU time 8.96 seconds
Started Mar 14 01:31:19 PM PDT 24
Finished Mar 14 01:31:28 PM PDT 24
Peak memory 202444 kb
Host smart-00ea5871-ca62-49c6-9dd1-a05ba9778fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32101
91959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3210191959
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1365640514
Short name T564
Test name
Test status
Simulation time 8405479407 ps
CPU time 9.04 seconds
Started Mar 14 01:31:01 PM PDT 24
Finished Mar 14 01:31:10 PM PDT 24
Peak memory 202564 kb
Host smart-6d3801c5-b81d-4eb0-bb1e-5514f6a123f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13656
40514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1365640514
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.725480214
Short name T572
Test name
Test status
Simulation time 8362776838 ps
CPU time 7.35 seconds
Started Mar 14 01:31:17 PM PDT 24
Finished Mar 14 01:31:24 PM PDT 24
Peak memory 202592 kb
Host smart-a81e4e44-40de-4d25-ae4c-82a4d4223cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72548
0214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.725480214
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2106481744
Short name T717
Test name
Test status
Simulation time 8414446611 ps
CPU time 7.82 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202540 kb
Host smart-da0c5de7-0e9b-419c-b759-ed3a28e23927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21064
81744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2106481744
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.4251278672
Short name T476
Test name
Test status
Simulation time 8372935117 ps
CPU time 8.15 seconds
Started Mar 14 01:31:21 PM PDT 24
Finished Mar 14 01:31:29 PM PDT 24
Peak memory 202584 kb
Host smart-6074b216-5fc4-4ad8-8ff6-557fb3f01eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42512
78672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4251278672
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2934921576
Short name T468
Test name
Test status
Simulation time 8373958694 ps
CPU time 8.68 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:28 PM PDT 24
Peak memory 202508 kb
Host smart-9b0b121d-f203-4ede-a38d-61fe45aac094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29349
21576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2934921576
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3825921166
Short name T395
Test name
Test status
Simulation time 23507049 ps
CPU time 0.65 seconds
Started Mar 14 01:31:19 PM PDT 24
Finished Mar 14 01:31:19 PM PDT 24
Peak memory 202464 kb
Host smart-f25c8e47-0562-4081-a0c5-4235e8e2cb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38259
21166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3825921166
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1900499778
Short name T517
Test name
Test status
Simulation time 8381092477 ps
CPU time 8.12 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202576 kb
Host smart-8af074ca-d76c-43d9-a2c4-d5cf77ddbae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19004
99778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1900499778
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.801413448
Short name T349
Test name
Test status
Simulation time 8379516627 ps
CPU time 8.94 seconds
Started Mar 14 01:31:21 PM PDT 24
Finished Mar 14 01:31:30 PM PDT 24
Peak memory 202572 kb
Host smart-35e43900-db8a-4329-96e3-907ab36db959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80141
3448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.801413448
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3188696606
Short name T730
Test name
Test status
Simulation time 8360667450 ps
CPU time 7.88 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:28 PM PDT 24
Peak memory 202488 kb
Host smart-ada08e29-5907-457e-9d50-ab5b4fae772a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31886
96606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3188696606
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.778789614
Short name T135
Test name
Test status
Simulation time 8479294032 ps
CPU time 8.89 seconds
Started Mar 14 01:31:02 PM PDT 24
Finished Mar 14 01:31:11 PM PDT 24
Peak memory 202604 kb
Host smart-5a23c5f9-29c8-4cf9-95d2-32ef1d7b90ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77878
9614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.778789614
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1304898066
Short name T347
Test name
Test status
Simulation time 8374679004 ps
CPU time 7.53 seconds
Started Mar 14 01:31:19 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202512 kb
Host smart-eb5fda5c-f7b9-4f18-a92b-344fa2938518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13048
98066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1304898066
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.829305530
Short name T206
Test name
Test status
Simulation time 248418360 ps
CPU time 2.06 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:20 PM PDT 24
Peak memory 202668 kb
Host smart-b069f551-e61e-4d92-a30f-885a2ff79baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82930
5530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.829305530
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.416886295
Short name T753
Test name
Test status
Simulation time 8362902177 ps
CPU time 7.55 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202516 kb
Host smart-358b08e4-1a1a-47c3-b59b-9ed41092f6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41688
6295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.416886295
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.212214069
Short name T698
Test name
Test status
Simulation time 8451914698 ps
CPU time 7.71 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:27 PM PDT 24
Peak memory 202508 kb
Host smart-1f6c7510-d741-45cd-8f51-4134e62b04bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21221
4069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.212214069
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.846856060
Short name T505
Test name
Test status
Simulation time 8406737535 ps
CPU time 7.65 seconds
Started Mar 14 01:31:19 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202584 kb
Host smart-2d76a667-0793-4e34-a4a4-e0c8e3bef9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84685
6060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.846856060
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3408301116
Short name T390
Test name
Test status
Simulation time 8362144956 ps
CPU time 7.42 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:25 PM PDT 24
Peak memory 202568 kb
Host smart-fc3cbd63-a2ab-444d-9733-9c8110da8f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34083
01116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3408301116
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3188535661
Short name T642
Test name
Test status
Simulation time 8367120906 ps
CPU time 7.67 seconds
Started Mar 14 01:31:17 PM PDT 24
Finished Mar 14 01:31:25 PM PDT 24
Peak memory 202488 kb
Host smart-ce646d13-9675-44fa-887b-ca1e310b6fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31885
35661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3188535661
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1515723294
Short name T375
Test name
Test status
Simulation time 8385018461 ps
CPU time 7.86 seconds
Started Mar 14 01:31:19 PM PDT 24
Finished Mar 14 01:31:27 PM PDT 24
Peak memory 202472 kb
Host smart-bb64475f-26b5-4824-b83e-93e1919f9dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15157
23294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1515723294
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3838410469
Short name T579
Test name
Test status
Simulation time 27192855 ps
CPU time 0.64 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:19 PM PDT 24
Peak memory 202444 kb
Host smart-031a19b6-cb27-4f1d-972e-eff470f7cc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38384
10469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3838410469
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3173256253
Short name T514
Test name
Test status
Simulation time 8436379926 ps
CPU time 7.88 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:28 PM PDT 24
Peak memory 202584 kb
Host smart-9020a503-dcf8-44a7-850a-6080b9c8f737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31732
56253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3173256253
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3154978831
Short name T443
Test name
Test status
Simulation time 8399240650 ps
CPU time 7.39 seconds
Started Mar 14 01:31:16 PM PDT 24
Finished Mar 14 01:31:24 PM PDT 24
Peak memory 202548 kb
Host smart-519a1c13-1e9b-4863-9546-76e9096524fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31549
78831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3154978831
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3971300249
Short name T553
Test name
Test status
Simulation time 8360783489 ps
CPU time 7.64 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202536 kb
Host smart-3b12314d-4f4f-4cd8-b5f6-1c5dc499f6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
00249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3971300249
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2139478317
Short name T380
Test name
Test status
Simulation time 8371932441 ps
CPU time 6.88 seconds
Started Mar 14 01:31:15 PM PDT 24
Finished Mar 14 01:31:22 PM PDT 24
Peak memory 202588 kb
Host smart-072c66b9-b0f9-48c1-80cc-d4caac36c067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21394
78317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2139478317
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2358654443
Short name T411
Test name
Test status
Simulation time 91086263 ps
CPU time 1.05 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:22 PM PDT 24
Peak memory 202680 kb
Host smart-b6946f30-e34f-43cf-b8a3-bb20921ae81b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23586
54443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2358654443
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.4285408176
Short name T512
Test name
Test status
Simulation time 8363337101 ps
CPU time 7.94 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202532 kb
Host smart-57198c1e-6fc2-46b9-b154-dbd0ba699c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
08176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.4285408176
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.576242907
Short name T407
Test name
Test status
Simulation time 8402241605 ps
CPU time 7.36 seconds
Started Mar 14 01:31:21 PM PDT 24
Finished Mar 14 01:31:28 PM PDT 24
Peak memory 202528 kb
Host smart-ac0b2cad-c997-4191-be82-4f6ce2a09b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57624
2907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.576242907
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.161895020
Short name T266
Test name
Test status
Simulation time 8366215083 ps
CPU time 7.53 seconds
Started Mar 14 01:31:16 PM PDT 24
Finished Mar 14 01:31:24 PM PDT 24
Peak memory 202456 kb
Host smart-0e2b787e-9fd2-4f94-8c8d-2aec6a261e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16189
5020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.161895020
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2298315520
Short name T705
Test name
Test status
Simulation time 8372578080 ps
CPU time 7.93 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202252 kb
Host smart-e8cdc652-b27c-4a48-ac35-eca948475e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22983
15520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2298315520
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.649719740
Short name T551
Test name
Test status
Simulation time 8390917173 ps
CPU time 7.97 seconds
Started Mar 14 01:31:23 PM PDT 24
Finished Mar 14 01:31:31 PM PDT 24
Peak memory 202500 kb
Host smart-e5d7e755-b633-410b-8ac1-7e7f00a728de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64971
9740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.649719740
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2165133604
Short name T466
Test name
Test status
Simulation time 28391525 ps
CPU time 0.64 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:19 PM PDT 24
Peak memory 202496 kb
Host smart-155254fe-bf9e-4456-8741-43b1fa88dad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21651
33604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2165133604
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3031382304
Short name T332
Test name
Test status
Simulation time 8401895619 ps
CPU time 7.53 seconds
Started Mar 14 01:31:19 PM PDT 24
Finished Mar 14 01:31:27 PM PDT 24
Peak memory 202576 kb
Host smart-b54ef06c-b25a-4716-8e1b-744bc1dc3040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30313
82304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3031382304
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1932899984
Short name T433
Test name
Test status
Simulation time 8363560908 ps
CPU time 7.92 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202568 kb
Host smart-452b6232-490d-4489-837c-8997f6ad7d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19328
99984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1932899984
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3056408660
Short name T425
Test name
Test status
Simulation time 8372704805 ps
CPU time 7.47 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:28 PM PDT 24
Peak memory 202640 kb
Host smart-7c36fe4e-0bb4-4d0b-80bf-9235b4993156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
08660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3056408660
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3402536037
Short name T684
Test name
Test status
Simulation time 49953155 ps
CPU time 1.34 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:20 PM PDT 24
Peak memory 202620 kb
Host smart-f64fd6b4-1764-45ba-b43b-c48db5216f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
36037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3402536037
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1436016445
Short name T649
Test name
Test status
Simulation time 8455687464 ps
CPU time 7.52 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:26 PM PDT 24
Peak memory 202576 kb
Host smart-350bfc8f-f1f8-4530-8dde-b1d5189c1ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14360
16445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1436016445
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2600534858
Short name T750
Test name
Test status
Simulation time 8407803867 ps
CPU time 7.21 seconds
Started Mar 14 01:31:23 PM PDT 24
Finished Mar 14 01:31:31 PM PDT 24
Peak memory 202536 kb
Host smart-8bcc434c-317a-4a61-94d6-54a391bf821f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26005
34858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2600534858
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.61952665
Short name T702
Test name
Test status
Simulation time 8363838058 ps
CPU time 9.62 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:30 PM PDT 24
Peak memory 202556 kb
Host smart-d688211a-4606-4916-a1d9-739865778262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61952
665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.61952665
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4107952066
Short name T94
Test name
Test status
Simulation time 8416436185 ps
CPU time 8.21 seconds
Started Mar 14 01:31:23 PM PDT 24
Finished Mar 14 01:31:32 PM PDT 24
Peak memory 202540 kb
Host smart-89c06d49-abb6-48f8-b898-ad48ac3ff78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
52066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4107952066
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.603356032
Short name T607
Test name
Test status
Simulation time 8391872560 ps
CPU time 7.34 seconds
Started Mar 14 01:31:21 PM PDT 24
Finished Mar 14 01:31:29 PM PDT 24
Peak memory 202504 kb
Host smart-1d30fe54-8f38-494a-8714-abfdf3bd698d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60335
6032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.603356032
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.748391292
Short name T683
Test name
Test status
Simulation time 8402541401 ps
CPU time 7.62 seconds
Started Mar 14 01:31:19 PM PDT 24
Finished Mar 14 01:31:27 PM PDT 24
Peak memory 202532 kb
Host smart-f0bd2dd6-328b-4abb-8047-2327c4d95e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74839
1292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.748391292
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2332613899
Short name T490
Test name
Test status
Simulation time 20731042 ps
CPU time 0.65 seconds
Started Mar 14 01:31:18 PM PDT 24
Finished Mar 14 01:31:19 PM PDT 24
Peak memory 202468 kb
Host smart-486ea41c-b517-4fe8-8665-ccbcfef682e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23326
13899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2332613899
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3321955282
Short name T421
Test name
Test status
Simulation time 8405120515 ps
CPU time 10.16 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:30 PM PDT 24
Peak memory 202512 kb
Host smart-db3d4f59-c46a-454a-803e-7fba330bdb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33219
55282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3321955282
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.2021261913
Short name T499
Test name
Test status
Simulation time 8401498833 ps
CPU time 8.46 seconds
Started Mar 14 01:31:22 PM PDT 24
Finished Mar 14 01:31:30 PM PDT 24
Peak memory 202548 kb
Host smart-ccd84b51-f661-4c2f-95eb-eaa422ea8071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20212
61913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.2021261913
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2803349256
Short name T757
Test name
Test status
Simulation time 8361196745 ps
CPU time 8.32 seconds
Started Mar 14 01:31:23 PM PDT 24
Finished Mar 14 01:31:32 PM PDT 24
Peak memory 202536 kb
Host smart-bde9f2af-76b0-42f7-bbd1-b8a3a9b64eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
49256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2803349256
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3214606999
Short name T694
Test name
Test status
Simulation time 8478246070 ps
CPU time 7.49 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:27 PM PDT 24
Peak memory 202672 kb
Host smart-3e620c7b-66f5-43a0-afc6-067225b7ea1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146
06999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3214606999
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.818045833
Short name T430
Test name
Test status
Simulation time 8368859225 ps
CPU time 8.05 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:28 PM PDT 24
Peak memory 202584 kb
Host smart-b49e4802-1063-4715-a533-ce4e92e3b82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81804
5833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.818045833
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3568854396
Short name T373
Test name
Test status
Simulation time 192576456 ps
CPU time 2.19 seconds
Started Mar 14 01:31:20 PM PDT 24
Finished Mar 14 01:31:22 PM PDT 24
Peak memory 202740 kb
Host smart-23d96f9f-6bac-43c2-9488-3c85e18b29be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35688
54396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3568854396
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.257957142
Short name T162
Test name
Test status
Simulation time 8358912144 ps
CPU time 7.64 seconds
Started Mar 14 01:31:29 PM PDT 24
Finished Mar 14 01:31:37 PM PDT 24
Peak memory 202608 kb
Host smart-7bb78461-44c6-4c23-a725-a3bbf835ccc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25795
7142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.257957142
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1789252557
Short name T360
Test name
Test status
Simulation time 8456201637 ps
CPU time 7.65 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202516 kb
Host smart-400a50f3-fd56-44fc-9173-7fc4dacd3b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17892
52557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1789252557
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2266284879
Short name T325
Test name
Test status
Simulation time 8409166865 ps
CPU time 7.9 seconds
Started Mar 14 01:31:36 PM PDT 24
Finished Mar 14 01:31:44 PM PDT 24
Peak memory 202584 kb
Host smart-49d57d5a-4fbc-43d6-9b99-39909429b401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22662
84879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2266284879
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.721567833
Short name T446
Test name
Test status
Simulation time 8366785634 ps
CPU time 7.32 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202272 kb
Host smart-aacad3d0-ac2c-4009-9cd4-d346969fb83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72156
7833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.721567833
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1368591840
Short name T521
Test name
Test status
Simulation time 8417630983 ps
CPU time 10.36 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:44 PM PDT 24
Peak memory 202468 kb
Host smart-7692d8e5-0a6e-4b01-a629-d1828bfc55b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13685
91840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1368591840
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3145055025
Short name T537
Test name
Test status
Simulation time 8387479766 ps
CPU time 8.74 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202584 kb
Host smart-17688a4b-2c98-48b4-a5a6-e67de740cb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31450
55025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3145055025
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3806643236
Short name T213
Test name
Test status
Simulation time 8367773471 ps
CPU time 8.21 seconds
Started Mar 14 01:31:32 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202528 kb
Host smart-887005f4-2f83-4119-918d-e8c32a30912b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
43236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3806643236
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3331600370
Short name T396
Test name
Test status
Simulation time 30132597 ps
CPU time 0.62 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:32 PM PDT 24
Peak memory 202460 kb
Host smart-b1571d73-f466-47c5-9322-5b2b4b5e2a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33316
00370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3331600370
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.119957050
Short name T301
Test name
Test status
Simulation time 8403483448 ps
CPU time 7.43 seconds
Started Mar 14 01:31:32 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202520 kb
Host smart-d9d29a42-ab53-4e4e-8a1a-e975f00d9bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11995
7050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.119957050
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.2320250219
Short name T452
Test name
Test status
Simulation time 8381892617 ps
CPU time 8.58 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:40 PM PDT 24
Peak memory 202568 kb
Host smart-6d162b55-0881-4594-bf95-6485a54e0eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
50219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.2320250219
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3191055962
Short name T638
Test name
Test status
Simulation time 8358575135 ps
CPU time 7.47 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202528 kb
Host smart-4195dd4c-c7c8-415f-b7e0-8385aab3fa72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31910
55962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3191055962
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2184622749
Short name T133
Test name
Test status
Simulation time 8476385025 ps
CPU time 8 seconds
Started Mar 14 01:31:22 PM PDT 24
Finished Mar 14 01:31:30 PM PDT 24
Peak memory 202580 kb
Host smart-a7882086-64d2-434c-9425-5dc2db3d560d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
22749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2184622749
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3532055292
Short name T596
Test name
Test status
Simulation time 8372164711 ps
CPU time 8.05 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202576 kb
Host smart-cbde9c1d-722b-45a5-a26b-03bae65538d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35320
55292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3532055292
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2084900646
Short name T217
Test name
Test status
Simulation time 233583524 ps
CPU time 1.98 seconds
Started Mar 14 01:31:30 PM PDT 24
Finished Mar 14 01:31:32 PM PDT 24
Peak memory 202732 kb
Host smart-002eda0b-b718-412c-a513-4dd1010f92e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20849
00646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2084900646
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1469064407
Short name T168
Test name
Test status
Simulation time 8355273611 ps
CPU time 7.6 seconds
Started Mar 14 01:31:30 PM PDT 24
Finished Mar 14 01:31:38 PM PDT 24
Peak memory 202596 kb
Host smart-59150e1b-81ab-48fc-a0a4-756be021a2f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14690
64407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1469064407
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3687003161
Short name T29
Test name
Test status
Simulation time 8437578008 ps
CPU time 7.77 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202444 kb
Host smart-6f7d924e-abfe-4666-9363-3c91753eebec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36870
03161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3687003161
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.788616145
Short name T294
Test name
Test status
Simulation time 8405072369 ps
CPU time 7.23 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202468 kb
Host smart-54d4a4f8-4339-434f-95f7-c660ff65ed33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78861
6145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.788616145
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2708005675
Short name T516
Test name
Test status
Simulation time 8363853320 ps
CPU time 9.57 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:43 PM PDT 24
Peak memory 202468 kb
Host smart-0c0ed71f-eb95-42d8-8e69-4e6422e4a684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080
05675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2708005675
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1773949971
Short name T98
Test name
Test status
Simulation time 8390466853 ps
CPU time 7.27 seconds
Started Mar 14 01:31:32 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202576 kb
Host smart-75fcd49a-4c52-4651-a932-66da77c64377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
49971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1773949971
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2634587955
Short name T555
Test name
Test status
Simulation time 8394321190 ps
CPU time 7.47 seconds
Started Mar 14 01:31:32 PM PDT 24
Finished Mar 14 01:31:40 PM PDT 24
Peak memory 202584 kb
Host smart-dcb697f9-e43d-4f22-964f-99f558ad7c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26345
87955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2634587955
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.585830484
Short name T623
Test name
Test status
Simulation time 8384050488 ps
CPU time 7.8 seconds
Started Mar 14 01:31:32 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202532 kb
Host smart-4a9aa01e-6475-41d9-8520-cc53a3ac9374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58583
0484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.585830484
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1051821069
Short name T322
Test name
Test status
Simulation time 25278663 ps
CPU time 0.64 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:34 PM PDT 24
Peak memory 202440 kb
Host smart-53796037-a7a5-41c2-a3e6-15db2b188da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10518
21069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1051821069
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.631244896
Short name T559
Test name
Test status
Simulation time 8398882945 ps
CPU time 7.54 seconds
Started Mar 14 01:31:29 PM PDT 24
Finished Mar 14 01:31:37 PM PDT 24
Peak memory 202496 kb
Host smart-c517d684-7374-4428-8d33-1381b49aac7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63124
4896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.631244896
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.4040031916
Short name T296
Test name
Test status
Simulation time 8360038456 ps
CPU time 9.13 seconds
Started Mar 14 01:31:29 PM PDT 24
Finished Mar 14 01:31:38 PM PDT 24
Peak memory 202492 kb
Host smart-cbece04e-5752-42c2-ba0a-3f8f4b3a39f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40400
31916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.4040031916
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.720879463
Short name T14
Test name
Test status
Simulation time 8480992062 ps
CPU time 8.09 seconds
Started Mar 14 01:31:36 PM PDT 24
Finished Mar 14 01:31:44 PM PDT 24
Peak memory 202612 kb
Host smart-966380bf-838d-4b54-83fe-2ff97f7eb384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72087
9463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.720879463
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2930026665
Short name T576
Test name
Test status
Simulation time 8368684380 ps
CPU time 7.98 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202504 kb
Host smart-58145b11-9f5f-4138-af35-9c8a03ab41d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29300
26665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2930026665
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1389055667
Short name T203
Test name
Test status
Simulation time 159822054 ps
CPU time 1.57 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:16 PM PDT 24
Peak memory 202640 kb
Host smart-d41d6430-ac0f-4f16-a022-2f6502ad183a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890
55667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1389055667
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2025766329
Short name T155
Test name
Test status
Simulation time 8356113531 ps
CPU time 7.26 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 202536 kb
Host smart-239aa68d-3db6-4274-b880-d967dad8ad62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257
66329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2025766329
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.638646780
Short name T287
Test name
Test status
Simulation time 8409851857 ps
CPU time 7.48 seconds
Started Mar 14 01:30:15 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202500 kb
Host smart-91993543-7fc5-4d6a-bc9b-023c9578354b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63864
6780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.638646780
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3761196173
Short name T720
Test name
Test status
Simulation time 8411128198 ps
CPU time 7.59 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 202548 kb
Host smart-a29f6854-6621-446d-abe1-41921ff559c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37611
96173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3761196173
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2647722287
Short name T529
Test name
Test status
Simulation time 8366741113 ps
CPU time 7.37 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 202552 kb
Host smart-1332970b-ff8a-43a6-b64d-42e6c84edbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26477
22287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2647722287
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1247824974
Short name T92
Test name
Test status
Simulation time 8404339476 ps
CPU time 8.85 seconds
Started Mar 14 01:30:25 PM PDT 24
Finished Mar 14 01:30:34 PM PDT 24
Peak memory 202536 kb
Host smart-ae477aea-69bb-4fd3-85da-621ee762f7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12478
24974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1247824974
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1567803890
Short name T583
Test name
Test status
Simulation time 8371635810 ps
CPU time 7.61 seconds
Started Mar 14 01:30:16 PM PDT 24
Finished Mar 14 01:30:24 PM PDT 24
Peak memory 202572 kb
Host smart-be1c80a3-5d7e-4de3-98fb-820989d4cd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15678
03890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1567803890
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3644503913
Short name T500
Test name
Test status
Simulation time 8388094490 ps
CPU time 8.25 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202376 kb
Host smart-1d24bd4b-d9bc-4197-bf51-424d39c952ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36445
03913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3644503913
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3112733738
Short name T262
Test name
Test status
Simulation time 8445790481 ps
CPU time 8.22 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:37 PM PDT 24
Peak memory 202572 kb
Host smart-c7d6388e-9b60-493e-9622-805e288049f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31127
33738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3112733738
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.3743807125
Short name T595
Test name
Test status
Simulation time 8377749661 ps
CPU time 8.38 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202648 kb
Host smart-debc2dd6-eb60-4504-b888-2f9b94e20ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37438
07125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.3743807125
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1069638762
Short name T51
Test name
Test status
Simulation time 107618260 ps
CPU time 0.96 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:31 PM PDT 24
Peak memory 217796 kb
Host smart-f8a8bb6c-a85b-4083-b466-9f20c4ae1378
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1069638762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1069638762
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.686533564
Short name T709
Test name
Test status
Simulation time 8360860955 ps
CPU time 7.78 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:36 PM PDT 24
Peak memory 202560 kb
Host smart-c7d6b0be-12c2-4fb7-adee-33a6fbe12d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68653
3564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.686533564
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3126050219
Short name T584
Test name
Test status
Simulation time 8373211264 ps
CPU time 7.73 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202536 kb
Host smart-04951876-6782-40f7-baf1-58756ce2b7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31260
50219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3126050219
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1395509440
Short name T419
Test name
Test status
Simulation time 160685728 ps
CPU time 1.44 seconds
Started Mar 14 01:31:28 PM PDT 24
Finished Mar 14 01:31:30 PM PDT 24
Peak memory 202612 kb
Host smart-4b8bb06d-46ee-4aff-8165-ccacdda4b693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13955
09440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1395509440
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3923135867
Short name T402
Test name
Test status
Simulation time 8361330434 ps
CPU time 9.3 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202532 kb
Host smart-adabfb11-eb4a-48da-bde3-150f5656ff50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39231
35867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3923135867
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1737941021
Short name T331
Test name
Test status
Simulation time 8431718635 ps
CPU time 7.47 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202532 kb
Host smart-3d3559ba-3277-4372-84d0-9d0e0c561f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17379
41021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1737941021
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1784510983
Short name T66
Test name
Test status
Simulation time 8411670454 ps
CPU time 7.45 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202560 kb
Host smart-10f414f7-164a-47d5-a9a0-23f3ab76f48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17845
10983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1784510983
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3752692953
Short name T231
Test name
Test status
Simulation time 8364018885 ps
CPU time 7.74 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202560 kb
Host smart-0abc6a21-7c3e-4292-9db5-cfddb2a143ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37526
92953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3752692953
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.811715621
Short name T104
Test name
Test status
Simulation time 8445581803 ps
CPU time 7.2 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202304 kb
Host smart-25c359d8-733f-49b4-8a42-2c0cb864bc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81171
5621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.811715621
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2402513262
Short name T270
Test name
Test status
Simulation time 8398777494 ps
CPU time 8.46 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:40 PM PDT 24
Peak memory 202548 kb
Host smart-912a379b-53fa-4c34-b2b1-d449767b9fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24025
13262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2402513262
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.985872790
Short name T496
Test name
Test status
Simulation time 8367624809 ps
CPU time 9.16 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:44 PM PDT 24
Peak memory 202476 kb
Host smart-3099937a-7ef0-4ca4-b2a8-94c394a12bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98587
2790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.985872790
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3261921494
Short name T626
Test name
Test status
Simulation time 24602864 ps
CPU time 0.62 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:34 PM PDT 24
Peak memory 202496 kb
Host smart-92ef3f7c-899a-4588-9dd7-2786fe914630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32619
21494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3261921494
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.907225297
Short name T507
Test name
Test status
Simulation time 8445579437 ps
CPU time 7.16 seconds
Started Mar 14 01:31:30 PM PDT 24
Finished Mar 14 01:31:38 PM PDT 24
Peak memory 202544 kb
Host smart-9e3a41eb-5c2e-49ac-93f2-090b4e3c49dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90722
5297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.907225297
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.2842672883
Short name T571
Test name
Test status
Simulation time 8377665081 ps
CPU time 7.53 seconds
Started Mar 14 01:31:30 PM PDT 24
Finished Mar 14 01:31:38 PM PDT 24
Peak memory 202588 kb
Host smart-6e8a115b-b484-466b-b0e7-9f41e97e956d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28426
72883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.2842672883
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1847580180
Short name T535
Test name
Test status
Simulation time 8357295141 ps
CPU time 7.42 seconds
Started Mar 14 01:31:32 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202568 kb
Host smart-fecccb4b-a0db-40e6-9ab1-ce9cd93bec78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18475
80180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1847580180
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.4169063120
Short name T139
Test name
Test status
Simulation time 8477649259 ps
CPU time 8.49 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:40 PM PDT 24
Peak memory 202548 kb
Host smart-49ca9e72-ab88-425a-8951-5dd03de72057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41690
63120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.4169063120
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1887850358
Short name T519
Test name
Test status
Simulation time 8367424245 ps
CPU time 7.92 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202552 kb
Host smart-c42c1c76-cb8e-48d2-9e63-c37b38de6447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18878
50358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1887850358
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2276760028
Short name T707
Test name
Test status
Simulation time 184217727 ps
CPU time 2 seconds
Started Mar 14 01:31:36 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202584 kb
Host smart-12415506-dc6b-4b51-b1fa-9cb3a2652c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767
60028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2276760028
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2344563118
Short name T164
Test name
Test status
Simulation time 8356714566 ps
CPU time 8.05 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202508 kb
Host smart-ea8b8a07-3544-4ea3-a8c4-a97d8a454349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23445
63118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2344563118
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3688494870
Short name T109
Test name
Test status
Simulation time 8440879741 ps
CPU time 8.08 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202496 kb
Host smart-7f59afa6-592f-434b-b301-1c2939f5ccd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36884
94870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3688494870
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3981851307
Short name T460
Test name
Test status
Simulation time 8407769318 ps
CPU time 6.98 seconds
Started Mar 14 01:31:32 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202588 kb
Host smart-118f7ba1-c70b-4ce7-8d5b-c6f6a64a6c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
51307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3981851307
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2357148931
Short name T629
Test name
Test status
Simulation time 8365070866 ps
CPU time 7.42 seconds
Started Mar 14 01:31:38 PM PDT 24
Finished Mar 14 01:31:45 PM PDT 24
Peak memory 202536 kb
Host smart-a33c048c-0e1a-4133-be3b-5ae604d6cc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23571
48931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2357148931
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1878481851
Short name T81
Test name
Test status
Simulation time 8396981117 ps
CPU time 7.12 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202556 kb
Host smart-4739a9bf-8918-4c2a-aa55-fa608c3b8003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18784
81851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1878481851
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2789785052
Short name T341
Test name
Test status
Simulation time 8392175620 ps
CPU time 7.99 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:43 PM PDT 24
Peak memory 202572 kb
Host smart-fd360385-d686-4b4a-94ea-3d1165e8d45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27897
85052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2789785052
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1119105769
Short name T554
Test name
Test status
Simulation time 8395620695 ps
CPU time 7.36 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:43 PM PDT 24
Peak memory 202400 kb
Host smart-8430d306-8002-4aad-9520-08d69a7d0737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11191
05769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1119105769
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.406067898
Short name T492
Test name
Test status
Simulation time 28802982 ps
CPU time 0.69 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:36 PM PDT 24
Peak memory 202260 kb
Host smart-2e21f7a5-9871-4965-9c09-f4d7eb5ed0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40606
7898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.406067898
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.463199099
Short name T597
Test name
Test status
Simulation time 8407763325 ps
CPU time 7.12 seconds
Started Mar 14 01:31:37 PM PDT 24
Finished Mar 14 01:31:45 PM PDT 24
Peak memory 202548 kb
Host smart-ceeb4985-c4ac-4ef3-88f8-30ee2cf67a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46319
9099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.463199099
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.952700124
Short name T356
Test name
Test status
Simulation time 8393279487 ps
CPU time 7.59 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:43 PM PDT 24
Peak memory 202560 kb
Host smart-90539866-fce9-4e82-ba9f-f7fff35c1272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95270
0124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.952700124
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1071213895
Short name T633
Test name
Test status
Simulation time 8359643687 ps
CPU time 7.32 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202444 kb
Host smart-c9bdee53-8fd9-428c-b895-32531ef2e93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10712
13895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1071213895
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1778397789
Short name T659
Test name
Test status
Simulation time 8472655664 ps
CPU time 7.34 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202572 kb
Host smart-ff633f9a-e7cb-4268-91ff-0e7be60c7c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17783
97789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1778397789
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.2901683874
Short name T41
Test name
Test status
Simulation time 8367708069 ps
CPU time 7.73 seconds
Started Mar 14 01:31:36 PM PDT 24
Finished Mar 14 01:31:44 PM PDT 24
Peak memory 202248 kb
Host smart-344f7481-b2ff-48e5-9ecb-6098357e9280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29016
83874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2901683874
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.4220076967
Short name T475
Test name
Test status
Simulation time 268687275 ps
CPU time 2.13 seconds
Started Mar 14 01:31:37 PM PDT 24
Finished Mar 14 01:31:40 PM PDT 24
Peak memory 202664 kb
Host smart-77d0981e-1140-47b5-931c-9a92d97e6d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42200
76967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.4220076967
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2648481911
Short name T655
Test name
Test status
Simulation time 8357882394 ps
CPU time 7.42 seconds
Started Mar 14 01:31:39 PM PDT 24
Finished Mar 14 01:31:48 PM PDT 24
Peak memory 202520 kb
Host smart-13488944-5f72-4ea5-ad6e-5f524369ad69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26484
81911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2648481911
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.4250979219
Short name T508
Test name
Test status
Simulation time 8438689068 ps
CPU time 7.48 seconds
Started Mar 14 01:31:39 PM PDT 24
Finished Mar 14 01:31:48 PM PDT 24
Peak memory 202524 kb
Host smart-d5eddcb6-c32e-4d23-8cf3-d4b11e7d22c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42509
79219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.4250979219
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1138929084
Short name T636
Test name
Test status
Simulation time 8409373388 ps
CPU time 7.47 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202516 kb
Host smart-6db967c0-cb43-4614-a016-558c392f72b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11389
29084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1138929084
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3943609813
Short name T261
Test name
Test status
Simulation time 8361789534 ps
CPU time 7.9 seconds
Started Mar 14 01:31:36 PM PDT 24
Finished Mar 14 01:31:44 PM PDT 24
Peak memory 202228 kb
Host smart-b1ea80df-d874-4af4-9863-04013d99a5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39436
09813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3943609813
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1998130668
Short name T85
Test name
Test status
Simulation time 8408324147 ps
CPU time 8.6 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:43 PM PDT 24
Peak memory 202568 kb
Host smart-ad72067c-bd8d-4bce-a2ce-56898058dd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981
30668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1998130668
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2879875792
Short name T263
Test name
Test status
Simulation time 8386873327 ps
CPU time 7.14 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202548 kb
Host smart-b9a0f654-ba99-41f6-b3eb-3296eb59be09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28798
75792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2879875792
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2428689726
Short name T69
Test name
Test status
Simulation time 8380997377 ps
CPU time 9.92 seconds
Started Mar 14 01:31:39 PM PDT 24
Finished Mar 14 01:31:50 PM PDT 24
Peak memory 202548 kb
Host smart-86776ff5-7e0b-43dc-90ac-9eb7166e2a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24286
89726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2428689726
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3162938216
Short name T368
Test name
Test status
Simulation time 26291795 ps
CPU time 0.67 seconds
Started Mar 14 01:31:38 PM PDT 24
Finished Mar 14 01:31:39 PM PDT 24
Peak memory 202468 kb
Host smart-161dff55-cfdd-45c7-913c-dc5499eaa911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31629
38216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3162938216
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2191642607
Short name T566
Test name
Test status
Simulation time 8403493716 ps
CPU time 8.36 seconds
Started Mar 14 01:31:39 PM PDT 24
Finished Mar 14 01:31:48 PM PDT 24
Peak memory 202548 kb
Host smart-2e455596-4251-49a9-aa85-b1c0bb569453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
42607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2191642607
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.4262972957
Short name T504
Test name
Test status
Simulation time 8386908001 ps
CPU time 8.63 seconds
Started Mar 14 01:31:39 PM PDT 24
Finished Mar 14 01:31:49 PM PDT 24
Peak memory 202520 kb
Host smart-49e5722e-e4a0-4057-9f52-67ec3b9ad3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42629
72957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.4262972957
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1621323157
Short name T16
Test name
Test status
Simulation time 8361405155 ps
CPU time 6.96 seconds
Started Mar 14 01:31:40 PM PDT 24
Finished Mar 14 01:31:48 PM PDT 24
Peak memory 202520 kb
Host smart-bf19fc0d-3cc8-4873-ac0c-b5e41388a730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16213
23157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1621323157
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3741983539
Short name T599
Test name
Test status
Simulation time 8370653537 ps
CPU time 9.56 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:43 PM PDT 24
Peak memory 202532 kb
Host smart-c0105ee2-b4c7-4335-a97b-67dc2138e307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37419
83539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3741983539
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1045837724
Short name T45
Test name
Test status
Simulation time 65922833 ps
CPU time 1.82 seconds
Started Mar 14 01:31:32 PM PDT 24
Finished Mar 14 01:31:34 PM PDT 24
Peak memory 202660 kb
Host smart-50d2d54f-4135-42b2-850f-3797bd578a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
37724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1045837724
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3384652900
Short name T174
Test name
Test status
Simulation time 8355182301 ps
CPU time 7.54 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202600 kb
Host smart-9e8b7662-6633-4458-9641-c5cc3b76c410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33846
52900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3384652900
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3091813904
Short name T565
Test name
Test status
Simulation time 8457680136 ps
CPU time 7.84 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202564 kb
Host smart-19b2ee92-2335-4bd7-a075-e98ff9abbea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30918
13904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3091813904
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.296910469
Short name T293
Test name
Test status
Simulation time 8407893606 ps
CPU time 8.71 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202568 kb
Host smart-b665be4c-1a14-4745-8aad-29a97bb904cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29691
0469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.296910469
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3027560241
Short name T562
Test name
Test status
Simulation time 8361280157 ps
CPU time 7.1 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202532 kb
Host smart-94db2a6a-7926-4462-aa1e-a3e954595ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30275
60241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3027560241
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3728825737
Short name T285
Test name
Test status
Simulation time 8371541111 ps
CPU time 7.87 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202508 kb
Host smart-0aa46449-f4ea-46fa-b915-0379d485e96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37288
25737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3728825737
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.249487472
Short name T300
Test name
Test status
Simulation time 8364977772 ps
CPU time 7.26 seconds
Started Mar 14 01:31:35 PM PDT 24
Finished Mar 14 01:31:42 PM PDT 24
Peak memory 202568 kb
Host smart-31465c2a-058e-4b26-87a9-6e015812f0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24948
7472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.249487472
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.971884492
Short name T480
Test name
Test status
Simulation time 26170364 ps
CPU time 0.62 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:34 PM PDT 24
Peak memory 202436 kb
Host smart-fbf8f2f5-938e-4757-aa73-e5cee910b3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97188
4492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.971884492
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2206582426
Short name T399
Test name
Test status
Simulation time 8416198778 ps
CPU time 7.46 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202564 kb
Host smart-09d4ad88-22ff-4667-abec-0f8972a11e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22065
82426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2206582426
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.580126298
Short name T327
Test name
Test status
Simulation time 8384623643 ps
CPU time 7.13 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202308 kb
Host smart-354d5683-f859-42bf-b60f-0c2892913064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58012
6298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.580126298
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2854809269
Short name T501
Test name
Test status
Simulation time 8358731898 ps
CPU time 7.41 seconds
Started Mar 14 01:31:33 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202564 kb
Host smart-5a00fb44-95f7-4a6f-948b-97b392f67b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28548
09269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2854809269
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1978960947
Short name T224
Test name
Test status
Simulation time 8472978718 ps
CPU time 8.22 seconds
Started Mar 14 01:31:31 PM PDT 24
Finished Mar 14 01:31:40 PM PDT 24
Peak memory 202544 kb
Host smart-31ffd72d-7109-46e1-a623-5ac37714cbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19789
60947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1978960947
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1453080583
Short name T202
Test name
Test status
Simulation time 8369698871 ps
CPU time 7.43 seconds
Started Mar 14 01:31:34 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 202500 kb
Host smart-9d610d94-aac6-46af-bf38-61a386062119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14530
80583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1453080583
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3900659843
Short name T711
Test name
Test status
Simulation time 161152904 ps
CPU time 1.49 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:52 PM PDT 24
Peak memory 202220 kb
Host smart-0e60be8a-adc7-4579-ba10-6ddb89ef54a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39006
59843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3900659843
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3440778819
Short name T159
Test name
Test status
Simulation time 8363222908 ps
CPU time 7.17 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 202556 kb
Host smart-fe83f264-06ad-4c56-9502-5946b83c2696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34407
78819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3440778819
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1332350493
Short name T8
Test name
Test status
Simulation time 8451367661 ps
CPU time 8.24 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:01 PM PDT 24
Peak memory 202468 kb
Host smart-62bbbf64-14e8-4edb-b44a-0c907600a771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13323
50493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1332350493
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.901678385
Short name T530
Test name
Test status
Simulation time 8406706343 ps
CPU time 9.37 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:32:04 PM PDT 24
Peak memory 202532 kb
Host smart-b7c7e26c-8cc2-42ad-b134-c37253030f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90167
8385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.901678385
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3391169030
Short name T464
Test name
Test status
Simulation time 8364337949 ps
CPU time 7.34 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 202548 kb
Host smart-89d6ffa5-b012-42c4-aca3-8b91d7d02800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33911
69030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3391169030
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2718191407
Short name T258
Test name
Test status
Simulation time 8403659782 ps
CPU time 8.72 seconds
Started Mar 14 01:31:48 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202568 kb
Host smart-91794f37-91ae-4476-96c8-05a440ffb790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27181
91407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2718191407
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2249004490
Short name T345
Test name
Test status
Simulation time 8388556840 ps
CPU time 8.31 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202140 kb
Host smart-961c498b-4c1a-42e7-a114-38aeab6294df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
04490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2249004490
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3468434350
Short name T126
Test name
Test status
Simulation time 8408487504 ps
CPU time 7.88 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:00 PM PDT 24
Peak memory 202344 kb
Host smart-2cff37fc-7674-4b6f-9987-320ae1918561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34684
34350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3468434350
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.927970559
Short name T557
Test name
Test status
Simulation time 8374851903 ps
CPU time 7.4 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:00 PM PDT 24
Peak memory 202464 kb
Host smart-6dca6ca7-14dd-450a-85db-1bb9a68f7ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92797
0559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.927970559
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2330313698
Short name T744
Test name
Test status
Simulation time 8361762372 ps
CPU time 8.85 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:01 PM PDT 24
Peak memory 202464 kb
Host smart-9647c6d9-523b-45e5-aff0-ded72ea08916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
13698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2330313698
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3618727693
Short name T379
Test name
Test status
Simulation time 8368115322 ps
CPU time 7.54 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202552 kb
Host smart-1b2fd06d-a90c-444b-b34c-92ff9a553a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36187
27693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3618727693
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2518956745
Short name T23
Test name
Test status
Simulation time 8356566914 ps
CPU time 8.3 seconds
Started Mar 14 01:31:48 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202532 kb
Host smart-39a57019-9809-4725-8425-5a40a49b45c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25189
56745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2518956745
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2369368150
Short name T598
Test name
Test status
Simulation time 8388365692 ps
CPU time 7.86 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:32:02 PM PDT 24
Peak memory 202524 kb
Host smart-4f1de537-cf1a-46a7-aed4-377542aef1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23693
68150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2369368150
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3249249488
Short name T580
Test name
Test status
Simulation time 8410920585 ps
CPU time 7.86 seconds
Started Mar 14 01:31:49 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202584 kb
Host smart-798e36f1-7236-4835-a681-755f31746316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32492
49488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3249249488
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3921786452
Short name T283
Test name
Test status
Simulation time 8368460578 ps
CPU time 7.24 seconds
Started Mar 14 01:31:58 PM PDT 24
Finished Mar 14 01:32:05 PM PDT 24
Peak memory 202584 kb
Host smart-d98df6b7-5839-4d3d-bac4-5f623222246d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39217
86452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3921786452
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2894462123
Short name T472
Test name
Test status
Simulation time 8398645907 ps
CPU time 7.56 seconds
Started Mar 14 01:31:48 PM PDT 24
Finished Mar 14 01:31:56 PM PDT 24
Peak memory 202516 kb
Host smart-b4b1ceac-0e8e-4b7f-aed4-5957a2bac176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28944
62123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2894462123
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2529771281
Short name T397
Test name
Test status
Simulation time 8403579459 ps
CPU time 7.69 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:00 PM PDT 24
Peak memory 202596 kb
Host smart-94a71d1b-edf1-432e-a2b1-6a0858f71b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25297
71281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2529771281
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3075572568
Short name T359
Test name
Test status
Simulation time 29954758 ps
CPU time 0.65 seconds
Started Mar 14 01:31:56 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202440 kb
Host smart-1eac3ca1-7e18-41e7-a600-2aeda070d3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30755
72568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3075572568
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2950226640
Short name T724
Test name
Test status
Simulation time 8455878145 ps
CPU time 7.61 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:58 PM PDT 24
Peak memory 202548 kb
Host smart-1a2b147f-5d3d-4645-b881-5cd2f92b523f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29502
26640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2950226640
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.241458245
Short name T223
Test name
Test status
Simulation time 8388884695 ps
CPU time 7.16 seconds
Started Mar 14 01:31:53 PM PDT 24
Finished Mar 14 01:32:01 PM PDT 24
Peak memory 202552 kb
Host smart-fc1c7c6e-ed5f-466f-b851-3b861e89d087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24145
8245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.241458245
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1579009528
Short name T330
Test name
Test status
Simulation time 8361473401 ps
CPU time 8.07 seconds
Started Mar 14 01:31:53 PM PDT 24
Finished Mar 14 01:32:02 PM PDT 24
Peak memory 202540 kb
Host smart-b707a2f0-9138-4614-9855-f31fe00ac833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15790
09528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1579009528
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1493428770
Short name T141
Test name
Test status
Simulation time 8468368218 ps
CPU time 7.39 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 202640 kb
Host smart-dda44374-14fe-411e-80cf-496381f64ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14934
28770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1493428770
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2621449813
Short name T612
Test name
Test status
Simulation time 8371842919 ps
CPU time 7.83 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202572 kb
Host smart-6a3945ae-1701-4b3b-8b8d-0a3fa18d2d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26214
49813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2621449813
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3711581209
Short name T394
Test name
Test status
Simulation time 253835630 ps
CPU time 2.01 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:31:54 PM PDT 24
Peak memory 202508 kb
Host smart-99ee9b4e-5c10-41a6-8035-57e8082c361b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
81209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3711581209
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3386959301
Short name T289
Test name
Test status
Simulation time 8361669465 ps
CPU time 7.57 seconds
Started Mar 14 01:31:49 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202520 kb
Host smart-0fa55207-5839-4f46-907e-a39720c2fee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33869
59301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3386959301
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2083730961
Short name T539
Test name
Test status
Simulation time 8457614652 ps
CPU time 9.85 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:05 PM PDT 24
Peak memory 202572 kb
Host smart-495c4d35-bb15-4daf-b773-bf25356dc58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20837
30961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2083730961
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.294797018
Short name T404
Test name
Test status
Simulation time 8408619980 ps
CPU time 7.66 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202456 kb
Host smart-5fcba8e1-8258-4cad-bbfb-7aba40ac44aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29479
7018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.294797018
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1209250355
Short name T268
Test name
Test status
Simulation time 8363636792 ps
CPU time 7.79 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202468 kb
Host smart-e42919a3-de52-463b-9424-4704e17db200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
50355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1209250355
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2468664383
Short name T95
Test name
Test status
Simulation time 8412616230 ps
CPU time 8.03 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202552 kb
Host smart-eacc01bb-c12c-4563-a757-3d3b9da8ee41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24686
64383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2468664383
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.4259153418
Short name T320
Test name
Test status
Simulation time 8370022188 ps
CPU time 8.06 seconds
Started Mar 14 01:31:58 PM PDT 24
Finished Mar 14 01:32:06 PM PDT 24
Peak memory 202584 kb
Host smart-5cf33a23-69c6-4961-84aa-59a9889a8569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42591
53418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.4259153418
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.4216814742
Short name T440
Test name
Test status
Simulation time 8388969925 ps
CPU time 7.42 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:00 PM PDT 24
Peak memory 202620 kb
Host smart-9a3c7f03-9250-4ff2-bbf5-9669635d14fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42168
14742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.4216814742
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1038837871
Short name T415
Test name
Test status
Simulation time 27711783 ps
CPU time 0.63 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:31:54 PM PDT 24
Peak memory 202468 kb
Host smart-44d7dd10-67dc-4646-a818-95dff7b84688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10388
37871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1038837871
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.4045843417
Short name T740
Test name
Test status
Simulation time 8414346864 ps
CPU time 7.94 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202556 kb
Host smart-3b28e61a-0de4-4765-821d-8d8722ebb9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40458
43417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.4045843417
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.1389892237
Short name T737
Test name
Test status
Simulation time 8392103197 ps
CPU time 7.76 seconds
Started Mar 14 01:31:51 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202596 kb
Host smart-72ed8533-6669-4993-b068-7010a8841f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13898
92237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.1389892237
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.48589029
Short name T741
Test name
Test status
Simulation time 8354206823 ps
CPU time 8.19 seconds
Started Mar 14 01:31:56 PM PDT 24
Finished Mar 14 01:32:05 PM PDT 24
Peak memory 202568 kb
Host smart-a84c930a-021b-4fef-bb44-308a7634fdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48589
029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.48589029
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3902460708
Short name T153
Test name
Test status
Simulation time 8472293676 ps
CPU time 8.64 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 202564 kb
Host smart-2fb7e3dd-e15e-48d1-aba8-bfeace3913b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39024
60708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3902460708
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3378040247
Short name T448
Test name
Test status
Simulation time 8367368284 ps
CPU time 8.66 seconds
Started Mar 14 01:31:49 PM PDT 24
Finished Mar 14 01:31:58 PM PDT 24
Peak memory 202600 kb
Host smart-e04f59cd-fb5e-462e-9b83-0fba4bbb80cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33780
40247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3378040247
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2387879401
Short name T727
Test name
Test status
Simulation time 137750071 ps
CPU time 1.7 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:31:56 PM PDT 24
Peak memory 202640 kb
Host smart-0e3f3686-fbe4-459b-abb7-c2bdfcec4321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
79401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2387879401
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2875597927
Short name T177
Test name
Test status
Simulation time 8357924654 ps
CPU time 7.32 seconds
Started Mar 14 01:31:56 PM PDT 24
Finished Mar 14 01:32:04 PM PDT 24
Peak memory 202524 kb
Host smart-1afa9d87-fb82-42a6-a524-47f6c7fc18a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
97927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2875597927
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.381681551
Short name T611
Test name
Test status
Simulation time 8400691150 ps
CPU time 8.41 seconds
Started Mar 14 01:31:50 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202512 kb
Host smart-090f75bf-7848-4cc9-981b-77b59f604b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38168
1551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.381681551
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.225979683
Short name T488
Test name
Test status
Simulation time 8406719021 ps
CPU time 8.21 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:01 PM PDT 24
Peak memory 202552 kb
Host smart-6e4db086-7484-4484-8f70-cf9eacd9c955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22597
9683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.225979683
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.4042162826
Short name T570
Test name
Test status
Simulation time 8360010631 ps
CPU time 7.32 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:02 PM PDT 24
Peak memory 202564 kb
Host smart-5a874db1-6ac5-40f4-acda-be6e81a0c3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40421
62826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.4042162826
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.335046855
Short name T671
Test name
Test status
Simulation time 8377482207 ps
CPU time 7.63 seconds
Started Mar 14 01:31:53 PM PDT 24
Finished Mar 14 01:32:01 PM PDT 24
Peak memory 202448 kb
Host smart-1899e27b-17ae-4990-b148-ac2ddc268b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33504
6855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.335046855
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.977370139
Short name T403
Test name
Test status
Simulation time 8386890594 ps
CPU time 7.52 seconds
Started Mar 14 01:31:49 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202544 kb
Host smart-c5778961-6bec-4e2e-b4cc-c041adca942d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97737
0139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.977370139
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3637464685
Short name T761
Test name
Test status
Simulation time 8390091112 ps
CPU time 7.3 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 202552 kb
Host smart-3f99dd0f-3b6a-4ab8-8803-5a84b5f2d9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36374
64685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3637464685
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1290787769
Short name T710
Test name
Test status
Simulation time 26324242 ps
CPU time 0.66 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:31:56 PM PDT 24
Peak memory 202408 kb
Host smart-acfd7623-380a-4d4d-bdb2-1ec89c2ee013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12907
87769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1290787769
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3068049943
Short name T130
Test name
Test status
Simulation time 8417773877 ps
CPU time 9.34 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:02 PM PDT 24
Peak memory 202512 kb
Host smart-52132bfe-9cec-4699-8953-6cb8b5f2291e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30680
49943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3068049943
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.3208797472
Short name T477
Test name
Test status
Simulation time 8385509972 ps
CPU time 7.58 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 202584 kb
Host smart-5f97293f-f5dc-4b9d-989b-958e51955560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32087
97472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.3208797472
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3622630803
Short name T318
Test name
Test status
Simulation time 8361821123 ps
CPU time 7.4 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:32:00 PM PDT 24
Peak memory 202424 kb
Host smart-106e3edc-7f96-4fd2-af22-9dd8f915deef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
30803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3622630803
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2140147015
Short name T486
Test name
Test status
Simulation time 8473863999 ps
CPU time 7.49 seconds
Started Mar 14 01:31:59 PM PDT 24
Finished Mar 14 01:32:06 PM PDT 24
Peak memory 202612 kb
Host smart-b9ee9853-82ab-4cbd-8c72-4c615b138ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21401
47015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2140147015
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.4114106465
Short name T389
Test name
Test status
Simulation time 8374199305 ps
CPU time 9.71 seconds
Started Mar 14 01:31:49 PM PDT 24
Finished Mar 14 01:31:59 PM PDT 24
Peak memory 202572 kb
Host smart-30cab7ee-5c9f-4a5a-9ea6-3aff5e9f9d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41141
06465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.4114106465
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.411708998
Short name T618
Test name
Test status
Simulation time 79931771 ps
CPU time 1.13 seconds
Started Mar 14 01:31:52 PM PDT 24
Finished Mar 14 01:31:54 PM PDT 24
Peak memory 202740 kb
Host smart-686d2a3c-4ebc-462a-9194-c1f4fda86072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41170
8998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.411708998
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1793115746
Short name T161
Test name
Test status
Simulation time 8357661073 ps
CPU time 7.79 seconds
Started Mar 14 01:31:49 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202784 kb
Host smart-0e6f2c9c-f63c-4938-99f7-ddbfb59b77d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17931
15746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1793115746
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.461540375
Short name T119
Test name
Test status
Simulation time 8449347524 ps
CPU time 8.26 seconds
Started Mar 14 01:31:57 PM PDT 24
Finished Mar 14 01:32:05 PM PDT 24
Peak memory 202416 kb
Host smart-249e200c-f627-4c50-aab6-f473d4673b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46154
0375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.461540375
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3951692605
Short name T337
Test name
Test status
Simulation time 8404977506 ps
CPU time 8.64 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 202596 kb
Host smart-b4b904a9-c25e-48fa-ad10-06b6d3eb8906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39516
92605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3951692605
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3572511575
Short name T685
Test name
Test status
Simulation time 8367242767 ps
CPU time 7.36 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:32:02 PM PDT 24
Peak memory 202488 kb
Host smart-dc4c4f59-f244-41fe-8cbf-d78c6202d8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35725
11575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3572511575
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.640290781
Short name T627
Test name
Test status
Simulation time 8384106385 ps
CPU time 7.76 seconds
Started Mar 14 01:31:58 PM PDT 24
Finished Mar 14 01:32:06 PM PDT 24
Peak memory 202580 kb
Host smart-2d6eb9f7-e11f-42e1-8a10-d6a58c9b241d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64029
0781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.640290781
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3184615874
Short name T664
Test name
Test status
Simulation time 8379829871 ps
CPU time 7.29 seconds
Started Mar 14 01:31:54 PM PDT 24
Finished Mar 14 01:32:02 PM PDT 24
Peak memory 202596 kb
Host smart-43f7ff95-c169-4016-9b6b-5589798be30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31846
15874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3184615874
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2963895484
Short name T210
Test name
Test status
Simulation time 28570496 ps
CPU time 0.66 seconds
Started Mar 14 01:31:57 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202468 kb
Host smart-e1e69e50-84e2-48c0-8f37-37c4340772d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29638
95484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2963895484
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.991921393
Short name T406
Test name
Test status
Simulation time 8417410365 ps
CPU time 9.28 seconds
Started Mar 14 01:31:58 PM PDT 24
Finished Mar 14 01:32:08 PM PDT 24
Peak memory 202552 kb
Host smart-b8805387-f5a0-433a-9220-5167f891b901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99192
1393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.991921393
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.410388600
Short name T726
Test name
Test status
Simulation time 8374231305 ps
CPU time 7.78 seconds
Started Mar 14 01:31:57 PM PDT 24
Finished Mar 14 01:32:05 PM PDT 24
Peak memory 202512 kb
Host smart-e037711e-2737-4fdc-9587-fe1c74fb2b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41038
8600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.410388600
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1046202282
Short name T371
Test name
Test status
Simulation time 8358855184 ps
CPU time 7.2 seconds
Started Mar 14 01:31:58 PM PDT 24
Finished Mar 14 01:32:05 PM PDT 24
Peak memory 202584 kb
Host smart-64a557f0-450d-44f6-89c9-c41aa075f7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10462
02282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1046202282
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3781056985
Short name T146
Test name
Test status
Simulation time 8475393526 ps
CPU time 7.52 seconds
Started Mar 14 01:31:50 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 202572 kb
Host smart-5bd91c62-2acf-4a7d-9768-26480395ced9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37810
56985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3781056985
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2424657706
Short name T378
Test name
Test status
Simulation time 8369147217 ps
CPU time 7.78 seconds
Started Mar 14 01:32:07 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202568 kb
Host smart-853968e3-45b5-4714-84e5-e595d1bbb124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24246
57706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2424657706
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3205652991
Short name T10
Test name
Test status
Simulation time 64143909 ps
CPU time 1.66 seconds
Started Mar 14 01:32:04 PM PDT 24
Finished Mar 14 01:32:08 PM PDT 24
Peak memory 202708 kb
Host smart-8d514456-e7a1-4ebf-9097-71691f1c7ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32056
52991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3205652991
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3076334893
Short name T173
Test name
Test status
Simulation time 8355705327 ps
CPU time 7.34 seconds
Started Mar 14 01:32:04 PM PDT 24
Finished Mar 14 01:32:13 PM PDT 24
Peak memory 202528 kb
Host smart-38652797-a783-44c6-8a7a-15a002738b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30763
34893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3076334893
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3059084017
Short name T471
Test name
Test status
Simulation time 8432544858 ps
CPU time 7.24 seconds
Started Mar 14 01:32:06 PM PDT 24
Finished Mar 14 01:32:14 PM PDT 24
Peak memory 202492 kb
Host smart-249b58ee-f5d6-4185-a785-3fe2bc2593fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30590
84017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3059084017
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1813044888
Short name T365
Test name
Test status
Simulation time 8408784930 ps
CPU time 7.49 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202532 kb
Host smart-a5d16728-b59b-4678-a118-079a4bbe200e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130
44888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1813044888
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1964834007
Short name T214
Test name
Test status
Simulation time 8366978817 ps
CPU time 7.49 seconds
Started Mar 14 01:32:04 PM PDT 24
Finished Mar 14 01:32:13 PM PDT 24
Peak memory 202576 kb
Host smart-0b6e6f2d-7e39-47b2-9d30-a2393877f9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19648
34007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1964834007
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.731811524
Short name T594
Test name
Test status
Simulation time 8422433394 ps
CPU time 8.47 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:20 PM PDT 24
Peak memory 202492 kb
Host smart-93aabe59-0a27-4aac-8bb6-11af70ecc77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73181
1524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.731811524
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1374800671
Short name T643
Test name
Test status
Simulation time 8387706935 ps
CPU time 7.2 seconds
Started Mar 14 01:32:12 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202516 kb
Host smart-86efa53d-d9e8-4dd5-a84b-ef5a91239b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13748
00671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1374800671
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3948484305
Short name T281
Test name
Test status
Simulation time 8370323634 ps
CPU time 7.44 seconds
Started Mar 14 01:32:08 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202560 kb
Host smart-ad592a80-7101-4e87-bb9e-65d12a3d0b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39484
84305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3948484305
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2871066576
Short name T351
Test name
Test status
Simulation time 24877618 ps
CPU time 0.65 seconds
Started Mar 14 01:32:09 PM PDT 24
Finished Mar 14 01:32:10 PM PDT 24
Peak memory 202556 kb
Host smart-0692b737-fe96-4cd0-b35b-7773239a6f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28710
66576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2871066576
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1423895066
Short name T646
Test name
Test status
Simulation time 8418222698 ps
CPU time 7.79 seconds
Started Mar 14 01:32:07 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202580 kb
Host smart-a47c4667-7342-46f4-a109-5aa04a834125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14238
95066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1423895066
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1933104700
Short name T568
Test name
Test status
Simulation time 8394640509 ps
CPU time 7.38 seconds
Started Mar 14 01:32:09 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202648 kb
Host smart-b05b3ad0-cba9-4ee9-b938-8aa1fe08994f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19331
04700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1933104700
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3162165292
Short name T748
Test name
Test status
Simulation time 8360504043 ps
CPU time 7.47 seconds
Started Mar 14 01:32:08 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202596 kb
Host smart-9a022d7d-fa4a-4183-91a9-962562d908e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31621
65292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3162165292
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2597221192
Short name T502
Test name
Test status
Simulation time 8479730128 ps
CPU time 8.08 seconds
Started Mar 14 01:31:55 PM PDT 24
Finished Mar 14 01:32:04 PM PDT 24
Peak memory 202580 kb
Host smart-986f8236-fa61-47c8-9d2f-f4a49d8a8b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25972
21192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2597221192
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1541981894
Short name T637
Test name
Test status
Simulation time 8367858055 ps
CPU time 7.51 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:36 PM PDT 24
Peak memory 202592 kb
Host smart-fdc282b7-4f64-4a10-aa02-ece551ce5909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15419
81894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1541981894
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3771786236
Short name T67
Test name
Test status
Simulation time 39629459 ps
CPU time 1.05 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:27 PM PDT 24
Peak memory 202740 kb
Host smart-287a2f90-28f5-423e-96e3-4cd55f578bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37717
86236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3771786236
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2861807044
Short name T167
Test name
Test status
Simulation time 8356175954 ps
CPU time 7.18 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:33 PM PDT 24
Peak memory 202584 kb
Host smart-cbfb6111-95ae-4d3a-a721-4c500da76d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
07044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2861807044
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1931695389
Short name T592
Test name
Test status
Simulation time 8406482620 ps
CPU time 7.49 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202532 kb
Host smart-1a8d9257-097c-4124-96c4-199c4efb07fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19316
95389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1931695389
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4017858823
Short name T661
Test name
Test status
Simulation time 8366641233 ps
CPU time 8.62 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:37 PM PDT 24
Peak memory 202540 kb
Host smart-17a6e589-3fa6-4137-b9eb-842c47a3d7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40178
58823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4017858823
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3871957073
Short name T558
Test name
Test status
Simulation time 8432623161 ps
CPU time 8.71 seconds
Started Mar 14 01:30:35 PM PDT 24
Finished Mar 14 01:30:45 PM PDT 24
Peak memory 202580 kb
Host smart-5c01275c-4446-413e-9300-9b3d5f48a9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38719
57073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3871957073
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2952561929
Short name T654
Test name
Test status
Simulation time 8404430835 ps
CPU time 8.12 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:34 PM PDT 24
Peak memory 202524 kb
Host smart-0073cde7-3154-4ebe-b8bd-b5d1ea7e4245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29525
61929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2952561929
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3285845604
Short name T336
Test name
Test status
Simulation time 8403674755 ps
CPU time 7.33 seconds
Started Mar 14 01:30:30 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202552 kb
Host smart-60441c50-72bb-43d3-bdb5-5ffc877237dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32858
45604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3285845604
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2861373589
Short name T333
Test name
Test status
Simulation time 28168761 ps
CPU time 0.63 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:28 PM PDT 24
Peak memory 202448 kb
Host smart-9c2f0ad0-e9ca-4232-aeec-da372a16c98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28613
73589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2861373589
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2627030643
Short name T634
Test name
Test status
Simulation time 8402994594 ps
CPU time 7.4 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:34 PM PDT 24
Peak memory 202540 kb
Host smart-b7f41491-b8b6-4990-bbcd-fb5a517bfd94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26270
30643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2627030643
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.2797881053
Short name T481
Test name
Test status
Simulation time 8371707862 ps
CPU time 7.67 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202552 kb
Host smart-1bbd1b6c-0293-41e1-a57f-c4622908fc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27978
81053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.2797881053
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1062315453
Short name T405
Test name
Test status
Simulation time 8362538001 ps
CPU time 7.67 seconds
Started Mar 14 01:30:36 PM PDT 24
Finished Mar 14 01:30:45 PM PDT 24
Peak memory 202560 kb
Host smart-2dbc78c2-aba5-4d40-a725-5973aab395a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10623
15453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1062315453
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.623892479
Short name T450
Test name
Test status
Simulation time 8478956790 ps
CPU time 7.37 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202412 kb
Host smart-315e7bdd-973a-4afc-8449-96351ae30e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62389
2479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.623892479
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.820561494
Short name T690
Test name
Test status
Simulation time 8373515933 ps
CPU time 7.52 seconds
Started Mar 14 01:32:07 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202512 kb
Host smart-4b187f96-579f-4fc3-8d01-20ebac73585a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82056
1494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.820561494
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3919361329
Short name T361
Test name
Test status
Simulation time 75230001 ps
CPU time 1.94 seconds
Started Mar 14 01:32:04 PM PDT 24
Finished Mar 14 01:32:06 PM PDT 24
Peak memory 202700 kb
Host smart-d7707288-a1c3-4c8d-a79b-839db23a2e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39193
61329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3919361329
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3213780757
Short name T156
Test name
Test status
Simulation time 8363676446 ps
CPU time 7.77 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202484 kb
Host smart-1dd47570-1009-4716-9d04-093b63809518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32137
80757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3213780757
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.992439617
Short name T451
Test name
Test status
Simulation time 8439011008 ps
CPU time 7.82 seconds
Started Mar 14 01:32:12 PM PDT 24
Finished Mar 14 01:32:20 PM PDT 24
Peak memory 202516 kb
Host smart-63707bba-b743-4f29-870f-db620e7996dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99243
9617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.992439617
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.966404325
Short name T497
Test name
Test status
Simulation time 8409526476 ps
CPU time 9.34 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 202552 kb
Host smart-0784335a-cc02-45ea-bde1-166c124d0b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96640
4325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.966404325
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1613986579
Short name T400
Test name
Test status
Simulation time 8366579080 ps
CPU time 8.43 seconds
Started Mar 14 01:32:03 PM PDT 24
Finished Mar 14 01:32:12 PM PDT 24
Peak memory 202472 kb
Host smart-1004eb01-7f73-429b-8ade-12b2149b772a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16139
86579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1613986579
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2929794918
Short name T662
Test name
Test status
Simulation time 8382248592 ps
CPU time 7.65 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202564 kb
Host smart-6467d07f-ab27-45b8-9e48-d8dd42c8e8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29297
94918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2929794918
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3334343350
Short name T303
Test name
Test status
Simulation time 8394148893 ps
CPU time 7.37 seconds
Started Mar 14 01:32:09 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202508 kb
Host smart-c52ff891-d37a-410d-884a-33f9a88e4cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33343
43350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3334343350
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1984182221
Short name T489
Test name
Test status
Simulation time 29485647 ps
CPU time 0.64 seconds
Started Mar 14 01:32:09 PM PDT 24
Finished Mar 14 01:32:10 PM PDT 24
Peak memory 202416 kb
Host smart-5d6032ea-7a86-4381-9411-d176f33239ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19841
82221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1984182221
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1278262340
Short name T117
Test name
Test status
Simulation time 8405650816 ps
CPU time 7.05 seconds
Started Mar 14 01:32:10 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202548 kb
Host smart-54efe0dc-cd4d-463b-9d64-d3278a20a4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12782
62340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1278262340
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3888605366
Short name T719
Test name
Test status
Simulation time 8403900549 ps
CPU time 8.46 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:14 PM PDT 24
Peak memory 202556 kb
Host smart-1492b204-a879-40aa-b3b0-13ab07d9a8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38886
05366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3888605366
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.813260208
Short name T526
Test name
Test status
Simulation time 8358839045 ps
CPU time 10.04 seconds
Started Mar 14 01:32:07 PM PDT 24
Finished Mar 14 01:32:18 PM PDT 24
Peak memory 202564 kb
Host smart-22d96ed4-8dc3-4d21-9deb-67465d5e37fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81326
0208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.813260208
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.268877993
Short name T121
Test name
Test status
Simulation time 8480322833 ps
CPU time 7.47 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:14 PM PDT 24
Peak memory 202616 kb
Host smart-77b21e9e-fb6b-4188-a3d4-eceeae0ec286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26887
7993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.268877993
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1371259854
Short name T423
Test name
Test status
Simulation time 8365129436 ps
CPU time 7.49 seconds
Started Mar 14 01:32:07 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202580 kb
Host smart-5d3e038d-32f4-4ea6-a938-88622b344b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13712
59854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1371259854
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.860209127
Short name T290
Test name
Test status
Simulation time 209608158 ps
CPU time 2.17 seconds
Started Mar 14 01:32:07 PM PDT 24
Finished Mar 14 01:32:10 PM PDT 24
Peak memory 202588 kb
Host smart-f62872a7-24b7-47a9-8a5b-274b8992a6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86020
9127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.860209127
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3073924967
Short name T2
Test name
Test status
Simulation time 8356645363 ps
CPU time 7.05 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:13 PM PDT 24
Peak memory 202544 kb
Host smart-69050ceb-63f5-402d-85af-b67e17a0badc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30739
24967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3073924967
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4169782023
Short name T732
Test name
Test status
Simulation time 8371890811 ps
CPU time 9.48 seconds
Started Mar 14 01:32:08 PM PDT 24
Finished Mar 14 01:32:18 PM PDT 24
Peak memory 202468 kb
Host smart-e3288770-f747-4707-bbeb-a0257adb3ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41697
82023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4169782023
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2419703048
Short name T672
Test name
Test status
Simulation time 8410386658 ps
CPU time 7.31 seconds
Started Mar 14 01:32:04 PM PDT 24
Finished Mar 14 01:32:13 PM PDT 24
Peak memory 202508 kb
Host smart-788c2fb9-cbaa-403e-8dd0-7c6e52ebcf40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24197
03048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2419703048
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3575964763
Short name T304
Test name
Test status
Simulation time 8368595153 ps
CPU time 10.12 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202552 kb
Host smart-2ae5af76-bf72-4dd6-807e-b216f2f1238b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
64763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3575964763
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.727942299
Short name T86
Test name
Test status
Simulation time 8429286216 ps
CPU time 8.92 seconds
Started Mar 14 01:32:08 PM PDT 24
Finished Mar 14 01:32:18 PM PDT 24
Peak memory 202556 kb
Host smart-c177901b-1cdb-474e-9c6a-d851de9d8c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72794
2299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.727942299
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.496731267
Short name T548
Test name
Test status
Simulation time 8391854493 ps
CPU time 7.62 seconds
Started Mar 14 01:32:14 PM PDT 24
Finished Mar 14 01:32:22 PM PDT 24
Peak memory 202560 kb
Host smart-a09e85b1-4fd8-4cfb-b6b5-312aeb899c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49673
1267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.496731267
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3123816830
Short name T593
Test name
Test status
Simulation time 8373062659 ps
CPU time 8.19 seconds
Started Mar 14 01:32:08 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202592 kb
Host smart-ec1c7e32-a35b-4794-b5d5-6e664ad7b172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31238
16830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3123816830
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.492582322
Short name T621
Test name
Test status
Simulation time 22615705 ps
CPU time 0.63 seconds
Started Mar 14 01:32:04 PM PDT 24
Finished Mar 14 01:32:06 PM PDT 24
Peak memory 202496 kb
Host smart-f432e955-714d-4229-9f37-8e5addf85453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49258
2322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.492582322
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.892453438
Short name T409
Test name
Test status
Simulation time 8382836381 ps
CPU time 8.08 seconds
Started Mar 14 01:32:10 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202564 kb
Host smart-2861ae97-0e2b-4d5e-912d-95af3bc6a9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89245
3438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.892453438
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.1237827648
Short name T302
Test name
Test status
Simulation time 8385256479 ps
CPU time 7.39 seconds
Started Mar 14 01:32:06 PM PDT 24
Finished Mar 14 01:32:15 PM PDT 24
Peak memory 202564 kb
Host smart-33cd8923-6b4d-453f-b227-09f588ef59e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
27648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.1237827648
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1413353481
Short name T383
Test name
Test status
Simulation time 8362658361 ps
CPU time 7.53 seconds
Started Mar 14 01:32:07 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202468 kb
Host smart-d204380f-d167-4080-9992-e1280f4c4f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14133
53481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1413353481
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.969259838
Short name T143
Test name
Test status
Simulation time 8473588497 ps
CPU time 7.69 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202612 kb
Host smart-a2fcd43a-cfbb-494e-81cb-63c3dbd7606d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96925
9838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.969259838
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2689473056
Short name T363
Test name
Test status
Simulation time 8372674242 ps
CPU time 7.41 seconds
Started Mar 14 01:32:10 PM PDT 24
Finished Mar 14 01:32:18 PM PDT 24
Peak memory 202512 kb
Host smart-c5ea15ee-1bbd-4986-972c-a4b68a9dbdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26894
73056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2689473056
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2003971577
Short name T72
Test name
Test status
Simulation time 101411492 ps
CPU time 1.34 seconds
Started Mar 14 01:32:04 PM PDT 24
Finished Mar 14 01:32:07 PM PDT 24
Peak memory 202672 kb
Host smart-99fd2bc7-70d3-4b8e-b9e0-c56783a0dc09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20039
71577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2003971577
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1499046079
Short name T170
Test name
Test status
Simulation time 8361589451 ps
CPU time 9.25 seconds
Started Mar 14 01:32:06 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202512 kb
Host smart-498f167f-c0c7-4326-ba56-53bf104abf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
46079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1499046079
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1251946351
Short name T701
Test name
Test status
Simulation time 8414804267 ps
CPU time 7.97 seconds
Started Mar 14 01:32:12 PM PDT 24
Finished Mar 14 01:32:20 PM PDT 24
Peak memory 202524 kb
Host smart-01ca0d33-66cc-4df4-a51f-243334dfcde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12519
46351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1251946351
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2349315528
Short name T273
Test name
Test status
Simulation time 8404088031 ps
CPU time 9.41 seconds
Started Mar 14 01:32:06 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202536 kb
Host smart-80ea0c62-484d-473c-9b4a-c852be69c5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23493
15528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2349315528
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.229325972
Short name T538
Test name
Test status
Simulation time 8363502516 ps
CPU time 7.42 seconds
Started Mar 14 01:32:08 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202540 kb
Host smart-77587397-03e4-451f-a0d7-691ff443a422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22932
5972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.229325972
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1628344853
Short name T22
Test name
Test status
Simulation time 8389361699 ps
CPU time 7.4 seconds
Started Mar 14 01:32:06 PM PDT 24
Finished Mar 14 01:32:15 PM PDT 24
Peak memory 202552 kb
Host smart-edcd392b-a54a-468a-a61b-9e3a1a6b99a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16283
44853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1628344853
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1723315657
Short name T608
Test name
Test status
Simulation time 8387439660 ps
CPU time 7.31 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:13 PM PDT 24
Peak memory 202552 kb
Host smart-51290e92-44c6-4a81-9d67-3b01f3cb77c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17233
15657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1723315657
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2273527404
Short name T760
Test name
Test status
Simulation time 22909208 ps
CPU time 0.64 seconds
Started Mar 14 01:32:10 PM PDT 24
Finished Mar 14 01:32:11 PM PDT 24
Peak memory 202464 kb
Host smart-846c0962-c42f-4d97-8a1b-8e41a797ba57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22735
27404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2273527404
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2822348422
Short name T427
Test name
Test status
Simulation time 8378327128 ps
CPU time 7.22 seconds
Started Mar 14 01:32:07 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202468 kb
Host smart-845139b6-d406-40e0-b47b-abee01d735de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223
48422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2822348422
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3903886078
Short name T601
Test name
Test status
Simulation time 8371555716 ps
CPU time 8.31 seconds
Started Mar 14 01:32:08 PM PDT 24
Finished Mar 14 01:32:18 PM PDT 24
Peak memory 202548 kb
Host smart-25944549-b26c-42db-ba07-a00e97a42ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39038
86078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3903886078
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2255686848
Short name T291
Test name
Test status
Simulation time 8359272873 ps
CPU time 8.45 seconds
Started Mar 14 01:32:10 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202560 kb
Host smart-287b9284-8967-4a2b-a42b-2d1a32b2a210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22556
86848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2255686848
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2894515149
Short name T670
Test name
Test status
Simulation time 8471585704 ps
CPU time 7.79 seconds
Started Mar 14 01:32:12 PM PDT 24
Finished Mar 14 01:32:20 PM PDT 24
Peak memory 202500 kb
Host smart-aff72e03-2e5f-49ef-8d4f-2c4f79c680c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28945
15149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2894515149
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3529648255
Short name T437
Test name
Test status
Simulation time 8372486888 ps
CPU time 7.32 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202588 kb
Host smart-9a39af15-dfa2-4290-ae18-8a3db10aafc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35296
48255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3529648255
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1611410088
Short name T299
Test name
Test status
Simulation time 41008441 ps
CPU time 1.06 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:13 PM PDT 24
Peak memory 202620 kb
Host smart-0837e78b-15b8-442a-a1ce-165026f41f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16114
10088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1611410088
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2006883
Short name T667
Test name
Test status
Simulation time 8362263536 ps
CPU time 8.11 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202532 kb
Host smart-caa6bf7c-16d2-4f45-bc42-66ac1d56db5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
83 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2006883
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1784616359
Short name T493
Test name
Test status
Simulation time 8383012137 ps
CPU time 8.46 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:15 PM PDT 24
Peak memory 202564 kb
Host smart-7deb0c5a-42d5-423f-9e96-639a4aa29714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17846
16359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1784616359
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2978074504
Short name T549
Test name
Test status
Simulation time 8411901195 ps
CPU time 7.53 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202496 kb
Host smart-06e39ed5-f3dd-443a-9cc6-a313d1a1587a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29780
74504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2978074504
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.4292205328
Short name T631
Test name
Test status
Simulation time 8370007700 ps
CPU time 8.14 seconds
Started Mar 14 01:32:10 PM PDT 24
Finished Mar 14 01:32:18 PM PDT 24
Peak memory 202548 kb
Host smart-1171d050-65d1-4542-9055-88faac463a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42922
05328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.4292205328
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3945834082
Short name T604
Test name
Test status
Simulation time 8392012142 ps
CPU time 7.26 seconds
Started Mar 14 01:32:10 PM PDT 24
Finished Mar 14 01:32:18 PM PDT 24
Peak memory 202560 kb
Host smart-99a69376-8452-4445-b125-5b3f3302a4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39458
34082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3945834082
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.638800540
Short name T483
Test name
Test status
Simulation time 8391434907 ps
CPU time 7.52 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:18 PM PDT 24
Peak memory 202588 kb
Host smart-850d014c-0618-4504-b332-f54295619cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63880
0540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.638800540
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3995752533
Short name T513
Test name
Test status
Simulation time 30110724 ps
CPU time 0.68 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:07 PM PDT 24
Peak memory 202508 kb
Host smart-d1bad0a6-4781-42b4-bd85-f18a6f64840c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39957
52533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3995752533
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2370837218
Short name T641
Test name
Test status
Simulation time 8415588001 ps
CPU time 7.41 seconds
Started Mar 14 01:32:05 PM PDT 24
Finished Mar 14 01:32:14 PM PDT 24
Peak memory 202560 kb
Host smart-8a095541-0b8e-4bd8-95c7-7de777cd46d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
37218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2370837218
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1243268843
Short name T271
Test name
Test status
Simulation time 8379941927 ps
CPU time 6.86 seconds
Started Mar 14 01:32:13 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 202560 kb
Host smart-7b1cc34f-dec9-40e0-81d7-a5d633531088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12432
68843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1243268843
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.557459298
Short name T366
Test name
Test status
Simulation time 8356323881 ps
CPU time 8.27 seconds
Started Mar 14 01:32:13 PM PDT 24
Finished Mar 14 01:32:22 PM PDT 24
Peak memory 202560 kb
Host smart-851421fc-db1b-43bf-9682-974c5412e944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55745
9298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.557459298
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.788265032
Short name T144
Test name
Test status
Simulation time 8478816301 ps
CPU time 7.95 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:20 PM PDT 24
Peak memory 202572 kb
Host smart-59c54d04-554e-4a4b-8c8d-0594e6ed7b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78826
5032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.788265032
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1957250420
Short name T391
Test name
Test status
Simulation time 8369207519 ps
CPU time 8.09 seconds
Started Mar 14 01:32:13 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 202572 kb
Host smart-2bc8e76c-131a-4999-8bbb-0bc8a2fb3e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19572
50420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1957250420
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1389562989
Short name T71
Test name
Test status
Simulation time 219413351 ps
CPU time 2.37 seconds
Started Mar 14 01:32:37 PM PDT 24
Finished Mar 14 01:32:40 PM PDT 24
Peak memory 202704 kb
Host smart-0768a29c-4b9d-41f7-a50e-60bfdc38fb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13895
62989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1389562989
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3911455806
Short name T157
Test name
Test status
Simulation time 8364766047 ps
CPU time 7.42 seconds
Started Mar 14 01:32:11 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 202492 kb
Host smart-af7fd1c1-b7f4-4f24-95ed-1f74a2173dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
55806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3911455806
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1035037792
Short name T385
Test name
Test status
Simulation time 8445765199 ps
CPU time 7.15 seconds
Started Mar 14 01:32:14 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 202536 kb
Host smart-c17d4fa0-7ce8-4001-b67a-8e532c6fd536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10350
37792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1035037792
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1847251678
Short name T651
Test name
Test status
Simulation time 8411188420 ps
CPU time 7.21 seconds
Started Mar 14 01:32:09 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202508 kb
Host smart-3274be8f-65bf-43f6-93c1-ea454f0d055e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18472
51678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1847251678
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1098606663
Short name T398
Test name
Test status
Simulation time 8367647108 ps
CPU time 8.52 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:26 PM PDT 24
Peak memory 202592 kb
Host smart-f497d11c-6c57-4545-afa0-82f219503c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10986
06663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1098606663
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1603196544
Short name T312
Test name
Test status
Simulation time 8399698132 ps
CPU time 7.47 seconds
Started Mar 14 01:32:14 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 202532 kb
Host smart-cdfd46c8-74c9-43b2-bba8-7e4458f3a760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
96544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1603196544
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1972241752
Short name T35
Test name
Test status
Simulation time 27368644 ps
CPU time 0.61 seconds
Started Mar 14 01:32:15 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202472 kb
Host smart-48e591f4-77d9-41b9-98df-bc5d4e9904ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19722
41752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1972241752
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2073238768
Short name T721
Test name
Test status
Simulation time 8412450675 ps
CPU time 7.19 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202576 kb
Host smart-b63900f9-9fd2-4a48-ad55-19465ff62032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20732
38768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2073238768
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.280388306
Short name T528
Test name
Test status
Simulation time 8377099237 ps
CPU time 7.53 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:25 PM PDT 24
Peak memory 202484 kb
Host smart-3e34322f-9d40-4774-a13a-2520d5fbede4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28038
8306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.280388306
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1186091737
Short name T11
Test name
Test status
Simulation time 8361710210 ps
CPU time 8.76 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202580 kb
Host smart-959f2d78-1148-4312-a53d-d229005e216e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11860
91737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1186091737
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.978074363
Short name T487
Test name
Test status
Simulation time 8472295881 ps
CPU time 8.5 seconds
Started Mar 14 01:32:15 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202748 kb
Host smart-c3585945-1ffd-4218-8e5d-d0cd5ea4ab5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97807
4363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.978074363
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.780040188
Short name T4
Test name
Test status
Simulation time 8375016827 ps
CPU time 7.44 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202504 kb
Host smart-98ff7adf-e369-4771-8fe7-75d88613c10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78004
0188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.780040188
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2806934978
Short name T216
Test name
Test status
Simulation time 184339137 ps
CPU time 1.81 seconds
Started Mar 14 01:32:14 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 202748 kb
Host smart-4662165e-543c-46b9-b6ad-0f895a1e3e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
34978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2806934978
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3588308172
Short name T738
Test name
Test status
Simulation time 8364682573 ps
CPU time 7.42 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202572 kb
Host smart-4f0a9fab-28ae-49f9-a1c1-64dbb9c5ceff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35883
08172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3588308172
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3847701277
Short name T274
Test name
Test status
Simulation time 8402776593 ps
CPU time 9.56 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:27 PM PDT 24
Peak memory 202536 kb
Host smart-3ebcf5e0-f9a2-42f7-85e0-f38566b108d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38477
01277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3847701277
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2767135164
Short name T675
Test name
Test status
Simulation time 8407152613 ps
CPU time 7.53 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:25 PM PDT 24
Peak memory 202592 kb
Host smart-6cd76e10-9490-4cf0-8b7c-8972ed17543d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27671
35164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2767135164
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1521097659
Short name T462
Test name
Test status
Simulation time 8367605423 ps
CPU time 7.68 seconds
Started Mar 14 01:32:14 PM PDT 24
Finished Mar 14 01:32:22 PM PDT 24
Peak memory 202548 kb
Host smart-bae5a3d9-c265-44d6-b0d8-c5f6f4e37738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
97659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1521097659
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3060549563
Short name T108
Test name
Test status
Simulation time 8437577978 ps
CPU time 7.68 seconds
Started Mar 14 01:32:14 PM PDT 24
Finished Mar 14 01:32:22 PM PDT 24
Peak memory 202592 kb
Host smart-f13b74e4-d350-42d9-acad-d9df7b98f04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30605
49563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3060549563
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1752941533
Short name T762
Test name
Test status
Simulation time 8377461131 ps
CPU time 7.67 seconds
Started Mar 14 01:32:16 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202532 kb
Host smart-e15014da-a7ab-4fed-8650-22f7764a4326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17529
41533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1752941533
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.4178706529
Short name T503
Test name
Test status
Simulation time 8384664161 ps
CPU time 8.22 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202508 kb
Host smart-1a1855e5-9457-408e-8d92-9790990d6657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41787
06529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.4178706529
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.3719259557
Short name T27
Test name
Test status
Simulation time 28375679 ps
CPU time 0.62 seconds
Started Mar 14 01:32:14 PM PDT 24
Finished Mar 14 01:32:15 PM PDT 24
Peak memory 202696 kb
Host smart-081658d0-72fa-4fda-8305-89f1012a3466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37192
59557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3719259557
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1878736382
Short name T582
Test name
Test status
Simulation time 8401957028 ps
CPU time 7.66 seconds
Started Mar 14 01:32:21 PM PDT 24
Finished Mar 14 01:32:29 PM PDT 24
Peak memory 202504 kb
Host smart-abc94f0b-ae5e-45e9-b877-369556bc3439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18787
36382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1878736382
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3751690171
Short name T463
Test name
Test status
Simulation time 8384055823 ps
CPU time 9 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202576 kb
Host smart-b105649a-b4e6-4bc3-96ec-fa45bda905c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37516
90171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3751690171
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1045658174
Short name T377
Test name
Test status
Simulation time 8360177898 ps
CPU time 7.77 seconds
Started Mar 14 01:32:16 PM PDT 24
Finished Mar 14 01:32:23 PM PDT 24
Peak memory 202464 kb
Host smart-5b0a28ae-f8a1-4c97-961c-8a8fb65381c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10456
58174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1045658174
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3090529720
Short name T147
Test name
Test status
Simulation time 8475835827 ps
CPU time 8.71 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202596 kb
Host smart-1ca5d030-de68-4c80-bd1b-e1e8fcc9dffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
29720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3090529720
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3365286544
Short name T426
Test name
Test status
Simulation time 8374962084 ps
CPU time 8.68 seconds
Started Mar 14 01:32:16 PM PDT 24
Finished Mar 14 01:32:25 PM PDT 24
Peak memory 202584 kb
Host smart-f82f4d8a-24cc-4b0e-b6af-f37bb569a5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33652
86544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3365286544
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.212661178
Short name T600
Test name
Test status
Simulation time 203958662 ps
CPU time 1.71 seconds
Started Mar 14 01:32:16 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 202632 kb
Host smart-a33cc73a-e786-4ac1-8613-f57de268e0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21266
1178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.212661178
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4247811619
Short name T286
Test name
Test status
Simulation time 8366043344 ps
CPU time 9.19 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202548 kb
Host smart-9f55cd57-6073-451d-9410-ec22cf6325b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42478
11619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4247811619
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2895531621
Short name T118
Test name
Test status
Simulation time 8429276620 ps
CPU time 9.45 seconds
Started Mar 14 01:32:15 PM PDT 24
Finished Mar 14 01:32:25 PM PDT 24
Peak memory 202520 kb
Host smart-ef0fc53e-85a7-464a-9aa0-53d0ff4064bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28955
31621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2895531621
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.153325897
Short name T688
Test name
Test status
Simulation time 8411056270 ps
CPU time 7.8 seconds
Started Mar 14 01:32:22 PM PDT 24
Finished Mar 14 01:32:30 PM PDT 24
Peak memory 202508 kb
Host smart-3cd982f4-9fdb-41e5-b51d-9b4a4f1b51e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15332
5897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.153325897
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.654116637
Short name T324
Test name
Test status
Simulation time 8362220396 ps
CPU time 8.46 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:25 PM PDT 24
Peak memory 202532 kb
Host smart-b467abb9-1894-4643-a4ea-eb3472d7ee85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65411
6637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.654116637
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1175116049
Short name T88
Test name
Test status
Simulation time 8440938022 ps
CPU time 8.04 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:26 PM PDT 24
Peak memory 202600 kb
Host smart-f1c0d297-2844-4d26-b23d-55b7d49aee83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11751
16049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1175116049
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.979274817
Short name T510
Test name
Test status
Simulation time 8387281022 ps
CPU time 7.19 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202576 kb
Host smart-084a5a41-f5b5-45f1-9b6e-3ef56c5ba2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97927
4817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.979274817
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.332566396
Short name T218
Test name
Test status
Simulation time 8384556871 ps
CPU time 8.01 seconds
Started Mar 14 01:32:15 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202512 kb
Host smart-9fb119a5-2858-4e85-bf16-535ed167684a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33256
6396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.332566396
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1599241090
Short name T578
Test name
Test status
Simulation time 22512571 ps
CPU time 0.63 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202508 kb
Host smart-cdeb3954-9679-4956-8a30-46bdfcaaebce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15992
41090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1599241090
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.130964399
Short name T615
Test name
Test status
Simulation time 8406330506 ps
CPU time 7.59 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:25 PM PDT 24
Peak memory 202500 kb
Host smart-f12f39e1-9205-4e56-9afa-6790dfb3cf81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13096
4399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.130964399
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.1034963825
Short name T691
Test name
Test status
Simulation time 8381390135 ps
CPU time 7.52 seconds
Started Mar 14 01:32:16 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202536 kb
Host smart-f248d1a8-ec76-4d1c-a051-ddb9439fc37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10349
63825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.1034963825
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.522869417
Short name T435
Test name
Test status
Simulation time 8361191822 ps
CPU time 7.16 seconds
Started Mar 14 01:32:21 PM PDT 24
Finished Mar 14 01:32:29 PM PDT 24
Peak memory 202576 kb
Host smart-ba820b6a-7ddd-4cf7-a16f-9aaef6ed9b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52286
9417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.522869417
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2298167852
Short name T751
Test name
Test status
Simulation time 8470767445 ps
CPU time 9.78 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202628 kb
Host smart-4d703e5a-5e14-4148-bcb2-4d340eebc25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22981
67852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2298167852
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3614216150
Short name T387
Test name
Test status
Simulation time 8371340146 ps
CPU time 7.27 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202524 kb
Host smart-924b46dc-42a9-4b10-a2f3-4e58963142e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36142
16150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3614216150
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3087605001
Short name T679
Test name
Test status
Simulation time 119605680 ps
CPU time 1.46 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:26 PM PDT 24
Peak memory 202728 kb
Host smart-3401452d-d02d-4c30-9a5f-c8d60a807194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876
05001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3087605001
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3741651381
Short name T412
Test name
Test status
Simulation time 8364025566 ps
CPU time 7.63 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:30 PM PDT 24
Peak memory 202580 kb
Host smart-5dfa242b-4ae6-477e-a3e8-021b41ef0e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37416
51381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3741651381
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3343468796
Short name T334
Test name
Test status
Simulation time 8410911359 ps
CPU time 7.15 seconds
Started Mar 14 01:32:16 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202504 kb
Host smart-fa5d4f75-e711-47d7-8fe0-f995cabdae70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33434
68796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3343468796
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2275815937
Short name T725
Test name
Test status
Simulation time 8366948773 ps
CPU time 7.21 seconds
Started Mar 14 01:32:29 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202576 kb
Host smart-ec0a5edf-3f78-4586-aaaa-5f1a98d0f6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22758
15937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2275815937
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1036246215
Short name T731
Test name
Test status
Simulation time 8413801239 ps
CPU time 7.7 seconds
Started Mar 14 01:32:13 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 202544 kb
Host smart-9c06bee8-e09d-4b07-84e3-899fbe68d7a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
46215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1036246215
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3152633954
Short name T722
Test name
Test status
Simulation time 8380730373 ps
CPU time 9.36 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202608 kb
Host smart-b7a7a04c-2c19-431b-bce5-65e594f25cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31526
33954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3152633954
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1413248180
Short name T362
Test name
Test status
Simulation time 8367829453 ps
CPU time 8.81 seconds
Started Mar 14 01:32:14 PM PDT 24
Finished Mar 14 01:32:23 PM PDT 24
Peak memory 202556 kb
Host smart-d1679ef6-e1ae-4abe-92de-d9a44f417a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14132
48180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1413248180
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3269846470
Short name T428
Test name
Test status
Simulation time 25763263 ps
CPU time 0.61 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202508 kb
Host smart-f85a024b-5481-41bc-b063-6c8516128763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32698
46470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3269846470
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.87764842
Short name T125
Test name
Test status
Simulation time 8430332547 ps
CPU time 7.7 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:25 PM PDT 24
Peak memory 202500 kb
Host smart-cce9a779-42d7-4b51-8cf3-666d1991c122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87764
842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.87764842
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.4284018557
Short name T305
Test name
Test status
Simulation time 8367069273 ps
CPU time 7.28 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:30 PM PDT 24
Peak memory 202584 kb
Host smart-7a32e10a-b89c-4ada-8bc0-cdd085b5582d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42840
18557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.4284018557
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3771952504
Short name T482
Test name
Test status
Simulation time 8360151159 ps
CPU time 7.32 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202564 kb
Host smart-cc9c528d-aa6c-405f-bdee-d99ee3b3eb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37719
52504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3771952504
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1178886971
Short name T154
Test name
Test status
Simulation time 8483209634 ps
CPU time 7.39 seconds
Started Mar 14 01:32:17 PM PDT 24
Finished Mar 14 01:32:24 PM PDT 24
Peak memory 202536 kb
Host smart-1de429f7-27db-4fad-bf56-454a899f662d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11788
86971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1178886971
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1558544707
Short name T364
Test name
Test status
Simulation time 8372287176 ps
CPU time 8.67 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202580 kb
Host smart-d8cf9c34-27a0-4f69-91c0-f899447e79bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
44707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1558544707
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3324670505
Short name T614
Test name
Test status
Simulation time 293140828 ps
CPU time 2.24 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:29 PM PDT 24
Peak memory 202432 kb
Host smart-c6a19d7b-f9b5-4500-b8c8-02837a2bc3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33246
70505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3324670505
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1294397317
Short name T522
Test name
Test status
Simulation time 8363505336 ps
CPU time 8.76 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:37 PM PDT 24
Peak memory 202468 kb
Host smart-48c50f36-cc5f-4c32-860a-40c2ea37f781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12943
97317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1294397317
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2392084300
Short name T739
Test name
Test status
Simulation time 8379728291 ps
CPU time 7.77 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202504 kb
Host smart-79db63fd-8e99-459a-9c9e-b338f83d9ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23920
84300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2392084300
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.189178362
Short name T680
Test name
Test status
Simulation time 8409160359 ps
CPU time 7.46 seconds
Started Mar 14 01:32:22 PM PDT 24
Finished Mar 14 01:32:30 PM PDT 24
Peak memory 202584 kb
Host smart-9c2b1a74-8fe0-4aff-bb1e-2136af94c180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18917
8362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.189178362
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1172872813
Short name T5
Test name
Test status
Simulation time 8370431345 ps
CPU time 7.51 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202472 kb
Host smart-aaeb2317-52b7-4f43-a632-665aeb0fb406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11728
72813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1172872813
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.808288323
Short name T718
Test name
Test status
Simulation time 8419634968 ps
CPU time 9.79 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202548 kb
Host smart-08cb78d8-530b-4bfa-ba27-814d4cdb07bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80828
8323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.808288323
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.623071004
Short name T259
Test name
Test status
Simulation time 8407348248 ps
CPU time 9.72 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202596 kb
Host smart-22081004-c7a6-4d7e-a17c-32718e0bd41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62307
1004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.623071004
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1101420609
Short name T278
Test name
Test status
Simulation time 8378266145 ps
CPU time 7.22 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202508 kb
Host smart-036755fc-5043-457b-831d-1cc6f9625551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11014
20609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1101420609
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1765002203
Short name T704
Test name
Test status
Simulation time 28771798 ps
CPU time 0.65 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:27 PM PDT 24
Peak memory 202432 kb
Host smart-0f3898f4-5125-409b-9347-cd14a9c7f954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17650
02203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1765002203
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1642506142
Short name T129
Test name
Test status
Simulation time 8414387849 ps
CPU time 7.91 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202564 kb
Host smart-068a914a-8480-4c87-9e8a-24e04b45c75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16425
06142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1642506142
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.698485129
Short name T215
Test name
Test status
Simulation time 8374748467 ps
CPU time 8.87 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202532 kb
Host smart-2822b630-c595-46b3-a423-29534e16b6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69848
5129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.698485129
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.946713082
Short name T485
Test name
Test status
Simulation time 8357163571 ps
CPU time 7.35 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202316 kb
Host smart-40dfee80-3077-43d8-8e35-b76a3e38d252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94671
3082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.946713082
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2229914182
Short name T150
Test name
Test status
Simulation time 8473878233 ps
CPU time 8.24 seconds
Started Mar 14 01:32:12 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 202500 kb
Host smart-6a5de074-71c7-4b90-9546-08f30fb88eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22299
14182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2229914182
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3647633525
Short name T37
Test name
Test status
Simulation time 8371430561 ps
CPU time 8.92 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202544 kb
Host smart-2f0e7351-daf3-46cd-9fec-0d133606f2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36476
33525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3647633525
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3844258972
Short name T569
Test name
Test status
Simulation time 287936802 ps
CPU time 2.3 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:28 PM PDT 24
Peak memory 202648 kb
Host smart-0995b29e-1b93-424d-957b-dcaf4a8ae04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38442
58972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3844258972
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.435299743
Short name T574
Test name
Test status
Simulation time 8358819263 ps
CPU time 8.82 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202484 kb
Host smart-e66e0427-e110-4209-b0ce-95ea482da054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43529
9743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.435299743
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2426314881
Short name T613
Test name
Test status
Simulation time 8372582343 ps
CPU time 7.86 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202512 kb
Host smart-2e5f375b-15b9-429c-a723-39876b73ad9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24263
14881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2426314881
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.398462397
Short name T552
Test name
Test status
Simulation time 8412694304 ps
CPU time 7.84 seconds
Started Mar 14 01:32:23 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202596 kb
Host smart-fad33bb7-f9a7-44aa-8bad-a81043dc7f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39846
2397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.398462397
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1206798604
Short name T284
Test name
Test status
Simulation time 8361909278 ps
CPU time 9.26 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202520 kb
Host smart-531b77c9-b4b1-4d0e-bc52-00c73591d15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12067
98604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1206798604
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2922600822
Short name T668
Test name
Test status
Simulation time 8392814063 ps
CPU time 8.32 seconds
Started Mar 14 01:32:22 PM PDT 24
Finished Mar 14 01:32:30 PM PDT 24
Peak memory 202536 kb
Host smart-2659ac93-ac2f-4e62-bc0a-b48eef0a4ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29226
00822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2922600822
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2670029710
Short name T282
Test name
Test status
Simulation time 8396187041 ps
CPU time 7.5 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:35 PM PDT 24
Peak memory 202532 kb
Host smart-ba68bf0f-be17-4642-a1d6-83a3317d6417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26700
29710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2670029710
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1446416739
Short name T706
Test name
Test status
Simulation time 26235342 ps
CPU time 0.63 seconds
Started Mar 14 01:32:30 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202492 kb
Host smart-ae7f25be-995d-452d-b468-791050a2570d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464
16739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1446416739
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1523375019
Short name T424
Test name
Test status
Simulation time 8439895471 ps
CPU time 7.71 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202448 kb
Host smart-7e76422a-6ab9-4d57-a233-037c4e9c86b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233
75019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1523375019
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.723102475
Short name T420
Test name
Test status
Simulation time 8362727940 ps
CPU time 7.33 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202516 kb
Host smart-2503a8a7-33e2-4298-95b4-354c1b107f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72310
2475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.723102475
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3298807543
Short name T314
Test name
Test status
Simulation time 8359657069 ps
CPU time 7.68 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202292 kb
Host smart-7b6e7498-a414-4a69-8604-0356294c9f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32988
07543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3298807543
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1088304763
Short name T38
Test name
Test status
Simulation time 8469494342 ps
CPU time 7.53 seconds
Started Mar 14 01:32:29 PM PDT 24
Finished Mar 14 01:32:37 PM PDT 24
Peak memory 202580 kb
Host smart-62459147-cdb9-40ce-88c3-47905c3acff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
04763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1088304763
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.308657485
Short name T676
Test name
Test status
Simulation time 8365453552 ps
CPU time 7.62 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:37 PM PDT 24
Peak memory 202584 kb
Host smart-851f7578-fe54-4c5d-90c9-5d1972771797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30865
7485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.308657485
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1709990344
Short name T275
Test name
Test status
Simulation time 108103906 ps
CPU time 1.31 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:29 PM PDT 24
Peak memory 202732 kb
Host smart-edffc25a-5cb8-410d-a833-60ef58967bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17099
90344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1709990344
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1759114207
Short name T169
Test name
Test status
Simulation time 8361136799 ps
CPU time 7.48 seconds
Started Mar 14 01:30:32 PM PDT 24
Finished Mar 14 01:30:41 PM PDT 24
Peak memory 202520 kb
Host smart-ca58e368-1c86-49f0-b055-72a79e7d1035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17591
14207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1759114207
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3574628177
Short name T230
Test name
Test status
Simulation time 8412379307 ps
CPU time 8.05 seconds
Started Mar 14 01:30:25 PM PDT 24
Finished Mar 14 01:30:33 PM PDT 24
Peak memory 202564 kb
Host smart-d5ee6170-8925-4209-bf8d-adba9b09b783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35746
28177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3574628177
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2246687418
Short name T696
Test name
Test status
Simulation time 8363157576 ps
CPU time 7.63 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 202468 kb
Host smart-6927c241-6fd8-4856-b690-f3f424608036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22466
87418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2246687418
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1428066909
Short name T17
Test name
Test status
Simulation time 8422878518 ps
CPU time 8.49 seconds
Started Mar 14 01:30:36 PM PDT 24
Finished Mar 14 01:30:45 PM PDT 24
Peak memory 202056 kb
Host smart-7b8f6c99-ff24-4e38-9b71-0ef66497622f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14280
66909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1428066909
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3166850942
Short name T413
Test name
Test status
Simulation time 8387850638 ps
CPU time 7.35 seconds
Started Mar 14 01:30:29 PM PDT 24
Finished Mar 14 01:30:37 PM PDT 24
Peak memory 202532 kb
Host smart-b22d22b5-9d5b-4a3a-a308-06b8506becde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31668
50942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3166850942
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.758085853
Short name T292
Test name
Test status
Simulation time 8406196988 ps
CPU time 7.78 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:36 PM PDT 24
Peak memory 202528 kb
Host smart-22200826-0424-4c32-a85c-896624a52620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75808
5853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.758085853
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3194608857
Short name T465
Test name
Test status
Simulation time 23211282 ps
CPU time 0.65 seconds
Started Mar 14 01:30:30 PM PDT 24
Finished Mar 14 01:30:31 PM PDT 24
Peak memory 202512 kb
Host smart-d98d6d28-31c0-4754-ae4b-38ef12a23788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31946
08857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3194608857
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.525429333
Short name T454
Test name
Test status
Simulation time 8404190189 ps
CPU time 7.14 seconds
Started Mar 14 01:30:30 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202576 kb
Host smart-e479df35-b6f5-4b16-b09b-5cd4dd459f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52542
9333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.525429333
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.4042308559
Short name T323
Test name
Test status
Simulation time 8380867962 ps
CPU time 7.08 seconds
Started Mar 14 01:30:26 PM PDT 24
Finished Mar 14 01:30:33 PM PDT 24
Peak memory 202552 kb
Host smart-cca13d15-fc23-464e-aa9b-a3a7f821b703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40423
08559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.4042308559
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.4025060987
Short name T49
Test name
Test status
Simulation time 207217914 ps
CPU time 0.95 seconds
Started Mar 14 01:30:24 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 217732 kb
Host smart-51963381-cfdb-43c8-b0c2-f06112b135dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4025060987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.4025060987
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.4258652606
Short name T12
Test name
Test status
Simulation time 8358695841 ps
CPU time 7.37 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:34 PM PDT 24
Peak memory 202548 kb
Host smart-66d225dd-fa47-481d-a6df-e1da51ee53d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42586
52606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.4258652606
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1875946731
Short name T723
Test name
Test status
Simulation time 8469295227 ps
CPU time 7.56 seconds
Started Mar 14 01:30:24 PM PDT 24
Finished Mar 14 01:30:32 PM PDT 24
Peak memory 202548 kb
Host smart-2aae4200-8ee6-4eb9-bb15-4d56b2987506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18759
46731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1875946731
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2790927886
Short name T457
Test name
Test status
Simulation time 8371232746 ps
CPU time 8.49 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202572 kb
Host smart-aad8ea69-876f-4cda-96d9-70ff3e0105df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27909
27886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2790927886
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3707977826
Short name T567
Test name
Test status
Simulation time 257254998 ps
CPU time 2.03 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:30 PM PDT 24
Peak memory 202636 kb
Host smart-fb05e2d9-c0e5-479a-9e70-6a0706ee7bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37079
77826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3707977826
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.4246685489
Short name T316
Test name
Test status
Simulation time 8361770878 ps
CPU time 7.33 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:35 PM PDT 24
Peak memory 202536 kb
Host smart-57fd7844-d5e0-4e8a-ab95-dbbc3f4a4018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42466
85489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.4246685489
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2350657728
Short name T115
Test name
Test status
Simulation time 8452662751 ps
CPU time 8.06 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202208 kb
Host smart-7daa8e65-d638-4e35-ab51-c37f191e0a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23506
57728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2350657728
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3132287521
Short name T541
Test name
Test status
Simulation time 8403815366 ps
CPU time 9.31 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202568 kb
Host smart-5ea13afc-0a8b-4012-9481-7d0c9cf9f289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31322
87521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3132287521
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.850686673
Short name T401
Test name
Test status
Simulation time 8360690859 ps
CPU time 7.2 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202588 kb
Host smart-b24c8b4c-941f-4926-8d6c-4ba95f67ec60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85068
6673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.850686673
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3219043759
Short name T84
Test name
Test status
Simulation time 8385957739 ps
CPU time 8.27 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202576 kb
Host smart-c45985a1-44fa-4e38-bdd3-48c1c16fed33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
43759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3219043759
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2458052836
Short name T639
Test name
Test status
Simulation time 8395100485 ps
CPU time 7.99 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202560 kb
Host smart-c1dcc04e-8114-4fd2-9bc1-63bd23807f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24580
52836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2458052836
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2718852014
Short name T509
Test name
Test status
Simulation time 8384065259 ps
CPU time 8.31 seconds
Started Mar 14 01:32:29 PM PDT 24
Finished Mar 14 01:32:38 PM PDT 24
Peak memory 202532 kb
Host smart-a1e92b5b-2f07-48ff-b72f-05e4f8840c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27188
52014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2718852014
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2532197983
Short name T754
Test name
Test status
Simulation time 25307934 ps
CPU time 0.64 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:28 PM PDT 24
Peak memory 202472 kb
Host smart-b7b6c723-2f01-4998-976c-49d43ef8c03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
97983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2532197983
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.245591829
Short name T132
Test name
Test status
Simulation time 8430960084 ps
CPU time 8.67 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:37 PM PDT 24
Peak memory 202552 kb
Host smart-dc96ad7e-eb7a-462c-8b5b-27de211e9805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24559
1829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.245591829
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1186502411
Short name T376
Test name
Test status
Simulation time 8365082689 ps
CPU time 9.85 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202584 kb
Host smart-d9b69779-8e28-45ef-aab9-69dda3e3c98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11865
02411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1186502411
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.28886890
Short name T524
Test name
Test status
Simulation time 8356335317 ps
CPU time 7.7 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:35 PM PDT 24
Peak memory 202564 kb
Host smart-bcb8dbc5-e558-427a-bb87-5c29fb515827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28886
890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.28886890
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2360734406
Short name T640
Test name
Test status
Simulation time 8368492978 ps
CPU time 8.06 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202596 kb
Host smart-28e3009c-488c-4b96-ac37-ec1e33dfb890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23607
34406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2360734406
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1687993352
Short name T221
Test name
Test status
Simulation time 37469095 ps
CPU time 1 seconds
Started Mar 14 01:32:33 PM PDT 24
Finished Mar 14 01:32:35 PM PDT 24
Peak memory 202700 kb
Host smart-27d9c1f4-0e7e-47c4-94d2-a99d6722262e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16879
93352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1687993352
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.3418452575
Short name T678
Test name
Test status
Simulation time 8361866643 ps
CPU time 7.55 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202548 kb
Host smart-a36d2128-4730-4865-8cff-4318d375df2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
52575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3418452575
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.852113927
Short name T681
Test name
Test status
Simulation time 8453403954 ps
CPU time 7.98 seconds
Started Mar 14 01:32:29 PM PDT 24
Finished Mar 14 01:32:37 PM PDT 24
Peak memory 202548 kb
Host smart-3f576677-f39e-46f2-92b0-21221af546c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85211
3927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.852113927
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3855370629
Short name T295
Test name
Test status
Simulation time 8411416932 ps
CPU time 7.34 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202468 kb
Host smart-dc1e29af-0407-40bf-a465-132e53781107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38553
70629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3855370629
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1437949232
Short name T560
Test name
Test status
Simulation time 8365510658 ps
CPU time 7.23 seconds
Started Mar 14 01:32:29 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202568 kb
Host smart-68306a3f-63ce-419b-9673-bf4857ac3f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14379
49232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1437949232
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3881896022
Short name T106
Test name
Test status
Simulation time 8413048423 ps
CPU time 8.11 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202468 kb
Host smart-0e437a9b-3eee-4226-ac76-9fe40a0a7c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818
96022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3881896022
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.913095897
Short name T473
Test name
Test status
Simulation time 8410593046 ps
CPU time 8.03 seconds
Started Mar 14 01:32:29 PM PDT 24
Finished Mar 14 01:32:37 PM PDT 24
Peak memory 202564 kb
Host smart-8f0b6337-c67e-42ae-ae4e-147dddb65001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91309
5897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.913095897
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1491747470
Short name T288
Test name
Test status
Simulation time 8387472058 ps
CPU time 8.06 seconds
Started Mar 14 01:32:25 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202544 kb
Host smart-5098e3b7-890b-406c-8107-397738426b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14917
47470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1491747470
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3038127891
Short name T34
Test name
Test status
Simulation time 25411185 ps
CPU time 0.68 seconds
Started Mar 14 01:32:30 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202496 kb
Host smart-3b344118-5fb8-4789-a40e-e5a9d0fb4ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30381
27891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3038127891
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1575453778
Short name T113
Test name
Test status
Simulation time 8410367074 ps
CPU time 8.54 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202528 kb
Host smart-fdf0f761-3699-4d1f-9915-bca5e461880d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15754
53778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1575453778
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2474734940
Short name T716
Test name
Test status
Simulation time 8401105117 ps
CPU time 7.41 seconds
Started Mar 14 01:32:30 PM PDT 24
Finished Mar 14 01:32:38 PM PDT 24
Peak memory 202568 kb
Host smart-46c415b2-eddd-4a05-bca9-33e395f26a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24747
34940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2474734940
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3254837359
Short name T653
Test name
Test status
Simulation time 8361525807 ps
CPU time 7.22 seconds
Started Mar 14 01:32:29 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202568 kb
Host smart-8864c55e-c4d2-487f-ba01-8eee7785707d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32548
37359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3254837359
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1152718080
Short name T111
Test name
Test status
Simulation time 8475930720 ps
CPU time 7.31 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202612 kb
Host smart-d7f02b20-9e2d-43e1-a892-9f2ac5582a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11527
18080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1152718080
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3333064584
Short name T348
Test name
Test status
Simulation time 8371403635 ps
CPU time 8.58 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:02 PM PDT 24
Peak memory 202384 kb
Host smart-4c082781-e770-48b3-a75b-9216a52bcc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33330
64584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3333064584
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3668259372
Short name T693
Test name
Test status
Simulation time 249184899 ps
CPU time 2.06 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:29 PM PDT 24
Peak memory 202708 kb
Host smart-f7751259-eaec-4c8c-b4d3-e772224bc8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
59372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3668259372
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.4190595590
Short name T182
Test name
Test status
Simulation time 8356274679 ps
CPU time 7.13 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 202528 kb
Host smart-d9deae41-a440-4a28-b654-766ee9a424ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41905
95590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.4190595590
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2900559230
Short name T116
Test name
Test status
Simulation time 8461871467 ps
CPU time 9 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:54 PM PDT 24
Peak memory 202360 kb
Host smart-5947e9ba-47d7-4199-8652-ef1c03dae7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29005
59230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2900559230
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.66637510
Short name T447
Test name
Test status
Simulation time 8408337166 ps
CPU time 7.07 seconds
Started Mar 14 01:32:45 PM PDT 24
Finished Mar 14 01:32:52 PM PDT 24
Peak memory 202144 kb
Host smart-b5d0ed2d-cfd0-4151-a86e-dfa102daabc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66637
510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.66637510
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.988769488
Short name T617
Test name
Test status
Simulation time 8364841043 ps
CPU time 7.31 seconds
Started Mar 14 01:32:45 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202416 kb
Host smart-ad6178ca-f823-4121-a3db-e7ff2c9dd093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98876
9488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.988769488
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3045588594
Short name T82
Test name
Test status
Simulation time 8409731515 ps
CPU time 7.43 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:35 PM PDT 24
Peak memory 202576 kb
Host smart-ea801203-b99a-4ec9-94ac-37daf538f5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30455
88594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3045588594
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2481655434
Short name T743
Test name
Test status
Simulation time 8398288889 ps
CPU time 7.57 seconds
Started Mar 14 01:32:45 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202276 kb
Host smart-d796b72e-17be-4e73-b58a-ad59a32f64f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
55434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2481655434
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3016444723
Short name T544
Test name
Test status
Simulation time 8371099163 ps
CPU time 7.86 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202388 kb
Host smart-74df1d8c-0d55-4e12-a189-1c7fdcdea035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30164
44723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3016444723
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.4071655034
Short name T340
Test name
Test status
Simulation time 25654805 ps
CPU time 0.65 seconds
Started Mar 14 01:32:30 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 202404 kb
Host smart-09e5195b-7491-46f9-bbdb-5a35ba87ef30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40716
55034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.4071655034
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.248102659
Short name T587
Test name
Test status
Simulation time 8413457405 ps
CPU time 7.95 seconds
Started Mar 14 01:32:28 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202576 kb
Host smart-78186911-df2c-4277-bc95-c2be0d0c15ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24810
2659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.248102659
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.635506220
Short name T573
Test name
Test status
Simulation time 8397364643 ps
CPU time 8.34 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202568 kb
Host smart-3bbf1e41-9cde-4f87-af8f-8adc974892e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63550
6220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.635506220
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1902238776
Short name T708
Test name
Test status
Simulation time 8363241311 ps
CPU time 8.41 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202572 kb
Host smart-9619a79f-89a7-4ae8-b3a1-8c30a9e77d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19022
38776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1902238776
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.925038337
Short name T506
Test name
Test status
Simulation time 8474973772 ps
CPU time 8.6 seconds
Started Mar 14 01:32:30 PM PDT 24
Finished Mar 14 01:32:39 PM PDT 24
Peak memory 202588 kb
Host smart-84e57309-4ff0-495d-ad9b-a3cb4e4b3fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92503
8337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.925038337
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1184422749
Short name T498
Test name
Test status
Simulation time 8372151527 ps
CPU time 9.07 seconds
Started Mar 14 01:32:29 PM PDT 24
Finished Mar 14 01:32:39 PM PDT 24
Peak memory 202472 kb
Host smart-e8d7d9b2-eef3-404c-9974-645eb2bac6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11844
22749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1184422749
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1518859046
Short name T414
Test name
Test status
Simulation time 60205056 ps
CPU time 1.72 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:29 PM PDT 24
Peak memory 202700 kb
Host smart-1d9afb63-74fb-40cd-af82-5cc19d03c680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15188
59046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1518859046
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2880104776
Short name T24
Test name
Test status
Simulation time 8364315822 ps
CPU time 7.39 seconds
Started Mar 14 01:32:51 PM PDT 24
Finished Mar 14 01:32:58 PM PDT 24
Peak memory 202568 kb
Host smart-b92c2e17-8141-48e8-989f-b3554dc42dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28801
04776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2880104776
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3197488837
Short name T110
Test name
Test status
Simulation time 8433840635 ps
CPU time 7.39 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202560 kb
Host smart-19b956d6-f23a-4e3b-bb11-b05aa9d5c008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31974
88837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3197488837
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2146800788
Short name T540
Test name
Test status
Simulation time 8407637399 ps
CPU time 7.6 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:35 PM PDT 24
Peak memory 202576 kb
Host smart-16532ef8-e987-4223-951e-2fdaf00d52e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21468
00788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2146800788
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2961420674
Short name T372
Test name
Test status
Simulation time 8362827935 ps
CPU time 7.75 seconds
Started Mar 14 01:32:24 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 202508 kb
Host smart-dbdb214d-8987-465f-b357-da0e357a63f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29614
20674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2961420674
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1660291227
Short name T103
Test name
Test status
Simulation time 8416238933 ps
CPU time 8.5 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:35 PM PDT 24
Peak memory 202508 kb
Host smart-5b4f690a-8dbe-4780-adee-fdb95805ad5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
91227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1660291227
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1279113621
Short name T382
Test name
Test status
Simulation time 8371620330 ps
CPU time 7.17 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202564 kb
Host smart-683478d2-df28-4b3b-91d5-5a6d65565f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12791
13621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1279113621
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2043277490
Short name T461
Test name
Test status
Simulation time 8383883927 ps
CPU time 7.65 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202560 kb
Host smart-f778bb5c-759e-4674-82d6-736e708998ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20432
77490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2043277490
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.441449505
Short name T33
Test name
Test status
Simulation time 26572472 ps
CPU time 0.73 seconds
Started Mar 14 01:32:43 PM PDT 24
Finished Mar 14 01:32:45 PM PDT 24
Peak memory 202440 kb
Host smart-363bc5d8-929f-47d3-9401-9e2b968ee3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44144
9505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.441449505
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3038258221
Short name T645
Test name
Test status
Simulation time 8393457150 ps
CPU time 8.09 seconds
Started Mar 14 01:32:27 PM PDT 24
Finished Mar 14 01:32:36 PM PDT 24
Peak memory 202560 kb
Host smart-38d21721-ffb3-43e4-8217-28703ac07543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30382
58221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3038258221
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.4150091567
Short name T68
Test name
Test status
Simulation time 8381938301 ps
CPU time 7.71 seconds
Started Mar 14 01:32:26 PM PDT 24
Finished Mar 14 01:32:34 PM PDT 24
Peak memory 202588 kb
Host smart-0b63e02a-6f5f-47da-bf1a-8211d21ea73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41500
91567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.4150091567
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3122154923
Short name T384
Test name
Test status
Simulation time 8357566879 ps
CPU time 9.09 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:54 PM PDT 24
Peak memory 202596 kb
Host smart-069144d4-9e08-4503-8a20-5a4d6fb9e2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31221
54923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3122154923
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2588436932
Short name T131
Test name
Test status
Simulation time 8471132792 ps
CPU time 9.87 seconds
Started Mar 14 01:32:43 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202380 kb
Host smart-6a30cb6c-e7e0-4c2f-a095-63048083db0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25884
36932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2588436932
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1930278780
Short name T458
Test name
Test status
Simulation time 8371145539 ps
CPU time 7.48 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:51 PM PDT 24
Peak memory 202548 kb
Host smart-4fc63b9a-f0b8-4a4d-b845-29395d89fe48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19302
78780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1930278780
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3575733412
Short name T212
Test name
Test status
Simulation time 80660093 ps
CPU time 2.11 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:47 PM PDT 24
Peak memory 202728 kb
Host smart-33f7ebe9-42bb-4717-9bda-013a5ea88718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35757
33412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3575733412
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.386337700
Short name T165
Test name
Test status
Simulation time 8358028304 ps
CPU time 7.88 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:52 PM PDT 24
Peak memory 202516 kb
Host smart-8677de1e-ad86-47ad-865e-26072d568c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633
7700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.386337700
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1536514667
Short name T124
Test name
Test status
Simulation time 8415540569 ps
CPU time 7.41 seconds
Started Mar 14 01:32:47 PM PDT 24
Finished Mar 14 01:32:54 PM PDT 24
Peak memory 202468 kb
Host smart-b65830d4-9e89-4aa8-b1e6-bec26203bdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15365
14667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1536514667
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.4166102341
Short name T355
Test name
Test status
Simulation time 8404473034 ps
CPU time 8.46 seconds
Started Mar 14 01:32:46 PM PDT 24
Finished Mar 14 01:32:54 PM PDT 24
Peak memory 202568 kb
Host smart-553b1ce2-0003-42d0-8d45-756059b2b2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
02341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.4166102341
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.4098791449
Short name T346
Test name
Test status
Simulation time 8367658343 ps
CPU time 9.14 seconds
Started Mar 14 01:32:42 PM PDT 24
Finished Mar 14 01:32:52 PM PDT 24
Peak memory 202592 kb
Host smart-9cd3b21c-80bf-4ed3-9793-40011ead91f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40987
91449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.4098791449
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.4017741995
Short name T89
Test name
Test status
Simulation time 8429610615 ps
CPU time 9.07 seconds
Started Mar 14 01:32:45 PM PDT 24
Finished Mar 14 01:32:54 PM PDT 24
Peak memory 202516 kb
Host smart-3062983a-5cd1-47f3-a43f-3fdd0b70dc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40177
41995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.4017741995
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4035897216
Short name T742
Test name
Test status
Simulation time 8392834839 ps
CPU time 7.89 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 202508 kb
Host smart-a141152b-39ab-409b-ba60-82fe07dc294d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40358
97216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4035897216
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2544466399
Short name T444
Test name
Test status
Simulation time 8397688395 ps
CPU time 7.56 seconds
Started Mar 14 01:32:45 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202560 kb
Host smart-d4ee6fb2-b62c-4815-bd24-5edc2943e3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25444
66399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2544466399
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2873437466
Short name T438
Test name
Test status
Simulation time 29675290 ps
CPU time 0.64 seconds
Started Mar 14 01:32:49 PM PDT 24
Finished Mar 14 01:32:49 PM PDT 24
Peak memory 202388 kb
Host smart-19f04d54-ba5b-4cbb-9dd9-6a4dd8540c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28734
37466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2873437466
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.710745479
Short name T120
Test name
Test status
Simulation time 8414675528 ps
CPU time 7.43 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:51 PM PDT 24
Peak memory 202552 kb
Host smart-096eb6e5-f70a-4dc2-a92b-c13f8700a042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71074
5479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.710745479
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.1183832381
Short name T358
Test name
Test status
Simulation time 8386195383 ps
CPU time 7.17 seconds
Started Mar 14 01:32:43 PM PDT 24
Finished Mar 14 01:32:50 PM PDT 24
Peak memory 202584 kb
Host smart-7cb97813-3231-4d91-9459-9543033fc137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11838
32381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.1183832381
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.546880507
Short name T527
Test name
Test status
Simulation time 8359910388 ps
CPU time 7.19 seconds
Started Mar 14 01:32:42 PM PDT 24
Finished Mar 14 01:32:49 PM PDT 24
Peak memory 202516 kb
Host smart-c5bbc4c0-1f9b-4639-bfe5-162d3c5d02d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54688
0507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.546880507
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.392834670
Short name T381
Test name
Test status
Simulation time 8473382667 ps
CPU time 7.28 seconds
Started Mar 14 01:32:51 PM PDT 24
Finished Mar 14 01:32:58 PM PDT 24
Peak memory 202616 kb
Host smart-30b2be99-3fae-4819-8de6-27b26da5e5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39283
4670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.392834670
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3282704961
Short name T692
Test name
Test status
Simulation time 8365597403 ps
CPU time 7.24 seconds
Started Mar 14 01:32:49 PM PDT 24
Finished Mar 14 01:32:56 PM PDT 24
Peak memory 202472 kb
Host smart-8bae515d-e447-4679-8dce-a092d7aa2748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32827
04961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3282704961
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3777333380
Short name T556
Test name
Test status
Simulation time 197816285 ps
CPU time 2.28 seconds
Started Mar 14 01:32:46 PM PDT 24
Finished Mar 14 01:32:48 PM PDT 24
Peak memory 202668 kb
Host smart-771acc7f-aedd-4ef1-b798-f5c65547091c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37773
33380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3777333380
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.4235966882
Short name T758
Test name
Test status
Simulation time 8360671052 ps
CPU time 7.76 seconds
Started Mar 14 01:32:45 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202532 kb
Host smart-b29bc5bd-7620-4e83-9149-1b2c5b6963a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42359
66882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.4235966882
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3302437446
Short name T30
Test name
Test status
Simulation time 8410107618 ps
CPU time 7.77 seconds
Started Mar 14 01:32:42 PM PDT 24
Finished Mar 14 01:32:50 PM PDT 24
Peak memory 202524 kb
Host smart-5f099f93-9c11-470d-a888-dd6b7d158aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33024
37446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3302437446
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1682627307
Short name T19
Test name
Test status
Simulation time 8411460365 ps
CPU time 7.39 seconds
Started Mar 14 01:32:47 PM PDT 24
Finished Mar 14 01:32:55 PM PDT 24
Peak memory 202472 kb
Host smart-33920d10-0710-4dbe-9d41-5d65b21c14ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16826
27307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1682627307
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3867693986
Short name T494
Test name
Test status
Simulation time 8365610112 ps
CPU time 7.19 seconds
Started Mar 14 01:32:42 PM PDT 24
Finished Mar 14 01:32:50 PM PDT 24
Peak memory 202588 kb
Host smart-7fb40cd0-27b5-4aa0-9a1a-4354f7fabf0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38676
93986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3867693986
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.659452932
Short name T97
Test name
Test status
Simulation time 8385043275 ps
CPU time 8.69 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202544 kb
Host smart-c47bc423-1c98-44b9-b5c2-5ded33be2805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65945
2932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.659452932
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3975954069
Short name T442
Test name
Test status
Simulation time 8382249984 ps
CPU time 7.71 seconds
Started Mar 14 01:32:45 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202512 kb
Host smart-19c423fa-c8e2-4cd4-afe5-333702d251cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759
54069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3975954069
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2135282088
Short name T660
Test name
Test status
Simulation time 8376458436 ps
CPU time 7.83 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:52 PM PDT 24
Peak memory 202580 kb
Host smart-4022327b-d61d-4bf3-995d-589b8ef11b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21352
82088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2135282088
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3160308581
Short name T26
Test name
Test status
Simulation time 26864330 ps
CPU time 0.6 seconds
Started Mar 14 01:32:41 PM PDT 24
Finished Mar 14 01:32:42 PM PDT 24
Peak memory 202468 kb
Host smart-a1c95485-e08c-4ce4-a24f-7718daf7e8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
08581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3160308581
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2214633019
Short name T392
Test name
Test status
Simulation time 8381395208 ps
CPU time 7.29 seconds
Started Mar 14 01:32:43 PM PDT 24
Finished Mar 14 01:32:50 PM PDT 24
Peak memory 202492 kb
Host smart-22229f37-d089-4693-b684-b657749dc310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146
33019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2214633019
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1862884266
Short name T228
Test name
Test status
Simulation time 8371485457 ps
CPU time 7.52 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:52 PM PDT 24
Peak memory 202568 kb
Host smart-af31d01d-6ff4-4605-a9bc-cece8e2ad510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18628
84266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1862884266
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2869232406
Short name T367
Test name
Test status
Simulation time 8362667517 ps
CPU time 7.55 seconds
Started Mar 14 01:32:49 PM PDT 24
Finished Mar 14 01:32:57 PM PDT 24
Peak memory 202500 kb
Host smart-483dd050-671f-404e-b402-86d319d06623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28692
32406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2869232406
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.780506085
Short name T697
Test name
Test status
Simulation time 8368090733 ps
CPU time 8.89 seconds
Started Mar 14 01:32:44 PM PDT 24
Finished Mar 14 01:32:53 PM PDT 24
Peak memory 202548 kb
Host smart-c98108c8-e9ad-4a9f-b507-ff03979c3995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78050
6085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.780506085
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3357648661
Short name T700
Test name
Test status
Simulation time 227051050 ps
CPU time 1.96 seconds
Started Mar 14 01:32:57 PM PDT 24
Finished Mar 14 01:32:59 PM PDT 24
Peak memory 202580 kb
Host smart-79b7e74f-6c45-4031-81f8-a4d5f983086f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33576
48661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3357648661
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1921563409
Short name T179
Test name
Test status
Simulation time 8361750532 ps
CPU time 8.79 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:02 PM PDT 24
Peak memory 202512 kb
Host smart-dfbf98e0-d66e-439a-8258-895c5ad46f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
63409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1921563409
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.668262612
Short name T315
Test name
Test status
Simulation time 8406975604 ps
CPU time 8.83 seconds
Started Mar 14 01:32:52 PM PDT 24
Finished Mar 14 01:33:01 PM PDT 24
Peak memory 202616 kb
Host smart-cab9531c-22d8-4eff-bc1c-4821515174f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66826
2612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.668262612
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2699958185
Short name T511
Test name
Test status
Simulation time 8407507082 ps
CPU time 7.81 seconds
Started Mar 14 01:32:51 PM PDT 24
Finished Mar 14 01:32:59 PM PDT 24
Peak memory 202588 kb
Host smart-5806019b-db0a-479b-8dbe-24be674d8640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26999
58185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2699958185
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.218374057
Short name T652
Test name
Test status
Simulation time 8366461634 ps
CPU time 9.14 seconds
Started Mar 14 01:32:57 PM PDT 24
Finished Mar 14 01:33:06 PM PDT 24
Peak memory 202584 kb
Host smart-6cf94426-d3c5-4d8f-9bff-f266f25e3cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
4057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.218374057
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3209828215
Short name T523
Test name
Test status
Simulation time 8422314383 ps
CPU time 9.56 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 202576 kb
Host smart-5206d273-fb06-4169-bac5-93caaa627976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32098
28215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3209828215
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.4050161086
Short name T577
Test name
Test status
Simulation time 8373243646 ps
CPU time 7.64 seconds
Started Mar 14 01:32:50 PM PDT 24
Finished Mar 14 01:32:58 PM PDT 24
Peak memory 202596 kb
Host smart-59a24376-a693-478e-81bc-42aadbe9f92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40501
61086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.4050161086
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1141793850
Short name T749
Test name
Test status
Simulation time 8390321129 ps
CPU time 7.59 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:01 PM PDT 24
Peak memory 202484 kb
Host smart-1023264d-b036-4185-b866-e6123859f8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11417
93850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1141793850
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2400009132
Short name T416
Test name
Test status
Simulation time 28486794 ps
CPU time 0.7 seconds
Started Mar 14 01:32:50 PM PDT 24
Finished Mar 14 01:32:51 PM PDT 24
Peak memory 202448 kb
Host smart-55699b93-3171-4f2f-812f-d4ba25f78ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24000
09132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2400009132
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.36442107
Short name T734
Test name
Test status
Simulation time 8423702034 ps
CPU time 7.5 seconds
Started Mar 14 01:32:51 PM PDT 24
Finished Mar 14 01:32:59 PM PDT 24
Peak memory 202568 kb
Host smart-d053158e-2123-4bfc-bb00-60968145f125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36442
107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.36442107
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1181236169
Short name T269
Test name
Test status
Simulation time 8391978763 ps
CPU time 8.38 seconds
Started Mar 14 01:32:58 PM PDT 24
Finished Mar 14 01:33:06 PM PDT 24
Peak memory 202596 kb
Host smart-a78119c4-fdf3-47f5-9eb1-f1b2d5a19f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11812
36169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1181236169
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1221488937
Short name T752
Test name
Test status
Simulation time 8359352677 ps
CPU time 7.76 seconds
Started Mar 14 01:32:51 PM PDT 24
Finished Mar 14 01:32:58 PM PDT 24
Peak memory 202568 kb
Host smart-6114df2d-443f-4132-9ed2-26d668daafc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12214
88937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1221488937
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.813065766
Short name T149
Test name
Test status
Simulation time 8474209959 ps
CPU time 9.18 seconds
Started Mar 14 01:32:51 PM PDT 24
Finished Mar 14 01:33:01 PM PDT 24
Peak memory 202600 kb
Host smart-ef66a1f6-9d9d-4281-8fe1-1a198c416491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81306
5766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.813065766
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2564723679
Short name T338
Test name
Test status
Simulation time 8368465633 ps
CPU time 6.99 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:00 PM PDT 24
Peak memory 202584 kb
Host smart-e074dafe-b9f2-4fa7-aa25-ba3a4379f3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25647
23679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2564723679
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2593717470
Short name T422
Test name
Test status
Simulation time 47533091 ps
CPU time 1.38 seconds
Started Mar 14 01:32:58 PM PDT 24
Finished Mar 14 01:32:59 PM PDT 24
Peak memory 202720 kb
Host smart-892f7b3c-15af-489a-aaf7-b68fbe7105d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25937
17470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2593717470
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2881825989
Short name T166
Test name
Test status
Simulation time 8363640212 ps
CPU time 8.91 seconds
Started Mar 14 01:32:56 PM PDT 24
Finished Mar 14 01:33:05 PM PDT 24
Peak memory 202552 kb
Host smart-d92f6c31-ccab-41b0-a142-ab112b6563c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28818
25989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2881825989
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3381879494
Short name T211
Test name
Test status
Simulation time 8430729516 ps
CPU time 7.94 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:01 PM PDT 24
Peak memory 202552 kb
Host smart-895c6916-4335-4e11-950a-2a3da4bc9d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33818
79494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3381879494
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3898438414
Short name T319
Test name
Test status
Simulation time 8405806418 ps
CPU time 8.08 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:01 PM PDT 24
Peak memory 202596 kb
Host smart-2f5d6ec3-997b-4580-ad93-68fcc353e85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38984
38414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3898438414
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.804044003
Short name T353
Test name
Test status
Simulation time 8360674877 ps
CPU time 8.05 seconds
Started Mar 14 01:32:51 PM PDT 24
Finished Mar 14 01:32:59 PM PDT 24
Peak memory 202584 kb
Host smart-4b048f3e-e386-4449-9977-8854344f01f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80404
4003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.804044003
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1411284797
Short name T21
Test name
Test status
Simulation time 8376224040 ps
CPU time 8.64 seconds
Started Mar 14 01:32:50 PM PDT 24
Finished Mar 14 01:32:59 PM PDT 24
Peak memory 202576 kb
Host smart-28771c2c-d354-4a23-9cfe-325aaadd2809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14112
84797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1411284797
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.353590072
Short name T728
Test name
Test status
Simulation time 8384113856 ps
CPU time 8.41 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 202508 kb
Host smart-2784ee59-c3c6-455a-ae34-59741ff9cd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35359
0072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.353590072
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2504863125
Short name T478
Test name
Test status
Simulation time 31786793 ps
CPU time 0.65 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:32:55 PM PDT 24
Peak memory 202456 kb
Host smart-7365d043-eba9-4b54-bbfa-7a60dec4b5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25048
63125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2504863125
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.701628572
Short name T28
Test name
Test status
Simulation time 8385220039 ps
CPU time 7.23 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:02 PM PDT 24
Peak memory 202548 kb
Host smart-908c42c0-69d3-4f43-a965-4dae44c3ef07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70162
8572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.701628572
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3803435983
Short name T343
Test name
Test status
Simulation time 8372449360 ps
CPU time 9.1 seconds
Started Mar 14 01:32:54 PM PDT 24
Finished Mar 14 01:33:04 PM PDT 24
Peak memory 202576 kb
Host smart-91b62c2c-0146-4cc6-8b71-be89e15d1467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38034
35983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3803435983
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3767350386
Short name T687
Test name
Test status
Simulation time 8362407018 ps
CPU time 8.03 seconds
Started Mar 14 01:32:52 PM PDT 24
Finished Mar 14 01:33:00 PM PDT 24
Peak memory 202504 kb
Host smart-887b8b60-0eac-49e9-ad8c-b557c0038189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
50386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3767350386
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3325173569
Short name T152
Test name
Test status
Simulation time 8480559554 ps
CPU time 8.05 seconds
Started Mar 14 01:32:57 PM PDT 24
Finished Mar 14 01:33:05 PM PDT 24
Peak memory 202612 kb
Host smart-d69170dd-aaf9-4e83-800b-8436417faee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33251
73569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3325173569
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1357411956
Short name T317
Test name
Test status
Simulation time 8369257997 ps
CPU time 7.62 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:02 PM PDT 24
Peak memory 202540 kb
Host smart-e4cc045b-949d-45f6-a5b4-b413bd77b587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13574
11956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1357411956
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3962902132
Short name T369
Test name
Test status
Simulation time 52344619 ps
CPU time 1.39 seconds
Started Mar 14 01:32:56 PM PDT 24
Finished Mar 14 01:32:58 PM PDT 24
Peak memory 202708 kb
Host smart-4febf9c8-3225-45a0-abc0-5fcbb3b43031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39629
02132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3962902132
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3581125760
Short name T163
Test name
Test status
Simulation time 8363392881 ps
CPU time 8.09 seconds
Started Mar 14 01:32:57 PM PDT 24
Finished Mar 14 01:33:05 PM PDT 24
Peak memory 202468 kb
Host smart-55021313-a19e-4f1d-b7ab-5b4d50a568e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35811
25760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3581125760
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1614976448
Short name T686
Test name
Test status
Simulation time 8404990270 ps
CPU time 7.83 seconds
Started Mar 14 01:32:52 PM PDT 24
Finished Mar 14 01:33:00 PM PDT 24
Peak memory 202640 kb
Host smart-2fd04dc3-5806-48fc-ab68-72728466707b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16149
76448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1614976448
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2421697944
Short name T624
Test name
Test status
Simulation time 8411567486 ps
CPU time 7.69 seconds
Started Mar 14 01:32:58 PM PDT 24
Finished Mar 14 01:33:05 PM PDT 24
Peak memory 202560 kb
Host smart-6cc1cf7b-3daf-45e3-8e0a-72b0f00be802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24216
97944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2421697944
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.115429771
Short name T669
Test name
Test status
Simulation time 8360455348 ps
CPU time 7.22 seconds
Started Mar 14 01:32:52 PM PDT 24
Finished Mar 14 01:32:59 PM PDT 24
Peak memory 202472 kb
Host smart-e6085d36-390e-44aa-a99a-8457f43e32f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11542
9771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.115429771
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2212218721
Short name T101
Test name
Test status
Simulation time 8423971528 ps
CPU time 8.66 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:04 PM PDT 24
Peak memory 202508 kb
Host smart-f9cf79c3-42c9-40cf-82b2-f9c560874bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22122
18721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2212218721
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3025864294
Short name T445
Test name
Test status
Simulation time 8400517628 ps
CPU time 8.18 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:02 PM PDT 24
Peak memory 202556 kb
Host smart-06aec384-1605-49ce-a8b6-178898529c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30258
64294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3025864294
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3844762124
Short name T550
Test name
Test status
Simulation time 8388449311 ps
CPU time 8.35 seconds
Started Mar 14 01:32:54 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 202536 kb
Host smart-8d293bb9-d1a4-4b6f-8b09-0d64b394fbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38447
62124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3844762124
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2650182219
Short name T605
Test name
Test status
Simulation time 33143717 ps
CPU time 0.68 seconds
Started Mar 14 01:32:57 PM PDT 24
Finished Mar 14 01:32:58 PM PDT 24
Peak memory 202456 kb
Host smart-3d746582-1ff1-4cc2-b40e-1647d00376d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26501
82219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2650182219
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3828389485
Short name T219
Test name
Test status
Simulation time 8419395474 ps
CPU time 7.36 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 202448 kb
Host smart-d214ec60-7573-4e8e-b0d2-c3df682f2f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38283
89485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3828389485
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2839488767
Short name T204
Test name
Test status
Simulation time 8368942332 ps
CPU time 9.49 seconds
Started Mar 14 01:32:54 PM PDT 24
Finished Mar 14 01:33:04 PM PDT 24
Peak memory 202532 kb
Host smart-2b045c70-a375-41d3-a41c-3d8691fb0f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28394
88767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2839488767
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1944685438
Short name T357
Test name
Test status
Simulation time 8356306362 ps
CPU time 7.77 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 202536 kb
Host smart-ef91f540-f24d-4ddb-b0aa-6a27072776d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19446
85438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1944685438
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.846685891
Short name T603
Test name
Test status
Simulation time 8479319984 ps
CPU time 7.74 seconds
Started Mar 14 01:32:57 PM PDT 24
Finished Mar 14 01:33:05 PM PDT 24
Peak memory 202576 kb
Host smart-280a451d-9fd8-417b-a08e-1636b7dd8764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84668
5891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.846685891
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.178551150
Short name T620
Test name
Test status
Simulation time 8372089754 ps
CPU time 8.78 seconds
Started Mar 14 01:32:57 PM PDT 24
Finished Mar 14 01:33:06 PM PDT 24
Peak memory 202592 kb
Host smart-5a1971e7-4c42-4c92-b00d-45fd2a45e60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17855
1150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.178551150
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.218822755
Short name T311
Test name
Test status
Simulation time 101523120 ps
CPU time 1.28 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:32:56 PM PDT 24
Peak memory 202652 kb
Host smart-a7297607-1a05-4739-bd26-c4afca50f80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21882
2755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.218822755
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2337610092
Short name T682
Test name
Test status
Simulation time 8356700918 ps
CPU time 9.61 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:05 PM PDT 24
Peak memory 202548 kb
Host smart-492047b1-dadf-4c6c-880a-2341f09da54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23376
10092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2337610092
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1548182359
Short name T112
Test name
Test status
Simulation time 8418121301 ps
CPU time 7.91 seconds
Started Mar 14 01:32:56 PM PDT 24
Finished Mar 14 01:33:04 PM PDT 24
Peak memory 202468 kb
Host smart-e7c0e0bd-cd25-4b87-abeb-97c13c973705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481
82359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1548182359
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3803300726
Short name T635
Test name
Test status
Simulation time 8404463682 ps
CPU time 8.03 seconds
Started Mar 14 01:32:56 PM PDT 24
Finished Mar 14 01:33:04 PM PDT 24
Peak memory 202468 kb
Host smart-5924f7ed-84b8-4fd9-8bc9-7d0f13ab92af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38033
00726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3803300726
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3596260073
Short name T644
Test name
Test status
Simulation time 8362491533 ps
CPU time 7.74 seconds
Started Mar 14 01:32:50 PM PDT 24
Finished Mar 14 01:32:58 PM PDT 24
Peak memory 202456 kb
Host smart-79dfd900-b189-4eba-8430-ada96826595f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35962
60073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3596260073
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2523068065
Short name T78
Test name
Test status
Simulation time 8405438163 ps
CPU time 9.88 seconds
Started Mar 14 01:32:50 PM PDT 24
Finished Mar 14 01:33:00 PM PDT 24
Peak memory 202596 kb
Host smart-d94e00d9-366e-4c31-9232-c7b33fbb7f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25230
68065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2523068065
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3571295047
Short name T205
Test name
Test status
Simulation time 8361382779 ps
CPU time 8.43 seconds
Started Mar 14 01:32:52 PM PDT 24
Finished Mar 14 01:33:00 PM PDT 24
Peak memory 202552 kb
Host smart-a06880f0-5225-43af-a669-b0ab1a7ca5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
95047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3571295047
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1455913818
Short name T525
Test name
Test status
Simulation time 8398440349 ps
CPU time 7.36 seconds
Started Mar 14 01:32:56 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 202564 kb
Host smart-c891a7a2-c142-4822-8b49-cbab3198565e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14559
13818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1455913818
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2189735689
Short name T695
Test name
Test status
Simulation time 26989616 ps
CPU time 0.62 seconds
Started Mar 14 01:32:54 PM PDT 24
Finished Mar 14 01:32:55 PM PDT 24
Peak memory 202472 kb
Host smart-2d695469-11e2-4dbb-b78e-029788618f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897
35689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2189735689
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2771586432
Short name T297
Test name
Test status
Simulation time 8415365518 ps
CPU time 7.76 seconds
Started Mar 14 01:32:55 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 202548 kb
Host smart-d530f5ac-cc94-4e09-9172-1831177ff6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
86432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2771586432
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.1557430722
Short name T260
Test name
Test status
Simulation time 8369686313 ps
CPU time 7.3 seconds
Started Mar 14 01:32:53 PM PDT 24
Finished Mar 14 01:33:01 PM PDT 24
Peak memory 202576 kb
Host smart-87ab3afc-9b0a-4afd-ba7a-d51d3870f104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15574
30722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.1557430722
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.4151362976
Short name T657
Test name
Test status
Simulation time 8359380180 ps
CPU time 9.77 seconds
Started Mar 14 01:32:57 PM PDT 24
Finished Mar 14 01:33:06 PM PDT 24
Peak memory 202552 kb
Host smart-319c0b60-f57e-4755-b702-21378af084ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41513
62976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.4151362976
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3660774128
Short name T410
Test name
Test status
Simulation time 8472512842 ps
CPU time 7.47 seconds
Started Mar 14 01:32:56 PM PDT 24
Finished Mar 14 01:33:04 PM PDT 24
Peak memory 202580 kb
Host smart-b9f98904-ea74-47bf-8b63-236b94b68324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36607
74128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3660774128
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.107018252
Short name T308
Test name
Test status
Simulation time 8367371715 ps
CPU time 7.31 seconds
Started Mar 14 01:30:32 PM PDT 24
Finished Mar 14 01:30:40 PM PDT 24
Peak memory 202004 kb
Host smart-575c2415-dfeb-4c3d-b3ea-f231bc9c2807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701
8252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.107018252
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.91016933
Short name T208
Test name
Test status
Simulation time 73753572 ps
CPU time 1.06 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:28 PM PDT 24
Peak memory 202632 kb
Host smart-1cd17dc7-1f09-4b9d-9c89-dd750498e7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91016
933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.91016933
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2208065399
Short name T456
Test name
Test status
Simulation time 8363544876 ps
CPU time 8.34 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 202536 kb
Host smart-e6b4e2ba-2685-4239-9ee5-3124ef8198dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22080
65399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2208065399
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1059848523
Short name T715
Test name
Test status
Simulation time 8372665817 ps
CPU time 7.12 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202524 kb
Host smart-da0e854a-6446-42ef-877e-17a284eef7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10598
48523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1059848523
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2855073532
Short name T602
Test name
Test status
Simulation time 8405966880 ps
CPU time 7.48 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:36 PM PDT 24
Peak memory 202508 kb
Host smart-f405bd45-35f2-41b9-934a-904d9a9e2b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28550
73532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2855073532
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2379707130
Short name T703
Test name
Test status
Simulation time 8362398944 ps
CPU time 7.33 seconds
Started Mar 14 01:30:33 PM PDT 24
Finished Mar 14 01:30:41 PM PDT 24
Peak memory 202528 kb
Host smart-2017db56-4c93-4faf-9f5b-cdbd7d801eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23797
07130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2379707130
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3581385886
Short name T100
Test name
Test status
Simulation time 8432933999 ps
CPU time 7.21 seconds
Started Mar 14 01:30:27 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 202548 kb
Host smart-0169fd21-8509-48af-818c-a8aa2eb8b553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
85886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3581385886
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1993899051
Short name T606
Test name
Test status
Simulation time 8403324972 ps
CPU time 7.95 seconds
Started Mar 14 01:30:35 PM PDT 24
Finished Mar 14 01:30:45 PM PDT 24
Peak memory 202580 kb
Host smart-f125c932-aebb-4c35-beb0-13c94fe56323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19938
99051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1993899051
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3932766566
Short name T532
Test name
Test status
Simulation time 8381546161 ps
CPU time 7.33 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202596 kb
Host smart-c4047947-61ce-4e74-8464-fc9d758ad862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39327
66566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3932766566
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3559485344
Short name T31
Test name
Test status
Simulation time 23365434 ps
CPU time 0.63 seconds
Started Mar 14 01:30:37 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202460 kb
Host smart-0a99d8f1-7253-45d2-b029-7efe76b6df96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
85344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3559485344
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.581955129
Short name T127
Test name
Test status
Simulation time 8377226469 ps
CPU time 8.26 seconds
Started Mar 14 01:30:36 PM PDT 24
Finished Mar 14 01:30:45 PM PDT 24
Peak memory 202584 kb
Host smart-89b6a7e8-94d3-4509-9dbb-354a1b19a2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58195
5129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.581955129
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.3079695944
Short name T265
Test name
Test status
Simulation time 8403131033 ps
CPU time 8.18 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202472 kb
Host smart-57533dfd-0c93-4e3b-8af4-b694fe0108ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30796
95944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.3079695944
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1249984075
Short name T533
Test name
Test status
Simulation time 8358732109 ps
CPU time 7.12 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202528 kb
Host smart-50b5eae9-4aa8-4779-a0b4-1386754dab53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12499
84075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1249984075
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3757462673
Short name T137
Test name
Test status
Simulation time 8484001873 ps
CPU time 9.55 seconds
Started Mar 14 01:30:28 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 202564 kb
Host smart-46e6cf95-2c41-49f6-b95d-c3205d55ac10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574
62673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3757462673
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3081417442
Short name T370
Test name
Test status
Simulation time 8366565370 ps
CPU time 7.39 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202564 kb
Host smart-8b9db252-9ed5-4294-85ed-b65534174506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30814
17442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3081417442
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1251843037
Short name T429
Test name
Test status
Simulation time 34690003 ps
CPU time 0.97 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:41 PM PDT 24
Peak memory 202720 kb
Host smart-4c2227ab-7c3b-4e70-a0f8-be22409d37dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12518
43037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1251843037
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2117802243
Short name T625
Test name
Test status
Simulation time 8357449529 ps
CPU time 8.23 seconds
Started Mar 14 01:30:41 PM PDT 24
Finished Mar 14 01:30:49 PM PDT 24
Peak memory 202532 kb
Host smart-a3ff0862-3aa0-4b0d-a0b9-c62fa89344d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21178
02243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2117802243
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3871728861
Short name T658
Test name
Test status
Simulation time 8416020983 ps
CPU time 9.47 seconds
Started Mar 14 01:30:38 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 202540 kb
Host smart-f06bb9db-fe47-432c-9582-6c68dd8a9b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
28861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3871728861
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1197399883
Short name T542
Test name
Test status
Simulation time 8409732839 ps
CPU time 8.41 seconds
Started Mar 14 01:30:36 PM PDT 24
Finished Mar 14 01:30:45 PM PDT 24
Peak memory 202496 kb
Host smart-5a1a9b04-9d5b-434b-b5bb-f0dd9a62579d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11973
99883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1197399883
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.393407232
Short name T408
Test name
Test status
Simulation time 8362271031 ps
CPU time 7.13 seconds
Started Mar 14 01:30:38 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202568 kb
Host smart-8e0e12cd-5acd-4678-8321-07df8ceb34d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39340
7232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.393407232
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.4035138389
Short name T91
Test name
Test status
Simulation time 8405773965 ps
CPU time 8.29 seconds
Started Mar 14 01:30:37 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202432 kb
Host smart-9785c10f-7000-4a93-bb84-b5fb78dc3f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40351
38389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.4035138389
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.626697970
Short name T656
Test name
Test status
Simulation time 8399589041 ps
CPU time 8.75 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 202468 kb
Host smart-ee2cb7de-f342-4605-87d3-1ffa656d5874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62669
7970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.626697970
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.415841573
Short name T759
Test name
Test status
Simulation time 8392571524 ps
CPU time 7.84 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 202476 kb
Host smart-f4cf59e5-3725-4f3a-bc92-9c1cca9d859b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41584
1573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.415841573
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.679475883
Short name T589
Test name
Test status
Simulation time 29393930 ps
CPU time 0.64 seconds
Started Mar 14 01:30:36 PM PDT 24
Finished Mar 14 01:30:37 PM PDT 24
Peak memory 202500 kb
Host smart-2a2efb1b-2f9b-4527-bad6-7849a1ab834c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67947
5883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.679475883
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3051751293
Short name T495
Test name
Test status
Simulation time 8403756303 ps
CPU time 8.42 seconds
Started Mar 14 01:30:41 PM PDT 24
Finished Mar 14 01:30:50 PM PDT 24
Peak memory 202532 kb
Host smart-7eeb5bde-df12-42e1-a421-c3b0e39f89ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30517
51293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3051751293
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.1444506781
Short name T257
Test name
Test status
Simulation time 8370310679 ps
CPU time 7.28 seconds
Started Mar 14 01:30:38 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202352 kb
Host smart-717eadc5-e7c8-45ad-911e-ee3c183d866a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14445
06781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.1444506781
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1514935353
Short name T310
Test name
Test status
Simulation time 8359949063 ps
CPU time 7.18 seconds
Started Mar 14 01:30:38 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202548 kb
Host smart-93295fb5-3071-4250-aedf-f6165e17813a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15149
35353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1514935353
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.2483390364
Short name T689
Test name
Test status
Simulation time 8474533623 ps
CPU time 7.5 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202572 kb
Host smart-0173fa9a-cdea-411e-aa23-46f1b997735d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24833
90364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2483390364
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2834060368
Short name T335
Test name
Test status
Simulation time 8371315907 ps
CPU time 8.62 seconds
Started Mar 14 01:30:38 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202404 kb
Host smart-375e4a00-c6fa-4993-b549-4855aea9e06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28340
60368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2834060368
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3832998167
Short name T307
Test name
Test status
Simulation time 50162935 ps
CPU time 1.3 seconds
Started Mar 14 01:30:42 PM PDT 24
Finished Mar 14 01:30:43 PM PDT 24
Peak memory 202764 kb
Host smart-fcad4955-4d55-4862-8b18-9be43959bcc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38329
98167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3832998167
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2654052371
Short name T756
Test name
Test status
Simulation time 8358083254 ps
CPU time 8.85 seconds
Started Mar 14 01:30:36 PM PDT 24
Finished Mar 14 01:30:45 PM PDT 24
Peak memory 202528 kb
Host smart-f696554f-d236-4ca9-8d59-eaf69c9837db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26540
52371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2654052371
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.4027991533
Short name T128
Test name
Test status
Simulation time 8423149147 ps
CPU time 7.77 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 202416 kb
Host smart-a6ec81af-c3a2-4289-b622-6af2bf912a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40279
91533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.4027991533
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2029937491
Short name T543
Test name
Test status
Simulation time 8409180455 ps
CPU time 7.58 seconds
Started Mar 14 01:30:37 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202576 kb
Host smart-7de6f212-d0ec-4ab8-ae39-9952978d3d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20299
37491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2029937491
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2955435450
Short name T518
Test name
Test status
Simulation time 8366002185 ps
CPU time 7.87 seconds
Started Mar 14 01:30:38 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202588 kb
Host smart-24a37348-077f-49d8-b3a6-4b8ed979db38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29554
35450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2955435450
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3470440857
Short name T13
Test name
Test status
Simulation time 8446029717 ps
CPU time 9.92 seconds
Started Mar 14 01:30:38 PM PDT 24
Finished Mar 14 01:30:49 PM PDT 24
Peak memory 202488 kb
Host smart-68e3f9e5-7bb1-43c1-b826-e9a2829c309a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34704
40857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3470440857
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2816665015
Short name T393
Test name
Test status
Simulation time 8379148236 ps
CPU time 7.46 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202448 kb
Host smart-e7588604-bc61-4190-843f-f292b0161c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28166
65015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2816665015
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3382688082
Short name T585
Test name
Test status
Simulation time 8401895604 ps
CPU time 8.19 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 202576 kb
Host smart-5db88eac-21da-4b79-8bd8-9e3f1173d043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33826
88082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3382688082
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.312313094
Short name T374
Test name
Test status
Simulation time 31540767 ps
CPU time 0.63 seconds
Started Mar 14 01:30:42 PM PDT 24
Finished Mar 14 01:30:42 PM PDT 24
Peak memory 202504 kb
Host smart-da9dcedb-5b6e-4e60-8ee3-0df7b7b25c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31231
3094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.312313094
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.2310201098
Short name T469
Test name
Test status
Simulation time 8408912220 ps
CPU time 8.39 seconds
Started Mar 14 01:30:50 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 202560 kb
Host smart-96141da7-4f09-419e-8a12-4283b07ae5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23102
01098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2310201098
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1704662791
Short name T674
Test name
Test status
Simulation time 8396178920 ps
CPU time 7.46 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202568 kb
Host smart-0caad387-bb25-46af-b04f-eff54bc14651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17046
62791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1704662791
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2071721619
Short name T666
Test name
Test status
Simulation time 8361527199 ps
CPU time 7.39 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202580 kb
Host smart-61939801-8226-4abf-b483-ee4b6c88de79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20717
21619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2071721619
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3627033841
Short name T40
Test name
Test status
Simulation time 8475154978 ps
CPU time 9.98 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:50 PM PDT 24
Peak memory 202568 kb
Host smart-53719190-0159-4e99-9762-2589e722a251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36270
33841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3627033841
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3463012248
Short name T36
Test name
Test status
Simulation time 8370028163 ps
CPU time 7.22 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 202592 kb
Host smart-e57eb789-67d1-4dc4-be44-27a87dc72b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34630
12248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3463012248
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1618612663
Short name T279
Test name
Test status
Simulation time 68143229 ps
CPU time 1.89 seconds
Started Mar 14 01:30:44 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202768 kb
Host smart-6b2927d9-dd0f-4ba8-8dea-0e6cbe6adc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16186
12663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1618612663
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3036273853
Short name T175
Test name
Test status
Simulation time 8363005423 ps
CPU time 7.72 seconds
Started Mar 14 01:30:46 PM PDT 24
Finished Mar 14 01:30:54 PM PDT 24
Peak memory 202556 kb
Host smart-e337f27c-bbf5-4a26-9c96-76d82fa9005f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30362
73853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3036273853
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.948942272
Short name T484
Test name
Test status
Simulation time 8383924296 ps
CPU time 8.1 seconds
Started Mar 14 01:30:44 PM PDT 24
Finished Mar 14 01:30:52 PM PDT 24
Peak memory 202576 kb
Host smart-c1ccd4bd-b89c-451c-b73b-72ab35b933c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94894
2272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.948942272
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.333681216
Short name T747
Test name
Test status
Simulation time 8411807203 ps
CPU time 8.86 seconds
Started Mar 14 01:30:39 PM PDT 24
Finished Mar 14 01:30:49 PM PDT 24
Peak memory 202532 kb
Host smart-975cf880-9399-48b3-9eb1-92315a21d2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33368
1216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.333681216
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1663172991
Short name T272
Test name
Test status
Simulation time 8366594276 ps
CPU time 9.18 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:50 PM PDT 24
Peak memory 202532 kb
Host smart-65c076ef-adac-47fc-9e47-51f7ad087d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16631
72991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1663172991
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.564210498
Short name T90
Test name
Test status
Simulation time 8417189387 ps
CPU time 8.34 seconds
Started Mar 14 01:30:44 PM PDT 24
Finished Mar 14 01:30:52 PM PDT 24
Peak memory 202576 kb
Host smart-a0e77726-24d6-48b9-9de3-7c779d756a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56421
0498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.564210498
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.438229579
Short name T534
Test name
Test status
Simulation time 8381621309 ps
CPU time 9.95 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:50 PM PDT 24
Peak memory 202504 kb
Host smart-b812d014-ebac-4d0b-8df1-77092fad1000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43822
9579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.438229579
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.561856697
Short name T352
Test name
Test status
Simulation time 8380104762 ps
CPU time 9.28 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:50 PM PDT 24
Peak memory 202524 kb
Host smart-3f49bb72-8377-4a65-b2f6-8c7c4c34d14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56185
6697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.561856697
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2968366410
Short name T677
Test name
Test status
Simulation time 32726365 ps
CPU time 0.62 seconds
Started Mar 14 01:30:44 PM PDT 24
Finished Mar 14 01:30:45 PM PDT 24
Peak memory 202520 kb
Host smart-3907cd51-cac9-457f-9712-3eb267b4fd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29683
66410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2968366410
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.133922829
Short name T220
Test name
Test status
Simulation time 8427173286 ps
CPU time 7.62 seconds
Started Mar 14 01:30:41 PM PDT 24
Finished Mar 14 01:30:49 PM PDT 24
Peak memory 202444 kb
Host smart-f0b517b2-d2f0-4ba3-9992-9a3370884373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13392
2829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.133922829
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3651528889
Short name T277
Test name
Test status
Simulation time 8371854529 ps
CPU time 8.34 seconds
Started Mar 14 01:30:46 PM PDT 24
Finished Mar 14 01:30:55 PM PDT 24
Peak memory 202496 kb
Host smart-e8424454-487c-4bfe-b0b3-2138fde9b164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36515
28889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3651528889
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2309095717
Short name T449
Test name
Test status
Simulation time 8361662985 ps
CPU time 7.44 seconds
Started Mar 14 01:30:41 PM PDT 24
Finished Mar 14 01:30:49 PM PDT 24
Peak memory 202452 kb
Host smart-f1c3e203-f17e-4fd3-8fd3-c7ce7948a40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23090
95717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2309095717
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1483057117
Short name T138
Test name
Test status
Simulation time 8473650353 ps
CPU time 7.66 seconds
Started Mar 14 01:30:40 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 202620 kb
Host smart-2704ba7e-6d92-4900-8831-58d0e79ef015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14830
57117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1483057117
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.4071126196
Short name T647
Test name
Test status
Simulation time 8373821977 ps
CPU time 7.38 seconds
Started Mar 14 01:30:45 PM PDT 24
Finished Mar 14 01:30:53 PM PDT 24
Peak memory 202580 kb
Host smart-6670f8f3-8236-4339-9c90-222835879a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40711
26196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.4071126196
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1413041743
Short name T222
Test name
Test status
Simulation time 168193238 ps
CPU time 1.86 seconds
Started Mar 14 01:30:46 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 202700 kb
Host smart-be2aea34-a1f3-43f2-9629-71ef99863db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14130
41743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1413041743
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1516835221
Short name T616
Test name
Test status
Simulation time 8357658227 ps
CPU time 9.79 seconds
Started Mar 14 01:30:50 PM PDT 24
Finished Mar 14 01:31:00 PM PDT 24
Peak memory 202568 kb
Host smart-aa3151d5-90dd-43e4-848a-87d85018a357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15168
35221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1516835221
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3476278895
Short name T326
Test name
Test status
Simulation time 8437788529 ps
CPU time 7.67 seconds
Started Mar 14 01:30:48 PM PDT 24
Finished Mar 14 01:30:55 PM PDT 24
Peak memory 202568 kb
Host smart-25406e35-d40e-4a8d-849b-3b8b5756c566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34762
78895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3476278895
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.245883579
Short name T7
Test name
Test status
Simulation time 8409655359 ps
CPU time 7.19 seconds
Started Mar 14 01:30:37 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 202600 kb
Host smart-60e458c4-d451-43a2-b1b3-f698aa75c5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24588
3579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.245883579
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2571075316
Short name T665
Test name
Test status
Simulation time 8365565784 ps
CPU time 7.47 seconds
Started Mar 14 01:30:45 PM PDT 24
Finished Mar 14 01:30:53 PM PDT 24
Peak memory 202584 kb
Host smart-e90e53b5-9342-4b31-9a05-f1f213eae05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25710
75316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2571075316
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1565643021
Short name T80
Test name
Test status
Simulation time 8436967915 ps
CPU time 8.36 seconds
Started Mar 14 01:30:45 PM PDT 24
Finished Mar 14 01:30:53 PM PDT 24
Peak memory 202560 kb
Host smart-69fe1379-fa8e-4d26-9332-1812657c0eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15656
43021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1565643021
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2553214667
Short name T712
Test name
Test status
Simulation time 8377285631 ps
CPU time 8.8 seconds
Started Mar 14 01:30:53 PM PDT 24
Finished Mar 14 01:31:02 PM PDT 24
Peak memory 202448 kb
Host smart-10b6cefc-af06-4598-a128-57a68f4abfd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25532
14667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2553214667
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2037358041
Short name T209
Test name
Test status
Simulation time 8383478479 ps
CPU time 9.43 seconds
Started Mar 14 01:30:52 PM PDT 24
Finished Mar 14 01:31:01 PM PDT 24
Peak memory 202436 kb
Host smart-f315f1de-59bb-4efd-8ecd-730d53a31d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373
58041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2037358041
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.100388677
Short name T735
Test name
Test status
Simulation time 29533478 ps
CPU time 0.67 seconds
Started Mar 14 01:30:51 PM PDT 24
Finished Mar 14 01:30:52 PM PDT 24
Peak memory 202436 kb
Host smart-0b6ae070-7eb0-4db0-869d-bc241fcd4049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10038
8677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.100388677
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.291068499
Short name T122
Test name
Test status
Simulation time 8414964788 ps
CPU time 8.26 seconds
Started Mar 14 01:30:49 PM PDT 24
Finished Mar 14 01:30:57 PM PDT 24
Peak memory 202564 kb
Host smart-76e54f51-dfc9-4491-a887-dd56b46c3d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106
8499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.291068499
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3556687437
Short name T591
Test name
Test status
Simulation time 8362748520 ps
CPU time 8.25 seconds
Started Mar 14 01:30:49 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 202532 kb
Host smart-2b246d9c-dc39-4d96-baaf-ed09e08b1e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35566
87437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3556687437
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2391404227
Short name T632
Test name
Test status
Simulation time 8362698977 ps
CPU time 7.24 seconds
Started Mar 14 01:30:55 PM PDT 24
Finished Mar 14 01:31:02 PM PDT 24
Peak memory 202544 kb
Host smart-2e7e5bdd-bf6f-4bc7-95bc-2c41b4f11d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23914
04227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2391404227
Directory /workspace/9.usbdev_setup_trans_ignored/latest
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