Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2556	1		T1	4		T2	2		T3	4
all_values[1]	2556	1		T1	4		T2	2		T3	4
all_values[2]	2556	1		T1	4		T2	2		T3	4
all_values[3]	2556	1		T1	4		T2	2		T3	4
all_values[4]	2556	1		T1	4		T2	2		T3	4
all_values[5]	2556	1		T1	4		T2	2		T3	4
all_values[6]	2556	1		T1	4		T2	2		T3	4
all_values[7]	2556	1		T1	4		T2	2		T3	4
all_values[8]	2556	1		T1	4		T2	2		T3	4
all_values[9]	2556	1		T1	4		T2	2		T3	4
all_values[10]	2556	1		T1	4		T2	2		T3	4
all_values[11]	2556	1		T1	4		T2	2		T3	4
all_values[12]	2556	1		T1	4		T2	2		T3	4
all_values[13]	2556	1		T1	4		T2	2		T3	4
all_values[14]	2556	1		T1	4		T2	2		T3	4
all_values[15]	2556	1		T1	4		T2	2		T3	4
all_values[16]	2556	1		T1	4		T2	2		T3	4
all_values[17]	2556	1		T1	4		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43912	1		T1	72		T2	36		T3	72
auto[1]	2096	1		T5	3		T7	3		T11	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43405	1		T1	72		T2	36		T3	72
auto[1]	2603	1		T73	67		T75	72		T76	67

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2153	1		T1	4		T2	2		T3	4
all_values[0]	auto[0]	auto[1]	61	1		T73	3		T77	4		T255	2
all_values[0]	auto[1]	auto[0]	265	1		T11	2		T12	3		T13	3
all_values[0]	auto[1]	auto[1]	77	1		T73	1		T75	3		T77	3
all_values[1]	auto[0]	auto[0]	2131	1		T1	4		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	73	1		T73	4		T75	2		T76	3
all_values[1]	auto[1]	auto[0]	275	1		T5	3		T7	3		T22	2
all_values[1]	auto[1]	auto[1]	77	1		T73	1		T75	3		T76	1
all_values[2]	auto[0]	auto[0]	2393	1		T1	4		T2	2		T3	4
all_values[2]	auto[0]	auto[1]	74	1		T73	1		T75	4		T76	1
all_values[2]	auto[1]	auto[0]	12	1		T81	4		T255	1		T80	1
all_values[2]	auto[1]	auto[1]	77	1		T73	4		T76	3		T78	4
all_values[3]	auto[0]	auto[0]	2392	1		T1	4		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	66	1		T73	5		T76	3		T77	3
all_values[3]	auto[1]	auto[0]	22	1		T75	1		T77	1		T78	5
all_values[3]	auto[1]	auto[1]	76	1		T75	4		T76	1		T77	4
all_values[4]	auto[0]	auto[0]	2391	1		T1	4		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	71	1		T73	4		T75	3		T76	3
all_values[4]	auto[1]	auto[0]	6	1		T81	1		T78	1		T256	1
all_values[4]	auto[1]	auto[1]	88	1		T73	1		T75	1		T76	1
all_values[5]	auto[0]	auto[0]	2413	1		T1	4		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	62	1		T75	1		T77	1		T78	1
all_values[5]	auto[1]	auto[0]	14	1		T73	1		T76	1		T81	1
all_values[5]	auto[1]	auto[1]	67	1		T75	3		T77	6		T78	4
all_values[6]	auto[0]	auto[0]	2396	1		T1	4		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	79	1		T73	4		T75	2		T76	3
all_values[6]	auto[1]	auto[0]	9	1		T257	2		T80	4		T258	2
all_values[6]	auto[1]	auto[1]	72	1		T73	1		T75	3		T76	2
all_values[7]	auto[0]	auto[0]	2396	1		T1	4		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	68	1		T75	4		T77	2		T81	4
all_values[7]	auto[1]	auto[0]	13	1		T73	3		T81	1		T257	3
all_values[7]	auto[1]	auto[1]	79	1		T75	1		T76	5		T77	4
all_values[8]	auto[0]	auto[0]	2389	1		T1	4		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	74	1		T75	4		T76	4		T77	2
all_values[8]	auto[1]	auto[0]	10	1		T73	1		T255	1		T256	1
all_values[8]	auto[1]	auto[1]	83	1		T73	4		T76	1		T77	6
all_values[9]	auto[0]	auto[0]	2400	1		T1	4		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	72	1		T73	4		T75	3		T76	4
all_values[9]	auto[1]	auto[0]	17	1		T75	1		T81	4		T255	2
all_values[9]	auto[1]	auto[1]	67	1		T73	1		T77	3		T78	3
all_values[10]	auto[0]	auto[0]	2388	1		T1	4		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	77	1		T73	3		T76	2		T77	1
all_values[10]	auto[1]	auto[0]	24	1		T73	1		T75	1		T77	4
all_values[10]	auto[1]	auto[1]	67	1		T75	4		T76	3		T77	3
all_values[11]	auto[0]	auto[0]	2397	1		T1	4		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	73	1		T76	1		T77	5		T81	4
all_values[11]	auto[1]	auto[0]	18	1		T73	1		T75	2		T255	5
all_values[11]	auto[1]	auto[1]	68	1		T73	3		T76	4		T77	3
all_values[12]	auto[0]	auto[0]	2387	1		T1	4		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	84	1		T73	4		T75	4		T76	1
all_values[12]	auto[1]	auto[0]	15	1		T73	1		T81	1		T78	1
all_values[12]	auto[1]	auto[1]	70	1		T75	1		T76	4		T77	4
all_values[13]	auto[0]	auto[0]	2404	1		T1	4		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	62	1		T75	4		T77	3		T81	3
all_values[13]	auto[1]	auto[0]	30	1		T73	1		T76	1		T77	1
all_values[13]	auto[1]	auto[1]	60	1		T73	3		T75	1		T77	4
all_values[14]	auto[0]	auto[0]	2389	1		T1	4		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	73	1		T73	1		T75	3		T77	5
all_values[14]	auto[1]	auto[0]	13	1		T77	2		T81	1		T79	1
all_values[14]	auto[1]	auto[1]	81	1		T73	4		T75	1		T76	3
all_values[15]	auto[0]	auto[0]	2393	1		T1	4		T2	2		T3	4
all_values[15]	auto[0]	auto[1]	83	1		T75	4		T76	1		T77	3
all_values[15]	auto[1]	auto[0]	8	1		T77	1		T79	1		T259	2
all_values[15]	auto[1]	auto[1]	72	1		T73	3		T75	1		T76	4
all_values[16]	auto[0]	auto[0]	2404	1		T1	4		T2	2		T3	4
all_values[16]	auto[0]	auto[1]	77	1		T73	4		T76	4		T77	2
all_values[16]	auto[1]	auto[0]	30	1		T73	1		T75	1		T77	1
all_values[16]	auto[1]	auto[1]	45	1		T75	3		T76	1		T77	3
all_values[17]	auto[0]	auto[0]	2395	1		T1	4		T2	2		T3	4
all_values[17]	auto[0]	auto[1]	72	1		T73	4		T75	4		T76	1
all_values[17]	auto[1]	auto[0]	13	1		T79	1		T257	1		T258	1
all_values[17]	auto[1]	auto[1]	76	1		T75	1		T76	3		T77	6