Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2556	1		T1	4		T2	2		T3	4
all_pins[1]	2556	1		T1	4		T2	2		T3	4
all_pins[2]	2556	1		T1	4		T2	2		T3	4
all_pins[3]	2556	1		T1	4		T2	2		T3	4
all_pins[4]	2556	1		T1	4		T2	2		T3	4
all_pins[5]	2556	1		T1	4		T2	2		T3	4
all_pins[6]	2556	1		T1	4		T2	2		T3	4
all_pins[7]	2556	1		T1	4		T2	2		T3	4
all_pins[8]	2556	1		T1	4		T2	2		T3	4
all_pins[9]	2556	1		T1	4		T2	2		T3	4
all_pins[10]	2556	1		T1	4		T2	2		T3	4
all_pins[11]	2556	1		T1	4		T2	2		T3	4
all_pins[12]	2556	1		T1	4		T2	2		T3	4
all_pins[13]	2556	1		T1	4		T2	2		T3	4
all_pins[14]	2556	1		T1	4		T2	2		T3	4
all_pins[15]	2556	1		T1	4		T2	2		T3	4
all_pins[16]	2556	1		T1	4		T2	2		T3	4
all_pins[17]	2556	1		T1	4		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45295	1		T1	72		T2	36		T3	72
values[0x1]	713	1		T5	1		T7	1		T22	1
transitions[0x0=>0x1]	544	1		T5	1		T7	1		T22	1
transitions[0x1=>0x0]	551	1		T5	1		T7	1		T22	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2528	1		T1	4		T2	2		T3	4
all_pins[0]	values[0x1]	28	1		T73	1		T75	1		T77	2
all_pins[0]	transitions[0x0=>0x1]	21	1		T73	1		T77	2		T257	1
all_pins[0]	transitions[0x1=>0x0]	118	1		T5	1		T7	1		T22	1
all_pins[1]	values[0x0]	2431	1		T1	4		T2	2		T3	4
all_pins[1]	values[0x1]	125	1		T5	1		T7	1		T22	1
all_pins[1]	transitions[0x0=>0x1]	114	1		T5	1		T7	1		T22	1
all_pins[1]	transitions[0x1=>0x0]	27	1		T73	2		T76	2		T79	2
all_pins[2]	values[0x0]	2518	1		T1	4		T2	2		T3	4
all_pins[2]	values[0x1]	38	1		T73	3		T76	2		T79	3
all_pins[2]	transitions[0x0=>0x1]	30	1		T73	3		T76	2		T79	3
all_pins[2]	transitions[0x1=>0x0]	27	1		T75	3		T76	1		T77	1
all_pins[3]	values[0x0]	2521	1		T1	4		T2	2		T3	4
all_pins[3]	values[0x1]	35	1		T75	3		T76	1		T77	1
all_pins[3]	transitions[0x0=>0x1]	25	1		T75	2		T77	1		T255	1
all_pins[3]	transitions[0x1=>0x0]	40	1		T73	1		T77	4		T81	2
all_pins[4]	values[0x0]	2506	1		T1	4		T2	2		T3	4
all_pins[4]	values[0x1]	50	1		T73	1		T75	1		T76	1
all_pins[4]	transitions[0x0=>0x1]	41	1		T73	1		T75	1		T76	1
all_pins[4]	transitions[0x1=>0x0]	27	1		T78	3		T79	2		T80	1
all_pins[5]	values[0x0]	2520	1		T1	4		T2	2		T3	4
all_pins[5]	values[0x1]	36	1		T78	3		T79	2		T80	1
all_pins[5]	transitions[0x0=>0x1]	26	1		T78	3		T79	2		T80	1
all_pins[5]	transitions[0x1=>0x0]	26	1		T73	1		T75	2		T76	2
all_pins[6]	values[0x0]	2520	1		T1	4		T2	2		T3	4
all_pins[6]	values[0x1]	36	1		T73	1		T75	2		T76	2
all_pins[6]	transitions[0x0=>0x1]	30	1		T73	1		T75	2		T258	3
all_pins[6]	transitions[0x1=>0x0]	29	1		T75	1		T77	1		T255	2
all_pins[7]	values[0x0]	2521	1		T1	4		T2	2		T3	4
all_pins[7]	values[0x1]	35	1		T75	1		T76	2		T77	1
all_pins[7]	transitions[0x0=>0x1]	23	1		T75	1		T76	1		T255	1
all_pins[7]	transitions[0x1=>0x0]	19	1		T73	1		T77	2		T81	1
all_pins[8]	values[0x0]	2525	1		T1	4		T2	2		T3	4
all_pins[8]	values[0x1]	31	1		T73	1		T76	1		T77	3
all_pins[8]	transitions[0x0=>0x1]	23	1		T76	1		T77	2		T81	1
all_pins[8]	transitions[0x1=>0x0]	23	1		T77	1		T78	2		T256	1
all_pins[9]	values[0x0]	2525	1		T1	4		T2	2		T3	4
all_pins[9]	values[0x1]	31	1		T73	1		T77	2		T78	2
all_pins[9]	transitions[0x0=>0x1]	20	1		T73	1		T77	2		T78	2
all_pins[9]	transitions[0x1=>0x0]	23	1		T75	2		T255	1		T79	2
all_pins[10]	values[0x0]	2522	1		T1	4		T2	2		T3	4
all_pins[10]	values[0x1]	34	1		T75	2		T255	1		T79	4
all_pins[10]	transitions[0x0=>0x1]	27	1		T75	2		T255	1		T79	4
all_pins[10]	transitions[0x1=>0x0]	29	1		T73	2		T76	3		T77	2
all_pins[11]	values[0x0]	2520	1		T1	4		T2	2		T3	4
all_pins[11]	values[0x1]	36	1		T73	2		T76	3		T77	2
all_pins[11]	transitions[0x0=>0x1]	24	1		T73	2		T76	1		T77	1
all_pins[11]	transitions[0x1=>0x0]	23	1		T76	1		T77	2		T81	1
all_pins[12]	values[0x0]	2521	1		T1	4		T2	2		T3	4
all_pins[12]	values[0x1]	35	1		T76	3		T77	3		T81	1
all_pins[12]	transitions[0x0=>0x1]	23	1		T76	3		T77	3		T260	3
all_pins[12]	transitions[0x1=>0x0]	21	1		T73	2		T81	1		T78	2
all_pins[13]	values[0x0]	2523	1		T1	4		T2	2		T3	4
all_pins[13]	values[0x1]	33	1		T73	2		T81	2		T78	2
all_pins[13]	transitions[0x0=>0x1]	21	1		T81	2		T78	2		T257	1
all_pins[13]	transitions[0x1=>0x0]	29	1		T73	1		T76	2		T81	2
all_pins[14]	values[0x0]	2515	1		T1	4		T2	2		T3	4
all_pins[14]	values[0x1]	41	1		T73	3		T76	2		T81	2
all_pins[14]	transitions[0x0=>0x1]	29	1		T73	1		T81	2		T255	1
all_pins[14]	transitions[0x1=>0x0]	29	1		T76	1		T77	3		T80	2
all_pins[15]	values[0x0]	2515	1		T1	4		T2	2		T3	4
all_pins[15]	values[0x1]	41	1		T73	2		T76	3		T77	3
all_pins[15]	transitions[0x0=>0x1]	37	1		T73	2		T76	3		T77	3
all_pins[15]	transitions[0x1=>0x0]	16	1		T75	2		T76	1		T79	2
all_pins[16]	values[0x0]	2536	1		T1	4		T2	2		T3	4
all_pins[16]	values[0x1]	20	1		T75	2		T76	1		T79	2
all_pins[16]	transitions[0x0=>0x1]	18	1		T75	2		T76	1		T79	2
all_pins[16]	transitions[0x1=>0x0]	26	1		T75	1		T76	1		T77	3
all_pins[17]	values[0x0]	2528	1		T1	4		T2	2		T3	4
all_pins[17]	values[0x1]	28	1		T75	1		T76	1		T77	3
all_pins[17]	transitions[0x0=>0x1]	12	1		T75	1		T76	1		T77	2
all_pins[17]	transitions[0x1=>0x0]	19	1		T73	1		T75	1		T77	1