Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	148	1		T73	4		T75	4		T76	4
all_values[1]	148	1		T73	4		T75	4		T76	4
all_values[2]	148	1		T73	4		T75	4		T76	4
all_values[3]	148	1		T73	4		T75	4		T76	4
all_values[4]	148	1		T73	4		T75	4		T76	4
all_values[5]	148	1		T73	4		T75	4		T76	4
all_values[6]	148	1		T73	4		T75	4		T76	4
all_values[7]	148	1		T73	4		T75	4		T76	4
all_values[8]	148	1		T73	4		T75	4		T76	4
all_values[9]	148	1		T73	4		T75	4		T76	4
all_values[10]	148	1		T73	4		T75	4		T76	4
all_values[11]	148	1		T73	4		T75	4		T76	4
all_values[12]	148	1		T73	4		T75	4		T76	4
all_values[13]	148	1		T73	4		T75	4		T76	4
all_values[14]	148	1		T73	4		T75	4		T76	4
all_values[15]	148	1		T73	4		T75	4		T76	4
all_values[16]	148	1		T73	4		T75	4		T76	4
all_values[17]	148	1		T73	4		T75	4		T76	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1429	1		T73	42		T75	46		T76	46
auto[1]	1235	1		T73	30		T75	26		T76	26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	525	1		T73	21		T75	17		T76	20
auto[1]	2139	1		T73	51		T75	55		T76	52

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1606	1		T73	47		T75	43		T76	44
auto[1]	1058	1		T73	25		T75	29		T76	28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	22	1		T75	2		T76	4		T77	1
all_values[0]	auto[0]	auto[0]	auto[1]	30	1		T73	1		T77	4		T255	2
all_values[0]	auto[0]	auto[1]	auto[0]	11	1		T73	1		T81	2		T78	2
all_values[0]	auto[0]	auto[1]	auto[1]	31	1		T75	1		T255	1		T257	1
all_values[0]	auto[1]	auto[0]	auto[1]	29	1		T73	1		T77	1		T255	1
all_values[0]	auto[1]	auto[1]	auto[1]	25	1		T73	1		T75	1		T77	1
all_values[1]	auto[0]	auto[0]	auto[0]	17	1		T76	1		T257	1		T261	1
all_values[1]	auto[0]	auto[0]	auto[1]	35	1		T73	2		T76	2		T77	1
all_values[1]	auto[0]	auto[1]	auto[0]	7	1		T262	1		T263	3		T264	1
all_values[1]	auto[0]	auto[1]	auto[1]	29	1		T75	1		T77	2		T81	2
all_values[1]	auto[1]	auto[0]	auto[1]	25	1		T73	1		T75	2		T76	1
all_values[1]	auto[1]	auto[1]	auto[1]	35	1		T73	1		T75	1		T77	3
all_values[2]	auto[0]	auto[0]	auto[0]	14	1		T75	1		T76	1		T77	1
all_values[2]	auto[0]	auto[0]	auto[1]	35	1		T73	1		T75	2		T77	5
all_values[2]	auto[0]	auto[1]	auto[0]	9	1		T81	2		T255	1		T80	1
all_values[2]	auto[0]	auto[1]	auto[1]	29	1		T73	2		T76	1		T78	2
all_values[2]	auto[1]	auto[0]	auto[1]	40	1		T75	1		T76	1		T77	1
all_values[2]	auto[1]	auto[1]	auto[1]	21	1		T73	1		T76	1		T79	3
all_values[3]	auto[0]	auto[0]	auto[0]	14	1		T76	1		T81	1		T79	2
all_values[3]	auto[0]	auto[0]	auto[1]	28	1		T73	2		T76	1		T77	3
all_values[3]	auto[0]	auto[1]	auto[0]	18	1		T75	1		T77	1		T78	4
all_values[3]	auto[0]	auto[1]	auto[1]	36	1		T75	2		T77	2		T81	2
all_values[3]	auto[1]	auto[0]	auto[1]	25	1		T73	2		T76	2		T81	1
all_values[3]	auto[1]	auto[1]	auto[1]	27	1		T75	1		T77	1		T255	1
all_values[4]	auto[0]	auto[0]	auto[0]	14	1		T75	1		T76	1		T81	1
all_values[4]	auto[0]	auto[0]	auto[1]	29	1		T73	2		T75	2		T76	1
all_values[4]	auto[0]	auto[1]	auto[0]	2	1		T256	2		-	-		-	-
all_values[4]	auto[0]	auto[1]	auto[1]	35	1		T77	2		T81	1		T255	1
all_values[4]	auto[1]	auto[0]	auto[1]	33	1		T73	1		T75	1		T76	2
all_values[4]	auto[1]	auto[1]	auto[1]	35	1		T73	1		T77	3		T81	2
all_values[5]	auto[0]	auto[0]	auto[0]	30	1		T73	3		T75	1		T76	4
all_values[5]	auto[0]	auto[0]	auto[1]	22	1		T77	2		T255	2		T79	1
all_values[5]	auto[0]	auto[1]	auto[0]	11	1		T73	1		T257	2		T256	1
all_values[5]	auto[0]	auto[1]	auto[1]	28	1		T75	2		T77	3		T78	2
all_values[5]	auto[1]	auto[0]	auto[1]	29	1		T75	1		T77	1		T255	1
all_values[5]	auto[1]	auto[1]	auto[1]	28	1		T78	2		T256	2		T258	2
all_values[6]	auto[0]	auto[0]	auto[0]	13	1		T78	1		T257	2		T256	4
all_values[6]	auto[0]	auto[0]	auto[1]	37	1		T73	2		T76	1		T77	4
all_values[6]	auto[0]	auto[1]	auto[0]	10	1		T257	2		T80	5		T258	2
all_values[6]	auto[0]	auto[1]	auto[1]	25	1		T75	1		T77	1		T255	2
all_values[6]	auto[1]	auto[0]	auto[1]	36	1		T73	1		T75	2		T76	1
all_values[6]	auto[1]	auto[1]	auto[1]	27	1		T73	1		T75	1		T76	2
all_values[7]	auto[0]	auto[0]	auto[0]	15	1		T73	2		T77	2		T81	1
all_values[7]	auto[0]	auto[0]	auto[1]	21	1		T75	2		T81	1		T78	2
all_values[7]	auto[0]	auto[1]	auto[0]	12	1		T73	2		T257	2		T80	1
all_values[7]	auto[0]	auto[1]	auto[1]	32	1		T76	2		T77	2		T255	2
all_values[7]	auto[1]	auto[0]	auto[1]	38	1		T77	3		T81	1		T78	2
all_values[7]	auto[1]	auto[1]	auto[1]	30	1		T75	2		T76	2		T81	1
all_values[8]	auto[0]	auto[0]	auto[0]	11	1		T75	1		T81	2		T255	1
all_values[8]	auto[0]	auto[0]	auto[1]	32	1		T75	1		T76	2		T77	1
all_values[8]	auto[0]	auto[1]	auto[0]	8	1		T73	1		T256	2		T258	2
all_values[8]	auto[0]	auto[1]	auto[1]	34	1		T73	2		T77	2		T81	1
all_values[8]	auto[1]	auto[0]	auto[1]	38	1		T75	2		T76	2		T77	2
all_values[8]	auto[1]	auto[1]	auto[1]	25	1		T73	1		T77	2		T81	1
all_values[9]	auto[0]	auto[0]	auto[0]	21	1		T76	1		T81	1		T255	1
all_values[9]	auto[0]	auto[0]	auto[1]	34	1		T73	1		T75	1		T76	1
all_values[9]	auto[0]	auto[1]	auto[0]	14	1		T75	2		T81	3		T255	1
all_values[9]	auto[0]	auto[1]	auto[1]	29	1		T73	1		T78	1		T255	1
all_values[9]	auto[1]	auto[0]	auto[1]	27	1		T73	2		T75	1		T76	2
all_values[9]	auto[1]	auto[1]	auto[1]	23	1		T77	3		T78	1		T255	1
all_values[10]	auto[0]	auto[0]	auto[0]	11	1		T73	1		T265	1		T266	2
all_values[10]	auto[0]	auto[0]	auto[1]	28	1		T73	1		T76	1		T255	2
all_values[10]	auto[0]	auto[1]	auto[0]	19	1		T73	1		T75	1		T77	4
all_values[10]	auto[0]	auto[1]	auto[1]	30	1		T75	1		T76	2		T77	1
all_values[10]	auto[1]	auto[0]	auto[1]	33	1		T73	1		T76	1		T81	1
all_values[10]	auto[1]	auto[1]	auto[1]	27	1		T75	2		T77	2		T81	1
all_values[11]	auto[0]	auto[0]	auto[0]	16	1		T73	1		T75	2		T255	1
all_values[11]	auto[0]	auto[0]	auto[1]	29	1		T77	3		T81	2		T79	1
all_values[11]	auto[0]	auto[1]	auto[0]	17	1		T73	1		T75	2		T255	3
all_values[11]	auto[0]	auto[1]	auto[1]	32	1		T73	1		T76	2		T81	1
all_values[11]	auto[1]	auto[0]	auto[1]	31	1		T77	1		T81	1		T78	2
all_values[11]	auto[1]	auto[1]	auto[1]	23	1		T73	1		T76	2		T77	3
all_values[12]	auto[0]	auto[0]	auto[0]	13	1		T81	1		T255	1		T79	1
all_values[12]	auto[0]	auto[0]	auto[1]	33	1		T73	2		T75	1		T76	1
all_values[12]	auto[0]	auto[1]	auto[0]	9	1		T73	1		T78	1		T257	1
all_values[12]	auto[0]	auto[1]	auto[1]	29	1		T76	1		T77	1		T255	1
all_values[12]	auto[1]	auto[0]	auto[1]	34	1		T73	1		T75	1		T76	1
all_values[12]	auto[1]	auto[1]	auto[1]	30	1		T75	2		T76	1		T77	3
all_values[13]	auto[0]	auto[0]	auto[0]	24	1		T73	1		T76	2		T255	3
all_values[13]	auto[0]	auto[0]	auto[1]	27	1		T75	1		T77	2		T81	2
all_values[13]	auto[0]	auto[1]	auto[0]	26	1		T73	1		T76	2		T77	1
all_values[13]	auto[0]	auto[1]	auto[1]	24	1		T73	1		T77	2		T78	1
all_values[13]	auto[1]	auto[0]	auto[1]	27	1		T75	3		T77	1		T81	1
all_values[13]	auto[1]	auto[1]	auto[1]	20	1		T73	1		T77	1		T81	1
all_values[14]	auto[0]	auto[0]	auto[0]	12	1		T75	1		T76	2		T81	1
all_values[14]	auto[0]	auto[0]	auto[1]	32	1		T73	1		T75	2		T77	1
all_values[14]	auto[0]	auto[1]	auto[0]	10	1		T77	2		T79	1		T257	2
all_values[14]	auto[0]	auto[1]	auto[1]	31	1		T73	1		T76	1		T77	2
all_values[14]	auto[1]	auto[0]	auto[1]	31	1		T75	1		T77	2		T255	1
all_values[14]	auto[1]	auto[1]	auto[1]	32	1		T73	2		T76	1		T81	2
all_values[15]	auto[0]	auto[0]	auto[0]	14	1		T73	2		T257	1		T259	2
all_values[15]	auto[0]	auto[0]	auto[1]	36	1		T75	3		T77	1		T81	1
all_values[15]	auto[0]	auto[1]	auto[0]	6	1		T77	1		T79	1		T259	2
all_values[15]	auto[0]	auto[1]	auto[1]	31	1		T73	1		T76	2		T77	2
all_values[15]	auto[1]	auto[0]	auto[1]	36	1		T75	1		T76	2		T77	2
all_values[15]	auto[1]	auto[1]	auto[1]	25	1		T73	1		T77	1		T78	2
all_values[16]	auto[0]	auto[0]	auto[0]	24	1		T75	2		T77	2		T81	1
all_values[16]	auto[0]	auto[0]	auto[1]	30	1		T73	1		T76	2		T77	1
all_values[16]	auto[0]	auto[1]	auto[0]	25	1		T73	1		T77	1		T81	3
all_values[16]	auto[0]	auto[1]	auto[1]	18	1		T75	1		T77	1		T79	1
all_values[16]	auto[1]	auto[0]	auto[1]	37	1		T73	2		T77	1		T78	1
all_values[16]	auto[1]	auto[1]	auto[1]	14	1		T75	1		T76	2		T77	1
all_values[17]	auto[0]	auto[0]	auto[0]	15	1		T73	1		T76	1		T77	1
all_values[17]	auto[0]	auto[0]	auto[1]	29	1		T73	1		T75	2		T81	1
all_values[17]	auto[0]	auto[1]	auto[0]	11	1		T79	1		T257	1		T258	1
all_values[17]	auto[0]	auto[1]	auto[1]	31	1		T76	1		T77	2		T81	2
all_values[17]	auto[1]	auto[0]	auto[1]	33	1		T73	2		T75	2		T76	1
all_values[17]	auto[1]	auto[1]	auto[1]	29	1		T76	1		T77	3		T78	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal