Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.52 96.31 88.57 97.17 46.88 94.11 97.36 92.25


Total test records in report: 904
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T160 /workspace/coverage/default/41.usbdev_smoke.246831467 Mar 19 12:56:04 PM PDT 24 Mar 19 12:56:13 PM PDT 24 8476256620 ps
T819 /workspace/coverage/default/49.usbdev_pkt_sent.3685110338 Mar 19 12:56:27 PM PDT 24 Mar 19 12:56:35 PM PDT 24 8408279022 ps
T820 /workspace/coverage/default/39.usbdev_in_stall.962897629 Mar 19 12:56:04 PM PDT 24 Mar 19 12:56:12 PM PDT 24 8360410294 ps
T821 /workspace/coverage/default/19.usbdev_out_trans_nak.1892373815 Mar 19 12:54:58 PM PDT 24 Mar 19 12:55:05 PM PDT 24 8399935328 ps
T822 /workspace/coverage/default/13.usbdev_random_length_out_trans.2779692367 Mar 19 12:54:43 PM PDT 24 Mar 19 12:54:53 PM PDT 24 8379069099 ps
T823 /workspace/coverage/default/34.usbdev_fifo_rst.3622836400 Mar 19 12:55:47 PM PDT 24 Mar 19 12:55:49 PM PDT 24 62864442 ps
T824 /workspace/coverage/default/36.usbdev_out_stall.2621481406 Mar 19 12:55:56 PM PDT 24 Mar 19 12:56:03 PM PDT 24 8406882776 ps
T185 /workspace/coverage/default/22.usbdev_in_stall.1758229018 Mar 19 12:55:15 PM PDT 24 Mar 19 12:55:24 PM PDT 24 8357144101 ps
T825 /workspace/coverage/default/15.usbdev_in_stall.469301969 Mar 19 12:54:53 PM PDT 24 Mar 19 12:55:01 PM PDT 24 8360665828 ps
T826 /workspace/coverage/default/17.usbdev_fifo_rst.493860061 Mar 19 12:54:53 PM PDT 24 Mar 19 12:54:54 PM PDT 24 121831386 ps
T827 /workspace/coverage/default/44.usbdev_out_trans_nak.3154745981 Mar 19 12:56:12 PM PDT 24 Mar 19 12:56:19 PM PDT 24 8398271598 ps
T828 /workspace/coverage/default/43.usbdev_min_length_out_transaction.3866188740 Mar 19 12:56:08 PM PDT 24 Mar 19 12:56:17 PM PDT 24 8367551411 ps
T829 /workspace/coverage/default/46.usbdev_out_trans_nak.416893014 Mar 19 12:56:23 PM PDT 24 Mar 19 12:56:31 PM PDT 24 8406334292 ps
T830 /workspace/coverage/default/49.usbdev_nak_trans.2943469521 Mar 19 12:56:32 PM PDT 24 Mar 19 12:56:40 PM PDT 24 8410004806 ps
T831 /workspace/coverage/default/7.usbdev_min_length_out_transaction.3695694832 Mar 19 12:54:26 PM PDT 24 Mar 19 12:54:34 PM PDT 24 8368059190 ps
T832 /workspace/coverage/default/45.usbdev_phy_pins_sense.2168992418 Mar 19 12:56:10 PM PDT 24 Mar 19 12:56:11 PM PDT 24 27542988 ps
T833 /workspace/coverage/default/5.usbdev_pkt_received.3654058460 Mar 19 12:54:11 PM PDT 24 Mar 19 12:54:20 PM PDT 24 8380897207 ps
T834 /workspace/coverage/default/20.usbdev_setup_trans_ignored.388034247 Mar 19 12:55:08 PM PDT 24 Mar 19 12:55:16 PM PDT 24 8358360443 ps
T835 /workspace/coverage/default/38.usbdev_phy_pins_sense.1330967713 Mar 19 12:56:02 PM PDT 24 Mar 19 12:56:03 PM PDT 24 29975069 ps
T836 /workspace/coverage/default/22.usbdev_out_trans_nak.1109382368 Mar 19 12:55:15 PM PDT 24 Mar 19 12:55:23 PM PDT 24 8402808109 ps
T837 /workspace/coverage/default/1.usbdev_enable.2449145873 Mar 19 12:53:49 PM PDT 24 Mar 19 12:53:57 PM PDT 24 8368107452 ps
T838 /workspace/coverage/default/40.usbdev_min_length_out_transaction.2626028888 Mar 19 12:56:03 PM PDT 24 Mar 19 12:56:12 PM PDT 24 8368594192 ps
T839 /workspace/coverage/default/36.usbdev_in_trans.3895647776 Mar 19 12:55:48 PM PDT 24 Mar 19 12:55:55 PM PDT 24 8381265236 ps
T102 /workspace/coverage/default/42.usbdev_nak_trans.958501204 Mar 19 12:56:09 PM PDT 24 Mar 19 12:56:17 PM PDT 24 8417653081 ps
T840 /workspace/coverage/default/26.usbdev_setup_trans_ignored.2998855357 Mar 19 12:55:26 PM PDT 24 Mar 19 12:55:34 PM PDT 24 8358190270 ps
T841 /workspace/coverage/default/18.usbdev_in_stall.1119940843 Mar 19 12:54:57 PM PDT 24 Mar 19 12:55:05 PM PDT 24 8361583225 ps
T842 /workspace/coverage/default/47.usbdev_in_trans.3880820906 Mar 19 12:56:18 PM PDT 24 Mar 19 12:56:27 PM PDT 24 8387467979 ps
T83 /workspace/coverage/default/2.usbdev_sec_cm.2207046299 Mar 19 12:53:54 PM PDT 24 Mar 19 12:53:56 PM PDT 24 95918428 ps
T843 /workspace/coverage/default/4.usbdev_random_length_out_trans.3410813022 Mar 19 12:54:08 PM PDT 24 Mar 19 12:54:17 PM PDT 24 8368677688 ps
T844 /workspace/coverage/default/34.usbdev_setup_trans_ignored.2443246638 Mar 19 12:55:46 PM PDT 24 Mar 19 12:55:54 PM PDT 24 8360557701 ps
T845 /workspace/coverage/default/29.usbdev_enable.515966277 Mar 19 12:55:30 PM PDT 24 Mar 19 12:55:39 PM PDT 24 8373751459 ps
T846 /workspace/coverage/default/33.usbdev_in_stall.2483919328 Mar 19 12:55:49 PM PDT 24 Mar 19 12:55:56 PM PDT 24 8360830600 ps
T847 /workspace/coverage/default/34.usbdev_pkt_received.3626375458 Mar 19 12:55:48 PM PDT 24 Mar 19 12:55:56 PM PDT 24 8371077623 ps
T848 /workspace/coverage/default/9.usbdev_random_length_out_trans.1272422402 Mar 19 12:54:33 PM PDT 24 Mar 19 12:54:41 PM PDT 24 8361127933 ps
T849 /workspace/coverage/default/12.usbdev_phy_pins_sense.671636744 Mar 19 12:54:41 PM PDT 24 Mar 19 12:54:42 PM PDT 24 28728543 ps
T850 /workspace/coverage/default/18.usbdev_out_stall.7958354 Mar 19 12:55:01 PM PDT 24 Mar 19 12:55:10 PM PDT 24 8389706327 ps
T851 /workspace/coverage/default/25.usbdev_setup_trans_ignored.380975873 Mar 19 12:55:25 PM PDT 24 Mar 19 12:55:33 PM PDT 24 8359880015 ps
T852 /workspace/coverage/default/25.usbdev_av_buffer.923976002 Mar 19 12:55:21 PM PDT 24 Mar 19 12:55:30 PM PDT 24 8368504187 ps
T853 /workspace/coverage/default/14.usbdev_out_trans_nak.1888916856 Mar 19 12:54:45 PM PDT 24 Mar 19 12:54:53 PM PDT 24 8384138798 ps
T854 /workspace/coverage/default/26.usbdev_enable.3808145477 Mar 19 12:55:26 PM PDT 24 Mar 19 12:55:33 PM PDT 24 8368660671 ps
T855 /workspace/coverage/default/18.usbdev_random_length_out_trans.1031039568 Mar 19 12:54:59 PM PDT 24 Mar 19 12:55:06 PM PDT 24 8403313059 ps
T856 /workspace/coverage/default/35.usbdev_min_length_out_transaction.2216753207 Mar 19 12:55:47 PM PDT 24 Mar 19 12:55:56 PM PDT 24 8370560339 ps
T857 /workspace/coverage/default/3.usbdev_out_trans_nak.1763218202 Mar 19 12:53:58 PM PDT 24 Mar 19 12:54:06 PM PDT 24 8368012181 ps
T858 /workspace/coverage/default/33.usbdev_out_trans_nak.3677341855 Mar 19 12:55:45 PM PDT 24 Mar 19 12:55:52 PM PDT 24 8380671266 ps
T859 /workspace/coverage/default/37.usbdev_out_trans_nak.2376135161 Mar 19 12:55:59 PM PDT 24 Mar 19 12:56:07 PM PDT 24 8388803367 ps
T54 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3149083206 Mar 19 12:28:09 PM PDT 24 Mar 19 12:28:10 PM PDT 24 101328796 ps
T70 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.314724582 Mar 19 12:28:25 PM PDT 24 Mar 19 12:28:26 PM PDT 24 66580339 ps
T55 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4143083234 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:39 PM PDT 24 103992063 ps
T66 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2955438452 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:48 PM PDT 24 26985152 ps
T67 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.929812908 Mar 19 12:28:25 PM PDT 24 Mar 19 12:28:26 PM PDT 24 25991611 ps
T63 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.341166121 Mar 19 12:28:06 PM PDT 24 Mar 19 12:28:07 PM PDT 24 26439203 ps
T64 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.799085777 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:11 PM PDT 24 74529897 ps
T199 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.404909614 Mar 19 12:27:48 PM PDT 24 Mar 19 12:27:49 PM PDT 24 101168585 ps
T71 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2296872041 Mar 19 12:27:41 PM PDT 24 Mar 19 12:27:43 PM PDT 24 69318120 ps
T56 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2832109484 Mar 19 12:27:59 PM PDT 24 Mar 19 12:28:01 PM PDT 24 94391524 ps
T73 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3195523346 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:11 PM PDT 24 26559504 ps
T860 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3949103215 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:20 PM PDT 24 152519655 ps
T861 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.287939403 Mar 19 12:27:49 PM PDT 24 Mar 19 12:27:52 PM PDT 24 84514344 ps
T74 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.75692483 Mar 19 12:27:50 PM PDT 24 Mar 19 12:27:51 PM PDT 24 63603005 ps
T75 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3777926664 Mar 19 12:28:24 PM PDT 24 Mar 19 12:28:26 PM PDT 24 25673637 ps
T65 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.570969753 Mar 19 12:28:32 PM PDT 24 Mar 19 12:28:34 PM PDT 24 40044246 ps
T68 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4129713349 Mar 19 12:28:29 PM PDT 24 Mar 19 12:28:31 PM PDT 24 35170101 ps
T200 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.838159331 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:14 PM PDT 24 62374539 ps
T192 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2071131055 Mar 19 12:28:22 PM PDT 24 Mar 19 12:28:25 PM PDT 24 246731889 ps
T76 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1701628117 Mar 19 12:28:17 PM PDT 24 Mar 19 12:28:18 PM PDT 24 21694264 ps
T94 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1599794264 Mar 19 12:28:33 PM PDT 24 Mar 19 12:28:35 PM PDT 24 76394680 ps
T77 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1311834158 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:16 PM PDT 24 29738741 ps
T81 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3315018638 Mar 19 12:28:22 PM PDT 24 Mar 19 12:28:23 PM PDT 24 25395892 ps
T78 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3458916759 Mar 19 12:28:29 PM PDT 24 Mar 19 12:28:30 PM PDT 24 25493834 ps
T201 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3336865394 Mar 19 12:28:08 PM PDT 24 Mar 19 12:28:10 PM PDT 24 59863078 ps
T69 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.746158809 Mar 19 12:28:08 PM PDT 24 Mar 19 12:28:13 PM PDT 24 192874528 ps
T862 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1054716874 Mar 19 12:28:24 PM PDT 24 Mar 19 12:28:26 PM PDT 24 237998373 ps
T193 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3959954108 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:13 PM PDT 24 97926953 ps
T202 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2466109083 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:13 PM PDT 24 26109171 ps
T255 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1006565596 Mar 19 12:28:33 PM PDT 24 Mar 19 12:28:35 PM PDT 24 25135976 ps
T79 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3504258279 Mar 19 12:28:08 PM PDT 24 Mar 19 12:28:09 PM PDT 24 29927588 ps
T194 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4033802030 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:20 PM PDT 24 125348356 ps
T60 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1636730795 Mar 19 12:28:17 PM PDT 24 Mar 19 12:28:19 PM PDT 24 54698143 ps
T195 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1793438892 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:15 PM PDT 24 63712954 ps
T257 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3154856041 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:16 PM PDT 24 23566029 ps
T80 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3487606967 Mar 19 12:28:22 PM PDT 24 Mar 19 12:28:28 PM PDT 24 29726700 ps
T196 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.855442972 Mar 19 12:28:17 PM PDT 24 Mar 19 12:28:20 PM PDT 24 147218349 ps
T197 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2652072297 Mar 19 12:28:05 PM PDT 24 Mar 19 12:28:06 PM PDT 24 77011549 ps
T198 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3721182114 Mar 19 12:28:22 PM PDT 24 Mar 19 12:28:24 PM PDT 24 71342389 ps
T203 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2974927238 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:19 PM PDT 24 38189757 ps
T256 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3790035972 Mar 19 12:28:33 PM PDT 24 Mar 19 12:28:34 PM PDT 24 22898578 ps
T863 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3993993921 Mar 19 12:27:54 PM PDT 24 Mar 19 12:27:58 PM PDT 24 152148765 ps
T864 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.932466353 Mar 19 12:27:48 PM PDT 24 Mar 19 12:27:51 PM PDT 24 130432261 ps
T865 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2373877522 Mar 19 12:28:25 PM PDT 24 Mar 19 12:28:27 PM PDT 24 57419719 ps
T258 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.404527149 Mar 19 12:28:11 PM PDT 24 Mar 19 12:28:12 PM PDT 24 22283301 ps
T866 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2980081945 Mar 19 12:28:40 PM PDT 24 Mar 19 12:28:41 PM PDT 24 79871592 ps
T867 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1182109491 Mar 19 12:28:11 PM PDT 24 Mar 19 12:28:12 PM PDT 24 69262918 ps
T868 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3138955893 Mar 19 12:28:35 PM PDT 24 Mar 19 12:28:37 PM PDT 24 70158651 ps
T72 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.722290424 Mar 19 12:27:51 PM PDT 24 Mar 19 12:27:52 PM PDT 24 27658741 ps
T869 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3118826569 Mar 19 12:28:09 PM PDT 24 Mar 19 12:28:10 PM PDT 24 35856224 ps
T249 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3633147846 Mar 19 12:28:08 PM PDT 24 Mar 19 12:28:10 PM PDT 24 184181902 ps
T61 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2720806847 Mar 19 12:28:05 PM PDT 24 Mar 19 12:28:05 PM PDT 24 50425983 ps
T204 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.157187841 Mar 19 12:28:23 PM PDT 24 Mar 19 12:28:24 PM PDT 24 68927316 ps
T262 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.292505953 Mar 19 12:28:22 PM PDT 24 Mar 19 12:28:23 PM PDT 24 29228580 ps
T870 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3094918994 Mar 19 12:28:23 PM PDT 24 Mar 19 12:28:24 PM PDT 24 45114605 ps
T871 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1695937340 Mar 19 12:28:27 PM PDT 24 Mar 19 12:28:29 PM PDT 24 120072813 ps
T250 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1650360793 Mar 19 12:28:30 PM PDT 24 Mar 19 12:28:34 PM PDT 24 96632659 ps
T253 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1604484497 Mar 19 12:28:21 PM PDT 24 Mar 19 12:28:22 PM PDT 24 76758260 ps
T254 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3825988296 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:14 PM PDT 24 140672966 ps
T872 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1712226493 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:39 PM PDT 24 120932229 ps
T251 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.57048432 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:18 PM PDT 24 64898760 ps
T873 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.473994486 Mar 19 12:28:04 PM PDT 24 Mar 19 12:28:05 PM PDT 24 36556402 ps
T874 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3218776332 Mar 19 12:28:11 PM PDT 24 Mar 19 12:28:12 PM PDT 24 43133273 ps
T875 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3909373722 Mar 19 12:28:20 PM PDT 24 Mar 19 12:28:22 PM PDT 24 118673318 ps
T252 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2481767253 Mar 19 12:28:37 PM PDT 24 Mar 19 12:28:38 PM PDT 24 61325848 ps
T876 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1100437510 Mar 19 12:28:14 PM PDT 24 Mar 19 12:28:15 PM PDT 24 54257463 ps
T261 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1343248914 Mar 19 12:28:34 PM PDT 24 Mar 19 12:28:36 PM PDT 24 22768649 ps
T259 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2367957822 Mar 19 12:28:18 PM PDT 24 Mar 19 12:28:19 PM PDT 24 34043192 ps
T205 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3732559153 Mar 19 12:28:01 PM PDT 24 Mar 19 12:28:03 PM PDT 24 199767977 ps
T177 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4043320230 Mar 19 12:28:20 PM PDT 24 Mar 19 12:28:21 PM PDT 24 151339911 ps
T877 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.373837174 Mar 19 12:28:04 PM PDT 24 Mar 19 12:28:05 PM PDT 24 59748955 ps
T206 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2548145100 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:18 PM PDT 24 147490483 ps
T260 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2817363478 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:11 PM PDT 24 27343170 ps
T263 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2886116763 Mar 19 12:28:13 PM PDT 24 Mar 19 12:28:14 PM PDT 24 21615355 ps
T878 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.427305514 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:13 PM PDT 24 56989315 ps
T879 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2918589597 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:13 PM PDT 24 25576557 ps
T207 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1665288178 Mar 19 12:28:12 PM PDT 24 Mar 19 12:28:14 PM PDT 24 69688241 ps
T880 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2125987318 Mar 19 12:28:02 PM PDT 24 Mar 19 12:28:04 PM PDT 24 33640068 ps
T208 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1099762122 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:56 PM PDT 24 73820040 ps
T881 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3126121182 Mar 19 12:28:05 PM PDT 24 Mar 19 12:28:06 PM PDT 24 32803043 ps
T265 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3391334067 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:18 PM PDT 24 27660581 ps
T882 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1355671055 Mar 19 12:28:28 PM PDT 24 Mar 19 12:28:29 PM PDT 24 64056479 ps
T883 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2040692601 Mar 19 12:27:48 PM PDT 24 Mar 19 12:27:50 PM PDT 24 144150145 ps
T264 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4277618242 Mar 19 12:28:45 PM PDT 24 Mar 19 12:28:46 PM PDT 24 24130036 ps
T884 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.203077545 Mar 19 12:27:49 PM PDT 24 Mar 19 12:27:50 PM PDT 24 41720913 ps
T885 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.764635272 Mar 19 12:28:25 PM PDT 24 Mar 19 12:28:26 PM PDT 24 84835504 ps
T886 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2513648773 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:12 PM PDT 24 26935533 ps
T209 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4151396539 Mar 19 12:27:45 PM PDT 24 Mar 19 12:27:47 PM PDT 24 42070842 ps
T887 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.193777046 Mar 19 12:28:23 PM PDT 24 Mar 19 12:28:24 PM PDT 24 75473178 ps
T266 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3158442587 Mar 19 12:28:25 PM PDT 24 Mar 19 12:28:26 PM PDT 24 25625802 ps
T888 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4000851304 Mar 19 12:28:11 PM PDT 24 Mar 19 12:28:12 PM PDT 24 35241562 ps
T889 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3899558173 Mar 19 12:28:06 PM PDT 24 Mar 19 12:28:06 PM PDT 24 27957846 ps
T890 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1800457347 Mar 19 12:28:08 PM PDT 24 Mar 19 12:28:09 PM PDT 24 29075037 ps
T62 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3804590762 Mar 19 12:27:47 PM PDT 24 Mar 19 12:27:48 PM PDT 24 48485129 ps
T891 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2741889409 Mar 19 12:28:24 PM PDT 24 Mar 19 12:28:26 PM PDT 24 42601991 ps
T892 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.208577560 Mar 19 12:28:06 PM PDT 24 Mar 19 12:28:09 PM PDT 24 152240073 ps
T893 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.402965996 Mar 19 12:28:03 PM PDT 24 Mar 19 12:28:03 PM PDT 24 21393849 ps
T894 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2718005774 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:12 PM PDT 24 125819243 ps
T895 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1781734435 Mar 19 12:28:38 PM PDT 24 Mar 19 12:28:38 PM PDT 24 25720718 ps
T896 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.464096807 Mar 19 12:28:10 PM PDT 24 Mar 19 12:28:11 PM PDT 24 115918631 ps
T897 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.883952629 Mar 19 12:27:53 PM PDT 24 Mar 19 12:27:54 PM PDT 24 110962085 ps
T898 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3714623589 Mar 19 12:28:36 PM PDT 24 Mar 19 12:28:37 PM PDT 24 28863435 ps
T899 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1542131728 Mar 19 12:28:44 PM PDT 24 Mar 19 12:28:45 PM PDT 24 28079932 ps
T900 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1616354281 Mar 19 12:28:16 PM PDT 24 Mar 19 12:28:18 PM PDT 24 127114331 ps
T901 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4280475424 Mar 19 12:28:39 PM PDT 24 Mar 19 12:28:42 PM PDT 24 226695920 ps
T168 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.371464962 Mar 19 12:28:08 PM PDT 24 Mar 19 12:28:10 PM PDT 24 143162035 ps
T902 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4190288816 Mar 19 12:27:50 PM PDT 24 Mar 19 12:27:53 PM PDT 24 128754006 ps
T903 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3214791900 Mar 19 12:28:19 PM PDT 24 Mar 19 12:28:20 PM PDT 24 87247856 ps
T904 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1818811659 Mar 19 12:28:15 PM PDT 24 Mar 19 12:28:17 PM PDT 24 132366952 ps

Test location /workspace/coverage/default/28.usbdev_pkt_sent.4199439113
Short name T5
Test name
Test status
Simulation time 8403662795 ps
CPU time 7.64 seconds
Started Mar 19 12:55:33 PM PDT 24
Finished Mar 19 12:55:41 PM PDT 24
Peak memory 203064 kb
Host smart-5cc2c071-462b-4586-9964-fb4c5171e376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41994
39113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.4199439113
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.678118902
Short name T38
Test name
Test status
Simulation time 47637676 ps
CPU time 1.29 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:54:57 PM PDT 24
Peak memory 203032 kb
Host smart-3aed505c-50c2-4a36-8533-172f70f62b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67811
8902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.678118902
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1311834158
Short name T77
Test name
Test status
Simulation time 29738741 ps
CPU time 0.63 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 202480 kb
Host smart-2a8bc111-0fde-493a-b5a6-d5f70e48b4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1311834158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1311834158
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.314724582
Short name T70
Test name
Test status
Simulation time 66580339 ps
CPU time 1 seconds
Started Mar 19 12:28:25 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 202784 kb
Host smart-40cd398b-df9a-4d43-90ce-1c5341526f0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314724582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.314724582
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3978405677
Short name T11
Test name
Test status
Simulation time 8471456153 ps
CPU time 9.34 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 202984 kb
Host smart-06570d5d-b385-45cc-ba98-8bd6db65f16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39784
05677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3978405677
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.4143083234
Short name T55
Test name
Test status
Simulation time 103992063 ps
CPU time 1.6 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 202908 kb
Host smart-8ed01163-00ba-43fd-8526-78e2713d7e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4143083234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.4143083234
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.292505953
Short name T262
Test name
Test status
Simulation time 29228580 ps
CPU time 0.66 seconds
Started Mar 19 12:28:22 PM PDT 24
Finished Mar 19 12:28:23 PM PDT 24
Peak memory 202488 kb
Host smart-dfb4328a-8f5b-42f5-ae3e-f03c35bd440c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=292505953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.292505953
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.4160494938
Short name T57
Test name
Test status
Simulation time 83746514 ps
CPU time 0.9 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:51 PM PDT 24
Peak memory 218972 kb
Host smart-f67c4b4f-fb2b-4963-a9e0-b00bf22b1200
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4160494938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.4160494938
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1366530803
Short name T23
Test name
Test status
Simulation time 8359535750 ps
CPU time 8.07 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 202888 kb
Host smart-385aa18c-4c7b-4816-b42b-7194388b5ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13665
30803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1366530803
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.4243164277
Short name T113
Test name
Test status
Simulation time 8426521253 ps
CPU time 7.18 seconds
Started Mar 19 12:55:43 PM PDT 24
Finished Mar 19 12:55:50 PM PDT 24
Peak memory 202992 kb
Host smart-6bfa4380-bcd8-4f43-b9b7-92e06a797194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42431
64277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.4243164277
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.22357571
Short name T27
Test name
Test status
Simulation time 27717581 ps
CPU time 0.61 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:15 PM PDT 24
Peak memory 202508 kb
Host smart-cde29e94-b146-4eb0-81e4-d0ff7bac84fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22357
571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.22357571
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.4276108935
Short name T294
Test name
Test status
Simulation time 8402225740 ps
CPU time 8.17 seconds
Started Mar 19 12:54:09 PM PDT 24
Finished Mar 19 12:54:17 PM PDT 24
Peak memory 202920 kb
Host smart-e27acdc8-e661-44c3-a33a-128fc4e3fdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42761
08935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.4276108935
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3195523346
Short name T73
Test name
Test status
Simulation time 26559504 ps
CPU time 0.72 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:11 PM PDT 24
Peak memory 201276 kb
Host smart-904fefda-dcd2-42e4-b45b-8d606db7a83c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3195523346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3195523346
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3315018638
Short name T81
Test name
Test status
Simulation time 25395892 ps
CPU time 0.61 seconds
Started Mar 19 12:28:22 PM PDT 24
Finished Mar 19 12:28:23 PM PDT 24
Peak memory 202508 kb
Host smart-d3b76c5b-8d83-46c1-a819-7b211b00aed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3315018638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3315018638
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3409498843
Short name T142
Test name
Test status
Simulation time 8480056661 ps
CPU time 7.85 seconds
Started Mar 19 12:54:33 PM PDT 24
Finished Mar 19 12:54:41 PM PDT 24
Peak memory 202952 kb
Host smart-2299c341-d918-4753-bffb-622b0975f1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34094
98843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3409498843
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1454749004
Short name T213
Test name
Test status
Simulation time 254061495 ps
CPU time 2.1 seconds
Started Mar 19 12:53:57 PM PDT 24
Finished Mar 19 12:54:00 PM PDT 24
Peak memory 203088 kb
Host smart-eafe9687-0d91-4c78-b193-09616c843115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
49004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1454749004
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1536618183
Short name T93
Test name
Test status
Simulation time 8479954916 ps
CPU time 9.23 seconds
Started Mar 19 12:54:10 PM PDT 24
Finished Mar 19 12:54:20 PM PDT 24
Peak memory 203004 kb
Host smart-96e9bae0-d113-4d11-8c68-22bd0cbfdfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15366
18183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1536618183
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3252308366
Short name T43
Test name
Test status
Simulation time 8474086498 ps
CPU time 7.64 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:26 PM PDT 24
Peak memory 202984 kb
Host smart-82a90c5a-f12c-4d1a-a851-a34be7e011b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32523
08366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3252308366
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4129713349
Short name T68
Test name
Test status
Simulation time 35170101 ps
CPU time 0.99 seconds
Started Mar 19 12:28:29 PM PDT 24
Finished Mar 19 12:28:31 PM PDT 24
Peak memory 202840 kb
Host smart-bbdaee35-1bf5-4b5a-96c1-011c52bbad56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129713349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.4129713349
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3645980858
Short name T155
Test name
Test status
Simulation time 8474241761 ps
CPU time 7.79 seconds
Started Mar 19 12:53:39 PM PDT 24
Finished Mar 19 12:53:48 PM PDT 24
Peak memory 203004 kb
Host smart-cdf25514-f52e-4fa3-9fa9-744ca6c85cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
80858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3645980858
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2308551449
Short name T151
Test name
Test status
Simulation time 8479245515 ps
CPU time 8.38 seconds
Started Mar 19 12:55:01 PM PDT 24
Finished Mar 19 12:55:10 PM PDT 24
Peak memory 202468 kb
Host smart-21539bf0-7f8d-4c77-881f-0228d085fce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23085
51449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2308551449
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_smoke.73149968
Short name T147
Test name
Test status
Simulation time 8474500187 ps
CPU time 7.88 seconds
Started Mar 19 12:55:33 PM PDT 24
Finished Mar 19 12:55:41 PM PDT 24
Peak memory 203048 kb
Host smart-af56f143-2a0e-4518-8fa1-6533084a1039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73149
968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.73149968
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_smoke.968627940
Short name T446
Test name
Test status
Simulation time 8473049477 ps
CPU time 8.45 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:43 PM PDT 24
Peak memory 202772 kb
Host smart-fce5960c-a46d-4add-ac3b-8445a36768a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96862
7940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.968627940
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3738460153
Short name T416
Test name
Test status
Simulation time 8389374507 ps
CPU time 8.05 seconds
Started Mar 19 12:53:40 PM PDT 24
Finished Mar 19 12:53:48 PM PDT 24
Peak memory 202980 kb
Host smart-d4780d83-9258-46ed-8f84-892958beca4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37384
60153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3738460153
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4277618242
Short name T264
Test name
Test status
Simulation time 24130036 ps
CPU time 0.63 seconds
Started Mar 19 12:28:45 PM PDT 24
Finished Mar 19 12:28:46 PM PDT 24
Peak memory 202488 kb
Host smart-2949f323-f2af-4016-8e77-70fd5aaa572d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4277618242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4277618242
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2720806847
Short name T61
Test name
Test status
Simulation time 50425983 ps
CPU time 0.81 seconds
Started Mar 19 12:28:05 PM PDT 24
Finished Mar 19 12:28:05 PM PDT 24
Peak memory 202588 kb
Host smart-bea755ef-852e-4948-b93c-1352cd724332
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720806847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2720806847
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2481767253
Short name T252
Test name
Test status
Simulation time 61325848 ps
CPU time 1.67 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 202864 kb
Host smart-836dcc4b-3171-41c1-b8a7-a56b5ce51c6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2481767253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2481767253
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2531431269
Short name T14
Test name
Test status
Simulation time 8477101123 ps
CPU time 7.84 seconds
Started Mar 19 12:56:15 PM PDT 24
Finished Mar 19 12:56:23 PM PDT 24
Peak memory 203052 kb
Host smart-d09337a6-9e75-4d39-b0c9-0cc4486ccef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25314
31269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2531431269
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3790035972
Short name T256
Test name
Test status
Simulation time 22898578 ps
CPU time 0.64 seconds
Started Mar 19 12:28:33 PM PDT 24
Finished Mar 19 12:28:34 PM PDT 24
Peak memory 202488 kb
Host smart-abf351a1-5de6-415a-be3f-15d6f9f628ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3790035972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3790035972
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3174406138
Short name T42
Test name
Test status
Simulation time 8472581082 ps
CPU time 7.52 seconds
Started Mar 19 12:55:25 PM PDT 24
Finished Mar 19 12:55:33 PM PDT 24
Peak memory 203004 kb
Host smart-908cd80b-75dc-4e84-ba7a-2a4d1c5fb842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31744
06138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3174406138
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.341166121
Short name T63
Test name
Test status
Simulation time 26439203 ps
CPU time 0.7 seconds
Started Mar 19 12:28:06 PM PDT 24
Finished Mar 19 12:28:07 PM PDT 24
Peak memory 202616 kb
Host smart-d020153d-a7ae-4f94-8016-f486faa5eec4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341166121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.341166121
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2638448673
Short name T490
Test name
Test status
Simulation time 30420047 ps
CPU time 0.65 seconds
Started Mar 19 12:54:29 PM PDT 24
Finished Mar 19 12:54:29 PM PDT 24
Peak memory 202512 kb
Host smart-7310bd96-c90e-40c3-93d5-e07897e8b6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26384
48673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2638448673
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4043320230
Short name T177
Test name
Test status
Simulation time 151339911 ps
CPU time 1.5 seconds
Started Mar 19 12:28:20 PM PDT 24
Finished Mar 19 12:28:21 PM PDT 24
Peak memory 202820 kb
Host smart-8a3eb597-b9fc-4ea8-b152-3e68bf3b564a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043320230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.4043320230
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.57048432
Short name T251
Test name
Test status
Simulation time 64898760 ps
CPU time 1.89 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 202836 kb
Host smart-796c48b0-0d6e-43af-bcf5-c542a3ec197c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=57048432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.57048432
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.371464962
Short name T168
Test name
Test status
Simulation time 143162035 ps
CPU time 1.5 seconds
Started Mar 19 12:28:08 PM PDT 24
Finished Mar 19 12:28:10 PM PDT 24
Peak memory 202812 kb
Host smart-fb868c78-0dd5-4c4c-9439-1222d5f120d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371464962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_cs
r_outstanding.371464962
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3563246415
Short name T13
Test name
Test status
Simulation time 8356923025 ps
CPU time 7.69 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 202892 kb
Host smart-71a5db4d-50be-47ee-8673-974b9ff1803d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35632
46415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3563246415
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1644958416
Short name T549
Test name
Test status
Simulation time 8472282741 ps
CPU time 7.77 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:55:04 PM PDT 24
Peak memory 202996 kb
Host smart-3bfe5a9c-0312-4d25-8ca3-65296c51b2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449
58416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1644958416
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_smoke.246831467
Short name T160
Test name
Test status
Simulation time 8476256620 ps
CPU time 8.2 seconds
Started Mar 19 12:56:04 PM PDT 24
Finished Mar 19 12:56:13 PM PDT 24
Peak memory 203048 kb
Host smart-4c95b604-ac50-46fb-a129-22d7af668bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24683
1467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.246831467
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.373837174
Short name T877
Test name
Test status
Simulation time 59748955 ps
CPU time 1.37 seconds
Started Mar 19 12:28:04 PM PDT 24
Finished Mar 19 12:28:05 PM PDT 24
Peak memory 202764 kb
Host smart-9f2f7c1a-a5d6-4141-b6c2-367acfed2628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373837174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_cs
r_outstanding.373837174
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3795825598
Short name T189
Test name
Test status
Simulation time 8358441110 ps
CPU time 9.44 seconds
Started Mar 19 12:53:47 PM PDT 24
Finished Mar 19 12:53:57 PM PDT 24
Peak memory 202800 kb
Host smart-bb5c5907-8138-49b5-b332-67170ee6b71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37958
25598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3795825598
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2248185672
Short name T117
Test name
Test status
Simulation time 8442919048 ps
CPU time 7.94 seconds
Started Mar 19 12:53:48 PM PDT 24
Finished Mar 19 12:53:57 PM PDT 24
Peak memory 203040 kb
Host smart-99bfdec7-7562-4fbb-8993-6ab378281975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22481
85672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2248185672
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1949410617
Short name T652
Test name
Test status
Simulation time 8434022427 ps
CPU time 10.06 seconds
Started Mar 19 12:53:48 PM PDT 24
Finished Mar 19 12:53:59 PM PDT 24
Peak memory 203036 kb
Host smart-a7cae1eb-4a9c-4bb0-9098-2ba7624539a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19494
10617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1949410617
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.77980515
Short name T107
Test name
Test status
Simulation time 8413972101 ps
CPU time 7.55 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 202980 kb
Host smart-2a46ce3f-ed62-4833-9f86-964ae484f58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77980
515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.77980515
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3212139549
Short name T110
Test name
Test status
Simulation time 8411239632 ps
CPU time 7.77 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 203008 kb
Host smart-faae831f-9d44-4d7c-ab9a-602014bff82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32121
39549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3212139549
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.4065823195
Short name T125
Test name
Test status
Simulation time 8435678826 ps
CPU time 8.63 seconds
Started Mar 19 12:54:48 PM PDT 24
Finished Mar 19 12:54:57 PM PDT 24
Peak memory 203036 kb
Host smart-5ccb501b-8515-4b19-a4b6-0277f9f45ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40658
23195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4065823195
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.469301969
Short name T825
Test name
Test status
Simulation time 8360665828 ps
CPU time 7.49 seconds
Started Mar 19 12:54:53 PM PDT 24
Finished Mar 19 12:55:01 PM PDT 24
Peak memory 202756 kb
Host smart-79691bd9-b5f8-46a0-886c-d2b28fd86c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46930
1969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.469301969
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2526862402
Short name T101
Test name
Test status
Simulation time 8407192306 ps
CPU time 8.06 seconds
Started Mar 19 12:54:45 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 203104 kb
Host smart-7b74d700-8650-4db4-b3cd-2c57534f8a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25268
62402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2526862402
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3680494376
Short name T104
Test name
Test status
Simulation time 8391392426 ps
CPU time 8.4 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:55:05 PM PDT 24
Peak memory 203072 kb
Host smart-5149b8ea-e16e-44ef-aa99-d1ac3272820c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36804
94376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3680494376
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4289351154
Short name T762
Test name
Test status
Simulation time 8397256973 ps
CPU time 9.01 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 203052 kb
Host smart-bb9dfb47-7e94-47c6-ab20-2c529adfcab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42893
51154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4289351154
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3495063214
Short name T99
Test name
Test status
Simulation time 8407110877 ps
CPU time 9.19 seconds
Started Mar 19 12:53:57 PM PDT 24
Finished Mar 19 12:54:07 PM PDT 24
Peak memory 202976 kb
Host smart-ab7ac949-53a4-41f2-b68d-5930a1d6afa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34950
63214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3495063214
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1563998155
Short name T500
Test name
Test status
Simulation time 8448178562 ps
CPU time 8.84 seconds
Started Mar 19 12:55:41 PM PDT 24
Finished Mar 19 12:55:51 PM PDT 24
Peak memory 203044 kb
Host smart-912eac28-96d0-412a-bd51-5d77ced5340c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15639
98155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1563998155
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1111820849
Short name T118
Test name
Test status
Simulation time 8422780068 ps
CPU time 7.28 seconds
Started Mar 19 12:56:07 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 203040 kb
Host smart-a7a4dc8f-c63f-4f35-a506-9cc1345753e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11118
20849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1111820849
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2296872041
Short name T71
Test name
Test status
Simulation time 69318120 ps
CPU time 1.91 seconds
Started Mar 19 12:27:41 PM PDT 24
Finished Mar 19 12:27:43 PM PDT 24
Peak memory 202696 kb
Host smart-8062cf99-ffd4-4824-a689-9dfaa25ea9e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296872041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2296872041
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1636730795
Short name T60
Test name
Test status
Simulation time 54698143 ps
CPU time 0.84 seconds
Started Mar 19 12:28:17 PM PDT 24
Finished Mar 19 12:28:19 PM PDT 24
Peak memory 202588 kb
Host smart-74a8e0cf-43ab-49f5-8a5b-976e05679737
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636730795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1636730795
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2955438452
Short name T66
Test name
Test status
Simulation time 26985152 ps
CPU time 0.8 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 202616 kb
Host smart-7949ec7e-591b-4ff4-a6a3-70d1e1041f9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955438452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2955438452
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4151396539
Short name T209
Test name
Test status
Simulation time 42070842 ps
CPU time 1.27 seconds
Started Mar 19 12:27:45 PM PDT 24
Finished Mar 19 12:27:47 PM PDT 24
Peak memory 202920 kb
Host smart-b8b75dd0-ee08-42a5-b8d3-64b42cd3b87b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4151396539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.4151396539
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3993993921
Short name T863
Test name
Test status
Simulation time 152148765 ps
CPU time 3.89 seconds
Started Mar 19 12:27:54 PM PDT 24
Finished Mar 19 12:27:58 PM PDT 24
Peak memory 202744 kb
Host smart-685a59b1-23d5-43e0-bc1d-80851abff870
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3993993921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3993993921
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3118826569
Short name T869
Test name
Test status
Simulation time 35856224 ps
CPU time 1 seconds
Started Mar 19 12:28:09 PM PDT 24
Finished Mar 19 12:28:10 PM PDT 24
Peak memory 202768 kb
Host smart-262594fb-1514-4e6d-949c-11030627f1c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118826569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.3118826569
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.883952629
Short name T897
Test name
Test status
Simulation time 110962085 ps
CPU time 1.45 seconds
Started Mar 19 12:27:53 PM PDT 24
Finished Mar 19 12:27:54 PM PDT 24
Peak memory 202944 kb
Host smart-a6f41bb1-f200-4f83-9647-87f01bf065e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=883952629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.883952629
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1099762122
Short name T208
Test name
Test status
Simulation time 73820040 ps
CPU time 2.05 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:56 PM PDT 24
Peak memory 202800 kb
Host smart-1c2699c5-0e45-4915-be19-04a81a262908
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099762122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1099762122
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3804590762
Short name T62
Test name
Test status
Simulation time 48485129 ps
CPU time 0.84 seconds
Started Mar 19 12:27:47 PM PDT 24
Finished Mar 19 12:27:48 PM PDT 24
Peak memory 202588 kb
Host smart-3f23fb2b-a6d9-4468-9fe2-1cf3508a11aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804590762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3804590762
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.404909614
Short name T199
Test name
Test status
Simulation time 101168585 ps
CPU time 1.38 seconds
Started Mar 19 12:27:48 PM PDT 24
Finished Mar 19 12:27:49 PM PDT 24
Peak memory 202760 kb
Host smart-88d08f78-9f68-4aca-980c-6a1a969e0e5e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=404909614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.404909614
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.287939403
Short name T861
Test name
Test status
Simulation time 84514344 ps
CPU time 2.25 seconds
Started Mar 19 12:27:49 PM PDT 24
Finished Mar 19 12:27:52 PM PDT 24
Peak memory 202868 kb
Host smart-e33f20c0-9970-4eef-8278-1952fc60d3cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=287939403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.287939403
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.464096807
Short name T896
Test name
Test status
Simulation time 115918631 ps
CPU time 1.42 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:11 PM PDT 24
Peak memory 202812 kb
Host smart-02babe48-5dce-42ce-91e7-503e1aa5a7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=464096807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.464096807
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3218776332
Short name T874
Test name
Test status
Simulation time 43133273 ps
CPU time 1.22 seconds
Started Mar 19 12:28:11 PM PDT 24
Finished Mar 19 12:28:12 PM PDT 24
Peak memory 211064 kb
Host smart-0709ceb3-de23-4ed1-94d7-b52189bbc4eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218776332 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.3218776332
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3126121182
Short name T881
Test name
Test status
Simulation time 32803043 ps
CPU time 0.79 seconds
Started Mar 19 12:28:05 PM PDT 24
Finished Mar 19 12:28:06 PM PDT 24
Peak memory 202592 kb
Host smart-c221881e-56e2-4f07-8939-00bdd6edabae
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126121182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3126121182
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.404527149
Short name T258
Test name
Test status
Simulation time 22283301 ps
CPU time 0.67 seconds
Started Mar 19 12:28:11 PM PDT 24
Finished Mar 19 12:28:12 PM PDT 24
Peak memory 202452 kb
Host smart-3899fd3c-3a82-48be-a22f-9f0c7d3e03db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=404527149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.404527149
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4280475424
Short name T901
Test name
Test status
Simulation time 226695920 ps
CPU time 2.95 seconds
Started Mar 19 12:28:39 PM PDT 24
Finished Mar 19 12:28:42 PM PDT 24
Peak memory 202940 kb
Host smart-47d12548-0bab-4800-8d02-f571d0bb5360
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4280475424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4280475424
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3214791900
Short name T903
Test name
Test status
Simulation time 87247856 ps
CPU time 1.24 seconds
Started Mar 19 12:28:19 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 211224 kb
Host smart-ccd4969a-913f-482a-b7e3-8db98aec942f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214791900 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3214791900
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.157187841
Short name T204
Test name
Test status
Simulation time 68927316 ps
CPU time 0.98 seconds
Started Mar 19 12:28:23 PM PDT 24
Finished Mar 19 12:28:24 PM PDT 24
Peak memory 202800 kb
Host smart-3514aa0e-5f60-4154-ba3b-65338194441a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157187841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.157187841
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3391334067
Short name T265
Test name
Test status
Simulation time 27660581 ps
CPU time 0.65 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 202484 kb
Host smart-82b6467a-3c39-4d91-8b92-f2ee3307bcce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3391334067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3391334067
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2718005774
Short name T894
Test name
Test status
Simulation time 125819243 ps
CPU time 1.44 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:12 PM PDT 24
Peak memory 202808 kb
Host smart-e8c3527b-887c-4202-958a-31eb983cc124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718005774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.2718005774
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3149083206
Short name T54
Test name
Test status
Simulation time 101328796 ps
CPU time 1.31 seconds
Started Mar 19 12:28:09 PM PDT 24
Finished Mar 19 12:28:10 PM PDT 24
Peak memory 202868 kb
Host smart-f6894749-f6b8-4eb7-bd82-c50db0c97ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3149083206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3149083206
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.929812908
Short name T67
Test name
Test status
Simulation time 25991611 ps
CPU time 0.81 seconds
Started Mar 19 12:28:25 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 202576 kb
Host smart-1a84d683-da53-49c0-b74e-ab960c32c9a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929812908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.929812908
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2513648773
Short name T886
Test name
Test status
Simulation time 26935533 ps
CPU time 0.66 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:12 PM PDT 24
Peak memory 202484 kb
Host smart-a421428d-639c-4f22-8e16-fb865589cda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2513648773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2513648773
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3909373722
Short name T875
Test name
Test status
Simulation time 118673318 ps
CPU time 1.65 seconds
Started Mar 19 12:28:20 PM PDT 24
Finished Mar 19 12:28:22 PM PDT 24
Peak memory 202840 kb
Host smart-79ce219d-bd0f-4939-a73c-a14ae35c64ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3909373722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3909373722
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1712226493
Short name T872
Test name
Test status
Simulation time 120932229 ps
CPU time 1.69 seconds
Started Mar 19 12:28:37 PM PDT 24
Finished Mar 19 12:28:39 PM PDT 24
Peak memory 211136 kb
Host smart-f3fcea33-2531-4847-9962-26ffc849eb7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712226493 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.1712226493
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.427305514
Short name T878
Test name
Test status
Simulation time 56989315 ps
CPU time 1.37 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:13 PM PDT 24
Peak memory 202736 kb
Host smart-08e67949-19cc-452c-a143-21699fac35b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427305514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_c
sr_outstanding.427305514
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3959954108
Short name T193
Test name
Test status
Simulation time 97926953 ps
CPU time 1.5 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:13 PM PDT 24
Peak memory 202832 kb
Host smart-05ffba55-1f31-47e4-9fd2-e72579d1d022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3959954108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3959954108
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1604484497
Short name T253
Test name
Test status
Simulation time 76758260 ps
CPU time 1.08 seconds
Started Mar 19 12:28:21 PM PDT 24
Finished Mar 19 12:28:22 PM PDT 24
Peak memory 218788 kb
Host smart-1a4efea5-8e65-4df9-9ba9-8f85a97473bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604484497 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.1604484497
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3154856041
Short name T257
Test name
Test status
Simulation time 23566029 ps
CPU time 0.62 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:16 PM PDT 24
Peak memory 202508 kb
Host smart-0a1f93c6-e626-4abb-9174-a8938f803d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3154856041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3154856041
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2071131055
Short name T192
Test name
Test status
Simulation time 246731889 ps
CPU time 2.71 seconds
Started Mar 19 12:28:22 PM PDT 24
Finished Mar 19 12:28:25 PM PDT 24
Peak memory 202788 kb
Host smart-57610cb0-87a2-4042-ab3d-d99596860df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2071131055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2071131055
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2918589597
Short name T879
Test name
Test status
Simulation time 25576557 ps
CPU time 0.62 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:13 PM PDT 24
Peak memory 202512 kb
Host smart-856c6c1a-5587-4736-b7bc-bfda7ad746d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2918589597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2918589597
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.855442972
Short name T196
Test name
Test status
Simulation time 147218349 ps
CPU time 1.74 seconds
Started Mar 19 12:28:17 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 211148 kb
Host smart-e2c8f730-a932-41d3-8355-1f928bfe2afa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855442972 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.855442972
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3094918994
Short name T870
Test name
Test status
Simulation time 45114605 ps
CPU time 0.8 seconds
Started Mar 19 12:28:23 PM PDT 24
Finished Mar 19 12:28:24 PM PDT 24
Peak memory 202568 kb
Host smart-79467f73-4509-4460-bf0c-844fe52683e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094918994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3094918994
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3899558173
Short name T889
Test name
Test status
Simulation time 27957846 ps
CPU time 0.63 seconds
Started Mar 19 12:28:06 PM PDT 24
Finished Mar 19 12:28:06 PM PDT 24
Peak memory 202484 kb
Host smart-4ff2b2c2-4fd5-4cb6-97ba-5af4c371b76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3899558173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3899558173
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3825988296
Short name T254
Test name
Test status
Simulation time 140672966 ps
CPU time 1.46 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:14 PM PDT 24
Peak memory 202812 kb
Host smart-23e67c0e-a42e-475b-bbe1-6a3015a9f0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825988296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.3825988296
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1818811659
Short name T904
Test name
Test status
Simulation time 132366952 ps
CPU time 1.67 seconds
Started Mar 19 12:28:15 PM PDT 24
Finished Mar 19 12:28:17 PM PDT 24
Peak memory 211032 kb
Host smart-101f8b5d-62f2-43f7-927b-6da3ec8b13fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818811659 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.1818811659
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.570969753
Short name T65
Test name
Test status
Simulation time 40044246 ps
CPU time 0.95 seconds
Started Mar 19 12:28:32 PM PDT 24
Finished Mar 19 12:28:34 PM PDT 24
Peak memory 202824 kb
Host smart-85c67c6f-0777-4cd0-ae9f-0dec1d3c13aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570969753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_c
sr_outstanding.570969753
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2373877522
Short name T865
Test name
Test status
Simulation time 57419719 ps
CPU time 1.69 seconds
Started Mar 19 12:28:25 PM PDT 24
Finished Mar 19 12:28:27 PM PDT 24
Peak memory 202852 kb
Host smart-bbc5a663-5057-42d7-9b56-5034636323cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2373877522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2373877522
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.193777046
Short name T887
Test name
Test status
Simulation time 75473178 ps
CPU time 1.01 seconds
Started Mar 19 12:28:23 PM PDT 24
Finished Mar 19 12:28:24 PM PDT 24
Peak memory 202920 kb
Host smart-c6a31ced-b870-44a3-b6e5-3577dc100758
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193777046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.193777046
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3138955893
Short name T868
Test name
Test status
Simulation time 70158651 ps
CPU time 1.13 seconds
Started Mar 19 12:28:35 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 212092 kb
Host smart-abaafbd8-31de-4dc7-9fa4-fca41b40a9fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138955893 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3138955893
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1599794264
Short name T94
Test name
Test status
Simulation time 76394680 ps
CPU time 1.06 seconds
Started Mar 19 12:28:33 PM PDT 24
Finished Mar 19 12:28:35 PM PDT 24
Peak memory 202824 kb
Host smart-5f7a918a-4c17-4216-8e84-2c35daab3234
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599794264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1599794264
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1695937340
Short name T871
Test name
Test status
Simulation time 120072813 ps
CPU time 1.56 seconds
Started Mar 19 12:28:27 PM PDT 24
Finished Mar 19 12:28:29 PM PDT 24
Peak memory 202772 kb
Host smart-9934f28e-9b69-4538-b33c-6f2620ea26b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695937340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.1695937340
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.764635272
Short name T885
Test name
Test status
Simulation time 84835504 ps
CPU time 1.24 seconds
Started Mar 19 12:28:25 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 202756 kb
Host smart-0343302e-f060-4a75-bd64-1af0f4358df6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=764635272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.764635272
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.722290424
Short name T72
Test name
Test status
Simulation time 27658741 ps
CPU time 0.73 seconds
Started Mar 19 12:27:51 PM PDT 24
Finished Mar 19 12:27:52 PM PDT 24
Peak memory 202576 kb
Host smart-27c7f627-7ebd-49ab-a373-a366239e3e20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722290424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.722290424
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2652072297
Short name T197
Test name
Test status
Simulation time 77011549 ps
CPU time 1.2 seconds
Started Mar 19 12:28:05 PM PDT 24
Finished Mar 19 12:28:06 PM PDT 24
Peak memory 211100 kb
Host smart-4bed3b65-8846-4f55-829b-fef780275c9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652072297 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.2652072297
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3777926664
Short name T75
Test name
Test status
Simulation time 25673637 ps
CPU time 0.61 seconds
Started Mar 19 12:28:24 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 202488 kb
Host smart-38cfca1e-7c9a-4292-b6e8-b070dc94f8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3777926664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3777926664
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3336865394
Short name T201
Test name
Test status
Simulation time 59863078 ps
CPU time 2.05 seconds
Started Mar 19 12:28:08 PM PDT 24
Finished Mar 19 12:28:10 PM PDT 24
Peak memory 202760 kb
Host smart-1b67776c-49f9-4706-a365-10f5fafebd8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3336865394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3336865394
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1054716874
Short name T862
Test name
Test status
Simulation time 237998373 ps
CPU time 2.49 seconds
Started Mar 19 12:28:24 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 202744 kb
Host smart-c3471c31-759e-45c9-8c57-619e03a0a88c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1054716874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1054716874
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2125987318
Short name T880
Test name
Test status
Simulation time 33640068 ps
CPU time 1.06 seconds
Started Mar 19 12:28:02 PM PDT 24
Finished Mar 19 12:28:04 PM PDT 24
Peak memory 202780 kb
Host smart-846683b5-e7c2-4f72-b58b-7ad9aee3ecbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125987318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.2125987318
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2832109484
Short name T56
Test name
Test status
Simulation time 94391524 ps
CPU time 1.5 seconds
Started Mar 19 12:27:59 PM PDT 24
Finished Mar 19 12:28:01 PM PDT 24
Peak memory 202836 kb
Host smart-06449fca-0218-4e18-9adc-8b317886c474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2832109484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2832109484
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1800457347
Short name T890
Test name
Test status
Simulation time 29075037 ps
CPU time 0.63 seconds
Started Mar 19 12:28:08 PM PDT 24
Finished Mar 19 12:28:09 PM PDT 24
Peak memory 202500 kb
Host smart-d1caa05d-e635-403e-a69b-1f18e44e9864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1800457347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1800457347
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.402965996
Short name T893
Test name
Test status
Simulation time 21393849 ps
CPU time 0.67 seconds
Started Mar 19 12:28:03 PM PDT 24
Finished Mar 19 12:28:03 PM PDT 24
Peak memory 202476 kb
Host smart-53f5e8b3-cded-49b7-9754-d0ae15d06bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=402965996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.402965996
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2886116763
Short name T263
Test name
Test status
Simulation time 21615355 ps
CPU time 0.61 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:14 PM PDT 24
Peak memory 202500 kb
Host smart-096437d3-1c7f-4849-9046-91ee86dee5f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2886116763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2886116763
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3732559153
Short name T205
Test name
Test status
Simulation time 199767977 ps
CPU time 2.28 seconds
Started Mar 19 12:28:01 PM PDT 24
Finished Mar 19 12:28:03 PM PDT 24
Peak memory 202840 kb
Host smart-4980c6c0-5b54-4a06-b972-877ff1db5591
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732559153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3732559153
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2980081945
Short name T866
Test name
Test status
Simulation time 79871592 ps
CPU time 1.34 seconds
Started Mar 19 12:28:40 PM PDT 24
Finished Mar 19 12:28:41 PM PDT 24
Peak memory 212108 kb
Host smart-1846ad9a-43a0-467c-b8a6-05150cd83750
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980081945 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2980081945
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3504258279
Short name T79
Test name
Test status
Simulation time 29927588 ps
CPU time 0.62 seconds
Started Mar 19 12:28:08 PM PDT 24
Finished Mar 19 12:28:09 PM PDT 24
Peak memory 202484 kb
Host smart-1e575b6e-a5d0-43e2-99d5-e758971eb26b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3504258279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3504258279
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2548145100
Short name T206
Test name
Test status
Simulation time 147490483 ps
CPU time 2.1 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 202736 kb
Host smart-a229d29e-9b64-4af8-880f-a54912c742c6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2548145100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2548145100
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.208577560
Short name T892
Test name
Test status
Simulation time 152240073 ps
CPU time 3.73 seconds
Started Mar 19 12:28:06 PM PDT 24
Finished Mar 19 12:28:09 PM PDT 24
Peak memory 202744 kb
Host smart-0b96fdce-6238-4ea1-af5f-594ab10b218b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=208577560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.208577560
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.203077545
Short name T884
Test name
Test status
Simulation time 41720913 ps
CPU time 0.96 seconds
Started Mar 19 12:27:49 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 202820 kb
Host smart-cae801bf-c1be-4c1f-9139-172337c25246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203077545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_cs
r_outstanding.203077545
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2040692601
Short name T883
Test name
Test status
Simulation time 144150145 ps
CPU time 1.84 seconds
Started Mar 19 12:27:48 PM PDT 24
Finished Mar 19 12:27:50 PM PDT 24
Peak memory 202936 kb
Host smart-a6492601-a9dc-4a37-9ac7-1aaa03c0afc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2040692601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2040692601
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3714623589
Short name T898
Test name
Test status
Simulation time 28863435 ps
CPU time 0.66 seconds
Started Mar 19 12:28:36 PM PDT 24
Finished Mar 19 12:28:37 PM PDT 24
Peak memory 202488 kb
Host smart-50d4eb28-71f9-46bd-a0ff-2a1ff144d4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3714623589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3714623589
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3487606967
Short name T80
Test name
Test status
Simulation time 29726700 ps
CPU time 0.63 seconds
Started Mar 19 12:28:22 PM PDT 24
Finished Mar 19 12:28:28 PM PDT 24
Peak memory 202632 kb
Host smart-45de0607-2501-4008-aecb-5046b37336a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3487606967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3487606967
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2367957822
Short name T259
Test name
Test status
Simulation time 34043192 ps
CPU time 0.66 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:19 PM PDT 24
Peak memory 202496 kb
Host smart-384665c4-c6c4-4a8a-9f10-5984ba0bdc07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2367957822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2367957822
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1343248914
Short name T261
Test name
Test status
Simulation time 22768649 ps
CPU time 0.62 seconds
Started Mar 19 12:28:34 PM PDT 24
Finished Mar 19 12:28:36 PM PDT 24
Peak memory 202476 kb
Host smart-7a766ff7-f94e-498b-a7d6-21f567eb1131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1343248914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1343248914
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4190288816
Short name T902
Test name
Test status
Simulation time 128754006 ps
CPU time 3.31 seconds
Started Mar 19 12:27:50 PM PDT 24
Finished Mar 19 12:27:53 PM PDT 24
Peak memory 201828 kb
Host smart-69893ad6-0ec3-4f88-bb75-a0d3a36e5a53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190288816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.4190288816
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.746158809
Short name T69
Test name
Test status
Simulation time 192874528 ps
CPU time 4.81 seconds
Started Mar 19 12:28:08 PM PDT 24
Finished Mar 19 12:28:13 PM PDT 24
Peak memory 202804 kb
Host smart-ccce1416-96d4-4ddc-a0ab-eb667d5618e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746158809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.746158809
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2466109083
Short name T202
Test name
Test status
Simulation time 26109171 ps
CPU time 0.78 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:13 PM PDT 24
Peak memory 202516 kb
Host smart-a6c8ad94-3657-4bcb-9386-c00b7888c2e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466109083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2466109083
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2817363478
Short name T260
Test name
Test status
Simulation time 27343170 ps
CPU time 0.63 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:11 PM PDT 24
Peak memory 202464 kb
Host smart-6135cdcc-a063-4f9a-aa5b-91afe6c3b70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2817363478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2817363478
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.838159331
Short name T200
Test name
Test status
Simulation time 62374539 ps
CPU time 2 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:14 PM PDT 24
Peak memory 202820 kb
Host smart-9099b907-238e-4312-bcdf-788db2e69058
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=838159331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.838159331
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3949103215
Short name T860
Test name
Test status
Simulation time 152519655 ps
CPU time 3.8 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 202748 kb
Host smart-37113ee7-97b3-43b2-9e95-b7d822b8929b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3949103215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3949103215
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.473994486
Short name T873
Test name
Test status
Simulation time 36556402 ps
CPU time 1.04 seconds
Started Mar 19 12:28:04 PM PDT 24
Finished Mar 19 12:28:05 PM PDT 24
Peak memory 202904 kb
Host smart-a262d1a8-f932-454b-b756-05f6d7f55b29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473994486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_cs
r_outstanding.473994486
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2741889409
Short name T891
Test name
Test status
Simulation time 42601991 ps
CPU time 1.35 seconds
Started Mar 19 12:28:24 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 202852 kb
Host smart-936faae9-9faf-4daf-b879-7a2163bd0020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2741889409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2741889409
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1781734435
Short name T895
Test name
Test status
Simulation time 25720718 ps
CPU time 0.64 seconds
Started Mar 19 12:28:38 PM PDT 24
Finished Mar 19 12:28:38 PM PDT 24
Peak memory 202500 kb
Host smart-5c22ecf2-442b-42aa-8b52-e7eeed285061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1781734435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1781734435
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1542131728
Short name T899
Test name
Test status
Simulation time 28079932 ps
CPU time 0.63 seconds
Started Mar 19 12:28:44 PM PDT 24
Finished Mar 19 12:28:45 PM PDT 24
Peak memory 202496 kb
Host smart-44edd404-29b7-4f50-a186-59e98faf54a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1542131728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1542131728
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3158442587
Short name T266
Test name
Test status
Simulation time 25625802 ps
CPU time 0.65 seconds
Started Mar 19 12:28:25 PM PDT 24
Finished Mar 19 12:28:26 PM PDT 24
Peak memory 202500 kb
Host smart-f14982ef-9bd9-4119-bb87-d90bfadd4a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3158442587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3158442587
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1616354281
Short name T900
Test name
Test status
Simulation time 127114331 ps
CPU time 1.77 seconds
Started Mar 19 12:28:16 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 211100 kb
Host smart-be6c6970-b29d-4031-9007-e4fb7e017b8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616354281 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1616354281
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2974927238
Short name T203
Test name
Test status
Simulation time 38189757 ps
CPU time 1 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:19 PM PDT 24
Peak memory 202780 kb
Host smart-e87b634b-75f0-4ae7-b201-d9b4bd6e9fdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974927238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2974927238
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1701628117
Short name T76
Test name
Test status
Simulation time 21694264 ps
CPU time 0.66 seconds
Started Mar 19 12:28:17 PM PDT 24
Finished Mar 19 12:28:18 PM PDT 24
Peak memory 202596 kb
Host smart-05d7ca6d-95e8-4b57-a441-3cd2c15a2ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1701628117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1701628117
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4033802030
Short name T194
Test name
Test status
Simulation time 125348356 ps
CPU time 1.72 seconds
Started Mar 19 12:28:18 PM PDT 24
Finished Mar 19 12:28:20 PM PDT 24
Peak memory 202868 kb
Host smart-04068316-000b-4697-8710-13d448a6b94a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4033802030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4033802030
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.932466353
Short name T864
Test name
Test status
Simulation time 130432261 ps
CPU time 1.84 seconds
Started Mar 19 12:27:48 PM PDT 24
Finished Mar 19 12:27:51 PM PDT 24
Peak memory 211048 kb
Host smart-f8cb2381-ae25-491a-926b-0b621bb649ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932466353 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.932466353
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1665288178
Short name T207
Test name
Test status
Simulation time 69688241 ps
CPU time 1.06 seconds
Started Mar 19 12:28:12 PM PDT 24
Finished Mar 19 12:28:14 PM PDT 24
Peak memory 202824 kb
Host smart-9cd81de7-533a-4a7f-9548-beb534228e05
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665288178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1665288178
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1006565596
Short name T255
Test name
Test status
Simulation time 25135976 ps
CPU time 0.61 seconds
Started Mar 19 12:28:33 PM PDT 24
Finished Mar 19 12:28:35 PM PDT 24
Peak memory 202480 kb
Host smart-ad1688cd-6a8e-4038-b1d7-ca7be1d2bd5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1006565596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1006565596
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.799085777
Short name T64
Test name
Test status
Simulation time 74529897 ps
CPU time 1.15 seconds
Started Mar 19 12:28:10 PM PDT 24
Finished Mar 19 12:28:11 PM PDT 24
Peak memory 201564 kb
Host smart-13b8b88b-b70a-472c-bbf3-c4b935356add
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799085777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_cs
r_outstanding.799085777
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1793438892
Short name T195
Test name
Test status
Simulation time 63712954 ps
CPU time 1.92 seconds
Started Mar 19 12:28:13 PM PDT 24
Finished Mar 19 12:28:15 PM PDT 24
Peak memory 202880 kb
Host smart-fc690ee5-a3a9-408b-a1e5-d2ba4645e057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1793438892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1793438892
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1182109491
Short name T867
Test name
Test status
Simulation time 69262918 ps
CPU time 1.22 seconds
Started Mar 19 12:28:11 PM PDT 24
Finished Mar 19 12:28:12 PM PDT 24
Peak memory 211036 kb
Host smart-4256be0e-e0cd-49eb-ba29-73a1936208ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182109491 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1182109491
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1355671055
Short name T882
Test name
Test status
Simulation time 64056479 ps
CPU time 0.99 seconds
Started Mar 19 12:28:28 PM PDT 24
Finished Mar 19 12:28:29 PM PDT 24
Peak memory 202796 kb
Host smart-e0eb0bc9-0449-45a3-9c5a-95c47080ca74
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355671055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1355671055
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4000851304
Short name T888
Test name
Test status
Simulation time 35241562 ps
CPU time 0.94 seconds
Started Mar 19 12:28:11 PM PDT 24
Finished Mar 19 12:28:12 PM PDT 24
Peak memory 202816 kb
Host smart-8925dc21-35c1-48b3-a45b-cbf10d6983d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000851304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.4000851304
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3721182114
Short name T198
Test name
Test status
Simulation time 71342389 ps
CPU time 2 seconds
Started Mar 19 12:28:22 PM PDT 24
Finished Mar 19 12:28:24 PM PDT 24
Peak memory 202836 kb
Host smart-4ff8b02e-ddaf-480f-bd4f-6c3250be29c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3721182114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3721182114
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.3458916759
Short name T78
Test name
Test status
Simulation time 25493834 ps
CPU time 0.69 seconds
Started Mar 19 12:28:29 PM PDT 24
Finished Mar 19 12:28:30 PM PDT 24
Peak memory 202492 kb
Host smart-c8696832-802d-4647-9021-c02387ddf7ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3458916759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.3458916759
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1100437510
Short name T876
Test name
Test status
Simulation time 54257463 ps
CPU time 1.37 seconds
Started Mar 19 12:28:14 PM PDT 24
Finished Mar 19 12:28:15 PM PDT 24
Peak memory 202880 kb
Host smart-afca4389-249d-4f04-8f83-5b85eeecb0e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100437510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.1100437510
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1650360793
Short name T250
Test name
Test status
Simulation time 96632659 ps
CPU time 2.94 seconds
Started Mar 19 12:28:30 PM PDT 24
Finished Mar 19 12:28:34 PM PDT 24
Peak memory 202880 kb
Host smart-26025df4-3525-4326-8d3b-1352a79f7a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1650360793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1650360793
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.75692483
Short name T74
Test name
Test status
Simulation time 63603005 ps
CPU time 1.04 seconds
Started Mar 19 12:27:50 PM PDT 24
Finished Mar 19 12:27:51 PM PDT 24
Peak memory 202764 kb
Host smart-de911a06-3aac-403f-baf1-01235f9c080e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75692483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr
_outstanding.75692483
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3633147846
Short name T249
Test name
Test status
Simulation time 184181902 ps
CPU time 2.09 seconds
Started Mar 19 12:28:08 PM PDT 24
Finished Mar 19 12:28:10 PM PDT 24
Peak memory 202848 kb
Host smart-f0c3423a-04dc-4072-af75-e4d5444df8f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3633147846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3633147846
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4185406774
Short name T85
Test name
Test status
Simulation time 8371011937 ps
CPU time 7.32 seconds
Started Mar 19 12:53:42 PM PDT 24
Finished Mar 19 12:53:50 PM PDT 24
Peak memory 203024 kb
Host smart-6e682f6f-8a3d-47e7-ab2a-1d0b408a193f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41854
06774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4185406774
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.589939660
Short name T519
Test name
Test status
Simulation time 8369234929 ps
CPU time 7.28 seconds
Started Mar 19 12:53:42 PM PDT 24
Finished Mar 19 12:53:49 PM PDT 24
Peak memory 202836 kb
Host smart-3e894a6c-54df-4881-9e66-f0b470db6ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58993
9660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.589939660
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.33218007
Short name T482
Test name
Test status
Simulation time 92640168 ps
CPU time 1.21 seconds
Started Mar 19 12:53:43 PM PDT 24
Finished Mar 19 12:53:44 PM PDT 24
Peak memory 202776 kb
Host smart-ebbe591e-ecce-4a9c-baf0-a2b4417094af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33218
007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.33218007
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2828450375
Short name T453
Test name
Test status
Simulation time 8405640242 ps
CPU time 7.89 seconds
Started Mar 19 12:53:41 PM PDT 24
Finished Mar 19 12:53:49 PM PDT 24
Peak memory 203068 kb
Host smart-73d75be2-bb2b-4976-86d2-bcf376798ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28284
50375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2828450375
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3080098479
Short name T477
Test name
Test status
Simulation time 8366308195 ps
CPU time 7.53 seconds
Started Mar 19 12:53:42 PM PDT 24
Finished Mar 19 12:53:49 PM PDT 24
Peak memory 202988 kb
Host smart-458383b4-7940-4deb-957d-92f171d25604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30800
98479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3080098479
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3012259414
Short name T555
Test name
Test status
Simulation time 8372735063 ps
CPU time 7.69 seconds
Started Mar 19 12:53:42 PM PDT 24
Finished Mar 19 12:53:50 PM PDT 24
Peak memory 202856 kb
Host smart-2f6d00c9-9ccd-4566-a4a9-ab6e5dee672e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30122
59414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3012259414
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3216568352
Short name T719
Test name
Test status
Simulation time 8405511996 ps
CPU time 8.23 seconds
Started Mar 19 12:53:40 PM PDT 24
Finished Mar 19 12:53:49 PM PDT 24
Peak memory 202828 kb
Host smart-03870dae-c1f7-436b-b4d1-ff67f14d452d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32165
68352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3216568352
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2700846516
Short name T33
Test name
Test status
Simulation time 28924233 ps
CPU time 0.64 seconds
Started Mar 19 12:53:42 PM PDT 24
Finished Mar 19 12:53:43 PM PDT 24
Peak memory 202624 kb
Host smart-dde539a1-51ed-4918-a378-1927d33cd52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27008
46516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2700846516
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2523036033
Short name T381
Test name
Test status
Simulation time 8373161151 ps
CPU time 7.56 seconds
Started Mar 19 12:53:41 PM PDT 24
Finished Mar 19 12:53:49 PM PDT 24
Peak memory 202816 kb
Host smart-f5e48a20-a336-4060-b22a-ba14f71e4f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25230
36033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2523036033
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.829591751
Short name T284
Test name
Test status
Simulation time 8396428161 ps
CPU time 9.61 seconds
Started Mar 19 12:53:41 PM PDT 24
Finished Mar 19 12:53:51 PM PDT 24
Peak memory 202940 kb
Host smart-d33cd9d2-10e0-41b9-a806-b5830bdf9733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82959
1751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.829591751
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1981584089
Short name T383
Test name
Test status
Simulation time 8364586566 ps
CPU time 7.23 seconds
Started Mar 19 12:53:40 PM PDT 24
Finished Mar 19 12:53:48 PM PDT 24
Peak memory 202824 kb
Host smart-122af4cd-2439-40a2-9ef4-142c3fbd2b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
84089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1981584089
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1093682047
Short name T464
Test name
Test status
Simulation time 8369410182 ps
CPU time 7.16 seconds
Started Mar 19 12:53:48 PM PDT 24
Finished Mar 19 12:53:56 PM PDT 24
Peak memory 202996 kb
Host smart-95b16cbb-989a-40d5-a10e-192b918421de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10936
82047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1093682047
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.2449145873
Short name T837
Test name
Test status
Simulation time 8368107452 ps
CPU time 7.32 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:57 PM PDT 24
Peak memory 202828 kb
Host smart-a5a42c5d-e598-4f9e-8278-cc21c210d20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24491
45873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2449145873
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1570795181
Short name T371
Test name
Test status
Simulation time 222836055 ps
CPU time 1.84 seconds
Started Mar 19 12:53:50 PM PDT 24
Finished Mar 19 12:53:52 PM PDT 24
Peak memory 203136 kb
Host smart-edc3f1bf-8781-4e39-842e-4d8608a61fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15707
95181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1570795181
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.693599693
Short name T190
Test name
Test status
Simulation time 8360648766 ps
CPU time 8.66 seconds
Started Mar 19 12:53:54 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 202772 kb
Host smart-4226e1a5-6cfe-4c3d-a1ad-96e3b31b956e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69359
9693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.693599693
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.359549868
Short name T571
Test name
Test status
Simulation time 8402823279 ps
CPU time 7.55 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:57 PM PDT 24
Peak memory 203012 kb
Host smart-f14ebdd0-68a1-4cdc-a01a-9ba3abce2989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35954
9868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.359549868
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1132865111
Short name T632
Test name
Test status
Simulation time 8366557587 ps
CPU time 7.94 seconds
Started Mar 19 12:53:50 PM PDT 24
Finished Mar 19 12:53:58 PM PDT 24
Peak memory 203044 kb
Host smart-4586c363-c0d2-41d2-86b2-208eae675502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11328
65111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1132865111
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.387205648
Short name T327
Test name
Test status
Simulation time 8374962011 ps
CPU time 8.11 seconds
Started Mar 19 12:53:48 PM PDT 24
Finished Mar 19 12:53:57 PM PDT 24
Peak memory 202904 kb
Host smart-69408b51-1d4b-49dd-80b9-0a5367d44b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38720
5648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.387205648
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3976088830
Short name T645
Test name
Test status
Simulation time 8400590016 ps
CPU time 8.98 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:59 PM PDT 24
Peak memory 202896 kb
Host smart-73a43e55-0671-4370-8a6c-c002dd762b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39760
88830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3976088830
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.755241534
Short name T507
Test name
Test status
Simulation time 29942830 ps
CPU time 0.62 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:51 PM PDT 24
Peak memory 202552 kb
Host smart-b172900c-5815-4bb1-8832-1cad3285d8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75524
1534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.755241534
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.196030513
Short name T215
Test name
Test status
Simulation time 8376445459 ps
CPU time 7.7 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:58 PM PDT 24
Peak memory 203008 kb
Host smart-cd2d7918-1c7d-4b8d-8305-198c4f852be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19603
0513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.196030513
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.4064336628
Short name T401
Test name
Test status
Simulation time 8439165305 ps
CPU time 7.6 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:58 PM PDT 24
Peak memory 202976 kb
Host smart-bd8725e8-de9e-43d3-885c-73bfeb56edc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40643
36628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.4064336628
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.187473968
Short name T393
Test name
Test status
Simulation time 8375956652 ps
CPU time 7.16 seconds
Started Mar 19 12:53:54 PM PDT 24
Finished Mar 19 12:54:02 PM PDT 24
Peak memory 202992 kb
Host smart-d5483320-a9ec-4bd3-97e2-42c6c3180bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18747
3968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.187473968
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.461708356
Short name T58
Test name
Test status
Simulation time 176435216 ps
CPU time 1.03 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:51 PM PDT 24
Peak memory 219360 kb
Host smart-43312eb2-47ce-42dc-bb89-11abbcc29820
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=461708356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.461708356
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.416700576
Short name T412
Test name
Test status
Simulation time 8361359956 ps
CPU time 7.18 seconds
Started Mar 19 12:53:48 PM PDT 24
Finished Mar 19 12:53:56 PM PDT 24
Peak memory 203032 kb
Host smart-0a4419b0-f082-42d7-bf71-b5333761992f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41670
0576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.416700576
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2271502183
Short name T156
Test name
Test status
Simulation time 8472798000 ps
CPU time 9.06 seconds
Started Mar 19 12:53:50 PM PDT 24
Finished Mar 19 12:53:59 PM PDT 24
Peak memory 203008 kb
Host smart-abaef919-5dac-4eae-9c1b-dc10eb994f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22715
02183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2271502183
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2133438730
Short name T619
Test name
Test status
Simulation time 8365839280 ps
CPU time 7.36 seconds
Started Mar 19 12:54:31 PM PDT 24
Finished Mar 19 12:54:40 PM PDT 24
Peak memory 203024 kb
Host smart-25328cf3-8990-4a8a-836e-b1c3c94450d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21334
38730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2133438730
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.4152730715
Short name T49
Test name
Test status
Simulation time 8371134611 ps
CPU time 7.61 seconds
Started Mar 19 12:54:31 PM PDT 24
Finished Mar 19 12:54:38 PM PDT 24
Peak memory 202812 kb
Host smart-0d76b60c-30c9-48ed-bb09-7e38aa03d646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41527
30715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.4152730715
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2820853136
Short name T229
Test name
Test status
Simulation time 240063377 ps
CPU time 2.14 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:37 PM PDT 24
Peak memory 203172 kb
Host smart-920798b7-a16d-4363-9355-79ffe1abe3c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28208
53136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2820853136
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.56688431
Short name T718
Test name
Test status
Simulation time 8361642084 ps
CPU time 7.22 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:41 PM PDT 24
Peak memory 202808 kb
Host smart-35ee846b-f945-401b-b60c-370701ba0af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56688
431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.56688431
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3026588890
Short name T543
Test name
Test status
Simulation time 8373087010 ps
CPU time 9.42 seconds
Started Mar 19 12:54:33 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 202988 kb
Host smart-7ba7bceb-9c44-44a0-a80f-c995124523f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30265
88890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3026588890
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1681916019
Short name T372
Test name
Test status
Simulation time 8406933650 ps
CPU time 9.03 seconds
Started Mar 19 12:54:33 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 203036 kb
Host smart-be8a4b48-5c4e-4628-b1b7-24306d13bca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16819
16019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1681916019
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1355076351
Short name T476
Test name
Test status
Simulation time 8364116874 ps
CPU time 7.96 seconds
Started Mar 19 12:54:35 PM PDT 24
Finished Mar 19 12:54:43 PM PDT 24
Peak memory 203048 kb
Host smart-9f38688b-cca5-40e4-ac68-02c6a3ec1560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13550
76351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1355076351
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.4122445230
Short name T19
Test name
Test status
Simulation time 8402002510 ps
CPU time 7.69 seconds
Started Mar 19 12:54:37 PM PDT 24
Finished Mar 19 12:54:45 PM PDT 24
Peak memory 202848 kb
Host smart-13dd3c77-a2ee-4b12-b9a3-7d00b23be707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41224
45230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.4122445230
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2700111283
Short name T633
Test name
Test status
Simulation time 8379776060 ps
CPU time 7.16 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:41 PM PDT 24
Peak memory 202760 kb
Host smart-7a978b18-f628-4e1b-b97d-9aa6075e8362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27001
11283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2700111283
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3728293147
Short name T226
Test name
Test status
Simulation time 25622407 ps
CPU time 0.66 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:35 PM PDT 24
Peak memory 202580 kb
Host smart-373cb1e2-db4f-4e97-ab6d-56e4bce4b123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37282
93147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3728293147
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.4133253776
Short name T659
Test name
Test status
Simulation time 8395175702 ps
CPU time 7.97 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 202660 kb
Host smart-04711d7b-4cb8-4f9e-a2e8-b85b5f29ccc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41332
53776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.4133253776
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3132837992
Short name T517
Test name
Test status
Simulation time 8406882951 ps
CPU time 8.05 seconds
Started Mar 19 12:54:38 PM PDT 24
Finished Mar 19 12:54:47 PM PDT 24
Peak memory 203052 kb
Host smart-b5bdbd6d-1876-4af4-b84f-819abcb43251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31328
37992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3132837992
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.799796151
Short name T421
Test name
Test status
Simulation time 8401750811 ps
CPU time 7.79 seconds
Started Mar 19 12:54:32 PM PDT 24
Finished Mar 19 12:54:40 PM PDT 24
Peak memory 202972 kb
Host smart-fa9f772f-b7da-4cbc-8ad2-0f546fb48c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79979
6151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.799796151
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1563700884
Short name T656
Test name
Test status
Simulation time 8358164877 ps
CPU time 9.65 seconds
Started Mar 19 12:54:33 PM PDT 24
Finished Mar 19 12:54:43 PM PDT 24
Peak memory 202884 kb
Host smart-fa7b76dc-b4f1-47e2-91f7-bc46c951e4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15637
00884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1563700884
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.905282559
Short name T40
Test name
Test status
Simulation time 8366395055 ps
CPU time 8.48 seconds
Started Mar 19 12:54:39 PM PDT 24
Finished Mar 19 12:54:47 PM PDT 24
Peak memory 203004 kb
Host smart-4a0840f9-618b-4aa6-8f61-af3b374003f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90528
2559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.905282559
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.2625137637
Short name T323
Test name
Test status
Simulation time 8371254971 ps
CPU time 7.55 seconds
Started Mar 19 12:54:37 PM PDT 24
Finished Mar 19 12:54:45 PM PDT 24
Peak memory 202900 kb
Host smart-ef5706b2-975f-4f61-b1e6-93b87c9a22d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26251
37637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2625137637
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2350757904
Short name T469
Test name
Test status
Simulation time 157325309 ps
CPU time 1.69 seconds
Started Mar 19 12:54:37 PM PDT 24
Finished Mar 19 12:54:40 PM PDT 24
Peak memory 202924 kb
Host smart-3d539556-e1c0-43b1-af60-df1237fb47c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23507
57904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2350757904
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1055842307
Short name T165
Test name
Test status
Simulation time 8356502326 ps
CPU time 7.55 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 202772 kb
Host smart-a7c0c676-9a3d-49c2-b999-57bdda72e5e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10558
42307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1055842307
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3834053107
Short name T498
Test name
Test status
Simulation time 8391049082 ps
CPU time 10.06 seconds
Started Mar 19 12:54:37 PM PDT 24
Finished Mar 19 12:54:48 PM PDT 24
Peak memory 203056 kb
Host smart-c3c8a20c-ffe0-431e-b2ae-850eb939cc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
53107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3834053107
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2835394207
Short name T595
Test name
Test status
Simulation time 8407181943 ps
CPU time 7.56 seconds
Started Mar 19 12:54:43 PM PDT 24
Finished Mar 19 12:54:51 PM PDT 24
Peak memory 202972 kb
Host smart-094ba836-b603-4cd1-8522-2332e449ef2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28353
94207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2835394207
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3491956755
Short name T537
Test name
Test status
Simulation time 8367921319 ps
CPU time 9.56 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:50 PM PDT 24
Peak memory 203024 kb
Host smart-96f086ea-d2dc-4cf1-87d1-b144da98bd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34919
56755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3491956755
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3857700488
Short name T417
Test name
Test status
Simulation time 8391696849 ps
CPU time 7.39 seconds
Started Mar 19 12:54:39 PM PDT 24
Finished Mar 19 12:54:47 PM PDT 24
Peak memory 202920 kb
Host smart-39faf4fa-f0e8-44cc-ab88-2bf6222f187d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38577
00488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3857700488
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2958176623
Short name T243
Test name
Test status
Simulation time 8386306987 ps
CPU time 8.49 seconds
Started Mar 19 12:54:39 PM PDT 24
Finished Mar 19 12:54:48 PM PDT 24
Peak memory 203008 kb
Host smart-68578f46-f1bf-4ca1-a451-3766696f36bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29581
76623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2958176623
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.67916205
Short name T512
Test name
Test status
Simulation time 25874070 ps
CPU time 0.66 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 202556 kb
Host smart-65ade9f9-d135-475c-b1c4-029277efe853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67916
205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.67916205
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2731057248
Short name T662
Test name
Test status
Simulation time 8404207643 ps
CPU time 8.27 seconds
Started Mar 19 12:54:38 PM PDT 24
Finished Mar 19 12:54:46 PM PDT 24
Peak memory 202832 kb
Host smart-57c30044-2d1d-4098-88ba-c18b26bc8d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27310
57248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2731057248
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.626258609
Short name T646
Test name
Test status
Simulation time 8418771115 ps
CPU time 7.39 seconds
Started Mar 19 12:54:38 PM PDT 24
Finished Mar 19 12:54:45 PM PDT 24
Peak memory 203024 kb
Host smart-4957c3cc-a470-4062-b8b2-4c71d476eb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62625
8609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.626258609
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3881210233
Short name T494
Test name
Test status
Simulation time 8365706207 ps
CPU time 7.81 seconds
Started Mar 19 12:54:39 PM PDT 24
Finished Mar 19 12:54:47 PM PDT 24
Peak memory 203000 kb
Host smart-351f6dfb-21fd-4938-9b11-61b5ca85edf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38812
10233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3881210233
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.4022620994
Short name T304
Test name
Test status
Simulation time 8369949481 ps
CPU time 7.66 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 202984 kb
Host smart-0627e28a-78e2-469b-bb03-f483281a6ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
20994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.4022620994
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.4248809739
Short name T570
Test name
Test status
Simulation time 8372165881 ps
CPU time 7.41 seconds
Started Mar 19 12:54:40 PM PDT 24
Finished Mar 19 12:54:48 PM PDT 24
Peak memory 202832 kb
Host smart-809252f3-bfb8-450a-b057-90d3e46c9c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42488
09739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.4248809739
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3681603556
Short name T91
Test name
Test status
Simulation time 206420928 ps
CPU time 1.74 seconds
Started Mar 19 12:54:43 PM PDT 24
Finished Mar 19 12:54:45 PM PDT 24
Peak memory 203040 kb
Host smart-093d35c3-26a8-4576-908d-f81ea2f6054e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36816
03556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3681603556
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4123190693
Short name T693
Test name
Test status
Simulation time 8362882261 ps
CPU time 8.96 seconds
Started Mar 19 12:54:38 PM PDT 24
Finished Mar 19 12:54:47 PM PDT 24
Peak memory 202784 kb
Host smart-d6c9da38-2aa4-408a-9a5c-2f4014dcfab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41231
90693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4123190693
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.4145605788
Short name T586
Test name
Test status
Simulation time 8437233035 ps
CPU time 7.37 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 203088 kb
Host smart-48da4999-72b0-49bd-b4ed-2854c2387732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41456
05788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.4145605788
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3688955612
Short name T230
Test name
Test status
Simulation time 8407128836 ps
CPU time 8.32 seconds
Started Mar 19 12:54:39 PM PDT 24
Finished Mar 19 12:54:48 PM PDT 24
Peak memory 203072 kb
Host smart-68f9b13e-b7eb-4099-bd47-210b588ab108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36889
55612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3688955612
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2166869474
Short name T291
Test name
Test status
Simulation time 8365148085 ps
CPU time 8.8 seconds
Started Mar 19 12:54:40 PM PDT 24
Finished Mar 19 12:54:50 PM PDT 24
Peak memory 203016 kb
Host smart-8cba4dab-a818-4cfd-8635-e5b5ae53e231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21668
69474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2166869474
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1868912552
Short name T516
Test name
Test status
Simulation time 8378336332 ps
CPU time 7.22 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 202840 kb
Host smart-b4dc41d1-9c23-4bec-95b3-f6d77a0d49ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18689
12552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1868912552
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3971369850
Short name T277
Test name
Test status
Simulation time 8394201250 ps
CPU time 7.39 seconds
Started Mar 19 12:54:37 PM PDT 24
Finished Mar 19 12:54:45 PM PDT 24
Peak memory 202856 kb
Host smart-e0388af8-5ab8-4684-b3fd-d98b962357ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
69850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3971369850
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.671636744
Short name T849
Test name
Test status
Simulation time 28728543 ps
CPU time 0.63 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 202568 kb
Host smart-beae6a67-b140-4b88-b4aa-80f979588e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67163
6744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.671636744
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.4194350664
Short name T336
Test name
Test status
Simulation time 8379772503 ps
CPU time 7.51 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:48 PM PDT 24
Peak memory 202844 kb
Host smart-36c0b44c-941f-4042-9450-5faa396767aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41943
50664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.4194350664
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1066433133
Short name T801
Test name
Test status
Simulation time 8402732136 ps
CPU time 8 seconds
Started Mar 19 12:54:42 PM PDT 24
Finished Mar 19 12:54:51 PM PDT 24
Peak memory 202980 kb
Host smart-8b343bd9-a503-4c70-a539-f20266c01ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10664
33133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1066433133
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.3051817045
Short name T394
Test name
Test status
Simulation time 8370735006 ps
CPU time 7.54 seconds
Started Mar 19 12:54:44 PM PDT 24
Finished Mar 19 12:54:52 PM PDT 24
Peak memory 203040 kb
Host smart-43c3af55-009e-4a86-95c3-11d014c57abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30518
17045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.3051817045
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1715002757
Short name T642
Test name
Test status
Simulation time 8357976558 ps
CPU time 8.3 seconds
Started Mar 19 12:54:41 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 202888 kb
Host smart-9d9c654d-a3ef-457b-b8ed-d73f8a3ed863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
02757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1715002757
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1259049957
Short name T141
Test name
Test status
Simulation time 8476083466 ps
CPU time 7.68 seconds
Started Mar 19 12:54:38 PM PDT 24
Finished Mar 19 12:54:46 PM PDT 24
Peak memory 203048 kb
Host smart-b6598e85-e3ac-4d69-b648-536e7f0162e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12590
49957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1259049957
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3072086648
Short name T288
Test name
Test status
Simulation time 8372553904 ps
CPU time 7.39 seconds
Started Mar 19 12:54:45 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 203016 kb
Host smart-0681b04c-c481-4f84-abd6-a6461c29c101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30720
86648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3072086648
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.1920551422
Short name T349
Test name
Test status
Simulation time 8371395844 ps
CPU time 7.83 seconds
Started Mar 19 12:54:47 PM PDT 24
Finished Mar 19 12:54:55 PM PDT 24
Peak memory 202772 kb
Host smart-983c6a9b-6602-448b-b938-2899aa95bd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19205
51422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1920551422
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3961536992
Short name T88
Test name
Test status
Simulation time 55859001 ps
CPU time 1.54 seconds
Started Mar 19 12:54:48 PM PDT 24
Finished Mar 19 12:54:49 PM PDT 24
Peak memory 203020 kb
Host smart-3e0a7aad-51b6-4f18-ae6f-21bb290a6bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39615
36992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3961536992
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2882856069
Short name T184
Test name
Test status
Simulation time 8360790837 ps
CPU time 8.77 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:55 PM PDT 24
Peak memory 202880 kb
Host smart-0c1eab3b-afff-4114-b18c-fca2ab3216ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28828
56069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2882856069
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2602721679
Short name T227
Test name
Test status
Simulation time 8439783481 ps
CPU time 8.54 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:55 PM PDT 24
Peak memory 203008 kb
Host smart-e45b9987-d84a-4ed2-b92a-5aade73f317a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26027
21679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2602721679
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3806645654
Short name T359
Test name
Test status
Simulation time 8411586620 ps
CPU time 8.44 seconds
Started Mar 19 12:54:45 PM PDT 24
Finished Mar 19 12:54:54 PM PDT 24
Peak memory 202996 kb
Host smart-0d43b046-9e57-4037-a641-e3d37634602e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38066
45654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3806645654
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.4065828868
Short name T413
Test name
Test status
Simulation time 8369103081 ps
CPU time 9.27 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 202972 kb
Host smart-08549d94-5d72-47ef-a5db-ccf4f326ac00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40658
28868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.4065828868
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.4162352928
Short name T9
Test name
Test status
Simulation time 8400531500 ps
CPU time 7.66 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:54 PM PDT 24
Peak memory 203020 kb
Host smart-a79ddfab-bab1-4436-862d-92191a5af531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41623
52928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.4162352928
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1372654370
Short name T306
Test name
Test status
Simulation time 8379369323 ps
CPU time 7.36 seconds
Started Mar 19 12:54:48 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 202884 kb
Host smart-1e3133ea-4085-48e5-9cf0-741a70311a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13726
54370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1372654370
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2710893818
Short name T606
Test name
Test status
Simulation time 8377760735 ps
CPU time 8.46 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:55 PM PDT 24
Peak memory 202828 kb
Host smart-2343341b-e131-4866-b518-99f1a0e52145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27108
93818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2710893818
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4205222839
Short name T300
Test name
Test status
Simulation time 24733313 ps
CPU time 0.64 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 202520 kb
Host smart-bcebba91-3c10-41f0-8786-fadada8b1b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42052
22839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4205222839
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.885728472
Short name T614
Test name
Test status
Simulation time 8400752237 ps
CPU time 7.35 seconds
Started Mar 19 12:54:44 PM PDT 24
Finished Mar 19 12:54:52 PM PDT 24
Peak memory 202840 kb
Host smart-e2e842ae-9d02-4b35-98d3-cc2212d9d10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88572
8472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.885728472
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3857954501
Short name T290
Test name
Test status
Simulation time 8447245455 ps
CPU time 9.18 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 202988 kb
Host smart-a3a08f84-8bee-41b3-8a27-ca7da5768973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38579
54501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3857954501
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.2779692367
Short name T822
Test name
Test status
Simulation time 8379069099 ps
CPU time 9.18 seconds
Started Mar 19 12:54:43 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 203076 kb
Host smart-dbdcc8fe-ec7b-47fd-9cc8-dfc4756c0843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27796
92367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.2779692367
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4210335938
Short name T725
Test name
Test status
Simulation time 8356642395 ps
CPU time 9.19 seconds
Started Mar 19 12:54:47 PM PDT 24
Finished Mar 19 12:54:57 PM PDT 24
Peak memory 202972 kb
Host smart-b1529804-b79a-403c-a403-a662b3b77be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42103
35938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4210335938
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.412577665
Short name T48
Test name
Test status
Simulation time 8474078079 ps
CPU time 7.44 seconds
Started Mar 19 12:54:48 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 203036 kb
Host smart-1a9780cc-9949-4b67-a8c7-d166b278026c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257
7665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.412577665
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2973958912
Short name T663
Test name
Test status
Simulation time 8373497815 ps
CPU time 8.4 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:55:04 PM PDT 24
Peak memory 202996 kb
Host smart-46dc7101-2f51-42bd-b5a9-9a8876d4b191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29739
58912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2973958912
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.3978063914
Short name T648
Test name
Test status
Simulation time 8369188840 ps
CPU time 7.59 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:54 PM PDT 24
Peak memory 203056 kb
Host smart-4a0b3b44-4e01-4157-8014-b0a5029e7841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39780
63914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3978063914
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3803825233
Short name T703
Test name
Test status
Simulation time 47854451 ps
CPU time 1.31 seconds
Started Mar 19 12:54:47 PM PDT 24
Finished Mar 19 12:54:48 PM PDT 24
Peak memory 203120 kb
Host smart-444d9aea-dc80-42b9-896f-f878c08400a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38038
25233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3803825233
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1403744963
Short name T191
Test name
Test status
Simulation time 8358233267 ps
CPU time 8.92 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 203116 kb
Host smart-cb6f4059-f392-47ad-9885-b2276aa1ab15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14037
44963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1403744963
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1288801581
Short name T144
Test name
Test status
Simulation time 8393918850 ps
CPU time 7.09 seconds
Started Mar 19 12:54:40 PM PDT 24
Finished Mar 19 12:54:47 PM PDT 24
Peak memory 203028 kb
Host smart-27bc0b84-5bb6-486a-bbf0-7db190f4a370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12888
01581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1288801581
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2087455193
Short name T17
Test name
Test status
Simulation time 8405104189 ps
CPU time 7.63 seconds
Started Mar 19 12:54:45 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 202972 kb
Host smart-30503906-b2c1-4606-9936-b21164931bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20874
55193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2087455193
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.4135714468
Short name T560
Test name
Test status
Simulation time 8364914800 ps
CPU time 8.55 seconds
Started Mar 19 12:54:43 PM PDT 24
Finished Mar 19 12:54:52 PM PDT 24
Peak memory 203028 kb
Host smart-8b972ba3-1d6c-478d-94ed-61bc97bdaa30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
14468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.4135714468
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1184046369
Short name T583
Test name
Test status
Simulation time 8394425939 ps
CPU time 7.58 seconds
Started Mar 19 12:54:43 PM PDT 24
Finished Mar 19 12:54:51 PM PDT 24
Peak memory 202900 kb
Host smart-23e0a985-9344-4e53-b99e-6919412b8d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11840
46369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1184046369
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1888916856
Short name T853
Test name
Test status
Simulation time 8384138798 ps
CPU time 7.8 seconds
Started Mar 19 12:54:45 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 202972 kb
Host smart-6e080953-564d-4d75-b0a1-0f6f6dbaf11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18889
16856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1888916856
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.4115583721
Short name T738
Test name
Test status
Simulation time 27503445 ps
CPU time 0.65 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:47 PM PDT 24
Peak memory 202544 kb
Host smart-34d6ec2e-38c5-440d-be88-fd82e3affdb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41155
83721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.4115583721
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3074107675
Short name T777
Test name
Test status
Simulation time 8392245706 ps
CPU time 8.44 seconds
Started Mar 19 12:54:44 PM PDT 24
Finished Mar 19 12:54:54 PM PDT 24
Peak memory 202852 kb
Host smart-80ad1328-d782-4810-aeaa-b39c75527dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30741
07675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3074107675
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2416804607
Short name T654
Test name
Test status
Simulation time 8385491251 ps
CPU time 8.95 seconds
Started Mar 19 12:54:43 PM PDT 24
Finished Mar 19 12:54:52 PM PDT 24
Peak memory 203000 kb
Host smart-1124b1d2-df81-48e8-a555-5379b75275b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24168
04607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2416804607
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3784034729
Short name T384
Test name
Test status
Simulation time 8362130346 ps
CPU time 8.76 seconds
Started Mar 19 12:54:44 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 202836 kb
Host smart-f4736a2e-3998-4367-9048-a46cf59ba8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37840
34729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3784034729
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1569069418
Short name T150
Test name
Test status
Simulation time 8473250012 ps
CPU time 7.42 seconds
Started Mar 19 12:54:49 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 203052 kb
Host smart-846d4ddd-85ed-40a0-a409-8a55c4357b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15690
69418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1569069418
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.252553255
Short name T450
Test name
Test status
Simulation time 8373745850 ps
CPU time 8.25 seconds
Started Mar 19 12:54:47 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 202992 kb
Host smart-ef1c20bd-32d2-4fd0-9ef3-655c49fc96ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25255
3255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.252553255
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.2598070036
Short name T805
Test name
Test status
Simulation time 8372910163 ps
CPU time 8.36 seconds
Started Mar 19 12:54:43 PM PDT 24
Finished Mar 19 12:54:52 PM PDT 24
Peak memory 202896 kb
Host smart-5d3469da-3d89-4442-a7f5-826b2f15100d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25980
70036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2598070036
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3468464954
Short name T720
Test name
Test status
Simulation time 185351332 ps
CPU time 2.07 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:54:58 PM PDT 24
Peak memory 202872 kb
Host smart-0453bdfa-b543-4918-a8ee-e15ec8c687ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34684
64954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3468464954
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2851129545
Short name T694
Test name
Test status
Simulation time 8419496610 ps
CPU time 7.59 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:55:03 PM PDT 24
Peak memory 202988 kb
Host smart-4110d4cf-4ca6-4720-962f-f275bb36c546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511
29545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2851129545
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.43585591
Short name T816
Test name
Test status
Simulation time 8401623198 ps
CPU time 7.79 seconds
Started Mar 19 12:54:45 PM PDT 24
Finished Mar 19 12:54:53 PM PDT 24
Peak memory 203076 kb
Host smart-9fd22d4c-5594-4da8-af7c-0dcdf4b9a637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43585
591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.43585591
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1944106510
Short name T599
Test name
Test status
Simulation time 8368940159 ps
CPU time 7.18 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:55:03 PM PDT 24
Peak memory 202980 kb
Host smart-cff241e6-3a71-479c-a6f9-2856bbc7d746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19441
06510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1944106510
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.953682607
Short name T480
Test name
Test status
Simulation time 8382864954 ps
CPU time 7.55 seconds
Started Mar 19 12:54:44 PM PDT 24
Finished Mar 19 12:54:52 PM PDT 24
Peak memory 202900 kb
Host smart-3409aef2-3eb2-4ab2-8194-4b60c704cf4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95368
2607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.953682607
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2110525584
Short name T620
Test name
Test status
Simulation time 8389705366 ps
CPU time 7.69 seconds
Started Mar 19 12:54:48 PM PDT 24
Finished Mar 19 12:54:56 PM PDT 24
Peak memory 202932 kb
Host smart-ccd71002-26f6-4939-8df8-140ad965dd4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105
25584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2110525584
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1928244503
Short name T724
Test name
Test status
Simulation time 31247270 ps
CPU time 0.64 seconds
Started Mar 19 12:54:51 PM PDT 24
Finished Mar 19 12:54:51 PM PDT 24
Peak memory 202580 kb
Host smart-43e4ba40-e0b2-42c6-b577-5bfa34b4dba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19282
44503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1928244503
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.213009981
Short name T456
Test name
Test status
Simulation time 8395380834 ps
CPU time 7.65 seconds
Started Mar 19 12:54:47 PM PDT 24
Finished Mar 19 12:54:55 PM PDT 24
Peak memory 203160 kb
Host smart-231fb5f2-833d-4994-b570-6aeeace0edc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21300
9981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.213009981
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2116885730
Short name T508
Test name
Test status
Simulation time 8418708806 ps
CPU time 7.82 seconds
Started Mar 19 12:54:46 PM PDT 24
Finished Mar 19 12:54:54 PM PDT 24
Peak memory 203044 kb
Host smart-fce8d5b7-7437-476c-98e2-ca42fbe8362c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21168
85730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2116885730
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.3592335449
Short name T410
Test name
Test status
Simulation time 8389790928 ps
CPU time 9.88 seconds
Started Mar 19 12:54:44 PM PDT 24
Finished Mar 19 12:54:54 PM PDT 24
Peak memory 203016 kb
Host smart-9acd5222-1976-46ed-9b5b-75e94d9a32c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923
35449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.3592335449
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.630354645
Short name T424
Test name
Test status
Simulation time 8359170093 ps
CPU time 7.43 seconds
Started Mar 19 12:54:51 PM PDT 24
Finished Mar 19 12:54:59 PM PDT 24
Peak memory 202848 kb
Host smart-68103821-1063-422d-8dfe-f1a47d7681c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63035
4645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.630354645
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.346431872
Short name T704
Test name
Test status
Simulation time 8366631007 ps
CPU time 7.56 seconds
Started Mar 19 12:54:50 PM PDT 24
Finished Mar 19 12:54:57 PM PDT 24
Peak memory 203040 kb
Host smart-0bdabd68-ac96-4de9-ad50-62f2e9b0ace2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34643
1872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.346431872
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.2612503754
Short name T332
Test name
Test status
Simulation time 8370800999 ps
CPU time 8.46 seconds
Started Mar 19 12:54:53 PM PDT 24
Finished Mar 19 12:55:02 PM PDT 24
Peak memory 202804 kb
Host smart-77857d66-3732-456b-a912-ee728c829c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26125
03754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2612503754
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1914131756
Short name T178
Test name
Test status
Simulation time 8365034716 ps
CPU time 7.34 seconds
Started Mar 19 12:54:50 PM PDT 24
Finished Mar 19 12:54:58 PM PDT 24
Peak memory 202852 kb
Host smart-ba06eb55-4bf0-4f20-9329-6266628884e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19141
31756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1914131756
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.734197967
Short name T139
Test name
Test status
Simulation time 8381550848 ps
CPU time 7.38 seconds
Started Mar 19 12:54:54 PM PDT 24
Finished Mar 19 12:55:02 PM PDT 24
Peak memory 202992 kb
Host smart-a7fc0a6c-dbb6-4882-8063-f2f7f82efe2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73419
7967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.734197967
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.641923476
Short name T429
Test name
Test status
Simulation time 8405767052 ps
CPU time 7.51 seconds
Started Mar 19 12:54:54 PM PDT 24
Finished Mar 19 12:55:01 PM PDT 24
Peak memory 203044 kb
Host smart-5369fa5c-3aab-4099-882a-2b95bcf2530c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64192
3476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.641923476
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.641095408
Short name T569
Test name
Test status
Simulation time 8362413090 ps
CPU time 8.49 seconds
Started Mar 19 12:54:57 PM PDT 24
Finished Mar 19 12:55:05 PM PDT 24
Peak memory 203080 kb
Host smart-e8c768ce-e623-4607-b959-19a3754e812a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64109
5408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.641095408
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2594941417
Short name T653
Test name
Test status
Simulation time 8386226746 ps
CPU time 8.53 seconds
Started Mar 19 12:54:54 PM PDT 24
Finished Mar 19 12:55:02 PM PDT 24
Peak memory 203036 kb
Host smart-23cd6c2d-c263-49f7-b1a5-59ebaa98f895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25949
41417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2594941417
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2759634499
Short name T324
Test name
Test status
Simulation time 8393541326 ps
CPU time 9.52 seconds
Started Mar 19 12:54:54 PM PDT 24
Finished Mar 19 12:55:04 PM PDT 24
Peak memory 203012 kb
Host smart-a1f5ad13-0f39-4f8a-8aa3-d7f90d157d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
34499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2759634499
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2693442296
Short name T682
Test name
Test status
Simulation time 28163207 ps
CPU time 0.66 seconds
Started Mar 19 12:54:52 PM PDT 24
Finished Mar 19 12:54:52 PM PDT 24
Peak memory 202512 kb
Host smart-99d2f8d0-2541-44b9-87c8-ebba912717bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26934
42296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2693442296
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3427825300
Short name T572
Test name
Test status
Simulation time 8366964037 ps
CPU time 7.15 seconds
Started Mar 19 12:54:50 PM PDT 24
Finished Mar 19 12:54:57 PM PDT 24
Peak memory 202776 kb
Host smart-9e017471-50a0-4c77-9197-d651a0b49956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34278
25300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3427825300
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1736406026
Short name T673
Test name
Test status
Simulation time 8405341015 ps
CPU time 9.07 seconds
Started Mar 19 12:54:52 PM PDT 24
Finished Mar 19 12:55:01 PM PDT 24
Peak memory 202952 kb
Host smart-37aa1707-d257-4eaa-a4ea-7b0cb02ff907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17364
06026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1736406026
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.1560510771
Short name T518
Test name
Test status
Simulation time 8386033503 ps
CPU time 9.56 seconds
Started Mar 19 12:54:50 PM PDT 24
Finished Mar 19 12:55:00 PM PDT 24
Peak memory 202944 kb
Host smart-96267a96-a2d0-4314-8c5f-99c9bd6ec5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15605
10771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.1560510771
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2244864576
Short name T783
Test name
Test status
Simulation time 8356928895 ps
CPU time 7.56 seconds
Started Mar 19 12:54:50 PM PDT 24
Finished Mar 19 12:54:58 PM PDT 24
Peak memory 202872 kb
Host smart-57937efa-a855-46fb-9841-6c9923c25d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22448
64576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2244864576
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2935278251
Short name T766
Test name
Test status
Simulation time 8474506122 ps
CPU time 8.27 seconds
Started Mar 19 12:54:52 PM PDT 24
Finished Mar 19 12:55:00 PM PDT 24
Peak memory 203016 kb
Host smart-383b8b4d-86b1-4135-a128-7738217fa619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29352
78251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2935278251
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2492957408
Short name T780
Test name
Test status
Simulation time 8366308536 ps
CPU time 7.38 seconds
Started Mar 19 12:54:52 PM PDT 24
Finished Mar 19 12:54:59 PM PDT 24
Peak memory 203080 kb
Host smart-e03375e9-3907-4478-bddc-337f79f0aa9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24929
57408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2492957408
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.3610918758
Short name T458
Test name
Test status
Simulation time 8368713255 ps
CPU time 7.73 seconds
Started Mar 19 12:54:51 PM PDT 24
Finished Mar 19 12:54:59 PM PDT 24
Peak memory 202780 kb
Host smart-45f5d6d1-58e5-4d63-ba4a-9204b6ab98fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
18758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3610918758
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.493860061
Short name T826
Test name
Test status
Simulation time 121831386 ps
CPU time 1.2 seconds
Started Mar 19 12:54:53 PM PDT 24
Finished Mar 19 12:54:54 PM PDT 24
Peak memory 202852 kb
Host smart-190a3bd6-6c04-4653-8f4a-a526acac389a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49386
0061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.493860061
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2618976158
Short name T727
Test name
Test status
Simulation time 8359609565 ps
CPU time 8.09 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:07 PM PDT 24
Peak memory 202812 kb
Host smart-f530fa5b-3907-487a-9fb5-0be587824268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26189
76158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2618976158
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3246140286
Short name T806
Test name
Test status
Simulation time 8418999844 ps
CPU time 7.43 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:06 PM PDT 24
Peak memory 203012 kb
Host smart-32fa2636-892b-4fa0-8c1f-79cd7ee638ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32461
40286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3246140286
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3878651081
Short name T432
Test name
Test status
Simulation time 8411306626 ps
CPU time 8.17 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 202976 kb
Host smart-2895ae6b-9a6d-4f34-bb34-ef3ee6337a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38786
51081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3878651081
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2233991253
Short name T797
Test name
Test status
Simulation time 8361829558 ps
CPU time 7.67 seconds
Started Mar 19 12:54:58 PM PDT 24
Finished Mar 19 12:55:06 PM PDT 24
Peak memory 203004 kb
Host smart-9fbbe2bf-453d-49f9-8962-8b56ac8716f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22339
91253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2233991253
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1471003302
Short name T575
Test name
Test status
Simulation time 8384217102 ps
CPU time 7.81 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 202836 kb
Host smart-b41e6f73-8a37-47ae-8ae5-f8ae7a71771f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14710
03302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1471003302
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.4196327163
Short name T299
Test name
Test status
Simulation time 8409952586 ps
CPU time 8.19 seconds
Started Mar 19 12:55:02 PM PDT 24
Finished Mar 19 12:55:10 PM PDT 24
Peak memory 202868 kb
Host smart-1f3972af-47ac-47a6-ac7f-5daacb602627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41963
27163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.4196327163
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2193596521
Short name T499
Test name
Test status
Simulation time 25773360 ps
CPU time 0.68 seconds
Started Mar 19 12:55:01 PM PDT 24
Finished Mar 19 12:55:02 PM PDT 24
Peak memory 202676 kb
Host smart-c5b54919-f9c8-43e2-b02a-14e0d9c5125e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21935
96521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2193596521
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3792773839
Short name T270
Test name
Test status
Simulation time 8365678973 ps
CPU time 7.54 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:06 PM PDT 24
Peak memory 202828 kb
Host smart-c2eadea1-3015-43d0-b7b0-e696c5e7a84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37927
73839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3792773839
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2979646086
Short name T368
Test name
Test status
Simulation time 8440292953 ps
CPU time 7.59 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:07 PM PDT 24
Peak memory 202984 kb
Host smart-ea040c8f-75b4-44b2-a24d-0ba932e4e2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796
46086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2979646086
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.2323384069
Short name T378
Test name
Test status
Simulation time 8374126995 ps
CPU time 7.94 seconds
Started Mar 19 12:54:57 PM PDT 24
Finished Mar 19 12:55:05 PM PDT 24
Peak memory 203044 kb
Host smart-ed5a2495-7219-4ca9-9f15-c0d916850d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23233
84069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.2323384069
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2659510373
Short name T577
Test name
Test status
Simulation time 8362394526 ps
CPU time 8.1 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 203016 kb
Host smart-5a8ec5ff-0b92-45de-86c8-ce545e51c0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26595
10373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2659510373
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2351945055
Short name T132
Test name
Test status
Simulation time 8476755593 ps
CPU time 7.66 seconds
Started Mar 19 12:54:52 PM PDT 24
Finished Mar 19 12:55:00 PM PDT 24
Peak memory 203048 kb
Host smart-0ee98053-ce3a-44bd-83b4-c97a5ff92fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23519
45055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2351945055
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3696330570
Short name T448
Test name
Test status
Simulation time 8368898559 ps
CPU time 7.78 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 203068 kb
Host smart-ddfa142e-a22d-4c48-af3f-d3cb2c751990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36963
30570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3696330570
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.2916631431
Short name T387
Test name
Test status
Simulation time 8372200439 ps
CPU time 7.32 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:06 PM PDT 24
Peak memory 202820 kb
Host smart-0bfaadca-426c-4e64-bc9a-dc01eea6f45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29166
31431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2916631431
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3918881936
Short name T743
Test name
Test status
Simulation time 73631374 ps
CPU time 2 seconds
Started Mar 19 12:54:56 PM PDT 24
Finished Mar 19 12:54:58 PM PDT 24
Peak memory 203048 kb
Host smart-f9e7c3a6-d7ec-4ee8-8f3b-15dd07c6a9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39188
81936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3918881936
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1119940843
Short name T841
Test name
Test status
Simulation time 8361583225 ps
CPU time 7.85 seconds
Started Mar 19 12:54:57 PM PDT 24
Finished Mar 19 12:55:05 PM PDT 24
Peak memory 202884 kb
Host smart-aa3486f4-c346-4c03-aaee-607e96cff61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11199
40843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1119940843
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2750865674
Short name T803
Test name
Test status
Simulation time 8431856671 ps
CPU time 8.79 seconds
Started Mar 19 12:55:05 PM PDT 24
Finished Mar 19 12:55:14 PM PDT 24
Peak memory 202996 kb
Host smart-da701538-4af2-44f4-b031-fa4c67e60f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27508
65674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2750865674
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.61040713
Short name T218
Test name
Test status
Simulation time 8406641318 ps
CPU time 9.41 seconds
Started Mar 19 12:54:58 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 203036 kb
Host smart-020d208e-eefd-46b3-a38e-f3d96de0bc08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61040
713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.61040713
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1590851802
Short name T418
Test name
Test status
Simulation time 8365340151 ps
CPU time 8.05 seconds
Started Mar 19 12:54:58 PM PDT 24
Finished Mar 19 12:55:06 PM PDT 24
Peak memory 202980 kb
Host smart-4123f0b4-a021-437f-8b4a-d32e577816f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
51802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1590851802
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.7958354
Short name T850
Test name
Test status
Simulation time 8389706327 ps
CPU time 8.98 seconds
Started Mar 19 12:55:01 PM PDT 24
Finished Mar 19 12:55:10 PM PDT 24
Peak memory 202292 kb
Host smart-0b72cde2-088d-4c54-b080-03932d4fd856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79583
54 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.7958354
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3149844515
Short name T217
Test name
Test status
Simulation time 8363911142 ps
CPU time 7.35 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 203004 kb
Host smart-39a34269-0bed-4f60-bbaf-ec3feedf2d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31498
44515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3149844515
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2889336669
Short name T37
Test name
Test status
Simulation time 28360242 ps
CPU time 0.63 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:01 PM PDT 24
Peak memory 202604 kb
Host smart-2ee27e91-0653-4a3e-ba1b-0eabac346396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
36669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2889336669
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.672001388
Short name T50
Test name
Test status
Simulation time 8377416629 ps
CPU time 7.53 seconds
Started Mar 19 12:54:58 PM PDT 24
Finished Mar 19 12:55:05 PM PDT 24
Peak memory 202840 kb
Host smart-ea0ad441-64a3-4cb4-9cd3-953ad41dcec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67200
1388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.672001388
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.311752740
Short name T128
Test name
Test status
Simulation time 8391853541 ps
CPU time 7.61 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 203008 kb
Host smart-b5c8ad98-b35c-4fa1-8f1d-771d6881e9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31175
2740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.311752740
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.1031039568
Short name T855
Test name
Test status
Simulation time 8403313059 ps
CPU time 7.22 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:06 PM PDT 24
Peak memory 203012 kb
Host smart-06c271cb-dfb1-486e-93dd-5b81c18993ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10310
39568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.1031039568
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2524749093
Short name T366
Test name
Test status
Simulation time 8359766510 ps
CPU time 9.32 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:09 PM PDT 24
Peak memory 203032 kb
Host smart-71d4cde9-296b-4816-919d-759a9811155e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25247
49093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2524749093
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.4197008301
Short name T814
Test name
Test status
Simulation time 8478690878 ps
CPU time 7.39 seconds
Started Mar 19 12:54:59 PM PDT 24
Finished Mar 19 12:55:07 PM PDT 24
Peak memory 203012 kb
Host smart-e5a7fa3b-ab87-4ecd-9bb3-508164b3af1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41970
08301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.4197008301
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3932935942
Short name T47
Test name
Test status
Simulation time 8372475005 ps
CPU time 9.11 seconds
Started Mar 19 12:54:58 PM PDT 24
Finished Mar 19 12:55:07 PM PDT 24
Peak memory 202980 kb
Host smart-a8a9ee3b-ef90-429c-bf29-ce23e46e5a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39329
35942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3932935942
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.1792030808
Short name T278
Test name
Test status
Simulation time 8370301946 ps
CPU time 7.88 seconds
Started Mar 19 12:54:57 PM PDT 24
Finished Mar 19 12:55:05 PM PDT 24
Peak memory 202992 kb
Host smart-b7340365-1149-4395-8a8e-e3a445afb1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17920
30808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1792030808
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.824130357
Short name T733
Test name
Test status
Simulation time 53759129 ps
CPU time 1.57 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:01 PM PDT 24
Peak memory 203044 kb
Host smart-b847975b-6c14-40c4-a683-5f7bc7bfd2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82413
0357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.824130357
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.4211152566
Short name T764
Test name
Test status
Simulation time 8358192038 ps
CPU time 7.06 seconds
Started Mar 19 12:55:05 PM PDT 24
Finished Mar 19 12:55:12 PM PDT 24
Peak memory 202820 kb
Host smart-0b4257cd-9096-42a0-99ec-220fa1390499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42111
52566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.4211152566
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2880078135
Short name T485
Test name
Test status
Simulation time 8431599860 ps
CPU time 8.23 seconds
Started Mar 19 12:55:01 PM PDT 24
Finished Mar 19 12:55:09 PM PDT 24
Peak memory 203008 kb
Host smart-d5b0bed1-1bf2-4c47-a95f-daf1e33d6a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28800
78135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2880078135
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.3928220492
Short name T411
Test name
Test status
Simulation time 8407513146 ps
CPU time 7.31 seconds
Started Mar 19 12:54:58 PM PDT 24
Finished Mar 19 12:55:06 PM PDT 24
Peak memory 203048 kb
Host smart-49376590-bd05-490c-bd1e-5a6120459c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282
20492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.3928220492
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1674056822
Short name T550
Test name
Test status
Simulation time 8359862595 ps
CPU time 7.77 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 202988 kb
Host smart-312d3195-42e0-4d16-a115-ac263b7f98ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16740
56822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1674056822
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.134338586
Short name T796
Test name
Test status
Simulation time 8398623421 ps
CPU time 8.97 seconds
Started Mar 19 12:55:02 PM PDT 24
Finished Mar 19 12:55:11 PM PDT 24
Peak memory 203008 kb
Host smart-3bc37121-d0ff-4ecb-abd0-e6b1301e0a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13433
8586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.134338586
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.4017960115
Short name T578
Test name
Test status
Simulation time 8384694235 ps
CPU time 7.88 seconds
Started Mar 19 12:55:00 PM PDT 24
Finished Mar 19 12:55:08 PM PDT 24
Peak memory 202996 kb
Host smart-a9c15d8b-9655-4c6c-972c-3859cd16890a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40179
60115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4017960115
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1892373815
Short name T821
Test name
Test status
Simulation time 8399935328 ps
CPU time 7.28 seconds
Started Mar 19 12:54:58 PM PDT 24
Finished Mar 19 12:55:05 PM PDT 24
Peak memory 203016 kb
Host smart-ee3a2b59-eeb1-4c6f-beff-cba74e5243fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18923
73815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1892373815
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1764678113
Short name T800
Test name
Test status
Simulation time 29837984 ps
CPU time 0.62 seconds
Started Mar 19 12:55:06 PM PDT 24
Finished Mar 19 12:55:07 PM PDT 24
Peak memory 202556 kb
Host smart-a2bc5387-a7ad-4cbd-866a-41c0f2ccb820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17646
78113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1764678113
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3439435398
Short name T548
Test name
Test status
Simulation time 8401404886 ps
CPU time 9.69 seconds
Started Mar 19 12:55:06 PM PDT 24
Finished Mar 19 12:55:16 PM PDT 24
Peak memory 202824 kb
Host smart-0f488c71-94fd-4762-9be6-3ecfa7f4115c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34394
35398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3439435398
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2919718754
Short name T29
Test name
Test status
Simulation time 8440487121 ps
CPU time 9.22 seconds
Started Mar 19 12:55:08 PM PDT 24
Finished Mar 19 12:55:17 PM PDT 24
Peak memory 203004 kb
Host smart-a92f04ac-7fdd-47fb-a92c-92d95f3685c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29197
18754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2919718754
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.2595443811
Short name T345
Test name
Test status
Simulation time 8411025995 ps
CPU time 7.86 seconds
Started Mar 19 12:55:07 PM PDT 24
Finished Mar 19 12:55:15 PM PDT 24
Peak memory 202976 kb
Host smart-d27ed81f-45d1-4842-a43c-b3426feceb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25954
43811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.2595443811
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2511122017
Short name T672
Test name
Test status
Simulation time 8356268526 ps
CPU time 7.79 seconds
Started Mar 19 12:55:09 PM PDT 24
Finished Mar 19 12:55:17 PM PDT 24
Peak memory 203064 kb
Host smart-38f5e8b4-0686-45df-bf9f-187962392f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25111
22017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2511122017
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2786069520
Short name T282
Test name
Test status
Simulation time 8369004439 ps
CPU time 7.79 seconds
Started Mar 19 12:53:49 PM PDT 24
Finished Mar 19 12:53:57 PM PDT 24
Peak memory 203024 kb
Host smart-11046a26-05e1-4139-ae3d-68acb2704018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27860
69520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2786069520
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.733286699
Short name T523
Test name
Test status
Simulation time 8370698618 ps
CPU time 7.94 seconds
Started Mar 19 12:53:56 PM PDT 24
Finished Mar 19 12:54:04 PM PDT 24
Peak memory 202788 kb
Host smart-8ca8fa57-482f-4f17-949d-b3d0653abe23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73328
6699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.733286699
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.116108966
Short name T337
Test name
Test status
Simulation time 68901637 ps
CPU time 1.04 seconds
Started Mar 19 12:53:55 PM PDT 24
Finished Mar 19 12:53:56 PM PDT 24
Peak memory 203044 kb
Host smart-64163da8-bd76-4b43-8a8b-d5f125beafeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11610
8966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.116108966
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2411577275
Short name T166
Test name
Test status
Simulation time 8362406797 ps
CPU time 7.66 seconds
Started Mar 19 12:53:55 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 202760 kb
Host smart-807c2159-d4ba-4b16-99cc-7be5d1838c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
77275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2411577275
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3820402603
Short name T22
Test name
Test status
Simulation time 8425706205 ps
CPU time 7.27 seconds
Started Mar 19 12:53:55 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 202996 kb
Host smart-886351ac-f51d-47ff-b226-617472554893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38204
02603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3820402603
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.605828140
Short name T379
Test name
Test status
Simulation time 8406689530 ps
CPU time 8.52 seconds
Started Mar 19 12:53:54 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 203004 kb
Host smart-3d949996-cd89-4528-9678-1d2753405c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60582
8140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.605828140
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3292205253
Short name T585
Test name
Test status
Simulation time 8364568868 ps
CPU time 8.05 seconds
Started Mar 19 12:53:55 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 202992 kb
Host smart-369bff17-3643-4eee-9c9b-0a3f06cb4dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32922
05253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3292205253
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2561431010
Short name T637
Test name
Test status
Simulation time 8379546955 ps
CPU time 7.47 seconds
Started Mar 19 12:53:55 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 202916 kb
Host smart-de6d3854-d1bb-47de-8fd2-d695308b2a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25614
31010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2561431010
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2574427387
Short name T487
Test name
Test status
Simulation time 8376045424 ps
CPU time 8.13 seconds
Started Mar 19 12:53:56 PM PDT 24
Finished Mar 19 12:54:05 PM PDT 24
Peak memory 202896 kb
Host smart-b1b0d9eb-c8fa-4e36-8d7e-c469a5c45d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25744
27387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2574427387
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.4091510585
Short name T212
Test name
Test status
Simulation time 24715287 ps
CPU time 0.64 seconds
Started Mar 19 12:53:56 PM PDT 24
Finished Mar 19 12:53:58 PM PDT 24
Peak memory 202556 kb
Host smart-0f6bbf22-3fb8-4535-aad3-4761e4d4af61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40915
10585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.4091510585
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.235784666
Short name T661
Test name
Test status
Simulation time 8408055776 ps
CPU time 7.33 seconds
Started Mar 19 12:53:54 PM PDT 24
Finished Mar 19 12:54:02 PM PDT 24
Peak memory 202848 kb
Host smart-61d54eaa-7dc9-4941-ac48-f80cdfea2b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23578
4666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.235784666
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.52804492
Short name T709
Test name
Test status
Simulation time 8411057826 ps
CPU time 7.98 seconds
Started Mar 19 12:53:55 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 203064 kb
Host smart-93fd9c90-2a56-46cd-aa10-0576fab6908d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52804
492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.52804492
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1018096869
Short name T223
Test name
Test status
Simulation time 8391618108 ps
CPU time 7.74 seconds
Started Mar 19 12:53:56 PM PDT 24
Finished Mar 19 12:54:05 PM PDT 24
Peak memory 203008 kb
Host smart-ae9a0f48-98e0-4656-ae83-f8421d78098a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10180
96869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1018096869
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2207046299
Short name T83
Test name
Test status
Simulation time 95918428 ps
CPU time 0.92 seconds
Started Mar 19 12:53:54 PM PDT 24
Finished Mar 19 12:53:56 PM PDT 24
Peak memory 218916 kb
Host smart-f46f158b-0e54-4687-b229-bce02e4345fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2207046299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2207046299
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3276505774
Short name T765
Test name
Test status
Simulation time 8361782339 ps
CPU time 7.33 seconds
Started Mar 19 12:53:55 PM PDT 24
Finished Mar 19 12:54:02 PM PDT 24
Peak memory 202884 kb
Host smart-e7e4cce9-1bfc-424a-ba0f-431d7b6b1b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32765
05774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3276505774
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3821195622
Short name T677
Test name
Test status
Simulation time 8478319705 ps
CPU time 8.6 seconds
Started Mar 19 12:53:51 PM PDT 24
Finished Mar 19 12:53:59 PM PDT 24
Peak memory 203076 kb
Host smart-8eeb7393-0d49-49c1-9390-8d628e91b8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38211
95622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3821195622
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2911197953
Short name T45
Test name
Test status
Simulation time 8371308316 ps
CPU time 7.62 seconds
Started Mar 19 12:55:06 PM PDT 24
Finished Mar 19 12:55:14 PM PDT 24
Peak memory 202988 kb
Host smart-cb3849c1-a33c-491f-858b-ae2d5a74c225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29111
97953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2911197953
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.3929874972
Short name T809
Test name
Test status
Simulation time 8370059166 ps
CPU time 9.52 seconds
Started Mar 19 12:55:07 PM PDT 24
Finished Mar 19 12:55:17 PM PDT 24
Peak memory 202816 kb
Host smart-775e6aba-1238-42ce-abd0-1f92fdb27fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39298
74972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3929874972
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3743947023
Short name T308
Test name
Test status
Simulation time 299131802 ps
CPU time 2.39 seconds
Started Mar 19 12:55:07 PM PDT 24
Finished Mar 19 12:55:10 PM PDT 24
Peak memory 203104 kb
Host smart-d5179041-8692-466e-92e8-7af62e17bdf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37439
47023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3743947023
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1779702610
Short name T553
Test name
Test status
Simulation time 8361563806 ps
CPU time 7.39 seconds
Started Mar 19 12:55:07 PM PDT 24
Finished Mar 19 12:55:15 PM PDT 24
Peak memory 202796 kb
Host smart-5b886f95-36e7-4c99-be13-75757787a96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
02610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1779702610
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3711107928
Short name T600
Test name
Test status
Simulation time 8398050107 ps
CPU time 9.69 seconds
Started Mar 19 12:55:08 PM PDT 24
Finished Mar 19 12:55:18 PM PDT 24
Peak memory 203068 kb
Host smart-70c78a75-cc57-45e6-a173-9ec37141aab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37111
07928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3711107928
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2073971122
Short name T280
Test name
Test status
Simulation time 8407500413 ps
CPU time 9.55 seconds
Started Mar 19 12:55:10 PM PDT 24
Finished Mar 19 12:55:20 PM PDT 24
Peak memory 203048 kb
Host smart-587a98eb-77ba-4bef-ac3b-1b2dc857e7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20739
71122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2073971122
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2827572444
Short name T772
Test name
Test status
Simulation time 8366304146 ps
CPU time 7.3 seconds
Started Mar 19 12:55:11 PM PDT 24
Finished Mar 19 12:55:19 PM PDT 24
Peak memory 202988 kb
Host smart-5833a0d5-a6ed-4283-81e9-d29d7895330a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28275
72444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2827572444
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3551168828
Short name T576
Test name
Test status
Simulation time 8420188205 ps
CPU time 8.89 seconds
Started Mar 19 12:55:06 PM PDT 24
Finished Mar 19 12:55:15 PM PDT 24
Peak memory 202976 kb
Host smart-de476ba4-f8ec-4705-aea5-48300f0438a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
68828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3551168828
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3191221033
Short name T618
Test name
Test status
Simulation time 8410677504 ps
CPU time 9.3 seconds
Started Mar 19 12:55:12 PM PDT 24
Finished Mar 19 12:55:22 PM PDT 24
Peak memory 202836 kb
Host smart-64982ed0-b8c9-4307-afb0-d88d628c1577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31912
21033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3191221033
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3462002519
Short name T752
Test name
Test status
Simulation time 8379239878 ps
CPU time 7.39 seconds
Started Mar 19 12:55:12 PM PDT 24
Finished Mar 19 12:55:20 PM PDT 24
Peak memory 202844 kb
Host smart-1022cc5c-933a-4e37-8ae7-d39aad94d8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34620
02519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3462002519
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.69826185
Short name T608
Test name
Test status
Simulation time 22747873 ps
CPU time 0.59 seconds
Started Mar 19 12:55:06 PM PDT 24
Finished Mar 19 12:55:07 PM PDT 24
Peak memory 202560 kb
Host smart-e4bc794e-094d-401d-bc12-3a0907fad02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69826
185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.69826185
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1546577327
Short name T525
Test name
Test status
Simulation time 8381152085 ps
CPU time 7.15 seconds
Started Mar 19 12:55:09 PM PDT 24
Finished Mar 19 12:55:16 PM PDT 24
Peak memory 202796 kb
Host smart-238403f0-2937-4fb1-8ef3-4db34168a76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
77327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1546577327
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.47412673
Short name T667
Test name
Test status
Simulation time 8436768752 ps
CPU time 8.03 seconds
Started Mar 19 12:55:10 PM PDT 24
Finished Mar 19 12:55:18 PM PDT 24
Peak memory 203048 kb
Host smart-28a29c57-1835-4e0a-89c5-86453a3746b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47412
673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.47412673
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.974855879
Short name T292
Test name
Test status
Simulation time 8394357648 ps
CPU time 9.42 seconds
Started Mar 19 12:55:08 PM PDT 24
Finished Mar 19 12:55:17 PM PDT 24
Peak memory 203044 kb
Host smart-58736d14-ed4a-44cc-87e6-255f417c7d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97485
5879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.974855879
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.388034247
Short name T834
Test name
Test status
Simulation time 8358360443 ps
CPU time 7.85 seconds
Started Mar 19 12:55:08 PM PDT 24
Finished Mar 19 12:55:16 PM PDT 24
Peak memory 203080 kb
Host smart-377b5612-0205-4aa3-8bc7-82885cce34c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38803
4247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.388034247
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1502290191
Short name T164
Test name
Test status
Simulation time 8479797007 ps
CPU time 8.24 seconds
Started Mar 19 12:55:10 PM PDT 24
Finished Mar 19 12:55:18 PM PDT 24
Peak memory 202992 kb
Host smart-4077883b-01c7-4df0-a427-4b46bacd480e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15022
90191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1502290191
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2758899573
Short name T443
Test name
Test status
Simulation time 8371576014 ps
CPU time 9.2 seconds
Started Mar 19 12:55:10 PM PDT 24
Finished Mar 19 12:55:19 PM PDT 24
Peak memory 203048 kb
Host smart-82712390-cca2-4531-8ca1-f9399ad43e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27588
99573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2758899573
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.407512117
Short name T610
Test name
Test status
Simulation time 8369076454 ps
CPU time 7.68 seconds
Started Mar 19 12:55:05 PM PDT 24
Finished Mar 19 12:55:13 PM PDT 24
Peak memory 202992 kb
Host smart-b76fa8e7-7b70-492f-ac78-53efb7d70b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
2117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.407512117
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2562876845
Short name T238
Test name
Test status
Simulation time 71897394 ps
CPU time 2.04 seconds
Started Mar 19 12:55:17 PM PDT 24
Finished Mar 19 12:55:19 PM PDT 24
Peak memory 202224 kb
Host smart-ae4a2095-8458-4824-8c6a-98bfc6a04775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25628
76845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2562876845
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2981440771
Short name T183
Test name
Test status
Simulation time 8363121160 ps
CPU time 7.89 seconds
Started Mar 19 12:55:14 PM PDT 24
Finished Mar 19 12:55:22 PM PDT 24
Peak memory 202812 kb
Host smart-b2597b93-04b6-40a7-8dba-ca2da05e61ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29814
40771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2981440771
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1976989435
Short name T90
Test name
Test status
Simulation time 8410044153 ps
CPU time 7.7 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 203052 kb
Host smart-4d0378c8-1df6-4dc0-8c43-72c5ac1c4717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19769
89435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1976989435
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.971016369
Short name T442
Test name
Test status
Simulation time 8405234940 ps
CPU time 7.61 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 203048 kb
Host smart-a9d26e78-9e5a-4b59-98a1-7828e54b2b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97101
6369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.971016369
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1288933618
Short name T237
Test name
Test status
Simulation time 8365447184 ps
CPU time 9.77 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:25 PM PDT 24
Peak memory 203000 kb
Host smart-3d592d48-e32a-429f-9ef6-c5eb91b2e1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889
33618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1288933618
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2490832799
Short name T121
Test name
Test status
Simulation time 8387849410 ps
CPU time 7.69 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:26 PM PDT 24
Peak memory 203060 kb
Host smart-9bc49964-31cd-4f52-b78e-03f7e3719d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24908
32799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2490832799
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1794861815
Short name T370
Test name
Test status
Simulation time 8383554353 ps
CPU time 7.65 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:26 PM PDT 24
Peak memory 202920 kb
Host smart-63a5e561-0b0b-425f-a579-b407eda0d683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17948
61815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1794861815
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.240447208
Short name T364
Test name
Test status
Simulation time 8370037809 ps
CPU time 8.06 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:26 PM PDT 24
Peak memory 202896 kb
Host smart-97d20553-7097-4acc-81d1-93fe45c695f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24044
7208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.240447208
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1707579437
Short name T222
Test name
Test status
Simulation time 8390978348 ps
CPU time 7.31 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 202960 kb
Host smart-b6d83a67-a3b7-47a4-a0e9-474324e042ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
79437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1707579437
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3632441653
Short name T127
Test name
Test status
Simulation time 8416438711 ps
CPU time 8.01 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:26 PM PDT 24
Peak memory 203080 kb
Host smart-0048c8fc-744c-4d11-84bc-b88cd623d404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36324
41653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3632441653
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1091299410
Short name T624
Test name
Test status
Simulation time 8389935979 ps
CPU time 9.91 seconds
Started Mar 19 12:55:17 PM PDT 24
Finished Mar 19 12:55:27 PM PDT 24
Peak memory 202980 kb
Host smart-4f55ee7c-452d-4a72-a433-5b67332a3e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10912
99410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1091299410
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3150265045
Short name T587
Test name
Test status
Simulation time 8356628289 ps
CPU time 7.41 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 202884 kb
Host smart-1fab6df3-d865-4b3b-8fe7-4f307ba5da89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502
65045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3150265045
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1363958400
Short name T584
Test name
Test status
Simulation time 8473749226 ps
CPU time 7.35 seconds
Started Mar 19 12:55:08 PM PDT 24
Finished Mar 19 12:55:15 PM PDT 24
Peak memory 202992 kb
Host smart-15ffef8c-d078-4edd-818a-2a5c48eac7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13639
58400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1363958400
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4001432585
Short name T650
Test name
Test status
Simulation time 8368084463 ps
CPU time 7.67 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 202948 kb
Host smart-8c984ffd-fd88-413d-a1f2-81d3c0129045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40014
32585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4001432585
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.3165346119
Short name T430
Test name
Test status
Simulation time 8369352633 ps
CPU time 7.72 seconds
Started Mar 19 12:55:14 PM PDT 24
Finished Mar 19 12:55:22 PM PDT 24
Peak memory 202888 kb
Host smart-37467995-f9e6-4975-bf89-9fa1ecf424d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
46119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3165346119
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3522286925
Short name T241
Test name
Test status
Simulation time 83874447 ps
CPU time 1.15 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:18 PM PDT 24
Peak memory 202848 kb
Host smart-5fb3db38-d4af-4adb-a372-cc0f661f3442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
86925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3522286925
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1758229018
Short name T185
Test name
Test status
Simulation time 8357144101 ps
CPU time 8.4 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 202740 kb
Host smart-23593198-4b5e-4650-9c10-84180a4ae838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17582
29018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1758229018
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2971836623
Short name T590
Test name
Test status
Simulation time 8420994575 ps
CPU time 7.23 seconds
Started Mar 19 12:55:20 PM PDT 24
Finished Mar 19 12:55:27 PM PDT 24
Peak memory 203080 kb
Host smart-486af7c1-71b4-4eea-aeb6-447a501008e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29718
36623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2971836623
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.4080927986
Short name T542
Test name
Test status
Simulation time 8407136094 ps
CPU time 7.17 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 203040 kb
Host smart-a89e4e88-eebd-4192-a01b-50575fb6015d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40809
27986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.4080927986
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.643913609
Short name T295
Test name
Test status
Simulation time 8367879604 ps
CPU time 8 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 203024 kb
Host smart-1541a330-5a11-47c2-aa37-8d191abeb990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64391
3609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.643913609
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2534861903
Short name T103
Test name
Test status
Simulation time 8391650096 ps
CPU time 7.29 seconds
Started Mar 19 12:55:17 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 203020 kb
Host smart-19ae3529-1cc4-4d8c-9b2d-c398b08c3b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25348
61903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2534861903
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2809853014
Short name T723
Test name
Test status
Simulation time 8375841559 ps
CPU time 7.6 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:22 PM PDT 24
Peak memory 202852 kb
Host smart-94bbcd8c-3af2-447b-92e2-02737eabcd11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28098
53014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2809853014
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1109382368
Short name T836
Test name
Test status
Simulation time 8402808109 ps
CPU time 8.55 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 202828 kb
Host smart-1dab4c5f-640d-4ad7-b5ea-6be3a87ba492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11093
82368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1109382368
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.301506800
Short name T792
Test name
Test status
Simulation time 27416546 ps
CPU time 0.64 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:16 PM PDT 24
Peak memory 202540 kb
Host smart-ae6eb0d0-b50b-4978-9cc4-4a3cf1d26760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150
6800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.301506800
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.94427777
Short name T328
Test name
Test status
Simulation time 8379588604 ps
CPU time 8.21 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:26 PM PDT 24
Peak memory 202844 kb
Host smart-b3711c5b-86bc-4ed0-8ab9-395e281dbda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94427
777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.94427777
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3247327354
Short name T329
Test name
Test status
Simulation time 8418860051 ps
CPU time 7.65 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 203016 kb
Host smart-7fa64fd5-2699-4815-98b8-968efd5d4939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
27354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3247327354
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.1251612476
Short name T468
Test name
Test status
Simulation time 8382529305 ps
CPU time 7.63 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:26 PM PDT 24
Peak memory 203044 kb
Host smart-f864f982-afec-4b97-9ec4-04ad58c77c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12516
12476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.1251612476
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1316112854
Short name T492
Test name
Test status
Simulation time 8361287354 ps
CPU time 8.88 seconds
Started Mar 19 12:55:17 PM PDT 24
Finished Mar 19 12:55:26 PM PDT 24
Peak memory 203028 kb
Host smart-4cb02b08-cfef-4d4a-b4fb-fd676dbc0035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13161
12854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1316112854
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1997148230
Short name T771
Test name
Test status
Simulation time 8371370081 ps
CPU time 7.26 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 203012 kb
Host smart-a0013577-ab38-4d76-bc1f-3731482e4d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19971
48230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1997148230
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.1280394034
Short name T286
Test name
Test status
Simulation time 8374501847 ps
CPU time 8.56 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:27 PM PDT 24
Peak memory 202792 kb
Host smart-22b04c1f-da98-4020-a1af-ff90324f5f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12803
94034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1280394034
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.4019397340
Short name T302
Test name
Test status
Simulation time 59800862 ps
CPU time 1.65 seconds
Started Mar 19 12:55:17 PM PDT 24
Finished Mar 19 12:55:19 PM PDT 24
Peak memory 203084 kb
Host smart-3bfd2e1d-3e04-4e13-b0d4-240df2d3cfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40193
97340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.4019397340
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.4260493398
Short name T636
Test name
Test status
Simulation time 8430087477 ps
CPU time 7.69 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 203068 kb
Host smart-bd688b0d-0a9c-482d-9dcf-2fa0ff231d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42604
93398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.4260493398
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3540533000
Short name T713
Test name
Test status
Simulation time 8406159261 ps
CPU time 7.6 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 203036 kb
Host smart-21e01549-ffab-4cdc-8da6-286003328ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35405
33000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3540533000
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2716875581
Short name T235
Test name
Test status
Simulation time 8359319482 ps
CPU time 7.7 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 203060 kb
Host smart-f06cb2fc-0b5d-4896-953b-f9947345c315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27168
75581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2716875581
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.476297605
Short name T96
Test name
Test status
Simulation time 8384377122 ps
CPU time 7.46 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:25 PM PDT 24
Peak memory 202888 kb
Host smart-16acc8f3-ff18-483c-ae3f-ce7bfcfd1a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47629
7605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.476297605
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1213119398
Short name T20
Test name
Test status
Simulation time 8402715274 ps
CPU time 7.38 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 202884 kb
Host smart-5002e34a-8661-4627-a862-c790e976b4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131
19398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1213119398
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1994276769
Short name T781
Test name
Test status
Simulation time 8379055646 ps
CPU time 7.65 seconds
Started Mar 19 12:55:20 PM PDT 24
Finished Mar 19 12:55:27 PM PDT 24
Peak memory 203064 kb
Host smart-ac191abe-5f5b-400b-b014-2a739bdc42da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19942
76769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1994276769
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2462262944
Short name T303
Test name
Test status
Simulation time 27641127 ps
CPU time 0.65 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:19 PM PDT 24
Peak memory 202592 kb
Host smart-b9c302b4-4c5e-4cdf-b879-e15055780843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24622
62944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2462262944
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.4161179217
Short name T740
Test name
Test status
Simulation time 8373912655 ps
CPU time 7.23 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 203032 kb
Host smart-3a1e7ab9-4546-456c-ab86-8ed2686c3dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
79217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.4161179217
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3262902361
Short name T276
Test name
Test status
Simulation time 8447626710 ps
CPU time 7.58 seconds
Started Mar 19 12:55:16 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 203028 kb
Host smart-3cd01ff0-89dd-4142-8c42-2abd38b2595a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32629
02361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3262902361
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.133635854
Short name T275
Test name
Test status
Simulation time 8405838008 ps
CPU time 8.75 seconds
Started Mar 19 12:55:14 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 202972 kb
Host smart-fc30bf2c-5409-4900-b765-6ea70080a42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
5854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.133635854
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1389995481
Short name T690
Test name
Test status
Simulation time 8357680239 ps
CPU time 9.16 seconds
Started Mar 19 12:55:18 PM PDT 24
Finished Mar 19 12:55:28 PM PDT 24
Peak memory 202836 kb
Host smart-114e23ea-00b9-4953-b945-cb1d5c83e79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13899
95481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1389995481
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3562616757
Short name T643
Test name
Test status
Simulation time 8480012741 ps
CPU time 8.5 seconds
Started Mar 19 12:55:15 PM PDT 24
Finished Mar 19 12:55:24 PM PDT 24
Peak memory 203040 kb
Host smart-193e5a64-3541-46bb-bb06-70124a71fc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35626
16757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3562616757
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3430169243
Short name T89
Test name
Test status
Simulation time 8372641844 ps
CPU time 7.55 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 203048 kb
Host smart-6dd8e002-940b-46d6-8596-e4f6a7263a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34301
69243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3430169243
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.2668128701
Short name T625
Test name
Test status
Simulation time 8366360076 ps
CPU time 7.73 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 202836 kb
Host smart-c879b80c-8edb-4e20-901f-3cc6becd11ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26681
28701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2668128701
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1512378278
Short name T87
Test name
Test status
Simulation time 161423412 ps
CPU time 1.56 seconds
Started Mar 19 12:55:21 PM PDT 24
Finished Mar 19 12:55:23 PM PDT 24
Peak memory 203096 kb
Host smart-89b87eae-aede-41d6-81df-1df40e3f290a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15123
78278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1512378278
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.4229018219
Short name T171
Test name
Test status
Simulation time 8360065175 ps
CPU time 7.62 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 202844 kb
Host smart-8accfaff-d3ed-4cc6-a38f-e52008c64067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42290
18219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.4229018219
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3237582447
Short name T134
Test name
Test status
Simulation time 8388656063 ps
CPU time 9.49 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:39 PM PDT 24
Peak memory 202980 kb
Host smart-f4cea213-96c2-4e6c-9d4f-a40fd755755a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32375
82447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3237582447
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2265789414
Short name T768
Test name
Test status
Simulation time 8409903927 ps
CPU time 9.56 seconds
Started Mar 19 12:55:27 PM PDT 24
Finished Mar 19 12:55:36 PM PDT 24
Peak memory 203044 kb
Host smart-a0826e34-37b8-4cef-91d9-0df80cfa8fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22657
89414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2265789414
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3029701138
Short name T607
Test name
Test status
Simulation time 8363569956 ps
CPU time 7.39 seconds
Started Mar 19 12:55:28 PM PDT 24
Finished Mar 19 12:55:35 PM PDT 24
Peak memory 203040 kb
Host smart-db9a8e7e-3809-4a85-a223-c07b5752fb0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30297
01138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3029701138
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2905282647
Short name T123
Test name
Test status
Simulation time 8422021761 ps
CPU time 8.95 seconds
Started Mar 19 12:55:23 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 203028 kb
Host smart-6e6c848d-8d55-4725-bf23-032a3f2fe9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29052
82647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2905282647
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.2365583868
Short name T403
Test name
Test status
Simulation time 8363576939 ps
CPU time 7.88 seconds
Started Mar 19 12:55:22 PM PDT 24
Finished Mar 19 12:55:30 PM PDT 24
Peak memory 202924 kb
Host smart-b0313f57-da7d-49ce-a61b-c0600446f413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23655
83868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2365583868
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2404124148
Short name T3
Test name
Test status
Simulation time 8371633541 ps
CPU time 7.28 seconds
Started Mar 19 12:55:23 PM PDT 24
Finished Mar 19 12:55:30 PM PDT 24
Peak memory 202816 kb
Host smart-ecbdc8fb-ad07-44c4-85fd-293cf29762bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24041
24148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2404124148
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1022111777
Short name T674
Test name
Test status
Simulation time 26480509 ps
CPU time 0.66 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:25 PM PDT 24
Peak memory 202572 kb
Host smart-eda20eca-3d16-497f-8660-aee530a583b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10221
11777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1022111777
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.339929442
Short name T350
Test name
Test status
Simulation time 8409837447 ps
CPU time 9 seconds
Started Mar 19 12:55:22 PM PDT 24
Finished Mar 19 12:55:31 PM PDT 24
Peak memory 202848 kb
Host smart-19ec4ed9-c479-4265-b4c4-3584cb1e03c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33992
9442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.339929442
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.452702777
Short name T592
Test name
Test status
Simulation time 8419448349 ps
CPU time 7.58 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 202984 kb
Host smart-a60ce1e5-be37-45cd-83e6-ba45b8301b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45270
2777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.452702777
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.2698503425
Short name T811
Test name
Test status
Simulation time 8382200707 ps
CPU time 7.32 seconds
Started Mar 19 12:55:23 PM PDT 24
Finished Mar 19 12:55:31 PM PDT 24
Peak memory 203044 kb
Host smart-5edb790d-c10d-40c0-9e3d-63fdebf07d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26985
03425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.2698503425
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1966075569
Short name T524
Test name
Test status
Simulation time 8359131455 ps
CPU time 7.44 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 202884 kb
Host smart-ddc27807-b118-462a-8320-ac733949ea8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19660
75569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1966075569
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.923976002
Short name T852
Test name
Test status
Simulation time 8368504187 ps
CPU time 9.09 seconds
Started Mar 19 12:55:21 PM PDT 24
Finished Mar 19 12:55:30 PM PDT 24
Peak memory 203004 kb
Host smart-f7b67a22-eb1d-4256-aff2-aaf5d0e10cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92397
6002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.923976002
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.3208143715
Short name T534
Test name
Test status
Simulation time 8373244707 ps
CPU time 7.61 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 202876 kb
Host smart-87363677-fcfd-4a60-9236-d0d3cc6f31c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32081
43715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3208143715
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1356417394
Short name T246
Test name
Test status
Simulation time 95353942 ps
CPU time 1.13 seconds
Started Mar 19 12:55:20 PM PDT 24
Finished Mar 19 12:55:22 PM PDT 24
Peak memory 203088 kb
Host smart-fa1e2f76-5f04-4afd-883b-bd4ae8c436fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13564
17394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1356417394
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4085441572
Short name T179
Test name
Test status
Simulation time 8361948334 ps
CPU time 8.34 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 202828 kb
Host smart-bc820b22-7da2-4a42-8c0c-d88c5694aac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40854
41572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4085441572
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.16886102
Short name T7
Test name
Test status
Simulation time 8379684060 ps
CPU time 8.93 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:41 PM PDT 24
Peak memory 203008 kb
Host smart-3039752d-ae89-4d1f-9656-c339613059fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16886
102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.16886102
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3694065129
Short name T679
Test name
Test status
Simulation time 8406318152 ps
CPU time 7.69 seconds
Started Mar 19 12:55:28 PM PDT 24
Finished Mar 19 12:55:36 PM PDT 24
Peak memory 203012 kb
Host smart-10089233-e654-42db-9d0f-bc9a2dbb4108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36940
65129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3694065129
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2010897428
Short name T10
Test name
Test status
Simulation time 8363585213 ps
CPU time 8.29 seconds
Started Mar 19 12:55:20 PM PDT 24
Finished Mar 19 12:55:29 PM PDT 24
Peak memory 203004 kb
Host smart-98c25c44-2f6c-47ed-a34a-f285124c0cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20108
97428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2010897428
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.4269361081
Short name T100
Test name
Test status
Simulation time 8441014968 ps
CPU time 7.43 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 203048 kb
Host smart-209fc000-a0c6-47e2-9d37-fdcf7335613c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42693
61081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.4269361081
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2493485858
Short name T701
Test name
Test status
Simulation time 8375467833 ps
CPU time 8.09 seconds
Started Mar 19 12:55:28 PM PDT 24
Finished Mar 19 12:55:36 PM PDT 24
Peak memory 202840 kb
Host smart-cbec0e1a-3380-492b-9519-2d205b00d822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24934
85858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2493485858
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1882147314
Short name T474
Test name
Test status
Simulation time 8400781936 ps
CPU time 7.25 seconds
Started Mar 19 12:55:23 PM PDT 24
Finished Mar 19 12:55:31 PM PDT 24
Peak memory 202892 kb
Host smart-fc2bdb22-b823-43e7-998e-98d601c8f1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18821
47314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1882147314
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.3400847857
Short name T491
Test name
Test status
Simulation time 23773492 ps
CPU time 0.65 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:25 PM PDT 24
Peak memory 202508 kb
Host smart-92b6cedb-0c56-48ed-8138-7565abb10867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34008
47857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.3400847857
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.556257610
Short name T402
Test name
Test status
Simulation time 8366060228 ps
CPU time 7.2 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:31 PM PDT 24
Peak memory 202844 kb
Host smart-7d2e1cd6-441b-4baf-9b4a-074067c8c40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55625
7610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.556257610
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3537905159
Short name T135
Test name
Test status
Simulation time 8373481595 ps
CPU time 8.58 seconds
Started Mar 19 12:55:22 PM PDT 24
Finished Mar 19 12:55:30 PM PDT 24
Peak memory 203016 kb
Host smart-c62edd9b-ddb0-425d-a148-b9fa4ddc5a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35379
05159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3537905159
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.2663019158
Short name T353
Test name
Test status
Simulation time 8382668094 ps
CPU time 7.17 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 203044 kb
Host smart-543005ee-5738-4af1-86ad-6c768c52b2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
19158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.2663019158
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.380975873
Short name T851
Test name
Test status
Simulation time 8359880015 ps
CPU time 7.6 seconds
Started Mar 19 12:55:25 PM PDT 24
Finished Mar 19 12:55:33 PM PDT 24
Peak memory 202896 kb
Host smart-26a9becf-9cd4-4708-990c-bfb3735fadab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38097
5873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.380975873
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.508546614
Short name T136
Test name
Test status
Simulation time 8468109615 ps
CPU time 7.71 seconds
Started Mar 19 12:55:23 PM PDT 24
Finished Mar 19 12:55:31 PM PDT 24
Peak memory 203012 kb
Host smart-f4666716-a4e1-4219-a80e-917960365968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50854
6614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.508546614
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.4175566206
Short name T644
Test name
Test status
Simulation time 8364628832 ps
CPU time 8.07 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:33 PM PDT 24
Peak memory 203052 kb
Host smart-e8a3fd4d-0fed-4ec6-9a31-4918dd5d66e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41755
66206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.4175566206
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.3808145477
Short name T854
Test name
Test status
Simulation time 8368660671 ps
CPU time 7.15 seconds
Started Mar 19 12:55:26 PM PDT 24
Finished Mar 19 12:55:33 PM PDT 24
Peak memory 202740 kb
Host smart-124cb0d2-a93b-4fd6-b9f3-2d07f7f02e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38081
45477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3808145477
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.194065408
Short name T774
Test name
Test status
Simulation time 165236489 ps
CPU time 1.91 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 203144 kb
Host smart-cec9cb7a-537d-47f2-b1ad-eab821666175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19406
5408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.194065408
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1642316737
Short name T172
Test name
Test status
Simulation time 8364253125 ps
CPU time 7.62 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 202776 kb
Host smart-2aeb6f45-6a4d-4d15-a350-f99399bbc9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16423
16737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1642316737
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1442432732
Short name T554
Test name
Test status
Simulation time 8447635888 ps
CPU time 7.83 seconds
Started Mar 19 12:55:23 PM PDT 24
Finished Mar 19 12:55:31 PM PDT 24
Peak memory 203044 kb
Host smart-c0378fb2-55d8-494c-bb48-460c6ec17904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
32732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1442432732
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4226345826
Short name T321
Test name
Test status
Simulation time 8408244263 ps
CPU time 8.72 seconds
Started Mar 19 12:55:27 PM PDT 24
Finished Mar 19 12:55:36 PM PDT 24
Peak memory 203008 kb
Host smart-77510eae-6a3d-4c14-8b12-64669ac6091a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42263
45826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4226345826
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2779878867
Short name T408
Test name
Test status
Simulation time 8367871154 ps
CPU time 9.74 seconds
Started Mar 19 12:55:28 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 203016 kb
Host smart-84400660-d05b-4d63-82aa-e30e71c25a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27798
78867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2779878867
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.801650408
Short name T115
Test name
Test status
Simulation time 8412375863 ps
CPU time 7.26 seconds
Started Mar 19 12:55:25 PM PDT 24
Finished Mar 19 12:55:33 PM PDT 24
Peak memory 202864 kb
Host smart-8183a9fe-a6ee-419e-8cce-14757aa52fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80165
0408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.801650408
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2887776551
Short name T18
Test name
Test status
Simulation time 8404131329 ps
CPU time 9.05 seconds
Started Mar 19 12:55:26 PM PDT 24
Finished Mar 19 12:55:36 PM PDT 24
Peak memory 202788 kb
Host smart-12573f2c-f135-4499-a946-8f80680cfbcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28877
76551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2887776551
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1147153560
Short name T481
Test name
Test status
Simulation time 8395209753 ps
CPU time 7.82 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 202972 kb
Host smart-a5549e81-7ee9-4046-9a26-187ea1e4eab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471
53560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1147153560
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1230077935
Short name T695
Test name
Test status
Simulation time 24068903 ps
CPU time 0.64 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:31 PM PDT 24
Peak memory 202652 kb
Host smart-b8bf12c1-ec08-4ad6-b59a-1fa5ba94f516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12300
77935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1230077935
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.436637770
Short name T406
Test name
Test status
Simulation time 8392711316 ps
CPU time 9.92 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:40 PM PDT 24
Peak memory 202832 kb
Host smart-31e9eef7-d64e-4b61-b33c-85e2e071f557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43663
7770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.436637770
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.886240812
Short name T655
Test name
Test status
Simulation time 8392747464 ps
CPU time 7.3 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:39 PM PDT 24
Peak memory 203004 kb
Host smart-aec96a56-ed3d-47f6-86ad-958c102969bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88624
0812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.886240812
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2998855357
Short name T840
Test name
Test status
Simulation time 8358190270 ps
CPU time 7.47 seconds
Started Mar 19 12:55:26 PM PDT 24
Finished Mar 19 12:55:34 PM PDT 24
Peak memory 202236 kb
Host smart-edffe75e-667d-41b0-93ad-0bc63e982810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
55357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2998855357
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2184400447
Short name T715
Test name
Test status
Simulation time 8474046881 ps
CPU time 8.29 seconds
Started Mar 19 12:55:26 PM PDT 24
Finished Mar 19 12:55:34 PM PDT 24
Peak memory 203004 kb
Host smart-bf50a20b-1123-499e-9841-08637c50e449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21844
00447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2184400447
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2415181952
Short name T647
Test name
Test status
Simulation time 8368709096 ps
CPU time 7.46 seconds
Started Mar 19 12:55:20 PM PDT 24
Finished Mar 19 12:55:28 PM PDT 24
Peak memory 203076 kb
Host smart-ef3986fc-d2ec-4a95-bda5-0637706a2ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24151
81952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2415181952
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.228922548
Short name T369
Test name
Test status
Simulation time 8366941721 ps
CPU time 8.55 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:39 PM PDT 24
Peak memory 203036 kb
Host smart-f269deb4-82d6-4816-ad65-1162869b9351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22892
2548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.228922548
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1656240907
Short name T269
Test name
Test status
Simulation time 189297717 ps
CPU time 1.6 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 203136 kb
Host smart-49e445f0-6f0f-42d9-aa8a-d85ca0815541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16562
40907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1656240907
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.852409577
Short name T173
Test name
Test status
Simulation time 8357728254 ps
CPU time 9.94 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 202820 kb
Host smart-5d4f455a-eda8-4fe5-8c66-33c524b6e924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85240
9577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.852409577
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.4240219969
Short name T818
Test name
Test status
Simulation time 8414434443 ps
CPU time 8.31 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 202956 kb
Host smart-b851a311-58c4-4b1c-9f63-889fbcaa135b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42402
19969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.4240219969
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3067591479
Short name T698
Test name
Test status
Simulation time 8406524065 ps
CPU time 7.86 seconds
Started Mar 19 12:55:24 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 202980 kb
Host smart-a757fab3-67d1-44f8-b019-e8bc468215da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30675
91479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3067591479
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3402771276
Short name T786
Test name
Test status
Simulation time 8361006168 ps
CPU time 7.32 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 202968 kb
Host smart-aa75d0b7-6190-4732-9dde-b611578f3843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34027
71276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3402771276
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1096250960
Short name T787
Test name
Test status
Simulation time 8406443663 ps
CPU time 8.33 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 203064 kb
Host smart-b0f19673-f6e0-4f29-b77a-984f09f65bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10962
50960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1096250960
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.664252751
Short name T385
Test name
Test status
Simulation time 8387270373 ps
CPU time 7.24 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 203004 kb
Host smart-b55c724a-2c8a-4fba-ba06-70f6df6d7bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66425
2751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.664252751
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2049374060
Short name T296
Test name
Test status
Simulation time 8395318843 ps
CPU time 7.22 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 203000 kb
Host smart-ec358e9f-5241-4763-bcd7-e1a8a832d46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20493
74060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2049374060
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2885709441
Short name T475
Test name
Test status
Simulation time 30731161 ps
CPU time 0.65 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:32 PM PDT 24
Peak memory 202568 kb
Host smart-64ab2231-181e-4faa-8a52-04a9c4145606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28857
09441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2885709441
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2169314778
Short name T622
Test name
Test status
Simulation time 8377298554 ps
CPU time 7.14 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 202832 kb
Host smart-8db31f89-172e-4c6e-be75-53bafdf725a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
14778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2169314778
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3444213255
Short name T228
Test name
Test status
Simulation time 8427060781 ps
CPU time 8.14 seconds
Started Mar 19 12:55:32 PM PDT 24
Finished Mar 19 12:55:40 PM PDT 24
Peak memory 202980 kb
Host smart-744699c5-0cd1-4147-a993-9f96b25b7cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34442
13255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3444213255
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.1466451696
Short name T804
Test name
Test status
Simulation time 8390080952 ps
CPU time 7.3 seconds
Started Mar 19 12:55:36 PM PDT 24
Finished Mar 19 12:55:44 PM PDT 24
Peak memory 203004 kb
Host smart-67229853-57c9-46a1-93e9-0f2ba42a4e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14664
51696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.1466451696
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2135964006
Short name T626
Test name
Test status
Simulation time 8362473943 ps
CPU time 9.78 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:40 PM PDT 24
Peak memory 202824 kb
Host smart-1cedb4f7-23d0-4c99-ab37-1c9753c094c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21359
64006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2135964006
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.4204004503
Short name T557
Test name
Test status
Simulation time 8472457091 ps
CPU time 7.99 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 202900 kb
Host smart-6edafe8a-e5a8-463a-94fb-7b89418771e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42040
04503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.4204004503
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1264713178
Short name T317
Test name
Test status
Simulation time 8372228407 ps
CPU time 7.7 seconds
Started Mar 19 12:55:35 PM PDT 24
Finished Mar 19 12:55:44 PM PDT 24
Peak memory 203012 kb
Host smart-90382207-b4eb-4517-b65f-d0fa62028bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12647
13178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1264713178
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.1246926921
Short name T530
Test name
Test status
Simulation time 8370280167 ps
CPU time 9.4 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:44 PM PDT 24
Peak memory 202204 kb
Host smart-f63b9075-c1f7-4a78-afdd-1749955b0fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12469
26921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1246926921
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.4054874452
Short name T658
Test name
Test status
Simulation time 44600163 ps
CPU time 1.29 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:33 PM PDT 24
Peak memory 203108 kb
Host smart-61e6b1b4-ecdb-44ad-9afb-ba17e581f2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40548
74452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.4054874452
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.861023173
Short name T529
Test name
Test status
Simulation time 8355719771 ps
CPU time 8.01 seconds
Started Mar 19 12:55:35 PM PDT 24
Finished Mar 19 12:55:44 PM PDT 24
Peak memory 202792 kb
Host smart-eba9fe20-3142-42ae-939b-6530453dbfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86102
3173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.861023173
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3919233980
Short name T143
Test name
Test status
Simulation time 8429474089 ps
CPU time 7.51 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 203060 kb
Host smart-fab0404b-cbf2-41cf-bfb6-3a00ec66b045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39192
33980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3919233980
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.432729361
Short name T273
Test name
Test status
Simulation time 8407063554 ps
CPU time 8.03 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 203028 kb
Host smart-d193119a-2649-42a5-b22d-0acba43213dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43272
9361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.432729361
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.4010980669
Short name T360
Test name
Test status
Simulation time 8362274671 ps
CPU time 9.38 seconds
Started Mar 19 12:55:28 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 202996 kb
Host smart-333c93eb-9c95-4824-a8ae-faa160aef827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109
80669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.4010980669
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.21383228
Short name T120
Test name
Test status
Simulation time 8388450143 ps
CPU time 7.99 seconds
Started Mar 19 12:55:32 PM PDT 24
Finished Mar 19 12:55:40 PM PDT 24
Peak memory 203036 kb
Host smart-599115e0-b26a-49d2-bf6c-9e9e813ce6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21383
228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.21383228
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.147379640
Short name T214
Test name
Test status
Simulation time 8387964259 ps
CPU time 7.8 seconds
Started Mar 19 12:55:36 PM PDT 24
Finished Mar 19 12:55:44 PM PDT 24
Peak memory 203000 kb
Host smart-1a2afb8a-c23b-41b6-a4a1-d795b6ce45e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14737
9640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.147379640
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1528978891
Short name T268
Test name
Test status
Simulation time 8363115273 ps
CPU time 7.68 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 202864 kb
Host smart-b80853a3-77dd-4155-a850-17ec9e6c5b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15289
78891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1528978891
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.4206025789
Short name T467
Test name
Test status
Simulation time 27815626 ps
CPU time 0.65 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:31 PM PDT 24
Peak memory 202728 kb
Host smart-4767eaeb-ed2e-4674-81d5-a2d2553b7eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42060
25789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.4206025789
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2418807238
Short name T808
Test name
Test status
Simulation time 8375439151 ps
CPU time 7.4 seconds
Started Mar 19 12:55:28 PM PDT 24
Finished Mar 19 12:55:36 PM PDT 24
Peak memory 202852 kb
Host smart-5b845e96-a729-43f4-a59d-5104c02af25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24188
07238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2418807238
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2870979852
Short name T318
Test name
Test status
Simulation time 8367739201 ps
CPU time 9.92 seconds
Started Mar 19 12:55:32 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 203032 kb
Host smart-3fc621e0-257b-4a52-a130-b3581fd65097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28709
79852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2870979852
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3579015984
Short name T526
Test name
Test status
Simulation time 8354710609 ps
CPU time 7.45 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 203052 kb
Host smart-1bff19bb-7bb5-47a0-be66-4516b6906927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35790
15984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3579015984
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2890209975
Short name T245
Test name
Test status
Simulation time 8475417078 ps
CPU time 9.94 seconds
Started Mar 19 12:55:28 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 203016 kb
Host smart-364c416c-8b15-49e6-a339-9fc910516a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28902
09975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2890209975
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2242967498
Short name T463
Test name
Test status
Simulation time 8371977863 ps
CPU time 7.62 seconds
Started Mar 19 12:55:33 PM PDT 24
Finished Mar 19 12:55:41 PM PDT 24
Peak memory 203064 kb
Host smart-f0681f46-c232-4425-afe9-43a006821c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22429
67498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2242967498
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.515966277
Short name T845
Test name
Test status
Simulation time 8373751459 ps
CPU time 8.02 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:39 PM PDT 24
Peak memory 202844 kb
Host smart-2b9ea392-d53c-4b9c-8328-4e90ca98dfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51596
6277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.515966277
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3677279650
Short name T433
Test name
Test status
Simulation time 50923999 ps
CPU time 1.36 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:34 PM PDT 24
Peak memory 203116 kb
Host smart-9b640e4c-d6fd-46b0-8509-c9896d010624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36772
79650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3677279650
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1108769689
Short name T775
Test name
Test status
Simulation time 8358462016 ps
CPU time 9.75 seconds
Started Mar 19 12:55:32 PM PDT 24
Finished Mar 19 12:55:43 PM PDT 24
Peak memory 202880 kb
Host smart-d699504b-f3ab-4266-ad62-830eda722947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11087
69689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1108769689
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3971173547
Short name T527
Test name
Test status
Simulation time 8390242849 ps
CPU time 7.12 seconds
Started Mar 19 12:55:29 PM PDT 24
Finished Mar 19 12:55:37 PM PDT 24
Peak memory 203036 kb
Host smart-0ae70da5-cdd0-4e0e-bd1c-1fd66ac1dc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39711
73547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3971173547
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.323870431
Short name T700
Test name
Test status
Simulation time 8407857711 ps
CPU time 7.64 seconds
Started Mar 19 12:55:35 PM PDT 24
Finished Mar 19 12:55:43 PM PDT 24
Peak memory 203008 kb
Host smart-6d72d677-fd2e-4d5e-bd0c-53d1dc9e86c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
0431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.323870431
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.463404381
Short name T362
Test name
Test status
Simulation time 8361440983 ps
CPU time 7.24 seconds
Started Mar 19 12:55:32 PM PDT 24
Finished Mar 19 12:55:39 PM PDT 24
Peak memory 203028 kb
Host smart-b23c4dbb-1c0e-4753-963d-7b78a2004433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46340
4381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.463404381
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1842753739
Short name T108
Test name
Test status
Simulation time 8414117675 ps
CPU time 7.67 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:39 PM PDT 24
Peak memory 203004 kb
Host smart-ccecee21-058f-4514-81aa-826f023992f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18427
53739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1842753739
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1931967250
Short name T741
Test name
Test status
Simulation time 8377834345 ps
CPU time 8.36 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:43 PM PDT 24
Peak memory 202840 kb
Host smart-5f27379a-46c8-4784-a95e-368003633b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19319
67250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1931967250
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.611255490
Short name T734
Test name
Test status
Simulation time 8384251930 ps
CPU time 7.62 seconds
Started Mar 19 12:55:30 PM PDT 24
Finished Mar 19 12:55:38 PM PDT 24
Peak memory 203008 kb
Host smart-46715f59-5ada-4948-920c-fc880e304ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61125
5490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.611255490
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2080858916
Short name T628
Test name
Test status
Simulation time 28633130 ps
CPU time 0.64 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:35 PM PDT 24
Peak memory 202516 kb
Host smart-2ee12e39-49a6-4ea3-aefb-962fc5bfef54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
58916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2080858916
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.4125426235
Short name T363
Test name
Test status
Simulation time 8372118884 ps
CPU time 8.19 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 202432 kb
Host smart-759e2631-ec99-4adf-ab66-fb016a45ada5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41254
26235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.4125426235
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3402515282
Short name T425
Test name
Test status
Simulation time 8421246652 ps
CPU time 8.72 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:43 PM PDT 24
Peak memory 202980 kb
Host smart-9a8b3ab0-2661-4e77-ae6b-51bcc599f960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
15282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3402515282
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.917135790
Short name T373
Test name
Test status
Simulation time 8383818025 ps
CPU time 9.81 seconds
Started Mar 19 12:55:32 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 203032 kb
Host smart-e930f201-6926-42fd-8167-603ba716ebb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91713
5790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.917135790
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.4095127747
Short name T312
Test name
Test status
Simulation time 8358970947 ps
CPU time 7.28 seconds
Started Mar 19 12:55:32 PM PDT 24
Finished Mar 19 12:55:40 PM PDT 24
Peak memory 203068 kb
Host smart-71804ac2-a9e3-4bf7-8424-21b412a4bb84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40951
27747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.4095127747
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2968052560
Short name T46
Test name
Test status
Simulation time 8368173963 ps
CPU time 7.78 seconds
Started Mar 19 12:53:56 PM PDT 24
Finished Mar 19 12:54:05 PM PDT 24
Peak memory 202980 kb
Host smart-5f327cea-9068-498f-9299-6ed96c3b38b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29680
52560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2968052560
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.1942650055
Short name T603
Test name
Test status
Simulation time 8367257413 ps
CPU time 9.47 seconds
Started Mar 19 12:53:57 PM PDT 24
Finished Mar 19 12:54:07 PM PDT 24
Peak memory 202812 kb
Host smart-bb1e5ee5-f5fb-4e0a-9d9c-5f73f3f08b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19426
50055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1942650055
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3459693085
Short name T167
Test name
Test status
Simulation time 8360178582 ps
CPU time 7.41 seconds
Started Mar 19 12:54:02 PM PDT 24
Finished Mar 19 12:54:10 PM PDT 24
Peak memory 202916 kb
Host smart-b4024ac7-9e40-4633-bb72-c66e49e89a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34596
93085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3459693085
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1267405299
Short name T130
Test name
Test status
Simulation time 8380132565 ps
CPU time 8.04 seconds
Started Mar 19 12:53:53 PM PDT 24
Finished Mar 19 12:54:01 PM PDT 24
Peak memory 203052 kb
Host smart-746f3918-c641-454b-9cb7-a1b2bfc7cbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
05299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1267405299
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3533834872
Short name T361
Test name
Test status
Simulation time 8406321846 ps
CPU time 8.96 seconds
Started Mar 19 12:53:56 PM PDT 24
Finished Mar 19 12:54:05 PM PDT 24
Peak memory 203024 kb
Host smart-7678099d-d802-4bbb-a2f6-c4beb6c7c030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35338
34872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3533834872
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3154735585
Short name T334
Test name
Test status
Simulation time 8363887139 ps
CPU time 9.19 seconds
Started Mar 19 12:53:54 PM PDT 24
Finished Mar 19 12:54:04 PM PDT 24
Peak memory 203104 kb
Host smart-cc6092c1-2874-4317-893c-c04e3155d429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31547
35585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3154735585
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1940961551
Short name T105
Test name
Test status
Simulation time 8442407628 ps
CPU time 8.05 seconds
Started Mar 19 12:53:57 PM PDT 24
Finished Mar 19 12:54:06 PM PDT 24
Peak memory 203020 kb
Host smart-24aec3e0-3b90-415b-8f13-c0afb5e8b701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409
61551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1940961551
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1471481859
Short name T746
Test name
Test status
Simulation time 8366639275 ps
CPU time 7.07 seconds
Started Mar 19 12:53:59 PM PDT 24
Finished Mar 19 12:54:06 PM PDT 24
Peak memory 202884 kb
Host smart-d9eb6464-6e07-4703-9cdc-c66967e8586d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
81859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1471481859
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1763218202
Short name T857
Test name
Test status
Simulation time 8368012181 ps
CPU time 7.29 seconds
Started Mar 19 12:53:58 PM PDT 24
Finished Mar 19 12:54:06 PM PDT 24
Peak memory 202840 kb
Host smart-03f263ef-f11d-4278-ab9c-0cf345a0c751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17632
18202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1763218202
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2901524481
Short name T333
Test name
Test status
Simulation time 27688404 ps
CPU time 0.66 seconds
Started Mar 19 12:54:01 PM PDT 24
Finished Mar 19 12:54:01 PM PDT 24
Peak memory 202620 kb
Host smart-3d43f8d0-cb1f-4890-b79d-81340b9f3a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29015
24481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2901524481
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2840095485
Short name T320
Test name
Test status
Simulation time 8384564956 ps
CPU time 7.1 seconds
Started Mar 19 12:53:55 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 202860 kb
Host smart-94eed716-20ca-49a2-a8d5-96ec4a188dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28400
95485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2840095485
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1277412350
Short name T478
Test name
Test status
Simulation time 8397819740 ps
CPU time 7.89 seconds
Started Mar 19 12:53:54 PM PDT 24
Finished Mar 19 12:54:03 PM PDT 24
Peak memory 203004 kb
Host smart-7aeb8710-c2e8-438d-baa7-076ec4992336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12774
12350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1277412350
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.1121938305
Short name T568
Test name
Test status
Simulation time 8376651407 ps
CPU time 7.51 seconds
Started Mar 19 12:54:02 PM PDT 24
Finished Mar 19 12:54:10 PM PDT 24
Peak memory 203028 kb
Host smart-9d1131db-2331-439f-a4bd-3e29341520ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219
38305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.1121938305
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2188271543
Short name T59
Test name
Test status
Simulation time 94856441 ps
CPU time 0.88 seconds
Started Mar 19 12:54:07 PM PDT 24
Finished Mar 19 12:54:08 PM PDT 24
Peak memory 218296 kb
Host smart-dc54e893-0e48-49af-8b18-c15f49569b27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2188271543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2188271543
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2555141229
Short name T301
Test name
Test status
Simulation time 8357049168 ps
CPU time 7.07 seconds
Started Mar 19 12:54:06 PM PDT 24
Finished Mar 19 12:54:14 PM PDT 24
Peak memory 203052 kb
Host smart-5ffadaa3-83d3-4e8e-80db-242d4e01ef04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25551
41229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2555141229
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.132864281
Short name T44
Test name
Test status
Simulation time 8478668515 ps
CPU time 9.8 seconds
Started Mar 19 12:53:54 PM PDT 24
Finished Mar 19 12:54:05 PM PDT 24
Peak memory 203016 kb
Host smart-641a083c-58d2-4c47-9970-8dd9fa608224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13286
4281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.132864281
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.744229079
Short name T41
Test name
Test status
Simulation time 8369862262 ps
CPU time 10 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:45 PM PDT 24
Peak memory 203000 kb
Host smart-d759e24b-7ec1-4121-9744-5d2d9f59ab40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74422
9079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.744229079
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.2526125258
Short name T501
Test name
Test status
Simulation time 8372794032 ps
CPU time 10.2 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 202908 kb
Host smart-1679d65f-dfa5-471d-8b3b-16b967c942c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25261
25258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2526125258
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2722028508
Short name T580
Test name
Test status
Simulation time 45863354 ps
CPU time 1.18 seconds
Started Mar 19 12:55:31 PM PDT 24
Finished Mar 19 12:55:33 PM PDT 24
Peak memory 202848 kb
Host smart-46b06a5f-290e-4a7f-b7a9-b092267620c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27220
28508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2722028508
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.952876510
Short name T170
Test name
Test status
Simulation time 8360243285 ps
CPU time 7.78 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 202852 kb
Host smart-74736b54-5d36-4afd-a933-67d8481759c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95287
6510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.952876510
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3729861131
Short name T451
Test name
Test status
Simulation time 8404001252 ps
CPU time 8.53 seconds
Started Mar 19 12:55:33 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 203100 kb
Host smart-da202672-da88-4d1a-9193-19de70d7ca4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37298
61131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3729861131
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.4124254349
Short name T589
Test name
Test status
Simulation time 8359777147 ps
CPU time 8.53 seconds
Started Mar 19 12:55:36 PM PDT 24
Finished Mar 19 12:55:45 PM PDT 24
Peak memory 203000 kb
Host smart-06765ff2-801f-488c-b5ac-ae3f72122d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41242
54349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.4124254349
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1643162154
Short name T671
Test name
Test status
Simulation time 8441259950 ps
CPU time 7.24 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:41 PM PDT 24
Peak memory 203052 kb
Host smart-b2679ab1-0d76-47a5-9991-29e836cee1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16431
62154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1643162154
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3969192636
Short name T612
Test name
Test status
Simulation time 8400530834 ps
CPU time 9.93 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:44 PM PDT 24
Peak memory 202980 kb
Host smart-68be08e5-1c0e-47d0-ba94-c09a93949a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39691
92636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3969192636
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1029038662
Short name T281
Test name
Test status
Simulation time 8369961413 ps
CPU time 8.75 seconds
Started Mar 19 12:55:32 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 202972 kb
Host smart-07581cdd-337c-4297-9ddd-51cfe1d0493f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10290
38662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1029038662
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3756390386
Short name T558
Test name
Test status
Simulation time 27252928 ps
CPU time 0.67 seconds
Started Mar 19 12:55:39 PM PDT 24
Finished Mar 19 12:55:39 PM PDT 24
Peak memory 202536 kb
Host smart-75da19d2-19bc-49c9-99c3-d3c413de9bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37563
90386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3756390386
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.217526687
Short name T793
Test name
Test status
Simulation time 8390515612 ps
CPU time 7.65 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 203000 kb
Host smart-1f179a05-d00d-454a-94c8-b5d31d27f463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21752
6687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.217526687
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1375953312
Short name T240
Test name
Test status
Simulation time 8452209862 ps
CPU time 8.25 seconds
Started Mar 19 12:55:35 PM PDT 24
Finished Mar 19 12:55:43 PM PDT 24
Peak memory 203012 kb
Host smart-71ef1c72-0af4-454d-b780-664b65e3a1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13759
53312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1375953312
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.534452417
Short name T8
Test name
Test status
Simulation time 8371713943 ps
CPU time 7.53 seconds
Started Mar 19 12:55:39 PM PDT 24
Finished Mar 19 12:55:46 PM PDT 24
Peak memory 202996 kb
Host smart-5a1ec745-b053-41a7-8483-df7b45ea683a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53445
2417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.534452417
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3087953495
Short name T596
Test name
Test status
Simulation time 8362119300 ps
CPU time 7.79 seconds
Started Mar 19 12:55:39 PM PDT 24
Finished Mar 19 12:55:47 PM PDT 24
Peak memory 202876 kb
Host smart-090c966c-9d25-490c-b81f-8a49d482d342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
53495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3087953495
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2735841006
Short name T133
Test name
Test status
Simulation time 8477854069 ps
CPU time 8.11 seconds
Started Mar 19 12:55:34 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 203064 kb
Host smart-034a5d24-36c0-413f-a8e4-20820be13f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27358
41006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2735841006
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3082116240
Short name T684
Test name
Test status
Simulation time 8368777840 ps
CPU time 8.3 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 202980 kb
Host smart-6503846a-9df7-47d6-96bb-d1748941ad3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30821
16240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3082116240
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.1512352983
Short name T415
Test name
Test status
Simulation time 8364513457 ps
CPU time 7.2 seconds
Started Mar 19 12:55:43 PM PDT 24
Finished Mar 19 12:55:50 PM PDT 24
Peak memory 202812 kb
Host smart-822ccd0b-c596-4f38-8807-1d246ab736c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15123
52983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1512352983
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.483424209
Short name T604
Test name
Test status
Simulation time 201412742 ps
CPU time 2.17 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:43 PM PDT 24
Peak memory 203104 kb
Host smart-5c36691b-b805-45b0-b8a9-49241a4525d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48342
4209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.483424209
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2870694087
Short name T53
Test name
Test status
Simulation time 8361999574 ps
CPU time 9.76 seconds
Started Mar 19 12:55:43 PM PDT 24
Finished Mar 19 12:55:54 PM PDT 24
Peak memory 202796 kb
Host smart-6635c006-364d-4289-a5e4-397c1c1f99ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28706
94087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2870694087
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2062347847
Short name T28
Test name
Test status
Simulation time 8387431121 ps
CPU time 7.2 seconds
Started Mar 19 12:55:45 PM PDT 24
Finished Mar 19 12:55:52 PM PDT 24
Peak memory 203088 kb
Host smart-7114a073-cbea-4a9b-ba62-57b6fe778c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20623
47847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2062347847
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.517763598
Short name T331
Test name
Test status
Simulation time 8405652833 ps
CPU time 9.85 seconds
Started Mar 19 12:55:42 PM PDT 24
Finished Mar 19 12:55:53 PM PDT 24
Peak memory 203008 kb
Host smart-6d28d7cd-9ac2-4da4-910c-342efe696f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51776
3598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.517763598
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.2528531017
Short name T638
Test name
Test status
Simulation time 8364371297 ps
CPU time 9.15 seconds
Started Mar 19 12:55:41 PM PDT 24
Finished Mar 19 12:55:51 PM PDT 24
Peak memory 202944 kb
Host smart-b9ee6841-85dd-4fbc-9a10-9f1b01260b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25285
31017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.2528531017
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1043137466
Short name T573
Test name
Test status
Simulation time 8367244642 ps
CPU time 8.4 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:49 PM PDT 24
Peak memory 202860 kb
Host smart-649ec351-d55e-495e-abc4-0e9e308940ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10431
37466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1043137466
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1110810978
Short name T86
Test name
Test status
Simulation time 8366304048 ps
CPU time 8.67 seconds
Started Mar 19 12:55:45 PM PDT 24
Finished Mar 19 12:55:54 PM PDT 24
Peak memory 202936 kb
Host smart-964433f4-df6b-4909-939b-a107d0328ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11108
10978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1110810978
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2699031719
Short name T392
Test name
Test status
Simulation time 26928647 ps
CPU time 0.7 seconds
Started Mar 19 12:55:43 PM PDT 24
Finished Mar 19 12:55:44 PM PDT 24
Peak memory 202580 kb
Host smart-1a66269e-48ec-4f80-aed6-96389decaaa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26990
31719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2699031719
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2817660055
Short name T778
Test name
Test status
Simulation time 8381519287 ps
CPU time 7.11 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 202840 kb
Host smart-08e5d89b-aa1b-4be8-ad96-e88e5100c846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28176
60055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2817660055
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2280475819
Short name T812
Test name
Test status
Simulation time 8391164070 ps
CPU time 7.75 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 203024 kb
Host smart-9ae6c21b-208b-4963-b055-8fff3769a8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22804
75819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2280475819
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3620564488
Short name T707
Test name
Test status
Simulation time 8366839220 ps
CPU time 8.69 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:57 PM PDT 24
Peak memory 202752 kb
Host smart-1ab60de8-800e-481c-ac98-37a1892189cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36205
64488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3620564488
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.920466005
Short name T297
Test name
Test status
Simulation time 8358787744 ps
CPU time 9.57 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:49 PM PDT 24
Peak memory 202852 kb
Host smart-27a65343-7a95-441f-b264-81930b27140b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92046
6005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.920466005
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1393215188
Short name T497
Test name
Test status
Simulation time 8477651425 ps
CPU time 7.62 seconds
Started Mar 19 12:55:39 PM PDT 24
Finished Mar 19 12:55:47 PM PDT 24
Peak memory 202984 kb
Host smart-5705ad12-4e72-4982-9536-2ad7dc79e269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932
15188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1393215188
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3969091907
Short name T352
Test name
Test status
Simulation time 8367261840 ps
CPU time 7.62 seconds
Started Mar 19 12:55:39 PM PDT 24
Finished Mar 19 12:55:47 PM PDT 24
Peak memory 203048 kb
Host smart-42d2fb3b-feb3-4f5a-8f3b-dfa63bd400c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39690
91907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3969091907
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.1003237567
Short name T736
Test name
Test status
Simulation time 8368023560 ps
CPU time 7.82 seconds
Started Mar 19 12:55:44 PM PDT 24
Finished Mar 19 12:55:52 PM PDT 24
Peak memory 202780 kb
Host smart-1f8eac5a-f31a-42f2-91df-8a99753b3b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10032
37567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1003237567
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2665621000
Short name T307
Test name
Test status
Simulation time 49075495 ps
CPU time 1.49 seconds
Started Mar 19 12:55:43 PM PDT 24
Finished Mar 19 12:55:45 PM PDT 24
Peak memory 203060 kb
Host smart-2dc6bd01-24c2-4b93-8902-8f04e6606bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26656
21000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2665621000
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.867183258
Short name T174
Test name
Test status
Simulation time 8357872848 ps
CPU time 9.61 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:50 PM PDT 24
Peak memory 202764 kb
Host smart-2cf12f69-7cfb-4995-bc90-0e13f33188be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86718
3258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.867183258
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1634225611
Short name T522
Test name
Test status
Simulation time 8400851382 ps
CPU time 7.28 seconds
Started Mar 19 12:55:40 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 202988 kb
Host smart-e2ea5856-c588-4978-ab72-0dc909c06d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16342
25611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1634225611
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2035084831
Short name T515
Test name
Test status
Simulation time 8408839069 ps
CPU time 7.86 seconds
Started Mar 19 12:55:38 PM PDT 24
Finished Mar 19 12:55:46 PM PDT 24
Peak memory 203096 kb
Host smart-3be86259-9f79-4884-a04a-755604a16aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20350
84831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2035084831
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1287662634
Short name T627
Test name
Test status
Simulation time 8359705807 ps
CPU time 8.89 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:57 PM PDT 24
Peak memory 202992 kb
Host smart-dab3a4c0-c86f-472e-8d58-140ab95f88db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12876
62634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1287662634
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1116318714
Short name T683
Test name
Test status
Simulation time 8421616468 ps
CPU time 7.42 seconds
Started Mar 19 12:55:39 PM PDT 24
Finished Mar 19 12:55:47 PM PDT 24
Peak memory 203040 kb
Host smart-6a275590-69e8-4246-8a4a-02b67dc4f45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11163
18714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1116318714
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.381992431
Short name T754
Test name
Test status
Simulation time 8373772442 ps
CPU time 10.16 seconds
Started Mar 19 12:55:37 PM PDT 24
Finished Mar 19 12:55:47 PM PDT 24
Peak memory 202884 kb
Host smart-accaab85-f794-45a9-9d1b-3ff23df48475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199
2431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.381992431
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2226330215
Short name T347
Test name
Test status
Simulation time 8383260971 ps
CPU time 7.42 seconds
Started Mar 19 12:55:44 PM PDT 24
Finished Mar 19 12:55:52 PM PDT 24
Peak memory 202808 kb
Host smart-e1bd2567-e9cc-4ba1-84ac-4c9ae8874ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
30215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2226330215
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2340583848
Short name T761
Test name
Test status
Simulation time 26762596 ps
CPU time 0.64 seconds
Started Mar 19 12:55:41 PM PDT 24
Finished Mar 19 12:55:42 PM PDT 24
Peak memory 202532 kb
Host smart-46f1bcdc-6d0a-4c0f-96f7-a5f75f81f452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23405
83848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2340583848
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.685707750
Short name T4
Test name
Test status
Simulation time 8383191166 ps
CPU time 9.65 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:58 PM PDT 24
Peak memory 202632 kb
Host smart-b962572c-11fb-45f2-bc31-631e5ccc9d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68570
7750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.685707750
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3825646688
Short name T440
Test name
Test status
Simulation time 8435047732 ps
CPU time 9.66 seconds
Started Mar 19 12:55:39 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 203032 kb
Host smart-5141dc62-9bf0-451d-ade4-290333706085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38256
46688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3825646688
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2851462084
Short name T341
Test name
Test status
Simulation time 8404304225 ps
CPU time 7.77 seconds
Started Mar 19 12:55:41 PM PDT 24
Finished Mar 19 12:55:49 PM PDT 24
Peak memory 203044 kb
Host smart-c72efe61-6a08-40d3-927d-a2e14f5850e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28514
62084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2851462084
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3425722510
Short name T685
Test name
Test status
Simulation time 8358448805 ps
CPU time 7.95 seconds
Started Mar 19 12:55:44 PM PDT 24
Finished Mar 19 12:55:52 PM PDT 24
Peak memory 202880 kb
Host smart-fc7c876e-3de5-44b2-97d2-e07ff07517b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34257
22510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3425722510
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1839416484
Short name T129
Test name
Test status
Simulation time 8475856824 ps
CPU time 9.81 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:57 PM PDT 24
Peak memory 202992 kb
Host smart-7254325f-923c-4b71-b293-3e2860742e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18394
16484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1839416484
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.123061043
Short name T311
Test name
Test status
Simulation time 8371021808 ps
CPU time 8 seconds
Started Mar 19 12:55:45 PM PDT 24
Finished Mar 19 12:55:53 PM PDT 24
Peak memory 202960 kb
Host smart-c1a07420-6537-4a4a-81b3-14d6b6f6b3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12306
1043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.123061043
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.2399048584
Short name T773
Test name
Test status
Simulation time 8369714628 ps
CPU time 7.76 seconds
Started Mar 19 12:55:41 PM PDT 24
Finished Mar 19 12:55:49 PM PDT 24
Peak memory 202740 kb
Host smart-3cee399c-dbe6-473e-8c11-498e9918d13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
48584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2399048584
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2355008492
Short name T681
Test name
Test status
Simulation time 86187005 ps
CPU time 1.17 seconds
Started Mar 19 12:55:44 PM PDT 24
Finished Mar 19 12:55:45 PM PDT 24
Peak memory 202796 kb
Host smart-1e5679fd-c488-4147-8523-7afbf3b52ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23550
08492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2355008492
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2483919328
Short name T846
Test name
Test status
Simulation time 8360830600 ps
CPU time 7.24 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 202764 kb
Host smart-389430bd-0045-4aef-a9c0-8b5723ff8735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24839
19328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2483919328
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3367327328
Short name T388
Test name
Test status
Simulation time 8406641642 ps
CPU time 8.05 seconds
Started Mar 19 12:55:41 PM PDT 24
Finished Mar 19 12:55:50 PM PDT 24
Peak memory 203048 kb
Host smart-d76cfb37-21f5-4aa7-a026-47be73789d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33673
27328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3367327328
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2322028911
Short name T562
Test name
Test status
Simulation time 8361344865 ps
CPU time 7.87 seconds
Started Mar 19 12:55:42 PM PDT 24
Finished Mar 19 12:55:51 PM PDT 24
Peak memory 202976 kb
Host smart-f6cecbf5-1d76-42e1-a1f5-141704c4ccfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23220
28911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2322028911
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3262763703
Short name T753
Test name
Test status
Simulation time 8404556938 ps
CPU time 8.03 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:57 PM PDT 24
Peak memory 202980 kb
Host smart-9ea8f5cc-04af-46f0-aa5c-e1f94dbf7eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32627
63703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3262763703
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3677341855
Short name T858
Test name
Test status
Simulation time 8380671266 ps
CPU time 7.2 seconds
Started Mar 19 12:55:45 PM PDT 24
Finished Mar 19 12:55:52 PM PDT 24
Peak memory 202884 kb
Host smart-e6046aec-70d2-4916-9342-f6ef38e7ef83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36773
41855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3677341855
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1010335525
Short name T35
Test name
Test status
Simulation time 26259498 ps
CPU time 0.64 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 202572 kb
Host smart-b32efae7-9413-4fba-88ab-99ba261ceed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
35525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1010335525
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2749192499
Short name T675
Test name
Test status
Simulation time 8391117891 ps
CPU time 7.62 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 202844 kb
Host smart-862443ce-2201-493b-96d0-d192df7d0b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27491
92499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2749192499
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1670565930
Short name T435
Test name
Test status
Simulation time 8383286116 ps
CPU time 7.45 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:55 PM PDT 24
Peak memory 203008 kb
Host smart-cbe071ea-da59-4c51-8138-6c5dd477f858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16705
65930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1670565930
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.320178263
Short name T339
Test name
Test status
Simulation time 8372943947 ps
CPU time 7.17 seconds
Started Mar 19 12:55:46 PM PDT 24
Finished Mar 19 12:55:54 PM PDT 24
Peak memory 203076 kb
Host smart-c1654cf7-8336-4204-8e3b-287eb79ddee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32017
8263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.320178263
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2866619904
Short name T817
Test name
Test status
Simulation time 8360204508 ps
CPU time 7.55 seconds
Started Mar 19 12:55:51 PM PDT 24
Finished Mar 19 12:55:59 PM PDT 24
Peak memory 202656 kb
Host smart-7ba58ff5-bb9d-4e15-a75e-23366762e6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28666
19904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2866619904
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2593165394
Short name T146
Test name
Test status
Simulation time 8475965747 ps
CPU time 7.36 seconds
Started Mar 19 12:55:45 PM PDT 24
Finished Mar 19 12:55:53 PM PDT 24
Peak memory 202944 kb
Host smart-e76e1aa0-fbc5-4d85-9769-e21e2f22650f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25931
65394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2593165394
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.786722521
Short name T313
Test name
Test status
Simulation time 8371847643 ps
CPU time 7.34 seconds
Started Mar 19 12:55:44 PM PDT 24
Finished Mar 19 12:55:52 PM PDT 24
Peak memory 203040 kb
Host smart-2caded8b-afc3-455c-a3df-00da9fac66d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78672
2521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.786722521
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.1957718112
Short name T233
Test name
Test status
Simulation time 8371959662 ps
CPU time 7.5 seconds
Started Mar 19 12:55:46 PM PDT 24
Finished Mar 19 12:55:54 PM PDT 24
Peak memory 203072 kb
Host smart-0013fa8e-ea01-4ecf-85a7-586617f7a0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19577
18112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.1957718112
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3622836400
Short name T823
Test name
Test status
Simulation time 62864442 ps
CPU time 1.7 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:49 PM PDT 24
Peak memory 202860 kb
Host smart-6f620403-7998-4a2d-b082-764c87d506f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36228
36400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3622836400
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.571938595
Short name T188
Test name
Test status
Simulation time 8355274061 ps
CPU time 7.4 seconds
Started Mar 19 12:55:51 PM PDT 24
Finished Mar 19 12:55:59 PM PDT 24
Peak memory 202648 kb
Host smart-8eac012b-68a9-480e-b7d2-fbf35cd1b679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57193
8595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.571938595
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.788173227
Short name T391
Test name
Test status
Simulation time 8398437156 ps
CPU time 7.69 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 203080 kb
Host smart-79720465-1f86-4b31-a46f-c5e0c5794ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78817
3227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.788173227
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3797250049
Short name T437
Test name
Test status
Simulation time 8408337018 ps
CPU time 7.89 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:57 PM PDT 24
Peak memory 203020 kb
Host smart-9c84d9ec-1048-4eb7-97ed-1a7353bcde02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37972
50049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3797250049
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.858591051
Short name T472
Test name
Test status
Simulation time 8362542624 ps
CPU time 7.7 seconds
Started Mar 19 12:55:45 PM PDT 24
Finished Mar 19 12:55:53 PM PDT 24
Peak memory 203044 kb
Host smart-d3a96eab-54be-4c14-81f4-74a6ecb43def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85859
1051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.858591051
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3576810063
Short name T722
Test name
Test status
Simulation time 8444362822 ps
CPU time 9.92 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:57 PM PDT 24
Peak memory 203072 kb
Host smart-d3c61b87-6d9c-4d72-9f54-6efba403f6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35768
10063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3576810063
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1904032396
Short name T757
Test name
Test status
Simulation time 8370645299 ps
CPU time 7.26 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:54 PM PDT 24
Peak memory 202888 kb
Host smart-c16c15f4-18bd-40e9-8ab9-c486e76db2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19040
32396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1904032396
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1121547690
Short name T315
Test name
Test status
Simulation time 8374086482 ps
CPU time 7.39 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 202896 kb
Host smart-8ce77b9b-f4e3-474e-b3de-f9290512215d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215
47690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1121547690
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.242431636
Short name T521
Test name
Test status
Simulation time 26693599 ps
CPU time 0.65 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:49 PM PDT 24
Peak memory 202544 kb
Host smart-b07e9a07-8fb0-4ef7-b26b-25ad55890d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
1636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.242431636
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3626375458
Short name T847
Test name
Test status
Simulation time 8371077623 ps
CPU time 7.33 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 202792 kb
Host smart-9edac9da-e91a-4a8b-a80f-8809a409a5da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36263
75458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3626375458
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.4176390311
Short name T137
Test name
Test status
Simulation time 8415509455 ps
CPU time 7.71 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:55 PM PDT 24
Peak memory 202992 kb
Host smart-ded7490e-42bd-49eb-bee7-6e34c7da8183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41763
90311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.4176390311
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.1205578508
Short name T210
Test name
Test status
Simulation time 8384861676 ps
CPU time 7.2 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 202992 kb
Host smart-22d65144-8a0b-4d25-aa75-7367eb08f020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12055
78508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.1205578508
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2443246638
Short name T844
Test name
Test status
Simulation time 8360557701 ps
CPU time 7.47 seconds
Started Mar 19 12:55:46 PM PDT 24
Finished Mar 19 12:55:54 PM PDT 24
Peak memory 202844 kb
Host smart-6a43a3eb-f9d6-4a25-9c41-fc15caf105aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24432
46638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2443246638
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3365441699
Short name T154
Test name
Test status
Simulation time 8468437151 ps
CPU time 7.73 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 203080 kb
Host smart-12f4187a-e7f3-42a8-bd1f-39f347bda4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33654
41699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3365441699
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.4221832406
Short name T574
Test name
Test status
Simulation time 8372834533 ps
CPU time 7.94 seconds
Started Mar 19 12:55:54 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 203012 kb
Host smart-6ce85265-539a-4af4-97a0-cd93c78a2fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218
32406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.4221832406
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.2872600931
Short name T790
Test name
Test status
Simulation time 8371755661 ps
CPU time 7.33 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 202836 kb
Host smart-389fd24b-6bce-40a9-8a9d-a581e1c4230c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28726
00931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2872600931
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1545514029
Short name T428
Test name
Test status
Simulation time 83718429 ps
CPU time 1.2 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 203092 kb
Host smart-c7cd00f0-3fc8-4495-8349-4e76172e3a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15455
14029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1545514029
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3197194680
Short name T502
Test name
Test status
Simulation time 8356470285 ps
CPU time 8.03 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 202760 kb
Host smart-9b0a85f6-4966-48be-9936-65e63912683c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31971
94680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3197194680
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3019783713
Short name T635
Test name
Test status
Simulation time 8406021097 ps
CPU time 7.51 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:55 PM PDT 24
Peak memory 203020 kb
Host smart-8a6472a9-fbce-43be-97a2-b28a63028fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30197
83713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3019783713
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1000403868
Short name T666
Test name
Test status
Simulation time 8412906019 ps
CPU time 7.76 seconds
Started Mar 19 12:55:44 PM PDT 24
Finished Mar 19 12:55:52 PM PDT 24
Peak memory 203016 kb
Host smart-65fa54cf-306b-438e-a20e-c6d584ef0cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10004
03868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1000403868
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2216753207
Short name T856
Test name
Test status
Simulation time 8370560339 ps
CPU time 9.02 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 203028 kb
Host smart-12236a98-f184-4cf0-be0c-c1744ce44dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22167
53207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2216753207
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3852821352
Short name T116
Test name
Test status
Simulation time 8398478989 ps
CPU time 8.21 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:58 PM PDT 24
Peak memory 203068 kb
Host smart-faf93fa0-888e-4f69-8ec6-871f6e25c4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38528
21352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3852821352
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.4080781958
Short name T697
Test name
Test status
Simulation time 8368426675 ps
CPU time 9.79 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:58 PM PDT 24
Peak memory 202884 kb
Host smart-068db211-bf73-44b4-82fc-7637f32db9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40807
81958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.4080781958
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3900919670
Short name T247
Test name
Test status
Simulation time 8367645368 ps
CPU time 7.98 seconds
Started Mar 19 12:55:44 PM PDT 24
Finished Mar 19 12:55:53 PM PDT 24
Peak memory 202972 kb
Host smart-6b6b438f-f8b3-4f1e-b503-c9ecd590bfe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39009
19670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3900919670
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1385450826
Short name T34
Test name
Test status
Simulation time 31487453 ps
CPU time 0.63 seconds
Started Mar 19 12:55:50 PM PDT 24
Finished Mar 19 12:55:51 PM PDT 24
Peak memory 202508 kb
Host smart-4cdc87f2-b650-483c-bf43-a3f10354d508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854
50826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1385450826
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2092398499
Short name T544
Test name
Test status
Simulation time 8387362995 ps
CPU time 7.29 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:55 PM PDT 24
Peak memory 202892 kb
Host smart-e87ace08-a19c-48ac-8d62-dd92902af468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20923
98499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2092398499
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1220607076
Short name T686
Test name
Test status
Simulation time 8408137855 ps
CPU time 9.81 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:59 PM PDT 24
Peak memory 202996 kb
Host smart-5c4ab1e6-acc6-4800-b2eb-966ae8c794be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12206
07076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1220607076
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.3273612457
Short name T664
Test name
Test status
Simulation time 8367442106 ps
CPU time 7.26 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:55 PM PDT 24
Peak memory 202472 kb
Host smart-bdc24dcd-a63c-448e-9ce6-6650cfaf6984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32736
12457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.3273612457
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.421758910
Short name T16
Test name
Test status
Simulation time 8358878485 ps
CPU time 7.53 seconds
Started Mar 19 12:55:45 PM PDT 24
Finished Mar 19 12:55:52 PM PDT 24
Peak memory 202996 kb
Host smart-797340cd-d0fc-4e97-bba9-88657f943053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175
8910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.421758910
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1538011088
Short name T153
Test name
Test status
Simulation time 8469502100 ps
CPU time 7.35 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:54 PM PDT 24
Peak memory 202980 kb
Host smart-04a584cd-5224-445c-a809-0f6d953f2633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15380
11088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1538011088
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2050294709
Short name T39
Test name
Test status
Simulation time 8371698729 ps
CPU time 7.71 seconds
Started Mar 19 12:55:45 PM PDT 24
Finished Mar 19 12:55:53 PM PDT 24
Peak memory 203024 kb
Host smart-ffe136a3-af69-4ad3-a758-1cb66d3a1582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20502
94709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2050294709
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.2965581745
Short name T593
Test name
Test status
Simulation time 8372443464 ps
CPU time 7.75 seconds
Started Mar 19 12:55:50 PM PDT 24
Finished Mar 19 12:55:58 PM PDT 24
Peak memory 202816 kb
Host smart-6fcd9e56-5f7b-4b24-8d59-e071ea867bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29655
81745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2965581745
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3578040594
Short name T687
Test name
Test status
Simulation time 100564688 ps
CPU time 1.16 seconds
Started Mar 19 12:55:47 PM PDT 24
Finished Mar 19 12:55:48 PM PDT 24
Peak memory 203156 kb
Host smart-14d03bf6-ea21-4361-8916-34bd212cbab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35780
40594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3578040594
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3500151088
Short name T728
Test name
Test status
Simulation time 8364747892 ps
CPU time 7.97 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202804 kb
Host smart-e27240ea-5507-4542-a3e1-5a3c5a023937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35001
51088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3500151088
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3895647776
Short name T839
Test name
Test status
Simulation time 8381265236 ps
CPU time 7.41 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:55 PM PDT 24
Peak memory 202368 kb
Host smart-f2711df0-a19b-484c-9f4f-2c07140f1878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38956
47776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3895647776
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1271831174
Short name T220
Test name
Test status
Simulation time 8409717984 ps
CPU time 7.24 seconds
Started Mar 19 12:55:46 PM PDT 24
Finished Mar 19 12:55:53 PM PDT 24
Peak memory 203008 kb
Host smart-b2d4567b-9602-421b-b076-305e830c28cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12718
31174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1271831174
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.321478032
Short name T536
Test name
Test status
Simulation time 8365255304 ps
CPU time 7.94 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:57 PM PDT 24
Peak memory 203060 kb
Host smart-1e66e9f1-f367-4c09-9bc0-8fbdd1885290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
8032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.321478032
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3913140563
Short name T594
Test name
Test status
Simulation time 8430726395 ps
CPU time 7.47 seconds
Started Mar 19 12:55:49 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 202980 kb
Host smart-7483fa18-2858-4654-ade2-2192954bf0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39131
40563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3913140563
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2621481406
Short name T824
Test name
Test status
Simulation time 8406882776 ps
CPU time 7.39 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 203064 kb
Host smart-1cae2756-2aac-42de-a3c5-f1b309105759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26214
81406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2621481406
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3647707949
Short name T445
Test name
Test status
Simulation time 8364214791 ps
CPU time 7.48 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 203040 kb
Host smart-710a21a4-3f1e-473e-97c3-df1ebc9d923b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36477
07949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3647707949
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.324337951
Short name T470
Test name
Test status
Simulation time 29983778 ps
CPU time 0.66 seconds
Started Mar 19 12:55:57 PM PDT 24
Finished Mar 19 12:55:58 PM PDT 24
Peak memory 202500 kb
Host smart-cc3228e3-34a3-4f8e-b011-7fb39d9058d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32433
7951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.324337951
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1908739464
Short name T396
Test name
Test status
Simulation time 8374728398 ps
CPU time 7.94 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202872 kb
Host smart-59594076-2ff7-465f-ac85-a00d4c87bf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19087
39464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1908739464
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3151052485
Short name T145
Test name
Test status
Simulation time 8384247811 ps
CPU time 9.2 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202984 kb
Host smart-1950fc92-4b67-48b0-bfe6-13c96d208653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31510
52485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3151052485
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2780594380
Short name T581
Test name
Test status
Simulation time 8403505508 ps
CPU time 8.9 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202980 kb
Host smart-8c778af6-4288-4111-ac70-790b3b1675a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27805
94380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2780594380
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3498596424
Short name T785
Test name
Test status
Simulation time 8360573455 ps
CPU time 7.32 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202832 kb
Host smart-06284b3b-bcd4-463e-bfcb-2c030f93f897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34985
96424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3498596424
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3132675310
Short name T149
Test name
Test status
Simulation time 8475034301 ps
CPU time 7.75 seconds
Started Mar 19 12:55:48 PM PDT 24
Finished Mar 19 12:55:55 PM PDT 24
Peak memory 203024 kb
Host smart-5d8025b6-4775-437e-8ade-2e54b9602aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31326
75310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3132675310
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1149685406
Short name T404
Test name
Test status
Simulation time 8369016973 ps
CPU time 9.3 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:05 PM PDT 24
Peak memory 203076 kb
Host smart-9d65944f-9310-435f-a584-468a48f63cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11496
85406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1149685406
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.738524622
Short name T505
Test name
Test status
Simulation time 8363995455 ps
CPU time 7.07 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:02 PM PDT 24
Peak memory 202828 kb
Host smart-81b09cd8-8d41-47f2-8229-277aae8e8371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73852
4622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.738524622
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3596739700
Short name T309
Test name
Test status
Simulation time 169996290 ps
CPU time 2.02 seconds
Started Mar 19 12:55:53 PM PDT 24
Finished Mar 19 12:55:55 PM PDT 24
Peak memory 203088 kb
Host smart-180f1849-df19-4056-87d8-e7a3b94ce5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35967
39700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3596739700
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3832978467
Short name T187
Test name
Test status
Simulation time 8364367534 ps
CPU time 7.18 seconds
Started Mar 19 12:55:53 PM PDT 24
Finished Mar 19 12:56:01 PM PDT 24
Peak memory 202888 kb
Host smart-e65f9e5e-7a55-427d-aa2f-fcba064798fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38329
78467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3832978467
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2597164550
Short name T641
Test name
Test status
Simulation time 8372304079 ps
CPU time 7.14 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 202984 kb
Host smart-d1cbd529-5df5-485b-ae57-85c5fd0d16ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25971
64550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2597164550
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2380482712
Short name T531
Test name
Test status
Simulation time 8407311351 ps
CPU time 10.1 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:06 PM PDT 24
Peak memory 203036 kb
Host smart-d67658f7-3df2-4536-a720-b478720844ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23804
82712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2380482712
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1346828648
Short name T813
Test name
Test status
Simulation time 8368859730 ps
CPU time 9.73 seconds
Started Mar 19 12:55:53 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 203104 kb
Host smart-6bbc3750-9cb0-440c-aecc-0424932a3c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13468
28648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1346828648
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3966167249
Short name T97
Test name
Test status
Simulation time 8415166757 ps
CPU time 7.36 seconds
Started Mar 19 12:55:59 PM PDT 24
Finished Mar 19 12:56:07 PM PDT 24
Peak memory 202992 kb
Host smart-b77fa9a4-97d6-4dd2-a2e1-801e35e5db9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39661
67249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3966167249
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2096845845
Short name T489
Test name
Test status
Simulation time 8367940812 ps
CPU time 7.43 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 202924 kb
Host smart-507cc43d-beac-4fd2-9836-90b1e7be96fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20968
45845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2096845845
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2376135161
Short name T859
Test name
Test status
Simulation time 8388803367 ps
CPU time 7.68 seconds
Started Mar 19 12:55:59 PM PDT 24
Finished Mar 19 12:56:07 PM PDT 24
Peak memory 202976 kb
Host smart-52ee6151-e97a-4932-9586-cb8879ed623b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
35161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2376135161
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2468748384
Short name T225
Test name
Test status
Simulation time 29071026 ps
CPU time 0.65 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:55:56 PM PDT 24
Peak memory 202600 kb
Host smart-f5887d71-41d6-4301-9d94-16cb0f7335c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24687
48384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2468748384
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3047052657
Short name T390
Test name
Test status
Simulation time 8393979844 ps
CPU time 8.06 seconds
Started Mar 19 12:55:53 PM PDT 24
Finished Mar 19 12:56:01 PM PDT 24
Peak memory 202980 kb
Host smart-99a292e2-2515-48aa-a599-c8ac1a700bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30470
52657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3047052657
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.320098857
Short name T631
Test name
Test status
Simulation time 8455902410 ps
CPU time 7.73 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 203020 kb
Host smart-e134e442-0e05-4894-89f3-2914712d0505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32009
8857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.320098857
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.1180816925
Short name T546
Test name
Test status
Simulation time 8371912221 ps
CPU time 7.71 seconds
Started Mar 19 12:55:54 PM PDT 24
Finished Mar 19 12:56:02 PM PDT 24
Peak memory 203012 kb
Host smart-653c004a-9aab-4c2d-8df2-0f6f0a20f280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11808
16925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.1180816925
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1732146801
Short name T211
Test name
Test status
Simulation time 8356483280 ps
CPU time 7.24 seconds
Started Mar 19 12:55:54 PM PDT 24
Finished Mar 19 12:56:01 PM PDT 24
Peak memory 203000 kb
Host smart-ffbbaf90-75b3-444c-857d-0f1f397fd5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17321
46801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1732146801
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2474817051
Short name T157
Test name
Test status
Simulation time 8472110177 ps
CPU time 9.47 seconds
Started Mar 19 12:55:52 PM PDT 24
Finished Mar 19 12:56:02 PM PDT 24
Peak memory 203108 kb
Host smart-2dc357e4-c323-42ad-ae75-af8f997b8038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24748
17051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2474817051
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2841218038
Short name T791
Test name
Test status
Simulation time 8365427312 ps
CPU time 7.15 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202996 kb
Host smart-8d21cb7d-58c6-4747-ae5e-f33a2bf3e84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28412
18038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2841218038
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.2385726258
Short name T611
Test name
Test status
Simulation time 8371711746 ps
CPU time 7.52 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202816 kb
Host smart-b4fc51d4-9549-40ec-a7f9-deb50e504762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23857
26258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2385726258
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.882177819
Short name T692
Test name
Test status
Simulation time 72665903 ps
CPU time 1.92 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:55:57 PM PDT 24
Peak memory 203108 kb
Host smart-d4dd2854-3cfd-4534-9c0a-949420cf1b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88217
7819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.882177819
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1475181250
Short name T634
Test name
Test status
Simulation time 8357058595 ps
CPU time 7.76 seconds
Started Mar 19 12:56:05 PM PDT 24
Finished Mar 19 12:56:13 PM PDT 24
Peak memory 202880 kb
Host smart-8837a538-5fa1-48d0-8c9e-bc477659629b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14751
81250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1475181250
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1432797563
Short name T552
Test name
Test status
Simulation time 8392518203 ps
CPU time 8.22 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 203056 kb
Host smart-ca907474-b7fb-4c10-bd6f-507f3933dea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14327
97563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1432797563
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2020084330
Short name T711
Test name
Test status
Simulation time 8407495358 ps
CPU time 9.92 seconds
Started Mar 19 12:55:56 PM PDT 24
Finished Mar 19 12:56:06 PM PDT 24
Peak memory 203012 kb
Host smart-b1fccc42-2e77-407a-a458-6ae70d1b96d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20200
84330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2020084330
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3880311226
Short name T283
Test name
Test status
Simulation time 8368921686 ps
CPU time 7.15 seconds
Started Mar 19 12:55:58 PM PDT 24
Finished Mar 19 12:56:05 PM PDT 24
Peak memory 202920 kb
Host smart-8ddadbe7-ded6-48db-bf20-c90765090e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38803
11226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3880311226
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1285658706
Short name T1
Test name
Test status
Simulation time 8396368940 ps
CPU time 9.91 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:05 PM PDT 24
Peak memory 202996 kb
Host smart-f5f187e2-d6cf-4c6f-8fa0-ff5d4590a507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856
58706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1285658706
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1904174128
Short name T702
Test name
Test status
Simulation time 8364837179 ps
CPU time 10.09 seconds
Started Mar 19 12:55:54 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202860 kb
Host smart-036a38a6-46e0-4693-9974-dbb780a99b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
74128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1904174128
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2360101760
Short name T705
Test name
Test status
Simulation time 8396121838 ps
CPU time 9.15 seconds
Started Mar 19 12:55:57 PM PDT 24
Finished Mar 19 12:56:07 PM PDT 24
Peak memory 202764 kb
Host smart-680f52a8-e73a-4a01-b272-be125dac8573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23601
01760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2360101760
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1330967713
Short name T835
Test name
Test status
Simulation time 29975069 ps
CPU time 0.68 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 202580 kb
Host smart-b80221a8-30a9-486a-829d-b3d4fb016174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13309
67713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1330967713
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1040701476
Short name T483
Test name
Test status
Simulation time 8382934316 ps
CPU time 8.25 seconds
Started Mar 19 12:55:52 PM PDT 24
Finished Mar 19 12:56:00 PM PDT 24
Peak memory 202976 kb
Host smart-e623a373-99be-463e-9778-5dca8ffe3815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10407
01476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1040701476
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.425088915
Short name T131
Test name
Test status
Simulation time 8408788750 ps
CPU time 8.04 seconds
Started Mar 19 12:55:54 PM PDT 24
Finished Mar 19 12:56:02 PM PDT 24
Peak memory 203020 kb
Host smart-d33ebc2a-c16e-4a04-8e49-1aa88da906c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42508
8915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.425088915
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.1471373836
Short name T419
Test name
Test status
Simulation time 8403232602 ps
CPU time 7.76 seconds
Started Mar 19 12:55:54 PM PDT 24
Finished Mar 19 12:56:02 PM PDT 24
Peak memory 202980 kb
Host smart-c121c38b-3440-43fa-aee3-13a1ae4579af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
73836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.1471373836
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1280334397
Short name T374
Test name
Test status
Simulation time 8356254107 ps
CPU time 7.26 seconds
Started Mar 19 12:56:07 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 202884 kb
Host smart-21c69433-9065-48ad-91d5-efd99f405d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12803
34397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1280334397
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1830334420
Short name T248
Test name
Test status
Simulation time 8475139182 ps
CPU time 7.76 seconds
Started Mar 19 12:55:55 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 203016 kb
Host smart-25acfcea-198d-4b4a-a073-e5ea3b8b4263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18303
34420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1830334420
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1165295645
Short name T326
Test name
Test status
Simulation time 8374111725 ps
CPU time 7.61 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:10 PM PDT 24
Peak memory 202992 kb
Host smart-eae7a9b5-6730-44f7-bbe4-e150006276b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11652
95645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1165295645
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.370911219
Short name T386
Test name
Test status
Simulation time 8370115782 ps
CPU time 7.38 seconds
Started Mar 19 12:56:04 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202840 kb
Host smart-f462439f-f36e-4222-8a1c-eba91967bb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37091
1219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.370911219
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.676239855
Short name T2
Test name
Test status
Simulation time 191846011 ps
CPU time 1.72 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:06 PM PDT 24
Peak memory 202772 kb
Host smart-68691224-42cd-4d37-8306-caa9991758f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67623
9855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.676239855
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.962897629
Short name T820
Test name
Test status
Simulation time 8360410294 ps
CPU time 7.26 seconds
Started Mar 19 12:56:04 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202820 kb
Host smart-ed87f44a-cbf8-4eb8-a542-e2c7c1d47c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96289
7629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.962897629
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.45428470
Short name T696
Test name
Test status
Simulation time 8372177120 ps
CPU time 8.52 seconds
Started Mar 19 12:56:01 PM PDT 24
Finished Mar 19 12:56:11 PM PDT 24
Peak memory 203008 kb
Host smart-84fc61c3-81f5-4089-90fc-34377e40268d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45428
470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.45428470
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.237520226
Short name T763
Test name
Test status
Simulation time 8408045491 ps
CPU time 9.62 seconds
Started Mar 19 12:56:04 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 202988 kb
Host smart-b74d156e-497a-4ea1-ae9a-8f8c16140259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23752
0226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.237520226
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3417166335
Short name T742
Test name
Test status
Simulation time 8367818152 ps
CPU time 8.01 seconds
Started Mar 19 12:56:06 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 202988 kb
Host smart-b2829a9e-d407-4772-a23b-2e22ae95d067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
66335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3417166335
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2524147770
Short name T124
Test name
Test status
Simulation time 8446911484 ps
CPU time 7.21 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:09 PM PDT 24
Peak memory 203036 kb
Host smart-feb4946f-2857-4817-a49a-5133906b7650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25241
47770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2524147770
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.887033534
Short name T551
Test name
Test status
Simulation time 8376267239 ps
CPU time 8.39 seconds
Started Mar 19 12:56:05 PM PDT 24
Finished Mar 19 12:56:13 PM PDT 24
Peak memory 202892 kb
Host smart-5db86fee-c59c-40d7-ab29-0d0b1ff289c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88703
3534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.887033534
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.4135988753
Short name T351
Test name
Test status
Simulation time 8378458394 ps
CPU time 7.77 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202864 kb
Host smart-141cd466-caa9-488d-9324-4020743cd343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41359
88753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.4135988753
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1666332019
Short name T25
Test name
Test status
Simulation time 28713888 ps
CPU time 0.63 seconds
Started Mar 19 12:56:05 PM PDT 24
Finished Mar 19 12:56:05 PM PDT 24
Peak memory 202552 kb
Host smart-75702ced-6392-4434-8adc-6a7cb9d49864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16663
32019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1666332019
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2165949328
Short name T511
Test name
Test status
Simulation time 8374188175 ps
CPU time 9.04 seconds
Started Mar 19 12:56:06 PM PDT 24
Finished Mar 19 12:56:15 PM PDT 24
Peak memory 202804 kb
Host smart-f6df20a4-d5c0-4be0-b006-91c98efa0df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21659
49328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2165949328
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3924461663
Short name T325
Test name
Test status
Simulation time 8429158566 ps
CPU time 7.89 seconds
Started Mar 19 12:56:06 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 203032 kb
Host smart-9ad1d3d0-a8c0-4b34-a87c-81a602e65374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39244
61663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3924461663
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.1836707441
Short name T267
Test name
Test status
Simulation time 8396436506 ps
CPU time 7 seconds
Started Mar 19 12:56:04 PM PDT 24
Finished Mar 19 12:56:11 PM PDT 24
Peak memory 203004 kb
Host smart-3f9eefdb-0f10-4c3a-a58d-45c34578bea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18367
07441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.1836707441
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2445823790
Short name T759
Test name
Test status
Simulation time 8357015828 ps
CPU time 7.69 seconds
Started Mar 19 12:56:04 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202880 kb
Host smart-ada07cda-cbef-4a8b-96c9-5fc559df1e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24458
23790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2445823790
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2765630248
Short name T158
Test name
Test status
Simulation time 8471103166 ps
CPU time 8.15 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:11 PM PDT 24
Peak memory 203044 kb
Host smart-78d8f5d3-6def-4566-aad7-dcfb8fc1b344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27656
30248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2765630248
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2840401201
Short name T231
Test name
Test status
Simulation time 8370546212 ps
CPU time 8.5 seconds
Started Mar 19 12:54:02 PM PDT 24
Finished Mar 19 12:54:11 PM PDT 24
Peak memory 203024 kb
Host smart-0f997f35-b5f2-4441-b1c7-e867de4e0470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28404
01201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2840401201
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.1977118870
Short name T591
Test name
Test status
Simulation time 8370213006 ps
CPU time 7.35 seconds
Started Mar 19 12:54:03 PM PDT 24
Finished Mar 19 12:54:11 PM PDT 24
Peak memory 202792 kb
Host smart-9eb0b935-105b-4d68-8bba-d0e70ba23c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19771
18870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1977118870
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3825873937
Short name T751
Test name
Test status
Simulation time 159129280 ps
CPU time 1.85 seconds
Started Mar 19 12:54:05 PM PDT 24
Finished Mar 19 12:54:07 PM PDT 24
Peak memory 202836 kb
Host smart-4441a269-09ed-4710-abac-cfedc7e1bd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
73937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3825873937
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1879690750
Short name T176
Test name
Test status
Simulation time 8357087884 ps
CPU time 7.62 seconds
Started Mar 19 12:54:10 PM PDT 24
Finished Mar 19 12:54:18 PM PDT 24
Peak memory 202824 kb
Host smart-af1eaf9a-8069-4cf3-897b-fd7d6fcb80da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
90750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1879690750
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.933970192
Short name T579
Test name
Test status
Simulation time 8388388871 ps
CPU time 9.2 seconds
Started Mar 19 12:54:06 PM PDT 24
Finished Mar 19 12:54:15 PM PDT 24
Peak memory 203040 kb
Host smart-34d99dac-862d-4c3e-8ff0-9d927412de78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93397
0192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.933970192
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2244087860
Short name T6
Test name
Test status
Simulation time 8402514733 ps
CPU time 7.72 seconds
Started Mar 19 12:54:05 PM PDT 24
Finished Mar 19 12:54:13 PM PDT 24
Peak memory 203044 kb
Host smart-0e9ec83b-b167-4f80-8237-8399b895790c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22440
87860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2244087860
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2104128218
Short name T414
Test name
Test status
Simulation time 8361969861 ps
CPU time 7.36 seconds
Started Mar 19 12:54:05 PM PDT 24
Finished Mar 19 12:54:12 PM PDT 24
Peak memory 202980 kb
Host smart-c1087da0-9175-4234-895c-e3c652eb0b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21041
28218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2104128218
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1277539261
Short name T122
Test name
Test status
Simulation time 8440338698 ps
CPU time 7.97 seconds
Started Mar 19 12:54:02 PM PDT 24
Finished Mar 19 12:54:11 PM PDT 24
Peak memory 203020 kb
Host smart-ad455ae6-0956-4f83-b0f8-030f2874476b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12775
39261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1277539261
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.948640124
Short name T382
Test name
Test status
Simulation time 8390093969 ps
CPU time 7.49 seconds
Started Mar 19 12:54:05 PM PDT 24
Finished Mar 19 12:54:12 PM PDT 24
Peak memory 202900 kb
Host smart-26eb13b4-51b1-4570-8eeb-f71cc99ec3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94864
0124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.948640124
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3562093558
Short name T355
Test name
Test status
Simulation time 8393598637 ps
CPU time 7.25 seconds
Started Mar 19 12:54:01 PM PDT 24
Finished Mar 19 12:54:09 PM PDT 24
Peak memory 202884 kb
Host smart-3a317899-b0a4-43f8-82fa-e7c98ca267df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35620
93558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3562093558
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1785624080
Short name T807
Test name
Test status
Simulation time 25306288 ps
CPU time 0.64 seconds
Started Mar 19 12:54:09 PM PDT 24
Finished Mar 19 12:54:10 PM PDT 24
Peak memory 202524 kb
Host smart-03d9f4b7-b035-406c-a566-6dc3a1b83507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17856
24080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1785624080
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1809798387
Short name T566
Test name
Test status
Simulation time 8394220042 ps
CPU time 7.35 seconds
Started Mar 19 12:54:01 PM PDT 24
Finished Mar 19 12:54:08 PM PDT 24
Peak memory 202892 kb
Host smart-504fe79c-8e09-4f33-9a74-c50e7d5cb412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18097
98387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1809798387
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.3297900214
Short name T409
Test name
Test status
Simulation time 8457299146 ps
CPU time 8.6 seconds
Started Mar 19 12:54:03 PM PDT 24
Finished Mar 19 12:54:12 PM PDT 24
Peak memory 203004 kb
Host smart-b01163bf-2d6b-4972-be6f-b534465e071d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32979
00214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3297900214
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3410813022
Short name T843
Test name
Test status
Simulation time 8368677688 ps
CPU time 7.69 seconds
Started Mar 19 12:54:08 PM PDT 24
Finished Mar 19 12:54:17 PM PDT 24
Peak memory 203052 kb
Host smart-b1bcc387-118a-4cd3-9e8f-e8566fc71a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34108
13022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3410813022
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1460422656
Short name T82
Test name
Test status
Simulation time 94641360 ps
CPU time 0.91 seconds
Started Mar 19 12:54:08 PM PDT 24
Finished Mar 19 12:54:10 PM PDT 24
Peak memory 218332 kb
Host smart-0f412116-ad63-4257-a04f-65a044265548
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1460422656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1460422656
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.628264811
Short name T367
Test name
Test status
Simulation time 8355748575 ps
CPU time 7.65 seconds
Started Mar 19 12:54:08 PM PDT 24
Finished Mar 19 12:54:17 PM PDT 24
Peak memory 202868 kb
Host smart-d3d4ff01-108c-4047-9222-fc2e87ea7b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62826
4811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.628264811
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.613744552
Short name T789
Test name
Test status
Simulation time 8471255770 ps
CPU time 8.77 seconds
Started Mar 19 12:54:06 PM PDT 24
Finished Mar 19 12:54:15 PM PDT 24
Peak memory 203048 kb
Host smart-554b2231-233d-4680-8285-1bbb74453c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61374
4552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.613744552
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2187376742
Short name T457
Test name
Test status
Simulation time 8368045207 ps
CPU time 8.77 seconds
Started Mar 19 12:56:06 PM PDT 24
Finished Mar 19 12:56:15 PM PDT 24
Peak memory 203028 kb
Host smart-1b4476ad-bcdd-48a4-97ed-1942bb5d5050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21873
76742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2187376742
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.1807894836
Short name T344
Test name
Test status
Simulation time 8371410041 ps
CPU time 9.21 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:13 PM PDT 24
Peak memory 202800 kb
Host smart-00a582d0-4635-433e-8627-540d1795361a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18078
94836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1807894836
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.299498713
Short name T224
Test name
Test status
Simulation time 47745219 ps
CPU time 1.25 seconds
Started Mar 19 12:56:01 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 203084 kb
Host smart-56d7ebd9-057e-4bad-8e60-776513446f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29949
8713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.299498713
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1563801115
Short name T169
Test name
Test status
Simulation time 8364293826 ps
CPU time 9.29 seconds
Started Mar 19 12:56:07 PM PDT 24
Finished Mar 19 12:56:16 PM PDT 24
Peak memory 202860 kb
Host smart-d6e41125-4f40-45ad-8859-cf7a3cbf4aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15638
01115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1563801115
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3671240867
Short name T426
Test name
Test status
Simulation time 8423165648 ps
CPU time 7.95 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 203040 kb
Host smart-084a6a39-ef55-4c97-aa49-bba2c77a8e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36712
40867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3671240867
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.546291675
Short name T471
Test name
Test status
Simulation time 8404941791 ps
CPU time 7.51 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:10 PM PDT 24
Peak memory 203004 kb
Host smart-22d6041f-a1c2-48a6-8f2f-f04d601b14b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54629
1675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.546291675
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2626028888
Short name T838
Test name
Test status
Simulation time 8368594192 ps
CPU time 7.86 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 203044 kb
Host smart-d6f62b0d-bfa1-48df-9610-6bdc7b2f3177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26260
28888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2626028888
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3576733693
Short name T588
Test name
Test status
Simulation time 8379408191 ps
CPU time 8.86 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202856 kb
Host smart-fd9d94a4-6797-4b9c-8572-141ee6ca424c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
33693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3576733693
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.884388499
Short name T547
Test name
Test status
Simulation time 8396564456 ps
CPU time 6.94 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:10 PM PDT 24
Peak memory 203032 kb
Host smart-553aa076-87ca-48ed-85b1-a4ee34bdd73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88438
8499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.884388499
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1364472735
Short name T462
Test name
Test status
Simulation time 27133126 ps
CPU time 0.65 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 202600 kb
Host smart-6f367019-ae75-4902-8c65-7c7fac700daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
72735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1364472735
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1333346429
Short name T431
Test name
Test status
Simulation time 8397484873 ps
CPU time 8.5 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:11 PM PDT 24
Peak memory 202848 kb
Host smart-f44b36b7-2205-4126-aaa6-6e64982e6c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
46429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1333346429
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3724712512
Short name T717
Test name
Test status
Simulation time 8389755288 ps
CPU time 7.4 seconds
Started Mar 19 12:56:01 PM PDT 24
Finished Mar 19 12:56:09 PM PDT 24
Peak memory 203072 kb
Host smart-bed3cf44-fe64-4db2-8a14-07b449ca34d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37247
12512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3724712512
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.649902955
Short name T559
Test name
Test status
Simulation time 8359036852 ps
CPU time 8.14 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:11 PM PDT 24
Peak memory 202928 kb
Host smart-d3bf99c9-97a1-42d0-9669-a3adc82108a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64990
2955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.649902955
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1759996027
Short name T161
Test name
Test status
Simulation time 8473285129 ps
CPU time 7.91 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 203044 kb
Host smart-75cd2c2d-abdd-404e-98d1-6c8762081027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17599
96027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1759996027
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3361250317
Short name T730
Test name
Test status
Simulation time 8364699392 ps
CPU time 7.03 seconds
Started Mar 19 12:56:06 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 203064 kb
Host smart-39790fc2-88a2-450b-84b1-3da7db3c5a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33612
50317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3361250317
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.3471473938
Short name T287
Test name
Test status
Simulation time 8374774583 ps
CPU time 8.62 seconds
Started Mar 19 12:56:05 PM PDT 24
Finished Mar 19 12:56:13 PM PDT 24
Peak memory 202812 kb
Host smart-8513a201-7d3a-487b-86e2-617d8087b5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34714
73938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3471473938
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1349218229
Short name T338
Test name
Test status
Simulation time 105790438 ps
CPU time 1.17 seconds
Started Mar 19 12:56:01 PM PDT 24
Finished Mar 19 12:56:03 PM PDT 24
Peak memory 203192 kb
Host smart-0ce18ac4-768e-482d-9bfb-44159c77504b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13492
18229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1349218229
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2776186833
Short name T535
Test name
Test status
Simulation time 8358875259 ps
CPU time 8.24 seconds
Started Mar 19 12:56:05 PM PDT 24
Finished Mar 19 12:56:13 PM PDT 24
Peak memory 202836 kb
Host smart-8ef7e418-cf46-4eec-84b9-f0f5be319118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27761
86833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2776186833
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3755679661
Short name T376
Test name
Test status
Simulation time 8443519217 ps
CPU time 9.97 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 203048 kb
Host smart-68e5dd18-6adc-4ea2-b54d-b94e34a38113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37556
79661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3755679661
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3577637032
Short name T272
Test name
Test status
Simulation time 8409078343 ps
CPU time 7.15 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:10 PM PDT 24
Peak memory 203020 kb
Host smart-ab6624a6-4ecf-4f15-8a77-3aec81b9f6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35776
37032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3577637032
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4258401857
Short name T289
Test name
Test status
Simulation time 8368562911 ps
CPU time 7.73 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202976 kb
Host smart-cd9a829e-d026-44f4-bc0e-b3f5a4185229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42584
01857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4258401857
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3308646576
Short name T111
Test name
Test status
Simulation time 8397160707 ps
CPU time 7.44 seconds
Started Mar 19 12:56:05 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202976 kb
Host smart-babf9ca1-1002-4ebe-ac77-ea3f9b5934e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
46576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3308646576
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.141203883
Short name T335
Test name
Test status
Simulation time 8378215752 ps
CPU time 7.98 seconds
Started Mar 19 12:56:06 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 202960 kb
Host smart-3abc6b3b-9b5d-4f1f-afb3-ef3f3f798436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14120
3883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.141203883
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3859283261
Short name T678
Test name
Test status
Simulation time 8381214640 ps
CPU time 9.48 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 202904 kb
Host smart-3500ad14-70df-4c6b-8c18-4cd05e17d974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38592
83261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3859283261
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.82674983
Short name T444
Test name
Test status
Simulation time 22402118 ps
CPU time 0.64 seconds
Started Mar 19 12:56:03 PM PDT 24
Finished Mar 19 12:56:04 PM PDT 24
Peak memory 202536 kb
Host smart-a6248b7f-f554-42d1-a709-e90fb6f508d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82674
983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.82674983
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.204741151
Short name T564
Test name
Test status
Simulation time 8399840579 ps
CPU time 7.43 seconds
Started Mar 19 12:56:04 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202844 kb
Host smart-03d1753d-93ca-4951-9e38-5cc56bcbc7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20474
1151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.204741151
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.850668597
Short name T597
Test name
Test status
Simulation time 8385611105 ps
CPU time 7.21 seconds
Started Mar 19 12:56:04 PM PDT 24
Finished Mar 19 12:56:12 PM PDT 24
Peak memory 202976 kb
Host smart-717bc59c-5e6a-4e1c-bbdd-8bdeb5d5d0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85066
8597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.850668597
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.4034470667
Short name T495
Test name
Test status
Simulation time 8388973977 ps
CPU time 7.24 seconds
Started Mar 19 12:56:06 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 203016 kb
Host smart-6d077f5b-c7f2-4bbb-812e-a7044fe05551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40344
70667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.4034470667
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.696191463
Short name T744
Test name
Test status
Simulation time 8358691764 ps
CPU time 7.65 seconds
Started Mar 19 12:56:02 PM PDT 24
Finished Mar 19 12:56:10 PM PDT 24
Peak memory 202876 kb
Host smart-66201f79-b143-4e22-8ea7-3c83beb18826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69619
1463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.696191463
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.896661914
Short name T357
Test name
Test status
Simulation time 8370681838 ps
CPU time 7.16 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:17 PM PDT 24
Peak memory 203048 kb
Host smart-dbf96b93-e5e9-4632-b30e-c5cb2cc24195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89666
1914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.896661914
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.4134337932
Short name T784
Test name
Test status
Simulation time 8372431239 ps
CPU time 7.23 seconds
Started Mar 19 12:56:14 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 202792 kb
Host smart-11250a03-215d-4bbe-9b28-6669ffe1f4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41343
37932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.4134337932
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3047998868
Short name T92
Test name
Test status
Simulation time 104309415 ps
CPU time 1.1 seconds
Started Mar 19 12:56:25 PM PDT 24
Finished Mar 19 12:56:26 PM PDT 24
Peak memory 202688 kb
Host smart-73cd242b-536e-4b79-80ae-82a5d2b2215d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30479
98868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3047998868
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2664816499
Short name T180
Test name
Test status
Simulation time 8357792116 ps
CPU time 7.82 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 202828 kb
Host smart-614206c3-cb20-4d1c-91ba-54e34986f440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26648
16499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2664816499
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.484938752
Short name T138
Test name
Test status
Simulation time 8401377657 ps
CPU time 8 seconds
Started Mar 19 12:56:15 PM PDT 24
Finished Mar 19 12:56:23 PM PDT 24
Peak memory 202988 kb
Host smart-c4dbfecd-efa5-4e66-a8fe-f888f328ee2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48493
8752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.484938752
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3945475814
Short name T731
Test name
Test status
Simulation time 8408898866 ps
CPU time 7.99 seconds
Started Mar 19 12:56:08 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 203044 kb
Host smart-e9df26a2-3859-47e1-bf73-a0f498bb75a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
75814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3945475814
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3555839373
Short name T616
Test name
Test status
Simulation time 8360764772 ps
CPU time 9.94 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 203032 kb
Host smart-afa0840b-0801-4c2b-9b80-e56490c991ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35558
39373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3555839373
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.958501204
Short name T102
Test name
Test status
Simulation time 8417653081 ps
CPU time 7.62 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:17 PM PDT 24
Peak memory 202984 kb
Host smart-a38c23a8-fff1-44a1-a7ef-e021e8752356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95850
1204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.958501204
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1098506546
Short name T420
Test name
Test status
Simulation time 8381735399 ps
CPU time 7.8 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 202852 kb
Host smart-324e9c74-a6f8-4c50-8975-ab2df3331f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10985
06546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1098506546
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1931049584
Short name T565
Test name
Test status
Simulation time 8403491026 ps
CPU time 8.5 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:23 PM PDT 24
Peak memory 202740 kb
Host smart-eebed593-3182-42c7-b68c-f84e6c00e290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19310
49584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1931049584
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3176950062
Short name T36
Test name
Test status
Simulation time 26807963 ps
CPU time 0.63 seconds
Started Mar 19 12:56:14 PM PDT 24
Finished Mar 19 12:56:15 PM PDT 24
Peak memory 202512 kb
Host smart-3bfd8510-f3f6-43fc-8725-97290dc8ba32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
50062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3176950062
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.270513983
Short name T400
Test name
Test status
Simulation time 8381727223 ps
CPU time 7.66 seconds
Started Mar 19 12:56:14 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 202784 kb
Host smart-02f748f2-50e4-4444-a34a-d59cef65d772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27051
3983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.270513983
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2025118582
Short name T688
Test name
Test status
Simulation time 8418341823 ps
CPU time 8.86 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:23 PM PDT 24
Peak memory 202988 kb
Host smart-b7eb7b02-b60e-402a-af5a-4e884e165ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20251
18582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2025118582
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.1894371590
Short name T377
Test name
Test status
Simulation time 8406696460 ps
CPU time 8.39 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 203008 kb
Host smart-11c909ad-dfd4-4018-9667-a006cf03e355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18943
71590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.1894371590
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.518194353
Short name T354
Test name
Test status
Simulation time 8362327908 ps
CPU time 9.93 seconds
Started Mar 19 12:56:11 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 202844 kb
Host smart-51b429a6-5dfa-42a4-bb65-d9ffd4f5f3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51819
4353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.518194353
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.450183593
Short name T615
Test name
Test status
Simulation time 8368208863 ps
CPU time 7.33 seconds
Started Mar 19 12:56:07 PM PDT 24
Finished Mar 19 12:56:15 PM PDT 24
Peak memory 203008 kb
Host smart-3c2cbb34-b9d1-4f0b-99ef-3a354392f700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45018
3593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.450183593
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.517436273
Short name T330
Test name
Test status
Simulation time 8373275743 ps
CPU time 7.7 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 202776 kb
Host smart-7c8fb2a8-4b62-404d-b46a-3c59e81ae098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51743
6273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.517436273
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1403091253
Short name T708
Test name
Test status
Simulation time 209169065 ps
CPU time 1.86 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:16 PM PDT 24
Peak memory 203100 kb
Host smart-6ae7155f-ed64-445a-8389-c3ab1e90b6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14030
91253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1403091253
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.495841180
Short name T24
Test name
Test status
Simulation time 8362344819 ps
CPU time 9.66 seconds
Started Mar 19 12:56:14 PM PDT 24
Finished Mar 19 12:56:24 PM PDT 24
Peak memory 202780 kb
Host smart-cf95ec45-09fb-4ea1-bbf8-b40e81da914d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49584
1180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.495841180
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1263808798
Short name T232
Test name
Test status
Simulation time 8425090939 ps
CPU time 10.27 seconds
Started Mar 19 12:56:11 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 203112 kb
Host smart-e89105f5-7c96-41e8-981d-e3c846bec010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12638
08798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1263808798
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3820657385
Short name T427
Test name
Test status
Simulation time 8404276078 ps
CPU time 7.37 seconds
Started Mar 19 12:56:08 PM PDT 24
Finished Mar 19 12:56:16 PM PDT 24
Peak memory 203016 kb
Host smart-be747043-efe0-4db7-a33d-49498a570cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38206
57385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3820657385
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3866188740
Short name T828
Test name
Test status
Simulation time 8367551411 ps
CPU time 7.44 seconds
Started Mar 19 12:56:08 PM PDT 24
Finished Mar 19 12:56:17 PM PDT 24
Peak memory 203004 kb
Host smart-914cf3ae-5f3d-4cf9-8d5d-8fc494d4a9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38661
88740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3866188740
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1020323193
Short name T729
Test name
Test status
Simulation time 8421751184 ps
CPU time 7.74 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 203016 kb
Host smart-480deb27-37a2-4cb7-97e0-f85029858bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10203
23193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1020323193
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2700129173
Short name T706
Test name
Test status
Simulation time 8373382232 ps
CPU time 7.57 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 203004 kb
Host smart-070dfa13-af75-40ca-b1b1-d5ef4e374185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27001
29173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2700129173
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3322216800
Short name T234
Test name
Test status
Simulation time 8366959186 ps
CPU time 7.96 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 203008 kb
Host smart-82239cc6-f8d6-462d-97b5-35a9a9e14285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33222
16800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3322216800
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.455779475
Short name T32
Test name
Test status
Simulation time 24569486 ps
CPU time 0.63 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:15 PM PDT 24
Peak memory 202488 kb
Host smart-47c3aeac-068e-4a6c-bbaa-ca51f15d632d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45577
9475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.455779475
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3201574029
Short name T322
Test name
Test status
Simulation time 8403240695 ps
CPU time 9.25 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:19 PM PDT 24
Peak memory 202924 kb
Host smart-608ba152-a5e5-4d86-a825-d713361d2171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32015
74029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3201574029
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3589860168
Short name T676
Test name
Test status
Simulation time 8422628862 ps
CPU time 10.11 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:21 PM PDT 24
Peak memory 203000 kb
Host smart-32d6f8a1-2d49-4a62-a55e-6b49060b9ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35898
60168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3589860168
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.2612584719
Short name T279
Test name
Test status
Simulation time 8391358525 ps
CPU time 7.82 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 202988 kb
Host smart-5826300b-29c2-4f03-95c1-32659cfaa094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26125
84719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.2612584719
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.87432790
Short name T782
Test name
Test status
Simulation time 8361801887 ps
CPU time 7.26 seconds
Started Mar 19 12:56:08 PM PDT 24
Finished Mar 19 12:56:17 PM PDT 24
Peak memory 203024 kb
Host smart-360c9c23-ff85-4b0a-a649-76fed320f2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87432
790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.87432790
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1765770973
Short name T140
Test name
Test status
Simulation time 8474933745 ps
CPU time 7.9 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:19 PM PDT 24
Peak memory 203068 kb
Host smart-98297759-b708-45f2-a720-3757b26b5bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17657
70973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1765770973
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2854579508
Short name T398
Test name
Test status
Simulation time 8370296323 ps
CPU time 9.06 seconds
Started Mar 19 12:56:24 PM PDT 24
Finished Mar 19 12:56:33 PM PDT 24
Peak memory 203016 kb
Host smart-ed965d38-43a2-4506-a805-882bf6910165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28545
79508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2854579508
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.1853890257
Short name T84
Test name
Test status
Simulation time 8370966220 ps
CPU time 7.96 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 202836 kb
Host smart-3d70053d-7529-4b72-bf4d-9b64c74252e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18538
90257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1853890257
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.708204199
Short name T310
Test name
Test status
Simulation time 302394493 ps
CPU time 2.49 seconds
Started Mar 19 12:56:12 PM PDT 24
Finished Mar 19 12:56:15 PM PDT 24
Peak memory 202768 kb
Host smart-9869aa5d-dedc-410a-a4a0-051832c47996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70820
4199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.708204199
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2445498760
Short name T449
Test name
Test status
Simulation time 8361711078 ps
CPU time 6.99 seconds
Started Mar 19 12:56:11 PM PDT 24
Finished Mar 19 12:56:24 PM PDT 24
Peak memory 202856 kb
Host smart-2404690a-881f-4d3f-b856-a0e4c2986c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24454
98760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2445498760
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.294790124
Short name T680
Test name
Test status
Simulation time 8380793965 ps
CPU time 7.81 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 203020 kb
Host smart-76c68925-ccd3-461e-8e9d-a0b5053eae18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29479
0124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.294790124
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2755311413
Short name T343
Test name
Test status
Simulation time 8407524756 ps
CPU time 7.99 seconds
Started Mar 19 12:56:08 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 203000 kb
Host smart-12b4d941-b470-4f5c-894b-029aa081d5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27553
11413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2755311413
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3396350770
Short name T540
Test name
Test status
Simulation time 8361999047 ps
CPU time 7.77 seconds
Started Mar 19 12:56:11 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 203072 kb
Host smart-506e3e8a-3131-4228-b879-f98f0f8da21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
50770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3396350770
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.276929116
Short name T114
Test name
Test status
Simulation time 8410291180 ps
CPU time 7.42 seconds
Started Mar 19 12:56:12 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 203028 kb
Host smart-a1c71900-212b-425d-bfed-4f6866cfa1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27692
9116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.276929116
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4063187229
Short name T423
Test name
Test status
Simulation time 8382054792 ps
CPU time 8.93 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:19 PM PDT 24
Peak memory 202880 kb
Host smart-2478b6aa-32a0-47e1-b323-b6c364d31c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40631
87229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4063187229
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3154745981
Short name T827
Test name
Test status
Simulation time 8398271598 ps
CPU time 7.18 seconds
Started Mar 19 12:56:12 PM PDT 24
Finished Mar 19 12:56:19 PM PDT 24
Peak memory 202860 kb
Host smart-6caebad7-6d3a-4892-80d1-2686986c62a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31547
45981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3154745981
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1181000412
Short name T305
Test name
Test status
Simulation time 28894282 ps
CPU time 0.67 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 202600 kb
Host smart-036ad8bb-b710-454a-ac7a-b1fafd140c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11810
00412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1181000412
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3455521736
Short name T541
Test name
Test status
Simulation time 8394419541 ps
CPU time 7.49 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 202784 kb
Host smart-9cedf6ab-a8e5-4149-8189-421f5b4c670e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34555
21736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3455521736
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3859371053
Short name T30
Test name
Test status
Simulation time 8403617523 ps
CPU time 8.09 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 203048 kb
Host smart-29d71cf0-009a-4ac8-afd3-9f655059a0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38593
71053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3859371053
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.3929551010
Short name T346
Test name
Test status
Simulation time 8394660752 ps
CPU time 8.03 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:19 PM PDT 24
Peak memory 203012 kb
Host smart-441aa12e-7ea3-4a76-99b5-c77e38d90339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39295
51010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.3929551010
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3383850561
Short name T602
Test name
Test status
Simulation time 8363368044 ps
CPU time 7.94 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 202940 kb
Host smart-349c434f-650c-421d-82a7-f1233df9d299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838
50561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3383850561
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3816934204
Short name T436
Test name
Test status
Simulation time 8372425760 ps
CPU time 9.25 seconds
Started Mar 19 12:56:18 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 203016 kb
Host smart-6f29a001-7bbf-4567-97ce-f3c07d5f62bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38169
34204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3816934204
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.516568320
Short name T689
Test name
Test status
Simulation time 8368817731 ps
CPU time 7.65 seconds
Started Mar 19 12:56:12 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 203024 kb
Host smart-312bb575-309b-4cad-926e-6771a2c83bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51656
8320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.516568320
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3311517151
Short name T747
Test name
Test status
Simulation time 53366253 ps
CPU time 1.58 seconds
Started Mar 19 12:56:12 PM PDT 24
Finished Mar 19 12:56:14 PM PDT 24
Peak memory 202888 kb
Host smart-cc6d0ff9-687d-408b-960a-ddbca2d6be91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33115
17151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3311517151
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.142061
Short name T699
Test name
Test status
Simulation time 8363227311 ps
CPU time 6.92 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:26 PM PDT 24
Peak memory 202792 kb
Host smart-5d93666d-4180-4842-abd8-4922ab240a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14206
1 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.142061
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2001818516
Short name T486
Test name
Test status
Simulation time 8405923357 ps
CPU time 7.91 seconds
Started Mar 19 12:56:11 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 203072 kb
Host smart-1a3cc6db-e1c5-4145-ac3b-3857667bdf9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20018
18516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2001818516
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.402394217
Short name T520
Test name
Test status
Simulation time 8409022922 ps
CPU time 9.2 seconds
Started Mar 19 12:56:11 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 203032 kb
Host smart-dfb102aa-5f0a-48c1-a88c-0b61e2e596e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40239
4217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.402394217
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.99803027
Short name T395
Test name
Test status
Simulation time 8361237040 ps
CPU time 7.36 seconds
Started Mar 19 12:56:14 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 203028 kb
Host smart-6c5d1a32-eaa9-48b0-a717-9eff2a6fc393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99803
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.99803027
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.407274120
Short name T126
Test name
Test status
Simulation time 8398595999 ps
CPU time 7.52 seconds
Started Mar 19 12:56:11 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 203032 kb
Host smart-cc83d4f5-03ac-4f59-b20d-ffd1b11858fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40727
4120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.407274120
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.87835287
Short name T649
Test name
Test status
Simulation time 8390438593 ps
CPU time 8.9 seconds
Started Mar 19 12:56:14 PM PDT 24
Finished Mar 19 12:56:23 PM PDT 24
Peak memory 202856 kb
Host smart-97b00a89-6d5f-47a0-97d3-4d2b1c54fe72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87835
287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.87835287
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2564907492
Short name T545
Test name
Test status
Simulation time 8378025938 ps
CPU time 7.42 seconds
Started Mar 19 12:56:14 PM PDT 24
Finished Mar 19 12:56:22 PM PDT 24
Peak memory 202848 kb
Host smart-6d3795e4-e0c3-48d1-b594-ad3142e1466b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25649
07492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2564907492
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2168992418
Short name T832
Test name
Test status
Simulation time 27542988 ps
CPU time 0.62 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:11 PM PDT 24
Peak memory 202628 kb
Host smart-aa0641b4-a9cf-492b-b18d-d830043f62f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21689
92418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2168992418
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1002611079
Short name T795
Test name
Test status
Simulation time 8374051570 ps
CPU time 7.23 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 202960 kb
Host smart-43f59763-d560-40c0-aff2-9f386bf38359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10026
11079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1002611079
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2417803902
Short name T380
Test name
Test status
Simulation time 8394788639 ps
CPU time 8.17 seconds
Started Mar 19 12:56:25 PM PDT 24
Finished Mar 19 12:56:33 PM PDT 24
Peak memory 203016 kb
Host smart-858bbc43-23e2-4ede-8e50-638cbb12ea44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24178
03902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2417803902
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.2088774955
Short name T455
Test name
Test status
Simulation time 8391911719 ps
CPU time 7.79 seconds
Started Mar 19 12:56:09 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 203012 kb
Host smart-d5388c4c-076a-44e2-82cc-a5ba0176c1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20887
74955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.2088774955
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.961484888
Short name T739
Test name
Test status
Simulation time 8359483686 ps
CPU time 8.14 seconds
Started Mar 19 12:56:18 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 203012 kb
Host smart-c5e0e8ee-33ef-4d7e-99f1-69334b52d9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96148
4888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.961484888
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3735050135
Short name T152
Test name
Test status
Simulation time 8478424141 ps
CPU time 9.7 seconds
Started Mar 19 12:56:13 PM PDT 24
Finished Mar 19 12:56:23 PM PDT 24
Peak memory 203032 kb
Host smart-b7516244-3f39-4bb3-a6bd-4f56a10c4b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37350
50135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3735050135
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.4074515906
Short name T356
Test name
Test status
Simulation time 8371190988 ps
CPU time 9.74 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 202952 kb
Host smart-ee319d6e-2331-44b4-a3a0-3d3785556640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40745
15906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.4074515906
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.2470610837
Short name T293
Test name
Test status
Simulation time 8367062895 ps
CPU time 7.32 seconds
Started Mar 19 12:56:16 PM PDT 24
Finished Mar 19 12:56:24 PM PDT 24
Peak memory 202800 kb
Host smart-2822d1c0-794d-49bf-b0a7-d95ebac7bf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24706
10837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2470610837
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3948571971
Short name T52
Test name
Test status
Simulation time 46433156 ps
CPU time 1.33 seconds
Started Mar 19 12:56:29 PM PDT 24
Finished Mar 19 12:56:30 PM PDT 24
Peak memory 203032 kb
Host smart-338a9d68-7f4b-4c64-a19b-327992942d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39485
71971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3948571971
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1333319049
Short name T175
Test name
Test status
Simulation time 8362853099 ps
CPU time 7.57 seconds
Started Mar 19 12:56:24 PM PDT 24
Finished Mar 19 12:56:32 PM PDT 24
Peak memory 202764 kb
Host smart-7c0b5528-3285-471d-a00e-a9da082fbb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
19049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1333319049
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1654771145
Short name T749
Test name
Test status
Simulation time 8412514660 ps
CPU time 9.77 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:29 PM PDT 24
Peak memory 203048 kb
Host smart-43ae7b28-2cdc-4bb3-b594-6599c4e44a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16547
71145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1654771145
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.688655797
Short name T239
Test name
Test status
Simulation time 8409508102 ps
CPU time 8.43 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 202980 kb
Host smart-807ca84e-bcaa-41e1-baf5-31d35bd47081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68865
5797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.688655797
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.16219813
Short name T506
Test name
Test status
Simulation time 8364711530 ps
CPU time 7.48 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 203020 kb
Host smart-11ed2426-335c-41c7-a5c6-07134bf3101c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16219
813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.16219813
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3764548395
Short name T473
Test name
Test status
Simulation time 8432423700 ps
CPU time 8.16 seconds
Started Mar 19 12:56:22 PM PDT 24
Finished Mar 19 12:56:30 PM PDT 24
Peak memory 202984 kb
Host smart-bd02b1ea-0118-4f12-9b2d-31c758cfbd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37645
48395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3764548395
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.451758173
Short name T538
Test name
Test status
Simulation time 8404441150 ps
CPU time 7.87 seconds
Started Mar 19 12:56:17 PM PDT 24
Finished Mar 19 12:56:25 PM PDT 24
Peak memory 202864 kb
Host smart-ada51021-d23e-494d-9964-ffdfacf7a386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45175
8173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.451758173
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.416893014
Short name T829
Test name
Test status
Simulation time 8406334292 ps
CPU time 7.73 seconds
Started Mar 19 12:56:23 PM PDT 24
Finished Mar 19 12:56:31 PM PDT 24
Peak memory 202852 kb
Host smart-aadf8777-f383-464e-9772-f28b7fb260a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41689
3014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.416893014
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3164394386
Short name T342
Test name
Test status
Simulation time 23478729 ps
CPU time 0.62 seconds
Started Mar 19 12:56:16 PM PDT 24
Finished Mar 19 12:56:17 PM PDT 24
Peak memory 202528 kb
Host smart-9835dec9-9551-4203-bdbd-ff8e401d0213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31643
94386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3164394386
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2097762488
Short name T721
Test name
Test status
Simulation time 8376938293 ps
CPU time 7.23 seconds
Started Mar 19 12:56:20 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 202836 kb
Host smart-03c450ef-dbde-4750-a31a-96c25656999c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20977
62488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2097762488
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3042809445
Short name T802
Test name
Test status
Simulation time 8404029007 ps
CPU time 7.29 seconds
Started Mar 19 12:56:20 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 203016 kb
Host smart-c0295ac5-86f3-4446-a4f0-9c2174bb4780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30428
09445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3042809445
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3360713608
Short name T732
Test name
Test status
Simulation time 8382794355 ps
CPU time 7.52 seconds
Started Mar 19 12:56:17 PM PDT 24
Finished Mar 19 12:56:25 PM PDT 24
Peak memory 203032 kb
Host smart-bef8a691-9d45-46d1-b2f8-1f1a6c524e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33607
13608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3360713608
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1555687875
Short name T365
Test name
Test status
Simulation time 8356079788 ps
CPU time 9.78 seconds
Started Mar 19 12:56:24 PM PDT 24
Finished Mar 19 12:56:34 PM PDT 24
Peak memory 202964 kb
Host smart-144c51a4-087d-4c6d-a80c-c5857d55aba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15556
87875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1555687875
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3090536296
Short name T163
Test name
Test status
Simulation time 8471362991 ps
CPU time 7.38 seconds
Started Mar 19 12:56:10 PM PDT 24
Finished Mar 19 12:56:18 PM PDT 24
Peak memory 202952 kb
Host smart-c42bc50c-91e7-49ed-ac44-962280cbd940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
36296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3090536296
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1633639548
Short name T665
Test name
Test status
Simulation time 8371550118 ps
CPU time 7.48 seconds
Started Mar 19 12:56:17 PM PDT 24
Finished Mar 19 12:56:25 PM PDT 24
Peak memory 203000 kb
Host smart-fd129031-f8bf-40c6-a124-afa1efb9d782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16336
39548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1633639548
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.3453881617
Short name T465
Test name
Test status
Simulation time 8368828436 ps
CPU time 7.21 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 202808 kb
Host smart-a22f9a73-f60d-4ecc-96d5-45bd9b7a5258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
81617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3453881617
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.169311156
Short name T726
Test name
Test status
Simulation time 142970226 ps
CPU time 1.63 seconds
Started Mar 19 12:56:29 PM PDT 24
Finished Mar 19 12:56:30 PM PDT 24
Peak memory 203044 kb
Host smart-2b35450d-19f9-4b0f-9dc8-3b9182baa05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16931
1156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.169311156
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.127651378
Short name T399
Test name
Test status
Simulation time 8358702419 ps
CPU time 7.34 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 202808 kb
Host smart-b3cf4b35-8dc5-4645-8f6c-c39d83ff8e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12765
1378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.127651378
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3880820906
Short name T842
Test name
Test status
Simulation time 8387467979 ps
CPU time 8.96 seconds
Started Mar 19 12:56:18 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 203004 kb
Host smart-b1139c3a-a30b-44cb-ba99-676d98e3449d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38808
20906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3880820906
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3910497755
Short name T609
Test name
Test status
Simulation time 8410003589 ps
CPU time 9.1 seconds
Started Mar 19 12:56:17 PM PDT 24
Finished Mar 19 12:56:26 PM PDT 24
Peak memory 203076 kb
Host smart-c3c38662-e87f-4eb3-bd58-4cff9cbbb2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39104
97755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3910497755
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.427670172
Short name T617
Test name
Test status
Simulation time 8368460154 ps
CPU time 8.02 seconds
Started Mar 19 12:56:20 PM PDT 24
Finished Mar 19 12:56:28 PM PDT 24
Peak memory 202984 kb
Host smart-e3fbcfe0-e322-455f-87b3-bcd10eb7ae4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42767
0172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.427670172
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3122079916
Short name T109
Test name
Test status
Simulation time 8414169926 ps
CPU time 7.12 seconds
Started Mar 19 12:56:21 PM PDT 24
Finished Mar 19 12:56:28 PM PDT 24
Peak memory 202928 kb
Host smart-72b312d8-b471-4b56-9a53-ce74742dae73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31220
79916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3122079916
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.366216316
Short name T221
Test name
Test status
Simulation time 8368971943 ps
CPU time 7.47 seconds
Started Mar 19 12:56:20 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 203004 kb
Host smart-7b1ca4e6-c4bc-477d-b6e0-407748eaf064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36621
6316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.366216316
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.613081835
Short name T405
Test name
Test status
Simulation time 8377080550 ps
CPU time 8.32 seconds
Started Mar 19 12:56:28 PM PDT 24
Finished Mar 19 12:56:37 PM PDT 24
Peak memory 202816 kb
Host smart-2ee2101f-0549-435d-9a15-7887a0ea3808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61308
1835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.613081835
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.968863248
Short name T539
Test name
Test status
Simulation time 23860980 ps
CPU time 0.65 seconds
Started Mar 19 12:56:23 PM PDT 24
Finished Mar 19 12:56:23 PM PDT 24
Peak memory 202576 kb
Host smart-26551269-abcf-4e17-bd44-fc0de242515d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96886
3248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.968863248
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2072071991
Short name T274
Test name
Test status
Simulation time 8408610851 ps
CPU time 8.31 seconds
Started Mar 19 12:56:23 PM PDT 24
Finished Mar 19 12:56:31 PM PDT 24
Peak memory 202804 kb
Host smart-1b4df8a3-afb4-4709-85b4-6574d4ec01fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20720
71991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2072071991
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.723575789
Short name T657
Test name
Test status
Simulation time 8382701000 ps
CPU time 7.32 seconds
Started Mar 19 12:56:23 PM PDT 24
Finished Mar 19 12:56:30 PM PDT 24
Peak memory 202992 kb
Host smart-2f8a8ba2-c9fd-4fbd-8ca9-1eacab9224ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72357
5789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.723575789
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1918527850
Short name T242
Test name
Test status
Simulation time 8405323551 ps
CPU time 7.55 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 202988 kb
Host smart-0001e7f3-f125-473e-93f5-198b46c2ca8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19185
27850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1918527850
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1693743606
Short name T358
Test name
Test status
Simulation time 8360845611 ps
CPU time 7.3 seconds
Started Mar 19 12:56:15 PM PDT 24
Finished Mar 19 12:56:23 PM PDT 24
Peak memory 203000 kb
Host smart-58ad2975-b2b5-43ab-b5d1-08eb4bddd1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16937
43606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1693743606
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1614456328
Short name T714
Test name
Test status
Simulation time 8481039411 ps
CPU time 8.22 seconds
Started Mar 19 12:56:18 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 203016 kb
Host smart-3e2344ec-27a1-40b1-9d04-312563388123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16144
56328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1614456328
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2301760930
Short name T640
Test name
Test status
Simulation time 8374814217 ps
CPU time 7.23 seconds
Started Mar 19 12:56:16 PM PDT 24
Finished Mar 19 12:56:24 PM PDT 24
Peak memory 203004 kb
Host smart-9d2e84fc-5837-42f6-97df-a461e010fb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23017
60930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2301760930
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.572033499
Short name T348
Test name
Test status
Simulation time 8366501489 ps
CPU time 7.19 seconds
Started Mar 19 12:56:18 PM PDT 24
Finished Mar 19 12:56:25 PM PDT 24
Peak memory 202836 kb
Host smart-2eb6da44-7ccf-4b62-b71c-1c87cf7052ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57203
3499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.572033499
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.402845203
Short name T735
Test name
Test status
Simulation time 46824686 ps
CPU time 1.37 seconds
Started Mar 19 12:56:17 PM PDT 24
Finished Mar 19 12:56:19 PM PDT 24
Peak memory 203144 kb
Host smart-d4246f36-8492-4c3f-869c-f0991905a7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40284
5203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.402845203
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3407393617
Short name T776
Test name
Test status
Simulation time 8355888603 ps
CPU time 7.29 seconds
Started Mar 19 12:56:20 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 202800 kb
Host smart-48b6c9fd-34e0-4baa-b2ff-05523b37beb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34073
93617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3407393617
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3653753976
Short name T794
Test name
Test status
Simulation time 8380676647 ps
CPU time 7.56 seconds
Started Mar 19 12:56:24 PM PDT 24
Finished Mar 19 12:56:31 PM PDT 24
Peak memory 203012 kb
Host smart-4f146b12-08da-4d97-9c9d-4447049d5a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36537
53976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3653753976
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2202950318
Short name T798
Test name
Test status
Simulation time 8403136713 ps
CPU time 7.41 seconds
Started Mar 19 12:56:21 PM PDT 24
Finished Mar 19 12:56:29 PM PDT 24
Peak memory 203012 kb
Host smart-6816393c-9bbe-4ea4-85d6-a732053179e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22029
50318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2202950318
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3863715804
Short name T528
Test name
Test status
Simulation time 8366765686 ps
CPU time 7.75 seconds
Started Mar 19 12:56:17 PM PDT 24
Finished Mar 19 12:56:25 PM PDT 24
Peak memory 203036 kb
Host smart-15a99615-d069-4d6a-a9a4-a02b0fba1e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38637
15804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3863715804
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2432527696
Short name T748
Test name
Test status
Simulation time 8415657456 ps
CPU time 7.98 seconds
Started Mar 19 12:56:21 PM PDT 24
Finished Mar 19 12:56:29 PM PDT 24
Peak memory 203064 kb
Host smart-46302981-5dbc-4275-be9c-cab9cc3915ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24325
27696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2432527696
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.4079858337
Short name T767
Test name
Test status
Simulation time 8398946177 ps
CPU time 9.55 seconds
Started Mar 19 12:56:20 PM PDT 24
Finished Mar 19 12:56:30 PM PDT 24
Peak memory 202872 kb
Host smart-7949a005-a177-4a05-830e-b3947bb86dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40798
58337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.4079858337
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1215827611
Short name T670
Test name
Test status
Simulation time 8402151752 ps
CPU time 7.19 seconds
Started Mar 19 12:56:28 PM PDT 24
Finished Mar 19 12:56:35 PM PDT 24
Peak memory 202968 kb
Host smart-b630d63a-3a61-45a0-ab83-ab5fbc24db28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12158
27611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1215827611
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.38481424
Short name T561
Test name
Test status
Simulation time 26976097 ps
CPU time 0.62 seconds
Started Mar 19 12:56:19 PM PDT 24
Finished Mar 19 12:56:20 PM PDT 24
Peak memory 202548 kb
Host smart-2216bd3d-4c38-4117-8d8e-3888a94c2bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38481
424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.38481424
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2439270003
Short name T460
Test name
Test status
Simulation time 8373044910 ps
CPU time 8.03 seconds
Started Mar 19 12:56:18 PM PDT 24
Finished Mar 19 12:56:26 PM PDT 24
Peak memory 202780 kb
Host smart-cacf8bed-a5d4-42b3-90e3-590ff5d08514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24392
70003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2439270003
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2839423970
Short name T493
Test name
Test status
Simulation time 8429273202 ps
CPU time 7.79 seconds
Started Mar 19 12:56:20 PM PDT 24
Finished Mar 19 12:56:28 PM PDT 24
Peak memory 203052 kb
Host smart-b6abcbb4-e21e-4fce-8bbd-d989899736f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28394
23970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2839423970
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3871240251
Short name T219
Test name
Test status
Simulation time 8382584446 ps
CPU time 7.75 seconds
Started Mar 19 12:56:18 PM PDT 24
Finished Mar 19 12:56:26 PM PDT 24
Peak memory 203016 kb
Host smart-3e55e72e-17ab-482a-829d-697fa0ad6e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
40251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3871240251
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3406790080
Short name T716
Test name
Test status
Simulation time 8355579541 ps
CPU time 7.7 seconds
Started Mar 19 12:56:25 PM PDT 24
Finished Mar 19 12:56:32 PM PDT 24
Peak memory 203004 kb
Host smart-d5351d47-5a18-4989-8a24-bf72f04048b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
90080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3406790080
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.406935576
Short name T162
Test name
Test status
Simulation time 8476766398 ps
CPU time 8.17 seconds
Started Mar 19 12:56:29 PM PDT 24
Finished Mar 19 12:56:37 PM PDT 24
Peak memory 202976 kb
Host smart-4d7ae70e-2b4a-42c5-b4f1-6dc376f02e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40693
5576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.406935576
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2916951306
Short name T510
Test name
Test status
Simulation time 8370430290 ps
CPU time 8.84 seconds
Started Mar 19 12:56:18 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 203052 kb
Host smart-1d47aa7f-fd62-45df-aa20-858046f224cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29169
51306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2916951306
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.2577949929
Short name T461
Test name
Test status
Simulation time 8368235081 ps
CPU time 7.11 seconds
Started Mar 19 12:56:20 PM PDT 24
Finished Mar 19 12:56:27 PM PDT 24
Peak memory 202824 kb
Host smart-6e8eab67-77fb-421c-9a68-4842e86bc203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
49929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2577949929
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1937481065
Short name T668
Test name
Test status
Simulation time 40045803 ps
CPU time 1.08 seconds
Started Mar 19 12:56:17 PM PDT 24
Finished Mar 19 12:56:19 PM PDT 24
Peak memory 203112 kb
Host smart-80f933db-f1e7-4ff4-8759-f3723497c1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19374
81065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1937481065
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3827034814
Short name T182
Test name
Test status
Simulation time 8359627245 ps
CPU time 7.99 seconds
Started Mar 19 12:56:27 PM PDT 24
Finished Mar 19 12:56:36 PM PDT 24
Peak memory 202768 kb
Host smart-3377b93d-5493-4d54-a0ab-0e71abc8b462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38270
34814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3827034814
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.749312953
Short name T669
Test name
Test status
Simulation time 8413303515 ps
CPU time 7.48 seconds
Started Mar 19 12:56:30 PM PDT 24
Finished Mar 19 12:56:38 PM PDT 24
Peak memory 202984 kb
Host smart-cf8128a9-d2fd-475f-a038-46f42edee969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74931
2953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.749312953
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2743080222
Short name T314
Test name
Test status
Simulation time 8405114917 ps
CPU time 9.63 seconds
Started Mar 19 12:56:26 PM PDT 24
Finished Mar 19 12:56:36 PM PDT 24
Peak memory 203020 kb
Host smart-aaad00de-b7a2-442b-9ed2-4e41387765c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27430
80222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2743080222
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1596398974
Short name T756
Test name
Test status
Simulation time 8359924455 ps
CPU time 7.23 seconds
Started Mar 19 12:56:29 PM PDT 24
Finished Mar 19 12:56:37 PM PDT 24
Peak memory 202980 kb
Host smart-0d8f54ab-a124-43bc-9932-4d53c3beffe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15963
98974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1596398974
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2943469521
Short name T830
Test name
Test status
Simulation time 8410004806 ps
CPU time 7.18 seconds
Started Mar 19 12:56:32 PM PDT 24
Finished Mar 19 12:56:40 PM PDT 24
Peak memory 203000 kb
Host smart-171191ec-96ab-48a1-9555-293fd4b2e28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
69521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2943469521
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3500984515
Short name T629
Test name
Test status
Simulation time 8397350254 ps
CPU time 7.86 seconds
Started Mar 19 12:56:28 PM PDT 24
Finished Mar 19 12:56:36 PM PDT 24
Peak memory 202920 kb
Host smart-f264eb9a-b049-44df-ae56-fecce02d600f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35009
84515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3500984515
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1579937933
Short name T503
Test name
Test status
Simulation time 8400150022 ps
CPU time 8.31 seconds
Started Mar 19 12:56:28 PM PDT 24
Finished Mar 19 12:56:36 PM PDT 24
Peak memory 202856 kb
Host smart-265851f3-b875-49ac-abb0-504f41b58a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15799
37933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1579937933
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.4239917424
Short name T26
Test name
Test status
Simulation time 30912907 ps
CPU time 0.67 seconds
Started Mar 19 12:56:27 PM PDT 24
Finished Mar 19 12:56:28 PM PDT 24
Peak memory 202644 kb
Host smart-f60fa027-fcbc-4c1c-99b0-d018c62c7fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42399
17424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4239917424
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1821018021
Short name T788
Test name
Test status
Simulation time 8370982669 ps
CPU time 8.35 seconds
Started Mar 19 12:56:25 PM PDT 24
Finished Mar 19 12:56:33 PM PDT 24
Peak memory 202792 kb
Host smart-46184af2-e4a7-4d98-8e01-f277062a25b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18210
18021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1821018021
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.3685110338
Short name T819
Test name
Test status
Simulation time 8408279022 ps
CPU time 8.01 seconds
Started Mar 19 12:56:27 PM PDT 24
Finished Mar 19 12:56:35 PM PDT 24
Peak memory 203012 kb
Host smart-5d12d3f3-0fb4-4552-b06c-0af8dfe39aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36851
10338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.3685110338
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.249432326
Short name T479
Test name
Test status
Simulation time 8383152337 ps
CPU time 7.33 seconds
Started Mar 19 12:56:33 PM PDT 24
Finished Mar 19 12:56:41 PM PDT 24
Peak memory 202968 kb
Host smart-9a7e24cb-b683-4692-a5b0-069b8e222b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24943
2326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.249432326
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.4174032798
Short name T447
Test name
Test status
Simulation time 8358277230 ps
CPU time 7.89 seconds
Started Mar 19 12:56:28 PM PDT 24
Finished Mar 19 12:56:36 PM PDT 24
Peak memory 202876 kb
Host smart-e92cad57-dd94-4d62-96e8-6bd1b396a003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41740
32798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.4174032798
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3913369919
Short name T452
Test name
Test status
Simulation time 8476657082 ps
CPU time 7.83 seconds
Started Mar 19 12:56:16 PM PDT 24
Finished Mar 19 12:56:25 PM PDT 24
Peak memory 202988 kb
Host smart-d72b6c78-ff26-4674-986c-9569def08630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39133
69919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3913369919
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2210247582
Short name T441
Test name
Test status
Simulation time 8372439225 ps
CPU time 9.34 seconds
Started Mar 19 12:54:08 PM PDT 24
Finished Mar 19 12:54:18 PM PDT 24
Peak memory 203008 kb
Host smart-17c3b45f-9c18-4c26-a841-331d8738881c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22102
47582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2210247582
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.4253794813
Short name T630
Test name
Test status
Simulation time 8372870890 ps
CPU time 8.3 seconds
Started Mar 19 12:54:11 PM PDT 24
Finished Mar 19 12:54:20 PM PDT 24
Peak memory 202808 kb
Host smart-7e826387-a528-4e3a-a53e-29d27e1daeb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42537
94813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.4253794813
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1184488358
Short name T815
Test name
Test status
Simulation time 138890614 ps
CPU time 1.66 seconds
Started Mar 19 12:54:09 PM PDT 24
Finished Mar 19 12:54:11 PM PDT 24
Peak memory 202840 kb
Host smart-492c0112-cbe9-45e5-90cd-1d0bf2972f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11844
88358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1184488358
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.4269861124
Short name T755
Test name
Test status
Simulation time 8362105105 ps
CPU time 7.39 seconds
Started Mar 19 12:54:11 PM PDT 24
Finished Mar 19 12:54:19 PM PDT 24
Peak memory 202836 kb
Host smart-18aaf2cf-6974-4751-830c-5c2a092853e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42698
61124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.4269861124
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2534680708
Short name T514
Test name
Test status
Simulation time 8430974441 ps
CPU time 7.35 seconds
Started Mar 19 12:54:07 PM PDT 24
Finished Mar 19 12:54:15 PM PDT 24
Peak memory 202984 kb
Host smart-922b2b41-dc01-48e4-ae5d-002704680f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25346
80708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2534680708
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.684996046
Short name T651
Test name
Test status
Simulation time 8405586062 ps
CPU time 8.1 seconds
Started Mar 19 12:54:09 PM PDT 24
Finished Mar 19 12:54:17 PM PDT 24
Peak memory 203000 kb
Host smart-e54c3445-1999-4b39-82ae-157929847388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68499
6046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.684996046
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3165019298
Short name T563
Test name
Test status
Simulation time 8363539039 ps
CPU time 7.59 seconds
Started Mar 19 12:54:11 PM PDT 24
Finished Mar 19 12:54:20 PM PDT 24
Peak memory 203012 kb
Host smart-7b17a85d-fbec-4bde-b801-07aa87e13ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31650
19298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3165019298
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1942053577
Short name T106
Test name
Test status
Simulation time 8426669409 ps
CPU time 7.62 seconds
Started Mar 19 12:54:10 PM PDT 24
Finished Mar 19 12:54:18 PM PDT 24
Peak memory 202980 kb
Host smart-801b06a0-cf84-4b04-84be-981351b9f962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
53577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1942053577
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3677683897
Short name T459
Test name
Test status
Simulation time 8392801216 ps
CPU time 7.45 seconds
Started Mar 19 12:54:09 PM PDT 24
Finished Mar 19 12:54:17 PM PDT 24
Peak memory 203004 kb
Host smart-4c1fbc43-0f18-4a64-96cb-092f8f1e3e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36776
83897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3677683897
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.824690059
Short name T340
Test name
Test status
Simulation time 21853250 ps
CPU time 0.67 seconds
Started Mar 19 12:54:08 PM PDT 24
Finished Mar 19 12:54:10 PM PDT 24
Peak memory 202512 kb
Host smart-d0ae61f8-4b20-48b5-8b4a-9319a7b736e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82469
0059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.824690059
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3654058460
Short name T833
Test name
Test status
Simulation time 8380897207 ps
CPU time 9.16 seconds
Started Mar 19 12:54:11 PM PDT 24
Finished Mar 19 12:54:20 PM PDT 24
Peak memory 202836 kb
Host smart-72af85fd-f7cb-491f-bf1b-3e122df859b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36540
58460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3654058460
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.691839160
Short name T810
Test name
Test status
Simulation time 8412720071 ps
CPU time 8.33 seconds
Started Mar 19 12:54:09 PM PDT 24
Finished Mar 19 12:54:18 PM PDT 24
Peak memory 203080 kb
Host smart-cae38d60-0d16-4a93-b643-8c6db77bbc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69183
9160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.691839160
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.3401325013
Short name T488
Test name
Test status
Simulation time 8397647993 ps
CPU time 7.7 seconds
Started Mar 19 12:54:10 PM PDT 24
Finished Mar 19 12:54:18 PM PDT 24
Peak memory 203028 kb
Host smart-1c72f4ac-e1a9-445a-a93e-decf1b53595f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34013
25013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.3401325013
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.893524165
Short name T316
Test name
Test status
Simulation time 8360582129 ps
CPU time 9.5 seconds
Started Mar 19 12:54:08 PM PDT 24
Finished Mar 19 12:54:19 PM PDT 24
Peak memory 203024 kb
Host smart-e3efee97-2a49-4891-beac-f1e27203c734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89352
4165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.893524165
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3314793526
Short name T509
Test name
Test status
Simulation time 8368238111 ps
CPU time 7.77 seconds
Started Mar 19 12:54:17 PM PDT 24
Finished Mar 19 12:54:26 PM PDT 24
Peak memory 203040 kb
Host smart-31a4b51a-93e2-4352-a454-8522acb24f5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33147
93526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3314793526
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.2767217668
Short name T484
Test name
Test status
Simulation time 8371362567 ps
CPU time 7.01 seconds
Started Mar 19 12:54:17 PM PDT 24
Finished Mar 19 12:54:25 PM PDT 24
Peak memory 202776 kb
Host smart-439df47a-907e-464e-b4a0-1659a65147f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672
17668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2767217668
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1460105181
Short name T582
Test name
Test status
Simulation time 136060375 ps
CPU time 1.28 seconds
Started Mar 19 12:54:17 PM PDT 24
Finished Mar 19 12:54:20 PM PDT 24
Peak memory 202940 kb
Host smart-a7a530f6-2272-47ef-be37-83eb192affa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14601
05181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1460105181
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3639301530
Short name T186
Test name
Test status
Simulation time 8359695256 ps
CPU time 7.4 seconds
Started Mar 19 12:54:16 PM PDT 24
Finished Mar 19 12:54:23 PM PDT 24
Peak memory 202820 kb
Host smart-787b9422-fb2c-43bd-a973-f9c9930bf923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36393
01530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3639301530
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.336122114
Short name T760
Test name
Test status
Simulation time 8459322851 ps
CPU time 7.29 seconds
Started Mar 19 12:54:16 PM PDT 24
Finished Mar 19 12:54:23 PM PDT 24
Peak memory 202984 kb
Host smart-2402a9b3-774b-42e7-af20-eb3c5d3173c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33612
2114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.336122114
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3357476963
Short name T407
Test name
Test status
Simulation time 8410939203 ps
CPU time 7.53 seconds
Started Mar 19 12:54:16 PM PDT 24
Finished Mar 19 12:54:24 PM PDT 24
Peak memory 203104 kb
Host smart-516661c0-cec9-4798-a59e-06229ae818de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33574
76963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3357476963
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.783716013
Short name T712
Test name
Test status
Simulation time 8360861420 ps
CPU time 7.54 seconds
Started Mar 19 12:54:15 PM PDT 24
Finished Mar 19 12:54:23 PM PDT 24
Peak memory 203000 kb
Host smart-bd5c12a2-ba59-404a-9ec4-1e9fadb90e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78371
6013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.783716013
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3810156334
Short name T112
Test name
Test status
Simulation time 8415006140 ps
CPU time 7.76 seconds
Started Mar 19 12:54:18 PM PDT 24
Finished Mar 19 12:54:26 PM PDT 24
Peak memory 202944 kb
Host smart-51dfff12-1ab9-45bf-ac93-213fa7f026e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38101
56334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3810156334
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1907040436
Short name T236
Test name
Test status
Simulation time 8401791130 ps
CPU time 7.43 seconds
Started Mar 19 12:54:17 PM PDT 24
Finished Mar 19 12:54:26 PM PDT 24
Peak memory 202984 kb
Host smart-3f81c51b-2086-437d-8fa0-1911a5ed51b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19070
40436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1907040436
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4292862416
Short name T319
Test name
Test status
Simulation time 8406216348 ps
CPU time 7.43 seconds
Started Mar 19 12:54:17 PM PDT 24
Finished Mar 19 12:54:26 PM PDT 24
Peak memory 202912 kb
Host smart-f6af8913-4b04-40a5-8b4e-7877c65ca882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42928
62416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4292862416
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2854664305
Short name T779
Test name
Test status
Simulation time 30596654 ps
CPU time 0.63 seconds
Started Mar 19 12:54:16 PM PDT 24
Finished Mar 19 12:54:17 PM PDT 24
Peak memory 202516 kb
Host smart-b6ebb8fb-adea-4c15-b644-714fbb280759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28546
64305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2854664305
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.710110490
Short name T454
Test name
Test status
Simulation time 8398594743 ps
CPU time 7.21 seconds
Started Mar 19 12:54:19 PM PDT 24
Finished Mar 19 12:54:26 PM PDT 24
Peak memory 202740 kb
Host smart-8c892995-8141-4904-af17-e26cd1dd1074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71011
0490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.710110490
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3370131836
Short name T567
Test name
Test status
Simulation time 8430062185 ps
CPU time 8.8 seconds
Started Mar 19 12:54:17 PM PDT 24
Finished Mar 19 12:54:27 PM PDT 24
Peak memory 203076 kb
Host smart-d4c6ffff-3434-4b8d-a063-d75f6dc8f458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33701
31836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3370131836
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2792404753
Short name T601
Test name
Test status
Simulation time 8370528528 ps
CPU time 9.63 seconds
Started Mar 19 12:54:18 PM PDT 24
Finished Mar 19 12:54:28 PM PDT 24
Peak memory 202972 kb
Host smart-23ba95cf-97e4-4b80-a6ed-9fac11d66def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27924
04753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2792404753
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.922707948
Short name T605
Test name
Test status
Simulation time 8360520865 ps
CPU time 7.49 seconds
Started Mar 19 12:54:17 PM PDT 24
Finished Mar 19 12:54:26 PM PDT 24
Peak memory 202864 kb
Host smart-146b4a8b-24e1-45bb-8007-a5e105dd9559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92270
7948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.922707948
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1463314312
Short name T737
Test name
Test status
Simulation time 8472603133 ps
CPU time 7.56 seconds
Started Mar 19 12:54:17 PM PDT 24
Finished Mar 19 12:54:26 PM PDT 24
Peak memory 203016 kb
Host smart-74694acd-90a9-45e4-be05-3d964423e427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14633
14312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1463314312
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.974763895
Short name T710
Test name
Test status
Simulation time 8368515791 ps
CPU time 7.45 seconds
Started Mar 19 12:54:26 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 203076 kb
Host smart-2d624f20-19ab-4b61-83a1-43673ff849d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97476
3895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.974763895
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.1901732161
Short name T422
Test name
Test status
Simulation time 8367361688 ps
CPU time 7.37 seconds
Started Mar 19 12:54:22 PM PDT 24
Finished Mar 19 12:54:30 PM PDT 24
Peak memory 202872 kb
Host smart-dba10768-fb89-48d1-8d99-69bb9a390abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
32161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1901732161
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2788554264
Short name T556
Test name
Test status
Simulation time 160414470 ps
CPU time 1.49 seconds
Started Mar 19 12:54:23 PM PDT 24
Finished Mar 19 12:54:25 PM PDT 24
Peak memory 203104 kb
Host smart-3e78bc5e-1c64-4003-953f-9d25eba9bc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
54264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2788554264
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.148663221
Short name T181
Test name
Test status
Simulation time 8358957634 ps
CPU time 7.47 seconds
Started Mar 19 12:54:23 PM PDT 24
Finished Mar 19 12:54:32 PM PDT 24
Peak memory 202804 kb
Host smart-576e7281-f25b-4295-bf27-1c4477fc014f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14866
3221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.148663221
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2451390957
Short name T513
Test name
Test status
Simulation time 8400500571 ps
CPU time 7.36 seconds
Started Mar 19 12:54:24 PM PDT 24
Finished Mar 19 12:54:32 PM PDT 24
Peak memory 203028 kb
Host smart-177926e8-326c-470d-aaf9-bcbc4ae87ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513
90957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2451390957
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3630606020
Short name T496
Test name
Test status
Simulation time 8409337775 ps
CPU time 9.36 seconds
Started Mar 19 12:54:23 PM PDT 24
Finished Mar 19 12:54:33 PM PDT 24
Peak memory 203052 kb
Host smart-44559e41-3fa4-4435-aa93-92dc041dc847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36306
06020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3630606020
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3695694832
Short name T831
Test name
Test status
Simulation time 8368059190 ps
CPU time 7.78 seconds
Started Mar 19 12:54:26 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 203032 kb
Host smart-35cc738b-e688-4939-8c0b-8e751ba6add9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36956
94832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3695694832
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1206522429
Short name T98
Test name
Test status
Simulation time 8447369500 ps
CPU time 7.8 seconds
Started Mar 19 12:54:25 PM PDT 24
Finished Mar 19 12:54:33 PM PDT 24
Peak memory 202988 kb
Host smart-f50bf06f-488f-471e-8318-47783b10af2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12065
22429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1206522429
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2318866561
Short name T375
Test name
Test status
Simulation time 8375277597 ps
CPU time 8.14 seconds
Started Mar 19 12:54:27 PM PDT 24
Finished Mar 19 12:54:35 PM PDT 24
Peak memory 202856 kb
Host smart-ea0f79f7-52e2-4e2a-9307-4c48312ed81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23188
66561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2318866561
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1045896443
Short name T298
Test name
Test status
Simulation time 8402527400 ps
CPU time 7.98 seconds
Started Mar 19 12:54:25 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 202912 kb
Host smart-21b60f79-b751-401f-897a-b641e990000a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
96443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1045896443
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3182557401
Short name T621
Test name
Test status
Simulation time 31218852 ps
CPU time 0.64 seconds
Started Mar 19 12:54:27 PM PDT 24
Finished Mar 19 12:54:28 PM PDT 24
Peak memory 202548 kb
Host smart-76c7607e-49e0-453b-9cdc-a89fb5a82951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31825
57401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3182557401
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.405137384
Short name T758
Test name
Test status
Simulation time 8385904799 ps
CPU time 7.21 seconds
Started Mar 19 12:54:23 PM PDT 24
Finished Mar 19 12:54:32 PM PDT 24
Peak memory 202840 kb
Host smart-0ab3460e-ebae-44e0-8bad-ae4ad53a8b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40513
7384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.405137384
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.254325067
Short name T504
Test name
Test status
Simulation time 8416245421 ps
CPU time 7.75 seconds
Started Mar 19 12:54:29 PM PDT 24
Finished Mar 19 12:54:38 PM PDT 24
Peak memory 202988 kb
Host smart-040fee18-2225-4aa0-a9a0-f9cebf8f02d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25432
5067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.254325067
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1408751030
Short name T769
Test name
Test status
Simulation time 8399105253 ps
CPU time 9.48 seconds
Started Mar 19 12:54:28 PM PDT 24
Finished Mar 19 12:54:38 PM PDT 24
Peak memory 202996 kb
Host smart-c66c6176-36aa-44b0-af67-5cedf956f60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
51030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1408751030
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.597014385
Short name T397
Test name
Test status
Simulation time 8358391646 ps
CPU time 8.52 seconds
Started Mar 19 12:54:24 PM PDT 24
Finished Mar 19 12:54:33 PM PDT 24
Peak memory 202992 kb
Host smart-d8849412-3b2b-42d9-96aa-d487ee86723b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59701
4385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.597014385
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.1813306767
Short name T159
Test name
Test status
Simulation time 8480486926 ps
CPU time 7.82 seconds
Started Mar 19 12:54:26 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 203036 kb
Host smart-e17485e6-ef14-4130-b4b5-29061c273851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18133
06767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1813306767
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1570605767
Short name T389
Test name
Test status
Simulation time 8369557136 ps
CPU time 7.3 seconds
Started Mar 19 12:54:26 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 202996 kb
Host smart-e9a6c10a-082f-419f-8d6f-0d571a306072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15706
05767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1570605767
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.3342643938
Short name T271
Test name
Test status
Simulation time 8365449546 ps
CPU time 9.45 seconds
Started Mar 19 12:54:24 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 202800 kb
Host smart-4519432b-61bc-4e82-a2f1-f6296d3a1522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33426
43938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3342643938
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2511792636
Short name T439
Test name
Test status
Simulation time 70280207 ps
CPU time 1.89 seconds
Started Mar 19 12:54:24 PM PDT 24
Finished Mar 19 12:54:26 PM PDT 24
Peak memory 202784 kb
Host smart-0436ad3a-8464-473b-bcc0-b648b00c134c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25117
92636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2511792636
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1580098530
Short name T21
Test name
Test status
Simulation time 8362246206 ps
CPU time 7.69 seconds
Started Mar 19 12:54:32 PM PDT 24
Finished Mar 19 12:54:40 PM PDT 24
Peak memory 202812 kb
Host smart-d5f93ba0-5dfd-4e48-87a2-af326fc83f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15800
98530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1580098530
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.4058903356
Short name T533
Test name
Test status
Simulation time 8406649891 ps
CPU time 7.24 seconds
Started Mar 19 12:54:27 PM PDT 24
Finished Mar 19 12:54:35 PM PDT 24
Peak memory 203008 kb
Host smart-d478d9c1-8b45-41f3-999b-8980a98b80dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40589
03356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.4058903356
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1434567156
Short name T51
Test name
Test status
Simulation time 8363223112 ps
CPU time 7.3 seconds
Started Mar 19 12:54:27 PM PDT 24
Finished Mar 19 12:54:35 PM PDT 24
Peak memory 203072 kb
Host smart-794e23a5-8d09-4604-8b82-c70dd0c72d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14345
67156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1434567156
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.532272364
Short name T119
Test name
Test status
Simulation time 8413999452 ps
CPU time 8.08 seconds
Started Mar 19 12:54:23 PM PDT 24
Finished Mar 19 12:54:31 PM PDT 24
Peak memory 203008 kb
Host smart-b2703b52-4308-46f5-a86c-fb08a5ccab9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53227
2364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.532272364
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2884015101
Short name T532
Test name
Test status
Simulation time 8406641560 ps
CPU time 7.43 seconds
Started Mar 19 12:54:25 PM PDT 24
Finished Mar 19 12:54:33 PM PDT 24
Peak memory 202932 kb
Host smart-fc00f94f-b1a1-46a0-9eed-bf3876daef53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28840
15101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2884015101
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.496338502
Short name T770
Test name
Test status
Simulation time 8369039286 ps
CPU time 8.1 seconds
Started Mar 19 12:54:25 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 203028 kb
Host smart-6671905a-1587-495f-b430-e33743db7bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49633
8502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.496338502
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3527320814
Short name T31
Test name
Test status
Simulation time 26139981 ps
CPU time 0.61 seconds
Started Mar 19 12:54:24 PM PDT 24
Finished Mar 19 12:54:25 PM PDT 24
Peak memory 202512 kb
Host smart-621d5e87-039e-4fd6-a424-b85c2cd9e614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35273
20814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3527320814
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3989144791
Short name T285
Test name
Test status
Simulation time 8372085549 ps
CPU time 7.55 seconds
Started Mar 19 12:54:25 PM PDT 24
Finished Mar 19 12:54:34 PM PDT 24
Peak memory 202940 kb
Host smart-5823a6dc-49ca-4ce7-8978-321bcd0d3c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39891
44791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3989144791
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3030530003
Short name T598
Test name
Test status
Simulation time 8397923696 ps
CPU time 7.77 seconds
Started Mar 19 12:54:23 PM PDT 24
Finished Mar 19 12:54:32 PM PDT 24
Peak memory 203016 kb
Host smart-e8a62d90-0f45-4736-be9c-1fd3d462426b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30305
30003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3030530003
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.698745122
Short name T691
Test name
Test status
Simulation time 8381430140 ps
CPU time 8.02 seconds
Started Mar 19 12:54:29 PM PDT 24
Finished Mar 19 12:54:38 PM PDT 24
Peak memory 203004 kb
Host smart-7fd2ef06-7014-43b9-97a0-a38d994ca993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69874
5122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.698745122
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.3936752928
Short name T12
Test name
Test status
Simulation time 8362304496 ps
CPU time 8.66 seconds
Started Mar 19 12:54:23 PM PDT 24
Finished Mar 19 12:54:33 PM PDT 24
Peak memory 202916 kb
Host smart-542fb595-45be-4016-abff-557514983fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39367
52928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.3936752928
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.4063477709
Short name T750
Test name
Test status
Simulation time 8471942986 ps
CPU time 7.35 seconds
Started Mar 19 12:54:24 PM PDT 24
Finished Mar 19 12:54:32 PM PDT 24
Peak memory 202980 kb
Host smart-45d4ebd8-c2ba-4a37-9c16-f815345aed5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40634
77709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.4063477709
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.3965670085
Short name T639
Test name
Test status
Simulation time 8368400493 ps
CPU time 8.05 seconds
Started Mar 19 12:54:31 PM PDT 24
Finished Mar 19 12:54:40 PM PDT 24
Peak memory 202996 kb
Host smart-af0289a0-ae57-474b-9a15-98d7f0cb4fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39656
70085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3965670085
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.3342699967
Short name T438
Test name
Test status
Simulation time 8372348724 ps
CPU time 7.67 seconds
Started Mar 19 12:54:30 PM PDT 24
Finished Mar 19 12:54:38 PM PDT 24
Peak memory 202840 kb
Host smart-4968f2ce-1a6c-4180-a9c4-320eba4c8ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33426
99967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3342699967
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.322118627
Short name T216
Test name
Test status
Simulation time 82181427 ps
CPU time 1.01 seconds
Started Mar 19 12:54:30 PM PDT 24
Finished Mar 19 12:54:32 PM PDT 24
Peak memory 203112 kb
Host smart-c7a3e724-a2a3-4955-b12d-30da19cfc429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32211
8627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.322118627
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.922820557
Short name T623
Test name
Test status
Simulation time 8365911770 ps
CPU time 7.55 seconds
Started Mar 19 12:54:29 PM PDT 24
Finished Mar 19 12:54:37 PM PDT 24
Peak memory 202836 kb
Host smart-235784df-baf0-45a7-9a82-75ecbe5e3a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92282
0557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.922820557
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.692550125
Short name T434
Test name
Test status
Simulation time 8455674121 ps
CPU time 7.57 seconds
Started Mar 19 12:54:32 PM PDT 24
Finished Mar 19 12:54:40 PM PDT 24
Peak memory 203056 kb
Host smart-c63e6587-52c0-4301-be91-70f3380a7466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69255
0125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.692550125
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3674014390
Short name T799
Test name
Test status
Simulation time 8409813340 ps
CPU time 7.66 seconds
Started Mar 19 12:54:33 PM PDT 24
Finished Mar 19 12:54:41 PM PDT 24
Peak memory 202980 kb
Host smart-98859d3e-15e3-4276-a2b9-c9ffee172817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
14390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3674014390
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.4028616966
Short name T613
Test name
Test status
Simulation time 8363476698 ps
CPU time 10 seconds
Started Mar 19 12:54:32 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 202992 kb
Host smart-d3887292-6aad-4e6e-82cd-bade2294a905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40286
16966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4028616966
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1279166026
Short name T95
Test name
Test status
Simulation time 8430348645 ps
CPU time 7.42 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:41 PM PDT 24
Peak memory 203044 kb
Host smart-a54712fb-01e1-4f23-b8db-7d8b5595c9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12791
66026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1279166026
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1963484663
Short name T660
Test name
Test status
Simulation time 8379955991 ps
CPU time 7.5 seconds
Started Mar 19 12:54:31 PM PDT 24
Finished Mar 19 12:54:38 PM PDT 24
Peak memory 202884 kb
Host smart-3c5fca4f-7eeb-4a05-af82-df2c938be8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19634
84663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1963484663
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2659537218
Short name T466
Test name
Test status
Simulation time 8402353011 ps
CPU time 7.2 seconds
Started Mar 19 12:54:31 PM PDT 24
Finished Mar 19 12:54:39 PM PDT 24
Peak memory 202868 kb
Host smart-d5c0af61-d2fb-4d3e-b13c-b098d2cc1098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26595
37218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2659537218
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.741887215
Short name T745
Test name
Test status
Simulation time 8393398781 ps
CPU time 8.18 seconds
Started Mar 19 12:54:31 PM PDT 24
Finished Mar 19 12:54:40 PM PDT 24
Peak memory 202808 kb
Host smart-053f0549-a605-4a86-890f-e120be4c433b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74188
7215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.741887215
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2316567497
Short name T148
Test name
Test status
Simulation time 8428090143 ps
CPU time 10.29 seconds
Started Mar 19 12:54:32 PM PDT 24
Finished Mar 19 12:54:43 PM PDT 24
Peak memory 202984 kb
Host smart-080ded74-2df4-4e5d-935c-19a25e5298c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23165
67497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2316567497
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1272422402
Short name T848
Test name
Test status
Simulation time 8361127933 ps
CPU time 7.54 seconds
Started Mar 19 12:54:33 PM PDT 24
Finished Mar 19 12:54:41 PM PDT 24
Peak memory 202980 kb
Host smart-886946db-7040-4825-9763-f7c9be7dac94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12724
22402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1272422402
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3094408423
Short name T244
Test name
Test status
Simulation time 8357344664 ps
CPU time 7.38 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 203068 kb
Host smart-31f4711d-12b0-4411-b1a6-78984364f26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944
08423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3094408423
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1023435956
Short name T15
Test name
Test status
Simulation time 8476770661 ps
CPU time 7.72 seconds
Started Mar 19 12:54:34 PM PDT 24
Finished Mar 19 12:54:42 PM PDT 24
Peak memory 203048 kb
Host smart-b42253e6-270e-4249-aaae-1bdee15bb585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10234
35956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1023435956
Directory /workspace/9.usbdev_smoke/latest
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