Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2895	1		T1	4		T2	2		T3	2
all_values[1]	2895	1		T1	4		T2	2		T3	2
all_values[2]	2895	1		T1	4		T2	2		T3	2
all_values[3]	2895	1		T1	4		T2	2		T3	2
all_values[4]	2895	1		T1	4		T2	2		T3	2
all_values[5]	2895	1		T1	4		T2	2		T3	2
all_values[6]	2895	1		T1	4		T2	2		T3	2
all_values[7]	2895	1		T1	4		T2	2		T3	2
all_values[8]	2895	1		T1	4		T2	2		T3	2
all_values[9]	2895	1		T1	4		T2	2		T3	2
all_values[10]	2895	1		T1	4		T2	2		T3	2
all_values[11]	2895	1		T1	4		T2	2		T3	2
all_values[12]	2895	1		T1	4		T2	2		T3	2
all_values[13]	2895	1		T1	4		T2	2		T3	2
all_values[14]	2895	1		T1	4		T2	2		T3	2
all_values[15]	2895	1		T1	4		T2	2		T3	2
all_values[16]	2895	1		T1	4		T2	2		T3	2
all_values[17]	2895	1		T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	50038	1		T1	68		T2	36		T3	36
auto[1]	2072	1		T1	4		T6	4		T11	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	50177	1		T1	72		T2	36		T3	36
auto[1]	1933	1		T58	58		T59	71		T60	128

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2131	1		T2	2		T3	2		T4	4
all_values[0]	auto[0]	auto[1]	55	1		T59	3		T60	3		T62	1
all_values[0]	auto[1]	auto[0]	664	1		T1	4		T6	4		T11	2
all_values[0]	auto[1]	auto[1]	45	1		T59	1		T61	3		T62	4
all_values[1]	auto[0]	auto[0]	2523	1		T1	4		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	57	1		T59	3		T60	4		T62	3
all_values[1]	auto[1]	auto[0]	266	1		T12	2		T23	3		T24	3
all_values[1]	auto[1]	auto[1]	49	1		T58	3		T59	2		T60	4
all_values[2]	auto[0]	auto[0]	2774	1		T1	4		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	52	1		T59	3		T60	1		T61	3
all_values[2]	auto[1]	auto[0]	8	1		T58	1		T59	1		T60	1
all_values[2]	auto[1]	auto[1]	61	1		T58	4		T59	1		T60	5
all_values[3]	auto[0]	auto[0]	2776	1		T1	4		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	60	1		T59	5		T60	4		T61	3
all_values[3]	auto[1]	auto[0]	14	1		T58	1		T61	2		T243	4
all_values[3]	auto[1]	auto[1]	45	1		T58	4		T60	4		T62	1
all_values[4]	auto[0]	auto[0]	2770	1		T1	4		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	60	1		T58	3		T60	7		T62	2
all_values[4]	auto[1]	auto[0]	3	1		T58	1		T245	1		T246	1
all_values[4]	auto[1]	auto[1]	62	1		T58	1		T59	5		T60	1
all_values[5]	auto[0]	auto[0]	2772	1		T1	4		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	68	1		T58	4		T59	4		T60	5
all_values[5]	auto[1]	auto[0]	15	1		T60	1		T61	1		T63	1
all_values[5]	auto[1]	auto[1]	40	1		T58	1		T59	1		T60	2
all_values[6]	auto[0]	auto[0]	2777	1		T1	4		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	61	1		T58	3		T59	3		T60	5
all_values[6]	auto[1]	auto[0]	13	1		T58	1		T61	4		T63	1
all_values[6]	auto[1]	auto[1]	44	1		T58	1		T59	2		T60	3
all_values[7]	auto[0]	auto[0]	2773	1		T1	4		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	59	1		T58	4		T59	1		T60	3
all_values[7]	auto[1]	auto[0]	6	1		T60	2		T61	1		T247	1
all_values[7]	auto[1]	auto[1]	57	1		T58	1		T59	4		T60	1
all_values[8]	auto[0]	auto[0]	2776	1		T1	4		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	39	1		T58	1		T60	4		T62	4
all_values[8]	auto[1]	auto[0]	12	1		T63	5		T248	1		T249	1
all_values[8]	auto[1]	auto[1]	68	1		T58	3		T59	4		T60	4
all_values[9]	auto[0]	auto[0]	2778	1		T1	4		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	48	1		T58	2		T60	5		T61	5
all_values[9]	auto[1]	auto[0]	12	1		T59	1		T63	1		T245	1
all_values[9]	auto[1]	auto[1]	57	1		T58	3		T59	3		T60	3
all_values[10]	auto[0]	auto[0]	2781	1		T1	4		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	41	1		T58	1		T59	1		T60	1
all_values[10]	auto[1]	auto[0]	12	1		T58	1		T62	1		T63	1
all_values[10]	auto[1]	auto[1]	61	1		T58	3		T59	4		T60	7
all_values[11]	auto[0]	auto[0]	2783	1		T1	4		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	54	1		T58	3		T60	6		T61	2
all_values[11]	auto[1]	auto[0]	7	1		T58	2		T250	1		T249	2
all_values[11]	auto[1]	auto[1]	51	1		T60	2		T61	3		T62	4
all_values[12]	auto[0]	auto[0]	2782	1		T1	4		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	40	1		T59	3		T60	1		T63	4
all_values[12]	auto[1]	auto[0]	14	1		T58	3		T60	1		T62	1
all_values[12]	auto[1]	auto[1]	59	1		T59	1		T60	5		T62	3
all_values[13]	auto[0]	auto[0]	2779	1		T1	4		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	50	1		T59	1		T60	4		T61	1
all_values[13]	auto[1]	auto[0]	21	1		T58	5		T60	1		T62	5
all_values[13]	auto[1]	auto[1]	45	1		T59	4		T60	2		T61	3
all_values[14]	auto[0]	auto[0]	2776	1		T1	4		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	50	1		T59	3		T60	1		T61	5
all_values[14]	auto[1]	auto[0]	8	1		T58	1		T59	1		T243	1
all_values[14]	auto[1]	auto[1]	61	1		T58	3		T60	7		T62	5
all_values[15]	auto[0]	auto[0]	2767	1		T1	4		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	55	1		T58	1		T59	2		T60	6
all_values[15]	auto[1]	auto[0]	7	1		T63	4		T243	1		T251	2
all_values[15]	auto[1]	auto[1]	66	1		T58	4		T59	3		T60	2
all_values[16]	auto[0]	auto[0]	2781	1		T1	4		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	58	1		T60	6		T61	4		T62	3
all_values[16]	auto[1]	auto[0]	14	1		T58	1		T62	1		T245	1
all_values[16]	auto[1]	auto[1]	42	1		T59	4		T60	2		T61	1
all_values[17]	auto[0]	auto[0]	2777	1		T1	4		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	55	1		T58	3		T60	1		T61	3
all_values[17]	auto[1]	auto[0]	5	1		T62	1		T249	1		T246	1
all_values[17]	auto[1]	auto[1]	58	1		T58	2		T60	7		T61	2