Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2895	1		T1	4		T2	2		T3	2
all_pins[1]	2895	1		T1	4		T2	2		T3	2
all_pins[2]	2895	1		T1	4		T2	2		T3	2
all_pins[3]	2895	1		T1	4		T2	2		T3	2
all_pins[4]	2895	1		T1	4		T2	2		T3	2
all_pins[5]	2895	1		T1	4		T2	2		T3	2
all_pins[6]	2895	1		T1	4		T2	2		T3	2
all_pins[7]	2895	1		T1	4		T2	2		T3	2
all_pins[8]	2895	1		T1	4		T2	2		T3	2
all_pins[9]	2895	1		T1	4		T2	2		T3	2
all_pins[10]	2895	1		T1	4		T2	2		T3	2
all_pins[11]	2895	1		T1	4		T2	2		T3	2
all_pins[12]	2895	1		T1	4		T2	2		T3	2
all_pins[13]	2895	1		T1	4		T2	2		T3	2
all_pins[14]	2895	1		T1	4		T2	2		T3	2
all_pins[15]	2895	1		T1	4		T2	2		T3	2
all_pins[16]	2895	1		T1	4		T2	2		T3	2
all_pins[17]	2895	1		T1	4		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51447	1		T1	71		T2	36		T3	36
values[0x1]	663	1		T1	1		T6	1		T31	1
transitions[0x0=>0x1]	547	1		T1	1		T6	1		T31	1
transitions[0x1=>0x0]	556	1		T1	1		T6	1		T31	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2778	1		T1	3		T2	2		T3	2
all_pins[0]	values[0x1]	117	1		T1	1		T6	1		T31	1
all_pins[0]	transitions[0x0=>0x1]	114	1		T1	1		T6	1		T31	1
all_pins[0]	transitions[0x1=>0x0]	105	1		T12	1		T23	1		T24	1
all_pins[1]	values[0x0]	2787	1		T1	4		T2	2		T3	2
all_pins[1]	values[0x1]	108	1		T12	1		T23	1		T24	1
all_pins[1]	transitions[0x0=>0x1]	104	1		T12	1		T23	1		T24	1
all_pins[1]	transitions[0x1=>0x0]	30	1		T58	2		T59	1		T60	4
all_pins[2]	values[0x0]	2861	1		T1	4		T2	2		T3	2
all_pins[2]	values[0x1]	34	1		T58	2		T59	2		T60	4
all_pins[2]	transitions[0x0=>0x1]	26	1		T58	1		T59	2		T60	2
all_pins[2]	transitions[0x1=>0x0]	15	1		T60	1		T62	1		T252	2
all_pins[3]	values[0x0]	2872	1		T1	4		T2	2		T3	2
all_pins[3]	values[0x1]	23	1		T58	1		T60	3		T62	1
all_pins[3]	transitions[0x0=>0x1]	18	1		T60	2		T62	1		T252	2
all_pins[3]	transitions[0x1=>0x0]	33	1		T59	3		T61	3		T62	2
all_pins[4]	values[0x0]	2857	1		T1	4		T2	2		T3	2
all_pins[4]	values[0x1]	38	1		T58	1		T59	3		T60	1
all_pins[4]	transitions[0x0=>0x1]	32	1		T58	1		T59	2		T60	1
all_pins[4]	transitions[0x1=>0x0]	14	1		T60	2		T62	2		T245	1
all_pins[5]	values[0x0]	2875	1		T1	4		T2	2		T3	2
all_pins[5]	values[0x1]	20	1		T59	1		T60	2		T61	2
all_pins[5]	transitions[0x0=>0x1]	14	1		T60	1		T61	2		T62	2
all_pins[5]	transitions[0x1=>0x0]	18	1		T58	1		T59	1		T245	4
all_pins[6]	values[0x0]	2871	1		T1	4		T2	2		T3	2
all_pins[6]	values[0x1]	24	1		T58	1		T59	2		T60	1
all_pins[6]	transitions[0x0=>0x1]	17	1		T58	1		T59	1		T245	3
all_pins[6]	transitions[0x1=>0x0]	16	1		T58	1		T59	1		T61	1
all_pins[7]	values[0x0]	2872	1		T1	4		T2	2		T3	2
all_pins[7]	values[0x1]	23	1		T58	1		T59	2		T60	1
all_pins[7]	transitions[0x0=>0x1]	15	1		T58	1		T59	1		T60	1
all_pins[7]	transitions[0x1=>0x0]	19	1		T59	1		T60	1		T62	1
all_pins[8]	values[0x0]	2868	1		T1	4		T2	2		T3	2
all_pins[8]	values[0x1]	27	1		T59	2		T60	1		T61	1
all_pins[8]	transitions[0x0=>0x1]	22	1		T59	1		T60	1		T61	1
all_pins[8]	transitions[0x1=>0x0]	20	1		T59	1		T62	1		T63	3
all_pins[9]	values[0x0]	2870	1		T1	4		T2	2		T3	2
all_pins[9]	values[0x1]	25	1		T59	2		T62	1		T63	3
all_pins[9]	transitions[0x0=>0x1]	19	1		T62	1		T63	3		T245	1
all_pins[9]	transitions[0x1=>0x0]	28	1		T59	1		T60	2		T61	2
all_pins[10]	values[0x0]	2861	1		T1	4		T2	2		T3	2
all_pins[10]	values[0x1]	34	1		T59	3		T60	2		T61	2
all_pins[10]	transitions[0x0=>0x1]	27	1		T59	3		T60	2		T61	2
all_pins[10]	transitions[0x1=>0x0]	10	1		T62	2		T245	2		T248	2
all_pins[11]	values[0x0]	2878	1		T1	4		T2	2		T3	2
all_pins[11]	values[0x1]	17	1		T62	2		T245	3		T253	1
all_pins[11]	transitions[0x0=>0x1]	9	1		T245	2		T253	1		T248	1
all_pins[11]	transitions[0x1=>0x0]	25	1		T59	1		T60	3		T63	1
all_pins[12]	values[0x0]	2862	1		T1	4		T2	2		T3	2
all_pins[12]	values[0x1]	33	1		T59	1		T60	3		T62	2
all_pins[12]	transitions[0x0=>0x1]	27	1		T59	1		T60	3		T62	2
all_pins[12]	transitions[0x1=>0x0]	11	1		T59	1		T63	2		T250	2
all_pins[13]	values[0x0]	2878	1		T1	4		T2	2		T3	2
all_pins[13]	values[0x1]	17	1		T59	1		T63	3		T245	2
all_pins[13]	transitions[0x0=>0x1]	9	1		T59	1		T63	3		T245	1
all_pins[13]	transitions[0x1=>0x0]	30	1		T58	2		T60	2		T62	4
all_pins[14]	values[0x0]	2857	1		T1	4		T2	2		T3	2
all_pins[14]	values[0x1]	38	1		T58	2		T60	2		T62	4
all_pins[14]	transitions[0x0=>0x1]	32	1		T58	2		T60	1		T62	4
all_pins[14]	transitions[0x1=>0x0]	23	1		T58	1		T59	2		T252	4
all_pins[15]	values[0x0]	2866	1		T1	4		T2	2		T3	2
all_pins[15]	values[0x1]	29	1		T58	1		T59	2		T60	1
all_pins[15]	transitions[0x0=>0x1]	22	1		T58	1		T60	1		T250	1
all_pins[15]	transitions[0x1=>0x0]	22	1		T59	1		T61	1		T245	3
all_pins[16]	values[0x0]	2866	1		T1	4		T2	2		T3	2
all_pins[16]	values[0x1]	29	1		T59	3		T61	1		T245	3
all_pins[16]	transitions[0x0=>0x1]	25	1		T59	3		T245	3		T243	1
all_pins[16]	transitions[0x1=>0x0]	23	1		T58	1		T60	4		T63	2
all_pins[17]	values[0x0]	2868	1		T1	4		T2	2		T3	2
all_pins[17]	values[0x1]	27	1		T58	1		T60	4		T61	1
all_pins[17]	transitions[0x0=>0x1]	15	1		T60	4		T63	1		T245	1
all_pins[17]	transitions[0x1=>0x0]	114	1		T1	1		T6	1		T31	1