Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.16 96.33 88.64 97.17 46.88 94.15 97.36 96.58


Total test records in report: 932
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T823 /workspace/coverage/default/40.usbdev_setup_trans_ignored.962909680 Mar 21 01:24:46 PM PDT 24 Mar 21 01:24:53 PM PDT 24 8357625174 ps
T824 /workspace/coverage/default/4.usbdev_out_stall.1266887452 Mar 21 01:23:04 PM PDT 24 Mar 21 01:23:12 PM PDT 24 8377892804 ps
T825 /workspace/coverage/default/27.usbdev_out_stall.3577646984 Mar 21 01:24:31 PM PDT 24 Mar 21 01:24:39 PM PDT 24 8408657903 ps
T826 /workspace/coverage/default/32.usbdev_enable.4248642048 Mar 21 01:24:29 PM PDT 24 Mar 21 01:24:36 PM PDT 24 8370464195 ps
T827 /workspace/coverage/default/37.usbdev_out_stall.2200370543 Mar 21 01:24:38 PM PDT 24 Mar 21 01:24:46 PM PDT 24 8372744735 ps
T828 /workspace/coverage/default/49.usbdev_min_length_out_transaction.1477860803 Mar 21 01:25:17 PM PDT 24 Mar 21 01:25:25 PM PDT 24 8360190984 ps
T829 /workspace/coverage/default/46.usbdev_pkt_received.3956524674 Mar 21 01:25:11 PM PDT 24 Mar 21 01:25:20 PM PDT 24 8409159252 ps
T830 /workspace/coverage/default/42.usbdev_in_trans.1093431552 Mar 21 01:24:42 PM PDT 24 Mar 21 01:24:50 PM PDT 24 8452377249 ps
T831 /workspace/coverage/default/32.usbdev_av_buffer.1680413797 Mar 21 01:24:30 PM PDT 24 Mar 21 01:24:38 PM PDT 24 8364512870 ps
T141 /workspace/coverage/default/20.usbdev_smoke.1167504822 Mar 21 01:24:12 PM PDT 24 Mar 21 01:24:20 PM PDT 24 8474145197 ps
T832 /workspace/coverage/default/28.usbdev_pkt_sent.3863617309 Mar 21 01:24:30 PM PDT 24 Mar 21 01:24:39 PM PDT 24 8407511395 ps
T833 /workspace/coverage/default/25.usbdev_min_length_out_transaction.1604597642 Mar 21 01:24:24 PM PDT 24 Mar 21 01:24:32 PM PDT 24 8360792236 ps
T173 /workspace/coverage/default/42.usbdev_in_stall.515238484 Mar 21 01:24:44 PM PDT 24 Mar 21 01:24:51 PM PDT 24 8357905469 ps
T834 /workspace/coverage/default/21.usbdev_enable.3013586949 Mar 21 01:24:16 PM PDT 24 Mar 21 01:24:24 PM PDT 24 8373021576 ps
T835 /workspace/coverage/default/35.usbdev_fifo_rst.1109001190 Mar 21 01:24:27 PM PDT 24 Mar 21 01:24:29 PM PDT 24 292692840 ps
T836 /workspace/coverage/default/6.usbdev_in_stall.506112135 Mar 21 01:23:03 PM PDT 24 Mar 21 01:23:11 PM PDT 24 8361331682 ps
T94 /workspace/coverage/default/47.usbdev_nak_trans.324446869 Mar 21 01:25:20 PM PDT 24 Mar 21 01:25:27 PM PDT 24 8435779117 ps
T837 /workspace/coverage/default/45.usbdev_in_stall.1958769978 Mar 21 01:25:08 PM PDT 24 Mar 21 01:25:17 PM PDT 24 8362302839 ps
T65 /workspace/coverage/default/4.usbdev_sec_cm.3910617574 Mar 21 01:23:24 PM PDT 24 Mar 21 01:23:25 PM PDT 24 77531917 ps
T838 /workspace/coverage/default/44.usbdev_in_stall.256101085 Mar 21 01:24:44 PM PDT 24 Mar 21 01:24:51 PM PDT 24 8359329807 ps
T839 /workspace/coverage/default/44.usbdev_nak_trans.1046209397 Mar 21 01:24:58 PM PDT 24 Mar 21 01:25:06 PM PDT 24 8405263665 ps
T840 /workspace/coverage/default/0.usbdev_pkt_received.2217627043 Mar 21 01:22:52 PM PDT 24 Mar 21 01:23:00 PM PDT 24 8382521699 ps
T841 /workspace/coverage/default/36.usbdev_pkt_received.3400353002 Mar 21 01:24:33 PM PDT 24 Mar 21 01:24:42 PM PDT 24 8376246548 ps
T842 /workspace/coverage/default/30.usbdev_min_length_out_transaction.3560932757 Mar 21 01:24:31 PM PDT 24 Mar 21 01:24:39 PM PDT 24 8366219682 ps
T843 /workspace/coverage/default/8.usbdev_pkt_received.442535772 Mar 21 01:23:49 PM PDT 24 Mar 21 01:23:56 PM PDT 24 8359659464 ps
T844 /workspace/coverage/default/33.usbdev_random_length_out_trans.1961328007 Mar 21 01:24:41 PM PDT 24 Mar 21 01:24:49 PM PDT 24 8411138121 ps
T845 /workspace/coverage/default/39.usbdev_enable.3482534920 Mar 21 01:24:37 PM PDT 24 Mar 21 01:24:47 PM PDT 24 8368068276 ps
T846 /workspace/coverage/default/34.usbdev_out_trans_nak.3844184795 Mar 21 01:24:40 PM PDT 24 Mar 21 01:24:47 PM PDT 24 8393225404 ps
T847 /workspace/coverage/default/13.usbdev_phy_pins_sense.788103496 Mar 21 01:24:18 PM PDT 24 Mar 21 01:24:19 PM PDT 24 28803567 ps
T848 /workspace/coverage/default/3.usbdev_min_length_out_transaction.461918527 Mar 21 01:22:50 PM PDT 24 Mar 21 01:22:59 PM PDT 24 8366408816 ps
T849 /workspace/coverage/default/0.usbdev_out_stall.3576392817 Mar 21 01:22:49 PM PDT 24 Mar 21 01:22:57 PM PDT 24 8404009504 ps
T850 /workspace/coverage/default/13.usbdev_in_trans.3982883090 Mar 21 01:23:47 PM PDT 24 Mar 21 01:23:54 PM PDT 24 8406473349 ps
T851 /workspace/coverage/default/48.usbdev_random_length_out_trans.4197018206 Mar 21 01:25:19 PM PDT 24 Mar 21 01:25:27 PM PDT 24 8408707095 ps
T852 /workspace/coverage/default/43.usbdev_fifo_rst.1441241051 Mar 21 01:25:00 PM PDT 24 Mar 21 01:25:01 PM PDT 24 81959905 ps
T853 /workspace/coverage/default/7.usbdev_phy_pins_sense.1228989355 Mar 21 01:23:21 PM PDT 24 Mar 21 01:23:22 PM PDT 24 23505439 ps
T854 /workspace/coverage/default/43.usbdev_max_length_out_transaction.1824867600 Mar 21 01:24:57 PM PDT 24 Mar 21 01:25:04 PM PDT 24 8412894079 ps
T855 /workspace/coverage/default/23.usbdev_setup_trans_ignored.4195990847 Mar 21 01:23:51 PM PDT 24 Mar 21 01:23:59 PM PDT 24 8359800397 ps
T856 /workspace/coverage/default/2.usbdev_in_trans.1530403592 Mar 21 01:22:48 PM PDT 24 Mar 21 01:22:55 PM PDT 24 8433688911 ps
T857 /workspace/coverage/default/29.usbdev_setup_trans_ignored.522645841 Mar 21 01:24:30 PM PDT 24 Mar 21 01:24:40 PM PDT 24 8357086882 ps
T858 /workspace/coverage/default/11.usbdev_enable.608626666 Mar 21 01:23:48 PM PDT 24 Mar 21 01:23:56 PM PDT 24 8370519859 ps
T859 /workspace/coverage/default/1.usbdev_nak_trans.1163592232 Mar 21 01:22:42 PM PDT 24 Mar 21 01:22:51 PM PDT 24 8384849295 ps
T860 /workspace/coverage/default/41.usbdev_max_length_out_transaction.2936438017 Mar 21 01:24:45 PM PDT 24 Mar 21 01:24:53 PM PDT 24 8406203002 ps
T861 /workspace/coverage/default/49.usbdev_smoke.1179362912 Mar 21 01:25:15 PM PDT 24 Mar 21 01:25:23 PM PDT 24 8475941274 ps
T58 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.255835726 Mar 21 01:03:23 PM PDT 24 Mar 21 01:03:23 PM PDT 24 22263875 ps
T59 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.12737441 Mar 21 01:02:42 PM PDT 24 Mar 21 01:02:43 PM PDT 24 19778943 ps
T47 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1683413588 Mar 21 01:03:17 PM PDT 24 Mar 21 01:03:19 PM PDT 24 245959510 ps
T54 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2507401073 Mar 21 01:03:22 PM PDT 24 Mar 21 01:03:24 PM PDT 24 145663052 ps
T55 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1030102341 Mar 21 01:03:00 PM PDT 24 Mar 21 01:03:01 PM PDT 24 45832725 ps
T56 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3604942989 Mar 21 01:03:21 PM PDT 24 Mar 21 01:03:22 PM PDT 24 31214110 ps
T48 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2944554418 Mar 21 01:02:44 PM PDT 24 Mar 21 01:02:46 PM PDT 24 72845161 ps
T78 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3272412006 Mar 21 01:03:04 PM PDT 24 Mar 21 01:03:05 PM PDT 24 50829643 ps
T49 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1456604593 Mar 21 01:03:21 PM PDT 24 Mar 21 01:03:23 PM PDT 24 124892049 ps
T79 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.19321198 Mar 21 01:02:58 PM PDT 24 Mar 21 01:03:00 PM PDT 24 55493245 ps
T193 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.822805366 Mar 21 01:02:36 PM PDT 24 Mar 21 01:02:38 PM PDT 24 88920203 ps
T184 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4097849254 Mar 21 01:03:00 PM PDT 24 Mar 21 01:03:02 PM PDT 24 46546258 ps
T185 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1346431278 Mar 21 01:03:31 PM PDT 24 Mar 21 01:03:33 PM PDT 24 182157197 ps
T80 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4132312242 Mar 21 01:02:58 PM PDT 24 Mar 21 01:03:00 PM PDT 24 77016128 ps
T81 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2123077025 Mar 21 01:03:24 PM PDT 24 Mar 21 01:03:26 PM PDT 24 245628968 ps
T82 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.196139506 Mar 21 01:02:43 PM PDT 24 Mar 21 01:02:44 PM PDT 24 56880226 ps
T186 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1280587872 Mar 21 01:03:13 PM PDT 24 Mar 21 01:03:17 PM PDT 24 470679955 ps
T187 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1661523040 Mar 21 01:03:05 PM PDT 24 Mar 21 01:03:06 PM PDT 24 108933137 ps
T188 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2878310800 Mar 21 01:02:50 PM PDT 24 Mar 21 01:02:52 PM PDT 24 124534145 ps
T194 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2566871343 Mar 21 01:02:47 PM PDT 24 Mar 21 01:02:49 PM PDT 24 52707290 ps
T191 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1479447581 Mar 21 01:02:56 PM PDT 24 Mar 21 01:02:59 PM PDT 24 212770566 ps
T60 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.56515599 Mar 21 01:02:47 PM PDT 24 Mar 21 01:02:48 PM PDT 24 22289671 ps
T61 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3291912604 Mar 21 01:03:23 PM PDT 24 Mar 21 01:03:23 PM PDT 24 24560758 ps
T62 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3998714736 Mar 21 01:03:42 PM PDT 24 Mar 21 01:03:43 PM PDT 24 25911049 ps
T195 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1977907789 Mar 21 01:02:48 PM PDT 24 Mar 21 01:02:51 PM PDT 24 379328784 ps
T53 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2226441992 Mar 21 01:02:46 PM PDT 24 Mar 21 01:02:47 PM PDT 24 37508882 ps
T204 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2603265496 Mar 21 01:03:16 PM PDT 24 Mar 21 01:03:17 PM PDT 24 38814501 ps
T63 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3450293844 Mar 21 01:03:27 PM PDT 24 Mar 21 01:03:28 PM PDT 24 23116952 ps
T196 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3674200428 Mar 21 01:02:40 PM PDT 24 Mar 21 01:02:41 PM PDT 24 31832137 ps
T245 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3422971308 Mar 21 01:03:22 PM PDT 24 Mar 21 01:03:23 PM PDT 24 21538252 ps
T197 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.741346776 Mar 21 01:02:49 PM PDT 24 Mar 21 01:02:50 PM PDT 24 44834750 ps
T198 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.759493953 Mar 21 01:02:49 PM PDT 24 Mar 21 01:02:50 PM PDT 24 45023985 ps
T189 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2184700316 Mar 21 01:03:13 PM PDT 24 Mar 21 01:03:15 PM PDT 24 76326579 ps
T250 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1701883545 Mar 21 01:03:20 PM PDT 24 Mar 21 01:03:21 PM PDT 24 18903730 ps
T199 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.19548555 Mar 21 01:02:53 PM PDT 24 Mar 21 01:02:54 PM PDT 24 30371187 ps
T862 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.764874608 Mar 21 01:02:46 PM PDT 24 Mar 21 01:02:47 PM PDT 24 103433958 ps
T201 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1147554498 Mar 21 01:03:06 PM PDT 24 Mar 21 01:03:07 PM PDT 24 35001441 ps
T243 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.287180372 Mar 21 01:03:08 PM PDT 24 Mar 21 01:03:08 PM PDT 24 28219556 ps
T242 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3797240498 Mar 21 01:02:55 PM PDT 24 Mar 21 01:02:56 PM PDT 24 37756920 ps
T252 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1085078606 Mar 21 01:03:05 PM PDT 24 Mar 21 01:03:06 PM PDT 24 18956032 ps
T863 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3087769613 Mar 21 01:02:50 PM PDT 24 Mar 21 01:02:52 PM PDT 24 121555173 ps
T247 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.935230934 Mar 21 01:03:23 PM PDT 24 Mar 21 01:03:24 PM PDT 24 22618743 ps
T864 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.878291061 Mar 21 01:03:09 PM PDT 24 Mar 21 01:03:10 PM PDT 24 49240509 ps
T190 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2483345729 Mar 21 01:02:51 PM PDT 24 Mar 21 01:02:53 PM PDT 24 85362696 ps
T865 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2799810622 Mar 21 01:03:09 PM PDT 24 Mar 21 01:03:11 PM PDT 24 97579202 ps
T192 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2320753979 Mar 21 01:03:08 PM PDT 24 Mar 21 01:03:13 PM PDT 24 453118014 ps
T241 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2965030024 Mar 21 01:02:58 PM PDT 24 Mar 21 01:03:00 PM PDT 24 51842109 ps
T866 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4259163555 Mar 21 01:02:57 PM PDT 24 Mar 21 01:02:59 PM PDT 24 125136804 ps
T867 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3983741195 Mar 21 01:03:00 PM PDT 24 Mar 21 01:03:03 PM PDT 24 76800872 ps
T244 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1392526751 Mar 21 01:02:59 PM PDT 24 Mar 21 01:03:01 PM PDT 24 133570056 ps
T236 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3353525661 Mar 21 01:03:15 PM PDT 24 Mar 21 01:03:18 PM PDT 24 231181443 ps
T868 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2090048472 Mar 21 01:02:44 PM PDT 24 Mar 21 01:02:46 PM PDT 24 70640783 ps
T237 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3273603733 Mar 21 01:03:07 PM PDT 24 Mar 21 01:03:08 PM PDT 24 125649633 ps
T240 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.865947661 Mar 21 01:03:09 PM PDT 24 Mar 21 01:03:11 PM PDT 24 203655942 ps
T253 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1615704592 Mar 21 01:03:22 PM PDT 24 Mar 21 01:03:22 PM PDT 24 26343407 ps
T869 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2203309244 Mar 21 01:03:11 PM PDT 24 Mar 21 01:03:13 PM PDT 24 58993477 ps
T238 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3358605687 Mar 21 01:02:58 PM PDT 24 Mar 21 01:03:00 PM PDT 24 262980547 ps
T870 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1515397615 Mar 21 01:03:02 PM PDT 24 Mar 21 01:03:05 PM PDT 24 356226970 ps
T202 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2081589116 Mar 21 01:02:47 PM PDT 24 Mar 21 01:02:48 PM PDT 24 41835198 ps
T200 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2236011126 Mar 21 01:02:41 PM PDT 24 Mar 21 01:02:43 PM PDT 24 26652668 ps
T871 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.755927235 Mar 21 01:02:44 PM PDT 24 Mar 21 01:02:46 PM PDT 24 74524846 ps
T203 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3661932700 Mar 21 01:03:15 PM PDT 24 Mar 21 01:03:16 PM PDT 24 52608072 ps
T872 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2688781862 Mar 21 01:03:05 PM PDT 24 Mar 21 01:03:07 PM PDT 24 82400853 ps
T259 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3459691423 Mar 21 01:02:47 PM PDT 24 Mar 21 01:02:49 PM PDT 24 216732901 ps
T239 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.775720198 Mar 21 01:03:16 PM PDT 24 Mar 21 01:03:19 PM PDT 24 324609936 ps
T873 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4227213025 Mar 21 01:03:18 PM PDT 24 Mar 21 01:03:19 PM PDT 24 31424269 ps
T874 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1618549857 Mar 21 01:03:07 PM PDT 24 Mar 21 01:03:08 PM PDT 24 53978442 ps
T875 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3060544020 Mar 21 01:02:52 PM PDT 24 Mar 21 01:02:54 PM PDT 24 86369834 ps
T876 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1223603946 Mar 21 01:02:49 PM PDT 24 Mar 21 01:02:50 PM PDT 24 30141299 ps
T877 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.306134260 Mar 21 01:02:47 PM PDT 24 Mar 21 01:02:49 PM PDT 24 110792189 ps
T878 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3719087354 Mar 21 01:03:15 PM PDT 24 Mar 21 01:03:16 PM PDT 24 75355227 ps
T206 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.511363899 Mar 21 01:02:51 PM PDT 24 Mar 21 01:02:55 PM PDT 24 485527423 ps
T879 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3063647676 Mar 21 01:03:11 PM PDT 24 Mar 21 01:03:13 PM PDT 24 70912862 ps
T258 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3920866088 Mar 21 01:03:11 PM PDT 24 Mar 21 01:03:13 PM PDT 24 104711861 ps
T256 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3632737739 Mar 21 01:02:47 PM PDT 24 Mar 21 01:02:49 PM PDT 24 223734359 ps
T57 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2051138538 Mar 21 01:02:42 PM PDT 24 Mar 21 01:02:43 PM PDT 24 34551806 ps
T880 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.886435088 Mar 21 01:03:09 PM PDT 24 Mar 21 01:03:11 PM PDT 24 58481920 ps
T881 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1985480239 Mar 21 01:02:48 PM PDT 24 Mar 21 01:02:50 PM PDT 24 66718735 ps
T882 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2738147048 Mar 21 01:03:01 PM PDT 24 Mar 21 01:03:03 PM PDT 24 80050218 ps
T883 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1161572663 Mar 21 01:03:22 PM PDT 24 Mar 21 01:03:23 PM PDT 24 68062045 ps
T248 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2523672468 Mar 21 01:02:58 PM PDT 24 Mar 21 01:02:59 PM PDT 24 28864113 ps
T884 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4103071970 Mar 21 01:03:08 PM PDT 24 Mar 21 01:03:09 PM PDT 24 26282836 ps
T260 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1157824533 Mar 21 01:03:00 PM PDT 24 Mar 21 01:03:02 PM PDT 24 120434157 ps
T885 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2486449002 Mar 21 01:03:19 PM PDT 24 Mar 21 01:03:20 PM PDT 24 23597460 ps
T886 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4185320092 Mar 21 01:03:23 PM PDT 24 Mar 21 01:03:24 PM PDT 24 56647479 ps
T887 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1355957313 Mar 21 01:02:56 PM PDT 24 Mar 21 01:02:57 PM PDT 24 30010586 ps
T888 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1500169345 Mar 21 01:03:21 PM PDT 24 Mar 21 01:03:22 PM PDT 24 39691480 ps
T889 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4125448576 Mar 21 01:03:21 PM PDT 24 Mar 21 01:03:21 PM PDT 24 29664256 ps
T249 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3170628252 Mar 21 01:03:22 PM PDT 24 Mar 21 01:03:23 PM PDT 24 27127869 ps
T890 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2248467452 Mar 21 01:03:22 PM PDT 24 Mar 21 01:03:24 PM PDT 24 81219988 ps
T891 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.626653304 Mar 21 01:03:16 PM PDT 24 Mar 21 01:03:16 PM PDT 24 24393689 ps
T892 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1110421489 Mar 21 01:03:07 PM PDT 24 Mar 21 01:03:09 PM PDT 24 148734349 ps
T893 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1865295724 Mar 21 01:02:46 PM PDT 24 Mar 21 01:02:49 PM PDT 24 369663709 ps
T894 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3076220686 Mar 21 01:03:16 PM PDT 24 Mar 21 01:03:17 PM PDT 24 35189238 ps
T895 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2879191208 Mar 21 01:02:49 PM PDT 24 Mar 21 01:02:52 PM PDT 24 87852520 ps
T896 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.741353842 Mar 21 01:03:20 PM PDT 24 Mar 21 01:03:21 PM PDT 24 130717226 ps
T897 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1916857870 Mar 21 01:03:07 PM PDT 24 Mar 21 01:03:09 PM PDT 24 67330938 ps
T898 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2465027904 Mar 21 01:02:48 PM PDT 24 Mar 21 01:02:50 PM PDT 24 138362113 ps
T899 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4265372434 Mar 21 01:03:14 PM PDT 24 Mar 21 01:03:17 PM PDT 24 213844945 ps
T900 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.49562830 Mar 21 01:03:08 PM PDT 24 Mar 21 01:03:09 PM PDT 24 56161694 ps
T901 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2010051270 Mar 21 01:02:56 PM PDT 24 Mar 21 01:02:57 PM PDT 24 106808028 ps
T902 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.377298094 Mar 21 01:02:57 PM PDT 24 Mar 21 01:03:00 PM PDT 24 272499752 ps
T254 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.726912490 Mar 21 01:03:16 PM PDT 24 Mar 21 01:03:17 PM PDT 24 26009475 ps
T903 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1606141057 Mar 21 01:03:16 PM PDT 24 Mar 21 01:03:18 PM PDT 24 244974755 ps
T904 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.722396306 Mar 21 01:03:06 PM PDT 24 Mar 21 01:03:08 PM PDT 24 170066681 ps
T905 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1999696304 Mar 21 01:03:15 PM PDT 24 Mar 21 01:03:17 PM PDT 24 213446655 ps
T906 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.159069124 Mar 21 01:02:58 PM PDT 24 Mar 21 01:03:01 PM PDT 24 148507391 ps
T907 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3516212415 Mar 21 01:03:06 PM PDT 24 Mar 21 01:03:08 PM PDT 24 133401624 ps
T262 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1591918609 Mar 21 01:03:07 PM PDT 24 Mar 21 01:03:09 PM PDT 24 209682280 ps
T257 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3388397337 Mar 21 01:02:44 PM PDT 24 Mar 21 01:02:46 PM PDT 24 110927663 ps
T908 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.841002513 Mar 21 01:03:00 PM PDT 24 Mar 21 01:03:02 PM PDT 24 52748186 ps
T909 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.813860941 Mar 21 01:02:47 PM PDT 24 Mar 21 01:02:50 PM PDT 24 267093823 ps
T910 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2782620358 Mar 21 01:02:59 PM PDT 24 Mar 21 01:03:00 PM PDT 24 63231044 ps
T911 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2408080174 Mar 21 01:03:09 PM PDT 24 Mar 21 01:03:10 PM PDT 24 40500581 ps
T246 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4233754222 Mar 21 01:03:03 PM PDT 24 Mar 21 01:03:04 PM PDT 24 24835198 ps
T912 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3332240099 Mar 21 01:03:09 PM PDT 24 Mar 21 01:03:10 PM PDT 24 82612294 ps
T913 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4201266000 Mar 21 01:02:43 PM PDT 24 Mar 21 01:02:45 PM PDT 24 127741343 ps
T255 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2432557133 Mar 21 01:03:27 PM PDT 24 Mar 21 01:03:28 PM PDT 24 31051998 ps
T251 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3160245042 Mar 21 01:03:19 PM PDT 24 Mar 21 01:03:20 PM PDT 24 25672668 ps
T914 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.580681969 Mar 21 01:03:06 PM PDT 24 Mar 21 01:03:08 PM PDT 24 128038905 ps
T915 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4036431414 Mar 21 01:02:59 PM PDT 24 Mar 21 01:03:03 PM PDT 24 471498095 ps
T916 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.306963886 Mar 21 01:03:08 PM PDT 24 Mar 21 01:03:10 PM PDT 24 76185042 ps
T917 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.860397716 Mar 21 01:03:17 PM PDT 24 Mar 21 01:03:18 PM PDT 24 26314038 ps
T918 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.989482401 Mar 21 01:02:56 PM PDT 24 Mar 21 01:02:57 PM PDT 24 81613431 ps
T919 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.930356670 Mar 21 01:03:15 PM PDT 24 Mar 21 01:03:17 PM PDT 24 78490001 ps
T920 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3307718999 Mar 21 01:02:36 PM PDT 24 Mar 21 01:02:39 PM PDT 24 188053373 ps
T261 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.325879044 Mar 21 01:03:16 PM PDT 24 Mar 21 01:03:20 PM PDT 24 460321109 ps
T921 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1041618987 Mar 21 01:03:13 PM PDT 24 Mar 21 01:03:15 PM PDT 24 139395519 ps
T922 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1501891477 Mar 21 01:02:45 PM PDT 24 Mar 21 01:02:46 PM PDT 24 30529959 ps
T923 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1288286402 Mar 21 01:03:21 PM PDT 24 Mar 21 01:03:22 PM PDT 24 38442780 ps
T924 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4279004131 Mar 21 01:02:45 PM PDT 24 Mar 21 01:02:47 PM PDT 24 56514850 ps
T925 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.237140436 Mar 21 01:02:42 PM PDT 24 Mar 21 01:02:46 PM PDT 24 147278693 ps
T926 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3197537482 Mar 21 01:02:47 PM PDT 24 Mar 21 01:02:49 PM PDT 24 91792666 ps
T927 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1159987909 Mar 21 01:03:21 PM PDT 24 Mar 21 01:03:23 PM PDT 24 143066506 ps
T928 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3085030113 Mar 21 01:02:58 PM PDT 24 Mar 21 01:03:00 PM PDT 24 41625163 ps
T929 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3664269660 Mar 21 01:02:59 PM PDT 24 Mar 21 01:03:03 PM PDT 24 428877457 ps
T930 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2005239060 Mar 21 01:02:51 PM PDT 24 Mar 21 01:02:53 PM PDT 24 61332584 ps
T931 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2700932657 Mar 21 01:03:23 PM PDT 24 Mar 21 01:03:24 PM PDT 24 34633360 ps
T932 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2516722197 Mar 21 01:02:55 PM PDT 24 Mar 21 01:02:57 PM PDT 24 86816067 ps

Test location /workspace/coverage/default/20.usbdev_av_buffer.2010644693
Short name T2
Test name
Test status
Simulation time 8373492256 ps
CPU time 9.63 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203444 kb
Host smart-27814c21-be0d-44af-a490-f37f89b25cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20106
44693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2010644693
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_smoke.767293181
Short name T11
Test name
Test status
Simulation time 8473786849 ps
CPU time 7.26 seconds
Started Mar 21 01:25:10 PM PDT 24
Finished Mar 21 01:25:18 PM PDT 24
Peak memory 203568 kb
Host smart-0c1e5cd6-5516-49dd-a38c-d6a2694482ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76729
3181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.767293181
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3422971308
Short name T245
Test name
Test status
Simulation time 21538252 ps
CPU time 0.66 seconds
Started Mar 21 01:03:22 PM PDT 24
Finished Mar 21 01:03:23 PM PDT 24
Peak memory 202076 kb
Host smart-eb32b9f8-832c-473e-a26a-870b2c2bad75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3422971308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3422971308
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1714478334
Short name T212
Test name
Test status
Simulation time 233111486 ps
CPU time 2.02 seconds
Started Mar 21 01:25:12 PM PDT 24
Finished Mar 21 01:25:14 PM PDT 24
Peak memory 203424 kb
Host smart-dd5a750b-76e5-4abb-afe9-6b01e2e3a55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17144
78334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1714478334
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1683413588
Short name T47
Test name
Test status
Simulation time 245959510 ps
CPU time 2.27 seconds
Started Mar 21 01:03:17 PM PDT 24
Finished Mar 21 01:03:19 PM PDT 24
Peak memory 202376 kb
Host smart-85935ac6-cc26-4570-a125-affaaeec02a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1683413588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1683413588
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3860888820
Short name T7
Test name
Test status
Simulation time 8358591003 ps
CPU time 7.61 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203212 kb
Host smart-b56a80e1-41bf-4d55-9e76-dd5dedec9c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38608
88820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3860888820
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.255835726
Short name T58
Test name
Test status
Simulation time 22263875 ps
CPU time 0.74 seconds
Started Mar 21 01:03:23 PM PDT 24
Finished Mar 21 01:03:23 PM PDT 24
Peak memory 202232 kb
Host smart-13227e12-d80b-4f5a-8a86-3f3a38e86dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=255835726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.255835726
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3973412341
Short name T19
Test name
Test status
Simulation time 8444607457 ps
CPU time 8.9 seconds
Started Mar 21 01:25:17 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 203476 kb
Host smart-1e967cda-c581-4e23-a262-9f7b8e36293a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39734
12341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3973412341
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1920375873
Short name T51
Test name
Test status
Simulation time 82367110 ps
CPU time 0.91 seconds
Started Mar 21 01:22:44 PM PDT 24
Finished Mar 21 01:22:46 PM PDT 24
Peak memory 219052 kb
Host smart-ea9e8f44-628c-4f78-aead-c4250d91ec20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1920375873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1920375873
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1346431278
Short name T185
Test name
Test status
Simulation time 182157197 ps
CPU time 2.25 seconds
Started Mar 21 01:03:31 PM PDT 24
Finished Mar 21 01:03:33 PM PDT 24
Peak memory 202564 kb
Host smart-f2c42646-233e-4eba-9536-129d2185290a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1346431278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1346431278
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1295770851
Short name T10
Test name
Test status
Simulation time 23738106 ps
CPU time 0.67 seconds
Started Mar 21 01:23:15 PM PDT 24
Finished Mar 21 01:23:16 PM PDT 24
Peak memory 202904 kb
Host smart-c99b7542-5c42-42f3-b3ed-669bd343b686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12957
70851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1295770851
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.862203517
Short name T210
Test name
Test status
Simulation time 8386944681 ps
CPU time 7.99 seconds
Started Mar 21 01:24:19 PM PDT 24
Finished Mar 21 01:24:27 PM PDT 24
Peak memory 203420 kb
Host smart-ce273f8c-7a5a-4577-bee6-4d47a88031bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86220
3517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.862203517
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2392684659
Short name T23
Test name
Test status
Simulation time 8410692663 ps
CPU time 8.02 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203432 kb
Host smart-2fd3fd81-d32e-4f30-abe6-00bee71cb0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23926
84659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2392684659
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1615704592
Short name T253
Test name
Test status
Simulation time 26343407 ps
CPU time 0.68 seconds
Started Mar 21 01:03:22 PM PDT 24
Finished Mar 21 01:03:22 PM PDT 24
Peak memory 202108 kb
Host smart-d052ff5e-6026-4e6b-9c66-844aa9df4f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1615704592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1615704592
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.196139506
Short name T82
Test name
Test status
Simulation time 56880226 ps
CPU time 0.86 seconds
Started Mar 21 01:02:43 PM PDT 24
Finished Mar 21 01:02:44 PM PDT 24
Peak memory 202392 kb
Host smart-efcf830a-ac77-4b5a-8534-952d369c5887
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196139506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.196139506
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1501435703
Short name T208
Test name
Test status
Simulation time 116448965 ps
CPU time 1.46 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:25:51 PM PDT 24
Peak memory 201028 kb
Host smart-f70f4d0f-b5bd-45a3-bb1d-d0742250931e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15014
35703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1501435703
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3160245042
Short name T251
Test name
Test status
Simulation time 25672668 ps
CPU time 0.61 seconds
Started Mar 21 01:03:19 PM PDT 24
Finished Mar 21 01:03:20 PM PDT 24
Peak memory 202184 kb
Host smart-49af0649-92df-4f89-bbfd-67fe3fb094d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3160245042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3160245042
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3347911929
Short name T13
Test name
Test status
Simulation time 8475679615 ps
CPU time 7.36 seconds
Started Mar 21 01:22:48 PM PDT 24
Finished Mar 21 01:22:55 PM PDT 24
Peak memory 203520 kb
Host smart-3e03c17c-acf4-4946-9a35-94515f647ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33479
11929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3347911929
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_smoke.286545009
Short name T115
Test name
Test status
Simulation time 8477615781 ps
CPU time 9.2 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:42 PM PDT 24
Peak memory 203496 kb
Host smart-dd2caae7-5067-4cb8-bb9a-2d06f6e0a2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28654
5009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.286545009
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3956287681
Short name T76
Test name
Test status
Simulation time 8473244065 ps
CPU time 7.99 seconds
Started Mar 21 01:24:26 PM PDT 24
Finished Mar 21 01:24:34 PM PDT 24
Peak memory 203500 kb
Host smart-40549ada-ec87-42d6-ad55-ab8ababb5720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39562
87681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3956287681
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1662931478
Short name T167
Test name
Test status
Simulation time 8364565459 ps
CPU time 7.63 seconds
Started Mar 21 01:24:26 PM PDT 24
Finished Mar 21 01:24:34 PM PDT 24
Peak memory 203252 kb
Host smart-84e5975e-89c7-4ff0-a436-4e2a80270008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16629
31478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1662931478
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3186757402
Short name T138
Test name
Test status
Simulation time 8475116249 ps
CPU time 8.24 seconds
Started Mar 21 01:24:03 PM PDT 24
Finished Mar 21 01:24:17 PM PDT 24
Peak memory 203556 kb
Host smart-e6b8a1c7-b035-49fe-a00c-5f9424976504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31867
57402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3186757402
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2479864820
Short name T148
Test name
Test status
Simulation time 8480111682 ps
CPU time 7.82 seconds
Started Mar 21 01:24:23 PM PDT 24
Finished Mar 21 01:24:32 PM PDT 24
Peak memory 203544 kb
Host smart-59841738-9497-4d93-a4ac-7f78e91e5a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
64820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2479864820
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2367515979
Short name T136
Test name
Test status
Simulation time 8479069470 ps
CPU time 8.64 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203464 kb
Host smart-38571114-9539-4836-a69d-de3b4546b9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23675
15979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2367515979
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1716097903
Short name T149
Test name
Test status
Simulation time 8472608900 ps
CPU time 7.28 seconds
Started Mar 21 01:23:54 PM PDT 24
Finished Mar 21 01:24:01 PM PDT 24
Peak memory 203548 kb
Host smart-1e3499e4-18e8-4a59-859d-d7cb59755799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17160
97903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1716097903
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2080833296
Short name T151
Test name
Test status
Simulation time 8474393966 ps
CPU time 8.16 seconds
Started Mar 21 01:24:04 PM PDT 24
Finished Mar 21 01:24:12 PM PDT 24
Peak memory 203512 kb
Host smart-ac358b34-0079-46e0-b2d8-e95e3093d153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
33296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2080833296
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3459691423
Short name T259
Test name
Test status
Simulation time 216732901 ps
CPU time 2.19 seconds
Started Mar 21 01:02:47 PM PDT 24
Finished Mar 21 01:02:49 PM PDT 24
Peak memory 202392 kb
Host smart-3db604a7-91cb-436e-a698-6e3a3da3e652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3459691423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3459691423
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3291912604
Short name T61
Test name
Test status
Simulation time 24560758 ps
CPU time 0.65 seconds
Started Mar 21 01:03:23 PM PDT 24
Finished Mar 21 01:03:23 PM PDT 24
Peak memory 202184 kb
Host smart-0023604a-d82a-48b4-a3a2-b160323226e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3291912604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3291912604
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2226441992
Short name T53
Test name
Test status
Simulation time 37508882 ps
CPU time 0.76 seconds
Started Mar 21 01:02:46 PM PDT 24
Finished Mar 21 01:02:47 PM PDT 24
Peak memory 202320 kb
Host smart-3ca8631d-ebed-4a6a-8efc-5e2c74b0e1f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226441992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2226441992
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/15.usbdev_enable.3152084232
Short name T38
Test name
Test status
Simulation time 8369703052 ps
CPU time 9.84 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:24:01 PM PDT 24
Peak memory 203456 kb
Host smart-7451d2e8-302a-4bc8-919f-6100af27ca8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31520
84232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3152084232
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3388397337
Short name T257
Test name
Test status
Simulation time 110927663 ps
CPU time 1.86 seconds
Started Mar 21 01:02:44 PM PDT 24
Finished Mar 21 01:02:46 PM PDT 24
Peak memory 202352 kb
Host smart-65fc7e8d-8cdd-4a40-ac46-0ebda7f97842
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3388397337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3388397337
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1591918609
Short name T262
Test name
Test status
Simulation time 209682280 ps
CPU time 2.28 seconds
Started Mar 21 01:03:07 PM PDT 24
Finished Mar 21 01:03:09 PM PDT 24
Peak memory 202412 kb
Host smart-4afd64d4-32a4-4663-ac7d-ab1bcf8ae2f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1591918609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1591918609
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1280587872
Short name T186
Test name
Test status
Simulation time 470679955 ps
CPU time 3.58 seconds
Started Mar 21 01:03:13 PM PDT 24
Finished Mar 21 01:03:17 PM PDT 24
Peak memory 202460 kb
Host smart-142433db-6e15-4cc4-beee-c34828c0adc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1280587872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1280587872
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2432557133
Short name T255
Test name
Test status
Simulation time 31051998 ps
CPU time 0.68 seconds
Started Mar 21 01:03:27 PM PDT 24
Finished Mar 21 01:03:28 PM PDT 24
Peak memory 202164 kb
Host smart-87e278f5-e5b0-413f-ae62-8ce3f071023c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2432557133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2432557133
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1157824533
Short name T260
Test name
Test status
Simulation time 120434157 ps
CPU time 2.01 seconds
Started Mar 21 01:03:00 PM PDT 24
Finished Mar 21 01:03:02 PM PDT 24
Peak memory 202408 kb
Host smart-216b1873-9566-45ad-a597-2e40738d5745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1157824533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1157824533
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3353525661
Short name T236
Test name
Test status
Simulation time 231181443 ps
CPU time 2.86 seconds
Started Mar 21 01:03:15 PM PDT 24
Finished Mar 21 01:03:18 PM PDT 24
Peak memory 202432 kb
Host smart-011a977e-a94a-496d-b26f-4b10eb3c14d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3353525661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3353525661
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1977918359
Short name T123
Test name
Test status
Simulation time 8474808101 ps
CPU time 7.39 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:45 PM PDT 24
Peak memory 203500 kb
Host smart-c3c7458e-cb23-4e01-9a6b-58b8861a0e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19779
18359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1977918359
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3408853190
Short name T230
Test name
Test status
Simulation time 255961066 ps
CPU time 2.06 seconds
Started Mar 21 01:24:00 PM PDT 24
Finished Mar 21 01:24:02 PM PDT 24
Peak memory 203268 kb
Host smart-9b632e48-078e-4270-8b9f-1aa6d9545fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34088
53190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3408853190
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3639807084
Short name T29
Test name
Test status
Simulation time 8473419277 ps
CPU time 8.5 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:21 PM PDT 24
Peak memory 203552 kb
Host smart-1ee2a631-9878-40b1-b7a7-6942153a48d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36398
07084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3639807084
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3383107216
Short name T337
Test name
Test status
Simulation time 27257829 ps
CPU time 0.62 seconds
Started Mar 21 01:23:42 PM PDT 24
Finished Mar 21 01:23:42 PM PDT 24
Peak memory 202912 kb
Host smart-f46f4c21-c26d-4fbb-bbb4-f46024998df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33831
07216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3383107216
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.511363899
Short name T206
Test name
Test status
Simulation time 485527423 ps
CPU time 3.49 seconds
Started Mar 21 01:02:51 PM PDT 24
Finished Mar 21 01:02:55 PM PDT 24
Peak memory 202320 kb
Host smart-add2b92b-6043-43b0-89be-7c18d2147da6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511363899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.511363899
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3397419919
Short name T17
Test name
Test status
Simulation time 8364700397 ps
CPU time 8.01 seconds
Started Mar 21 01:22:44 PM PDT 24
Finished Mar 21 01:22:53 PM PDT 24
Peak memory 203284 kb
Host smart-b89969eb-7b7b-405f-aa33-21c8fbe38d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33974
19919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3397419919
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2254062795
Short name T143
Test name
Test status
Simulation time 8475670605 ps
CPU time 7.87 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203564 kb
Host smart-5b0d7d87-b59c-42f9-b1b5-c8ad07c8622f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22540
62795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2254062795
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2051138538
Short name T57
Test name
Test status
Simulation time 34551806 ps
CPU time 0.72 seconds
Started Mar 21 01:02:42 PM PDT 24
Finished Mar 21 01:02:43 PM PDT 24
Peak memory 202304 kb
Host smart-ca9f9e8f-d14d-4444-b071-f59dd52be85f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051138538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2051138538
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3797240498
Short name T242
Test name
Test status
Simulation time 37756920 ps
CPU time 0.76 seconds
Started Mar 21 01:02:55 PM PDT 24
Finished Mar 21 01:02:56 PM PDT 24
Peak memory 202204 kb
Host smart-5a7a3d88-dbef-4946-b0fd-b53feef96a62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797240498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3797240498
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3833214020
Short name T88
Test name
Test status
Simulation time 8424625209 ps
CPU time 8.24 seconds
Started Mar 21 01:22:41 PM PDT 24
Finished Mar 21 01:22:50 PM PDT 24
Peak memory 203404 kb
Host smart-4ac59777-ba0f-4d29-9497-3d95710c1e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38332
14020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3833214020
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1811981256
Short name T171
Test name
Test status
Simulation time 8363589995 ps
CPU time 7.63 seconds
Started Mar 21 01:22:53 PM PDT 24
Finished Mar 21 01:23:01 PM PDT 24
Peak memory 203232 kb
Host smart-e5b00d5b-0949-44f5-a33c-29631beb115a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18119
81256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1811981256
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1163592232
Short name T859
Test name
Test status
Simulation time 8384849295 ps
CPU time 8.1 seconds
Started Mar 21 01:22:42 PM PDT 24
Finished Mar 21 01:22:51 PM PDT 24
Peak memory 203500 kb
Host smart-1aeaa2ef-b85f-49e7-9029-7c6b19b20f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11635
92232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1163592232
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2088875565
Short name T155
Test name
Test status
Simulation time 8362226798 ps
CPU time 8.71 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203304 kb
Host smart-c6247bbb-4295-4a06-bff4-ad02211370b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20888
75565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2088875565
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3617143180
Short name T103
Test name
Test status
Simulation time 8401278802 ps
CPU time 8.46 seconds
Started Mar 21 01:23:40 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203388 kb
Host smart-4e623adb-0331-4d33-902b-01f6772f4d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36171
43180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3617143180
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2628335157
Short name T162
Test name
Test status
Simulation time 8355831364 ps
CPU time 6.85 seconds
Started Mar 21 01:23:54 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203160 kb
Host smart-2ddfbfcd-4a5a-4d96-a035-88e2d5395818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26283
35157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2628335157
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3977929682
Short name T593
Test name
Test status
Simulation time 8438690447 ps
CPU time 7.04 seconds
Started Mar 21 01:23:56 PM PDT 24
Finished Mar 21 01:24:03 PM PDT 24
Peak memory 203400 kb
Host smart-37c61d73-6131-40d6-8e5a-6e4db5ef0954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39779
29682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3977929682
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1530516079
Short name T106
Test name
Test status
Simulation time 8433188838 ps
CPU time 9.16 seconds
Started Mar 21 01:23:45 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203372 kb
Host smart-129ac78f-eb25-403f-a0dc-d0849dd48a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15305
16079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1530516079
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2290026658
Short name T95
Test name
Test status
Simulation time 8392703248 ps
CPU time 8.25 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203492 kb
Host smart-402d8726-ab7d-4937-8509-6a80f65aa9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22900
26658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2290026658
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3662385173
Short name T97
Test name
Test status
Simulation time 8422580763 ps
CPU time 9.03 seconds
Started Mar 21 01:24:11 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203464 kb
Host smart-2bcc311d-2502-4aa7-8371-e8e8d3407513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36623
85173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3662385173
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1214757161
Short name T24
Test name
Test status
Simulation time 8398008747 ps
CPU time 7.9 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:22 PM PDT 24
Peak memory 203480 kb
Host smart-a09efbeb-a2a9-4cb3-8878-aa0bfe8a9769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147
57161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1214757161
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1881797489
Short name T164
Test name
Test status
Simulation time 8363492199 ps
CPU time 6.94 seconds
Started Mar 21 01:24:01 PM PDT 24
Finished Mar 21 01:24:08 PM PDT 24
Peak memory 203192 kb
Host smart-cd6fb59b-cbea-4ea7-b6d0-013919a92c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18817
97489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1881797489
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1045494775
Short name T179
Test name
Test status
Simulation time 8360150498 ps
CPU time 7.55 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:24:02 PM PDT 24
Peak memory 203208 kb
Host smart-77ebc093-ca1c-4bf7-8ee9-188f0d1d5c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10454
94775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1045494775
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.694400184
Short name T85
Test name
Test status
Simulation time 8437566259 ps
CPU time 8.03 seconds
Started Mar 21 01:24:20 PM PDT 24
Finished Mar 21 01:24:28 PM PDT 24
Peak memory 203484 kb
Host smart-635898ab-1ece-4ab6-b752-55cf1d18fe8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69440
0184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.694400184
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3227014986
Short name T83
Test name
Test status
Simulation time 8426705558 ps
CPU time 7.13 seconds
Started Mar 21 01:24:21 PM PDT 24
Finished Mar 21 01:24:28 PM PDT 24
Peak memory 203448 kb
Host smart-bea51c25-bd54-4810-ba25-ac1d58a8fcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
14986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3227014986
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3548526
Short name T25
Test name
Test status
Simulation time 8356653882 ps
CPU time 10.09 seconds
Started Mar 21 01:22:56 PM PDT 24
Finished Mar 21 01:23:07 PM PDT 24
Peak memory 203264 kb
Host smart-01a9ff1b-4399-496d-8c90-cfba6376d088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
26 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3548526
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1140968271
Short name T160
Test name
Test status
Simulation time 8358816947 ps
CPU time 7.16 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:45 PM PDT 24
Peak memory 203260 kb
Host smart-e3338d6b-a478-4d0d-9c2b-f015fa0d2328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11409
68271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1140968271
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1467837974
Short name T92
Test name
Test status
Simulation time 8437588475 ps
CPU time 7.87 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203348 kb
Host smart-c23ec7f2-7d9b-4c2b-a311-40cd8f4c7df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14678
37974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1467837974
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.161513825
Short name T105
Test name
Test status
Simulation time 8390856990 ps
CPU time 8.79 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203496 kb
Host smart-b5e38317-2470-49b8-948d-64515c58a239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16151
3825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.161513825
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4201266000
Short name T913
Test name
Test status
Simulation time 127741343 ps
CPU time 1.74 seconds
Started Mar 21 01:02:43 PM PDT 24
Finished Mar 21 01:02:45 PM PDT 24
Peak memory 202412 kb
Host smart-41e33644-f8b0-4047-ad85-c0beb7244e4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201266000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4201266000
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2465027904
Short name T898
Test name
Test status
Simulation time 138362113 ps
CPU time 1.76 seconds
Started Mar 21 01:02:48 PM PDT 24
Finished Mar 21 01:02:50 PM PDT 24
Peak memory 210816 kb
Host smart-fb312379-00de-4155-a1d6-8d48c54d74a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465027904 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2465027904
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.56515599
Short name T60
Test name
Test status
Simulation time 22289671 ps
CPU time 0.76 seconds
Started Mar 21 01:02:47 PM PDT 24
Finished Mar 21 01:02:48 PM PDT 24
Peak memory 202120 kb
Host smart-aa6ee63f-eadd-4e9a-8974-f352d426e0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=56515599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.56515599
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3307718999
Short name T920
Test name
Test status
Simulation time 188053373 ps
CPU time 2.27 seconds
Started Mar 21 01:02:36 PM PDT 24
Finished Mar 21 01:02:39 PM PDT 24
Peak memory 201472 kb
Host smart-bbdc8581-185e-4ca6-9fc2-caeed94edc03
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3307718999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3307718999
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.237140436
Short name T925
Test name
Test status
Simulation time 147278693 ps
CPU time 3.82 seconds
Started Mar 21 01:02:42 PM PDT 24
Finished Mar 21 01:02:46 PM PDT 24
Peak memory 202420 kb
Host smart-89f8da22-e521-40b9-bbd6-f127f9fd79ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=237140436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.237140436
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2005239060
Short name T930
Test name
Test status
Simulation time 61332584 ps
CPU time 1.05 seconds
Started Mar 21 01:02:51 PM PDT 24
Finished Mar 21 01:02:53 PM PDT 24
Peak memory 202508 kb
Host smart-30cdf9e0-310c-4b8a-b875-d658f1a98dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005239060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.2005239060
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2944554418
Short name T48
Test name
Test status
Simulation time 72845161 ps
CPU time 2.18 seconds
Started Mar 21 01:02:44 PM PDT 24
Finished Mar 21 01:02:46 PM PDT 24
Peak memory 202372 kb
Host smart-0b8472c9-c884-4241-943a-29cb076edb39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2944554418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2944554418
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2566871343
Short name T194
Test name
Test status
Simulation time 52707290 ps
CPU time 1.47 seconds
Started Mar 21 01:02:47 PM PDT 24
Finished Mar 21 01:02:49 PM PDT 24
Peak memory 202336 kb
Host smart-50ed9ec7-2c8f-47e0-9b42-c6a6ee0f4682
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566871343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2566871343
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1865295724
Short name T893
Test name
Test status
Simulation time 369663709 ps
CPU time 3.6 seconds
Started Mar 21 01:02:46 PM PDT 24
Finished Mar 21 01:02:49 PM PDT 24
Peak memory 202492 kb
Host smart-a374647d-b038-44d7-a442-feb0823e0ac7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865295724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1865295724
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2236011126
Short name T200
Test name
Test status
Simulation time 26652668 ps
CPU time 0.73 seconds
Started Mar 21 01:02:41 PM PDT 24
Finished Mar 21 01:02:43 PM PDT 24
Peak memory 202152 kb
Host smart-789417da-6c81-4c7b-a4fb-c39bdd2a78a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236011126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2236011126
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.755927235
Short name T871
Test name
Test status
Simulation time 74524846 ps
CPU time 2.02 seconds
Started Mar 21 01:02:44 PM PDT 24
Finished Mar 21 01:02:46 PM PDT 24
Peak memory 210636 kb
Host smart-2a7f5edb-c1a3-4917-a552-7680aa5f26ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755927235 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.755927235
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3674200428
Short name T196
Test name
Test status
Simulation time 31832137 ps
CPU time 0.82 seconds
Started Mar 21 01:02:40 PM PDT 24
Finished Mar 21 01:02:41 PM PDT 24
Peak memory 202176 kb
Host smart-f5443dc6-3b5e-4f11-81d1-493697674f24
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674200428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3674200428
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.12737441
Short name T59
Test name
Test status
Simulation time 19778943 ps
CPU time 0.68 seconds
Started Mar 21 01:02:42 PM PDT 24
Finished Mar 21 01:02:43 PM PDT 24
Peak memory 202040 kb
Host smart-444b8501-d9f4-4575-b687-e95e51f1c5d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=12737441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.12737441
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.759493953
Short name T198
Test name
Test status
Simulation time 45023985 ps
CPU time 1.27 seconds
Started Mar 21 01:02:49 PM PDT 24
Finished Mar 21 01:02:50 PM PDT 24
Peak memory 202380 kb
Host smart-114ac768-eb85-47f1-a87d-2ea625e78b84
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=759493953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.759493953
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.306134260
Short name T877
Test name
Test status
Simulation time 110792189 ps
CPU time 1.25 seconds
Started Mar 21 01:02:47 PM PDT 24
Finished Mar 21 01:02:49 PM PDT 24
Peak memory 202336 kb
Host smart-38fb4a5d-e4cf-45db-891f-7e8160cc0e77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306134260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_cs
r_outstanding.306134260
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.813860941
Short name T909
Test name
Test status
Simulation time 267093823 ps
CPU time 2.82 seconds
Started Mar 21 01:02:47 PM PDT 24
Finished Mar 21 01:02:50 PM PDT 24
Peak memory 202500 kb
Host smart-c2fb3fd1-cf25-4aa6-a82f-46f5b7c0e642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=813860941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.813860941
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1110421489
Short name T892
Test name
Test status
Simulation time 148734349 ps
CPU time 1.79 seconds
Started Mar 21 01:03:07 PM PDT 24
Finished Mar 21 01:03:09 PM PDT 24
Peak memory 210680 kb
Host smart-4884349f-a085-4635-b178-0cd3c9be47e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110421489 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.1110421489
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1147554498
Short name T201
Test name
Test status
Simulation time 35001441 ps
CPU time 0.92 seconds
Started Mar 21 01:03:06 PM PDT 24
Finished Mar 21 01:03:07 PM PDT 24
Peak memory 202404 kb
Host smart-ad8496fe-f2d0-4cdf-bc36-94d16667a1fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147554498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1147554498
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.726912490
Short name T254
Test name
Test status
Simulation time 26009475 ps
CPU time 0.69 seconds
Started Mar 21 01:03:16 PM PDT 24
Finished Mar 21 01:03:17 PM PDT 24
Peak memory 202176 kb
Host smart-85267c63-ecad-408a-9fa4-4f9c9fca9554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=726912490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.726912490
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.580681969
Short name T914
Test name
Test status
Simulation time 128038905 ps
CPU time 1.43 seconds
Started Mar 21 01:03:06 PM PDT 24
Finished Mar 21 01:03:08 PM PDT 24
Peak memory 202468 kb
Host smart-b99da088-c4a5-4a97-85f3-6fcb71bec2db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580681969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_c
sr_outstanding.580681969
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1515397615
Short name T870
Test name
Test status
Simulation time 356226970 ps
CPU time 3.67 seconds
Started Mar 21 01:03:02 PM PDT 24
Finished Mar 21 01:03:05 PM PDT 24
Peak memory 202496 kb
Host smart-8f01192b-c7e9-4205-aeac-de126056fa8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1515397615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1515397615
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4036431414
Short name T915
Test name
Test status
Simulation time 471498095 ps
CPU time 4 seconds
Started Mar 21 01:02:59 PM PDT 24
Finished Mar 21 01:03:03 PM PDT 24
Peak memory 202388 kb
Host smart-5ec8fe8c-f220-4fd8-952b-486aa3814822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4036431414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.4036431414
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2688781862
Short name T872
Test name
Test status
Simulation time 82400853 ps
CPU time 1.37 seconds
Started Mar 21 01:03:05 PM PDT 24
Finished Mar 21 01:03:07 PM PDT 24
Peak memory 210784 kb
Host smart-2b673528-5ed3-4bac-b168-d201372ef039
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688781862 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2688781862
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2408080174
Short name T911
Test name
Test status
Simulation time 40500581 ps
CPU time 0.84 seconds
Started Mar 21 01:03:09 PM PDT 24
Finished Mar 21 01:03:10 PM PDT 24
Peak memory 202280 kb
Host smart-3e5ab81d-bbd7-49fb-b79b-844d859aa235
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408080174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2408080174
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.287180372
Short name T243
Test name
Test status
Simulation time 28219556 ps
CPU time 0.62 seconds
Started Mar 21 01:03:08 PM PDT 24
Finished Mar 21 01:03:08 PM PDT 24
Peak memory 202096 kb
Host smart-b11a2706-b9db-44f2-8410-311d00473ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=287180372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.287180372
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3076220686
Short name T894
Test name
Test status
Simulation time 35189238 ps
CPU time 1.01 seconds
Started Mar 21 01:03:16 PM PDT 24
Finished Mar 21 01:03:17 PM PDT 24
Peak memory 202512 kb
Host smart-a6dc408c-f9bf-4427-a575-fde8eaa9f192
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076220686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.3076220686
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.722396306
Short name T904
Test name
Test status
Simulation time 170066681 ps
CPU time 2.03 seconds
Started Mar 21 01:03:06 PM PDT 24
Finished Mar 21 01:03:08 PM PDT 24
Peak memory 202548 kb
Host smart-48c8e6d7-eeb9-4220-a5a4-fdeb8723b378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=722396306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.722396306
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.306963886
Short name T916
Test name
Test status
Simulation time 76185042 ps
CPU time 2.3 seconds
Started Mar 21 01:03:08 PM PDT 24
Finished Mar 21 01:03:10 PM PDT 24
Peak memory 210592 kb
Host smart-6836ef0a-3c6e-41f7-9e1d-64df18c3e1bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306963886 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.306963886
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4103071970
Short name T884
Test name
Test status
Simulation time 26282836 ps
CPU time 0.74 seconds
Started Mar 21 01:03:08 PM PDT 24
Finished Mar 21 01:03:09 PM PDT 24
Peak memory 202096 kb
Host smart-3f326c25-4c24-4caa-b7a9-03fc05e82548
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103071970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4103071970
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3719087354
Short name T878
Test name
Test status
Simulation time 75355227 ps
CPU time 1.02 seconds
Started Mar 21 01:03:15 PM PDT 24
Finished Mar 21 01:03:16 PM PDT 24
Peak memory 202432 kb
Host smart-bde33230-156a-4b54-a44b-4a7976fa9ad3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719087354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.3719087354
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.865947661
Short name T240
Test name
Test status
Simulation time 203655942 ps
CPU time 2.32 seconds
Started Mar 21 01:03:09 PM PDT 24
Finished Mar 21 01:03:11 PM PDT 24
Peak memory 202444 kb
Host smart-e6ace29c-fc03-4e74-8bbf-c600c02572b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=865947661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.865947661
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1606141057
Short name T903
Test name
Test status
Simulation time 244974755 ps
CPU time 2.35 seconds
Started Mar 21 01:03:16 PM PDT 24
Finished Mar 21 01:03:18 PM PDT 24
Peak memory 202368 kb
Host smart-61ad4bdf-bd43-4bfe-9551-e2c2a147d94e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1606141057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1606141057
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2203309244
Short name T869
Test name
Test status
Simulation time 58993477 ps
CPU time 1.9 seconds
Started Mar 21 01:03:11 PM PDT 24
Finished Mar 21 01:03:13 PM PDT 24
Peak memory 210688 kb
Host smart-8b338f22-05ad-4626-afb3-f23b4f74c202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203309244 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.2203309244
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.878291061
Short name T864
Test name
Test status
Simulation time 49240509 ps
CPU time 0.94 seconds
Started Mar 21 01:03:09 PM PDT 24
Finished Mar 21 01:03:10 PM PDT 24
Peak memory 202420 kb
Host smart-04ad0121-ab24-4367-bc60-f00690ed5e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878291061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.878291061
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2799810622
Short name T865
Test name
Test status
Simulation time 97579202 ps
CPU time 1.54 seconds
Started Mar 21 01:03:09 PM PDT 24
Finished Mar 21 01:03:11 PM PDT 24
Peak memory 202532 kb
Host smart-1d88f1ea-d341-48f0-91ca-147d776ba606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799810622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.2799810622
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1916857870
Short name T897
Test name
Test status
Simulation time 67330938 ps
CPU time 1.9 seconds
Started Mar 21 01:03:07 PM PDT 24
Finished Mar 21 01:03:09 PM PDT 24
Peak memory 202456 kb
Host smart-ba7149f2-4061-4b31-85de-0c4c52f271e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1916857870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1916857870
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2320753979
Short name T192
Test name
Test status
Simulation time 453118014 ps
CPU time 4.31 seconds
Started Mar 21 01:03:08 PM PDT 24
Finished Mar 21 01:03:13 PM PDT 24
Peak memory 202548 kb
Host smart-31a122b6-b7ec-4b8d-a4e0-b0cf8ea3254c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2320753979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2320753979
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3063647676
Short name T879
Test name
Test status
Simulation time 70912862 ps
CPU time 2.18 seconds
Started Mar 21 01:03:11 PM PDT 24
Finished Mar 21 01:03:13 PM PDT 24
Peak memory 213268 kb
Host smart-c63d26f5-94ba-43f4-97da-d57eaf660edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063647676 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.3063647676
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1618549857
Short name T874
Test name
Test status
Simulation time 53978442 ps
CPU time 0.89 seconds
Started Mar 21 01:03:07 PM PDT 24
Finished Mar 21 01:03:08 PM PDT 24
Peak memory 202416 kb
Host smart-29d99cf8-ebfe-4240-90f3-c4db2431a952
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618549857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1618549857
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3332240099
Short name T912
Test name
Test status
Simulation time 82612294 ps
CPU time 1.08 seconds
Started Mar 21 01:03:09 PM PDT 24
Finished Mar 21 01:03:10 PM PDT 24
Peak memory 202372 kb
Host smart-0f783aa8-3dc2-4293-b3a4-0e3b9b68a68b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332240099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.3332240099
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.886435088
Short name T880
Test name
Test status
Simulation time 58481920 ps
CPU time 1.82 seconds
Started Mar 21 01:03:09 PM PDT 24
Finished Mar 21 01:03:11 PM PDT 24
Peak memory 202476 kb
Host smart-bee08d5d-42ea-4b14-9ae3-d2679a62ec3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=886435088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.886435088
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3920866088
Short name T258
Test name
Test status
Simulation time 104711861 ps
CPU time 2.02 seconds
Started Mar 21 01:03:11 PM PDT 24
Finished Mar 21 01:03:13 PM PDT 24
Peak memory 202416 kb
Host smart-4d0791c8-1350-45af-9c06-5cad349a88f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3920866088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3920866088
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1159987909
Short name T927
Test name
Test status
Simulation time 143066506 ps
CPU time 1.93 seconds
Started Mar 21 01:03:21 PM PDT 24
Finished Mar 21 01:03:23 PM PDT 24
Peak memory 210836 kb
Host smart-4fe06e44-353e-430a-9418-cd985ff12723
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159987909 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.1159987909
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.626653304
Short name T891
Test name
Test status
Simulation time 24393689 ps
CPU time 0.77 seconds
Started Mar 21 01:03:16 PM PDT 24
Finished Mar 21 01:03:16 PM PDT 24
Peak memory 202308 kb
Host smart-cced96fe-44ec-48eb-95b1-e0eae8ae81db
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626653304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.626653304
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.860397716
Short name T917
Test name
Test status
Simulation time 26314038 ps
CPU time 0.65 seconds
Started Mar 21 01:03:17 PM PDT 24
Finished Mar 21 01:03:18 PM PDT 24
Peak memory 202060 kb
Host smart-f1dfbc33-dace-48bb-b8e5-b31b2fff1705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=860397716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.860397716
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1288286402
Short name T923
Test name
Test status
Simulation time 38442780 ps
CPU time 1.01 seconds
Started Mar 21 01:03:21 PM PDT 24
Finished Mar 21 01:03:22 PM PDT 24
Peak memory 202428 kb
Host smart-a111c5a0-fab8-45d5-847b-e027e1acff11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288286402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.1288286402
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4265372434
Short name T899
Test name
Test status
Simulation time 213844945 ps
CPU time 2.7 seconds
Started Mar 21 01:03:14 PM PDT 24
Finished Mar 21 01:03:17 PM PDT 24
Peak memory 202344 kb
Host smart-05788499-6759-41e3-89cf-f61603300c86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4265372434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4265372434
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.930356670
Short name T919
Test name
Test status
Simulation time 78490001 ps
CPU time 2.54 seconds
Started Mar 21 01:03:15 PM PDT 24
Finished Mar 21 01:03:17 PM PDT 24
Peak memory 210724 kb
Host smart-5fc0c108-69a9-4bf7-9faf-033e45d1f065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930356670 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.930356670
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3604942989
Short name T56
Test name
Test status
Simulation time 31214110 ps
CPU time 0.91 seconds
Started Mar 21 01:03:21 PM PDT 24
Finished Mar 21 01:03:22 PM PDT 24
Peak memory 202520 kb
Host smart-873e4dfb-9041-4856-96aa-4661e7a3f6e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604942989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3604942989
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1500169345
Short name T888
Test name
Test status
Simulation time 39691480 ps
CPU time 0.99 seconds
Started Mar 21 01:03:21 PM PDT 24
Finished Mar 21 01:03:22 PM PDT 24
Peak memory 202460 kb
Host smart-7eeac382-c85e-4e22-a7ad-4d86f401fdab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500169345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.1500169345
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.775720198
Short name T239
Test name
Test status
Simulation time 324609936 ps
CPU time 3.3 seconds
Started Mar 21 01:03:16 PM PDT 24
Finished Mar 21 01:03:19 PM PDT 24
Peak memory 202496 kb
Host smart-cc64250c-7531-4da7-afe7-3ec3cd44e18e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=775720198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.775720198
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2184700316
Short name T189
Test name
Test status
Simulation time 76326579 ps
CPU time 2.3 seconds
Started Mar 21 01:03:13 PM PDT 24
Finished Mar 21 01:03:15 PM PDT 24
Peak memory 210648 kb
Host smart-5ba07fca-b092-49b4-a082-3903fbbb6841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184700316 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.2184700316
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4227213025
Short name T873
Test name
Test status
Simulation time 31424269 ps
CPU time 0.85 seconds
Started Mar 21 01:03:18 PM PDT 24
Finished Mar 21 01:03:19 PM PDT 24
Peak memory 202420 kb
Host smart-cead1f54-f350-4b09-97c2-fce2e51b1e22
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227213025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4227213025
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2603265496
Short name T204
Test name
Test status
Simulation time 38814501 ps
CPU time 0.92 seconds
Started Mar 21 01:03:16 PM PDT 24
Finished Mar 21 01:03:17 PM PDT 24
Peak memory 202496 kb
Host smart-bf5fb6fe-d03a-4c52-89b4-da94a2008868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603265496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.2603265496
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1041618987
Short name T921
Test name
Test status
Simulation time 139395519 ps
CPU time 1.84 seconds
Started Mar 21 01:03:13 PM PDT 24
Finished Mar 21 01:03:15 PM PDT 24
Peak memory 202568 kb
Host smart-767d7047-3f20-4bc8-a167-ec2c4c5c58ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1041618987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1041618987
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2248467452
Short name T890
Test name
Test status
Simulation time 81219988 ps
CPU time 1.34 seconds
Started Mar 21 01:03:22 PM PDT 24
Finished Mar 21 01:03:24 PM PDT 24
Peak memory 202440 kb
Host smart-fa9a14e1-7a67-4fea-94b2-bc6e9cfc6614
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248467452 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.2248467452
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4185320092
Short name T886
Test name
Test status
Simulation time 56647479 ps
CPU time 0.96 seconds
Started Mar 21 01:03:23 PM PDT 24
Finished Mar 21 01:03:24 PM PDT 24
Peak memory 202424 kb
Host smart-10392edd-7dcc-4a6a-ba74-3282a43f20b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185320092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4185320092
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.741353842
Short name T896
Test name
Test status
Simulation time 130717226 ps
CPU time 1.33 seconds
Started Mar 21 01:03:20 PM PDT 24
Finished Mar 21 01:03:21 PM PDT 24
Peak memory 202544 kb
Host smart-7589f74d-3817-4d38-bc45-d99786f08f34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741353842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_c
sr_outstanding.741353842
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1456604593
Short name T49
Test name
Test status
Simulation time 124892049 ps
CPU time 2.04 seconds
Started Mar 21 01:03:21 PM PDT 24
Finished Mar 21 01:03:23 PM PDT 24
Peak memory 202460 kb
Host smart-13b1f08e-bda4-4aba-8dc9-79dc24734cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1456604593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1456604593
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1161572663
Short name T883
Test name
Test status
Simulation time 68062045 ps
CPU time 1.21 seconds
Started Mar 21 01:03:22 PM PDT 24
Finished Mar 21 01:03:23 PM PDT 24
Peak memory 202548 kb
Host smart-5f67461b-8652-4aff-9699-fd87e7741b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161572663 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.1161572663
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2700932657
Short name T931
Test name
Test status
Simulation time 34633360 ps
CPU time 0.8 seconds
Started Mar 21 01:03:23 PM PDT 24
Finished Mar 21 01:03:24 PM PDT 24
Peak memory 202136 kb
Host smart-6a64d16c-1f7d-480b-b6e7-a287ed4bbcaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700932657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2700932657
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4125448576
Short name T889
Test name
Test status
Simulation time 29664256 ps
CPU time 0.68 seconds
Started Mar 21 01:03:21 PM PDT 24
Finished Mar 21 01:03:21 PM PDT 24
Peak memory 202160 kb
Host smart-258bfe30-4751-4431-b9bf-14ea4d29477d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4125448576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4125448576
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2507401073
Short name T54
Test name
Test status
Simulation time 145663052 ps
CPU time 1.48 seconds
Started Mar 21 01:03:22 PM PDT 24
Finished Mar 21 01:03:24 PM PDT 24
Peak memory 202360 kb
Host smart-2ee94fd1-059a-4684-b3e6-7941a4b7af08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507401073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.2507401073
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2123077025
Short name T81
Test name
Test status
Simulation time 245628968 ps
CPU time 2.3 seconds
Started Mar 21 01:03:24 PM PDT 24
Finished Mar 21 01:03:26 PM PDT 24
Peak memory 202460 kb
Host smart-251074a6-d42f-4e2f-a6a4-0acbe9819fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2123077025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2123077025
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3197537482
Short name T926
Test name
Test status
Simulation time 91792666 ps
CPU time 2.38 seconds
Started Mar 21 01:02:47 PM PDT 24
Finished Mar 21 01:02:49 PM PDT 24
Peak memory 202404 kb
Host smart-d07acef5-18c3-4fd9-92c9-e42582925e87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197537482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3197537482
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2878310800
Short name T188
Test name
Test status
Simulation time 124534145 ps
CPU time 1.78 seconds
Started Mar 21 01:02:50 PM PDT 24
Finished Mar 21 01:02:52 PM PDT 24
Peak memory 210688 kb
Host smart-4a55c45d-2763-4a3e-a69b-76da82ae13c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878310800 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.2878310800
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.19548555
Short name T199
Test name
Test status
Simulation time 30371187 ps
CPU time 0.84 seconds
Started Mar 21 01:02:53 PM PDT 24
Finished Mar 21 01:02:54 PM PDT 24
Peak memory 202356 kb
Host smart-4aa5596a-f456-4418-ae0c-4155f7f6ac11
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.19548555
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.822805366
Short name T193
Test name
Test status
Simulation time 88920203 ps
CPU time 1.34 seconds
Started Mar 21 01:02:36 PM PDT 24
Finished Mar 21 01:02:38 PM PDT 24
Peak memory 202320 kb
Host smart-868a8a20-0536-4703-b517-60efa26a8dca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=822805366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.822805366
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2010051270
Short name T901
Test name
Test status
Simulation time 106808028 ps
CPU time 1.35 seconds
Started Mar 21 01:02:56 PM PDT 24
Finished Mar 21 01:02:57 PM PDT 24
Peak memory 202456 kb
Host smart-08b68c74-465e-4c16-98d3-b109134bb2cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010051270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.2010051270
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2879191208
Short name T895
Test name
Test status
Simulation time 87852520 ps
CPU time 2.6 seconds
Started Mar 21 01:02:49 PM PDT 24
Finished Mar 21 01:02:52 PM PDT 24
Peak memory 202496 kb
Host smart-9095519a-b263-4f21-ae94-84fb471c87c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2879191208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2879191208
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4259163555
Short name T866
Test name
Test status
Simulation time 125136804 ps
CPU time 1.82 seconds
Started Mar 21 01:02:57 PM PDT 24
Finished Mar 21 01:02:59 PM PDT 24
Peak memory 202356 kb
Host smart-b8a8a4d5-41ad-4dd4-82f8-baef1766cfba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4259163555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4259163555
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1701883545
Short name T250
Test name
Test status
Simulation time 18903730 ps
CPU time 0.63 seconds
Started Mar 21 01:03:20 PM PDT 24
Finished Mar 21 01:03:21 PM PDT 24
Peak memory 202092 kb
Host smart-6e39a810-5f82-417a-9818-6f1e86a9b54a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1701883545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1701883545
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3087769613
Short name T863
Test name
Test status
Simulation time 121555173 ps
CPU time 1.74 seconds
Started Mar 21 01:02:50 PM PDT 24
Finished Mar 21 01:02:52 PM PDT 24
Peak memory 202420 kb
Host smart-bfdbcbc7-62be-43ed-a56f-6ca572720aaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087769613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3087769613
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1355957313
Short name T887
Test name
Test status
Simulation time 30010586 ps
CPU time 0.73 seconds
Started Mar 21 01:02:56 PM PDT 24
Finished Mar 21 01:02:57 PM PDT 24
Peak memory 202236 kb
Host smart-14331f58-e43a-4ed9-96ff-449fda7d1fb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355957313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1355957313
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2090048472
Short name T868
Test name
Test status
Simulation time 70640783 ps
CPU time 1.18 seconds
Started Mar 21 01:02:44 PM PDT 24
Finished Mar 21 01:02:46 PM PDT 24
Peak memory 210624 kb
Host smart-207d7cba-faa9-4903-84b6-77c41a230ee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090048472 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2090048472
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.741346776
Short name T197
Test name
Test status
Simulation time 44834750 ps
CPU time 0.88 seconds
Started Mar 21 01:02:49 PM PDT 24
Finished Mar 21 01:02:50 PM PDT 24
Peak memory 202420 kb
Host smart-e7bbaf34-b30e-4625-a52b-0396c9b9fc26
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741346776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.741346776
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4233754222
Short name T246
Test name
Test status
Simulation time 24835198 ps
CPU time 0.64 seconds
Started Mar 21 01:03:03 PM PDT 24
Finished Mar 21 01:03:04 PM PDT 24
Peak memory 202376 kb
Host smart-df29996a-0147-4889-891b-27670db15fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4233754222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.4233754222
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2081589116
Short name T202
Test name
Test status
Simulation time 41835198 ps
CPU time 1.34 seconds
Started Mar 21 01:02:47 PM PDT 24
Finished Mar 21 01:02:48 PM PDT 24
Peak memory 202412 kb
Host smart-5df3070d-9ae5-4ddf-84b4-ec68669f0eb3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2081589116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2081589116
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2516722197
Short name T932
Test name
Test status
Simulation time 86816067 ps
CPU time 2.33 seconds
Started Mar 21 01:02:55 PM PDT 24
Finished Mar 21 01:02:57 PM PDT 24
Peak memory 202360 kb
Host smart-27792358-2a57-4233-b8f1-c7182cc1dc26
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2516722197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2516722197
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1223603946
Short name T876
Test name
Test status
Simulation time 30141299 ps
CPU time 0.87 seconds
Started Mar 21 01:02:49 PM PDT 24
Finished Mar 21 01:02:50 PM PDT 24
Peak memory 202492 kb
Host smart-6ca5afec-5aa1-4153-a6db-9276534e756d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223603946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.1223603946
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2738147048
Short name T882
Test name
Test status
Simulation time 80050218 ps
CPU time 2.34 seconds
Started Mar 21 01:03:01 PM PDT 24
Finished Mar 21 01:03:03 PM PDT 24
Peak memory 202472 kb
Host smart-dceabfc8-f808-4d7a-a07b-4408bf421bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2738147048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2738147048
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2486449002
Short name T885
Test name
Test status
Simulation time 23597460 ps
CPU time 0.59 seconds
Started Mar 21 01:03:19 PM PDT 24
Finished Mar 21 01:03:20 PM PDT 24
Peak memory 202168 kb
Host smart-145713f4-fbed-4d4c-b39b-db2263626e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2486449002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2486449002
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3450293844
Short name T63
Test name
Test status
Simulation time 23116952 ps
CPU time 0.67 seconds
Started Mar 21 01:03:27 PM PDT 24
Finished Mar 21 01:03:28 PM PDT 24
Peak memory 202156 kb
Host smart-ea0b85a5-7adb-4c77-9ef0-dfe6ad9e8a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3450293844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3450293844
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.935230934
Short name T247
Test name
Test status
Simulation time 22618743 ps
CPU time 0.64 seconds
Started Mar 21 01:03:23 PM PDT 24
Finished Mar 21 01:03:24 PM PDT 24
Peak memory 202004 kb
Host smart-6fe849d8-224b-4b8b-9405-12f67a34590b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=935230934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.935230934
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.4279004131
Short name T924
Test name
Test status
Simulation time 56514850 ps
CPU time 1.58 seconds
Started Mar 21 01:02:45 PM PDT 24
Finished Mar 21 01:02:47 PM PDT 24
Peak memory 202436 kb
Host smart-44da8daa-ed6b-4e80-948c-4c48bc1399ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279004131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.4279004131
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1977907789
Short name T195
Test name
Test status
Simulation time 379328784 ps
CPU time 3.47 seconds
Started Mar 21 01:02:48 PM PDT 24
Finished Mar 21 01:02:51 PM PDT 24
Peak memory 202412 kb
Host smart-e888dc22-2545-43c4-92b2-0fdaddd071cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977907789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1977907789
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2483345729
Short name T190
Test name
Test status
Simulation time 85362696 ps
CPU time 1.22 seconds
Started Mar 21 01:02:51 PM PDT 24
Finished Mar 21 01:02:53 PM PDT 24
Peak memory 202572 kb
Host smart-39f98516-46c6-4c27-a32c-3df2a0bfc3fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483345729 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2483345729
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1501891477
Short name T922
Test name
Test status
Simulation time 30529959 ps
CPU time 0.72 seconds
Started Mar 21 01:02:45 PM PDT 24
Finished Mar 21 01:02:46 PM PDT 24
Peak memory 202176 kb
Host smart-e2aa59f1-ab6a-494b-a8a6-5dfe4d48d9e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501891477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1501891477
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3060544020
Short name T875
Test name
Test status
Simulation time 86369834 ps
CPU time 1.39 seconds
Started Mar 21 01:02:52 PM PDT 24
Finished Mar 21 01:02:54 PM PDT 24
Peak memory 202400 kb
Host smart-a9893d6b-c659-48d4-96f6-a9be2c34ed8b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3060544020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3060544020
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.764874608
Short name T862
Test name
Test status
Simulation time 103433958 ps
CPU time 1.24 seconds
Started Mar 21 01:02:46 PM PDT 24
Finished Mar 21 01:02:47 PM PDT 24
Peak memory 202504 kb
Host smart-b975a04e-862a-4bd7-ad3a-3f1c05672bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764874608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_cs
r_outstanding.764874608
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.377298094
Short name T902
Test name
Test status
Simulation time 272499752 ps
CPU time 2.59 seconds
Started Mar 21 01:02:57 PM PDT 24
Finished Mar 21 01:03:00 PM PDT 24
Peak memory 202396 kb
Host smart-078c5c42-8c71-490e-904e-05123dc4b923
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=377298094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.377298094
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3632737739
Short name T256
Test name
Test status
Simulation time 223734359 ps
CPU time 2.3 seconds
Started Mar 21 01:02:47 PM PDT 24
Finished Mar 21 01:02:49 PM PDT 24
Peak memory 202436 kb
Host smart-b7a4c227-950e-435a-a486-17b961e300df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3632737739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3632737739
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3170628252
Short name T249
Test name
Test status
Simulation time 27127869 ps
CPU time 0.67 seconds
Started Mar 21 01:03:22 PM PDT 24
Finished Mar 21 01:03:23 PM PDT 24
Peak memory 202080 kb
Host smart-942381e4-46b2-44a7-ae33-a494931dd015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3170628252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3170628252
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3998714736
Short name T62
Test name
Test status
Simulation time 25911049 ps
CPU time 0.65 seconds
Started Mar 21 01:03:42 PM PDT 24
Finished Mar 21 01:03:43 PM PDT 24
Peak memory 202156 kb
Host smart-c7d43250-8f04-4b91-845e-2d69372d18db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3998714736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3998714736
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3516212415
Short name T907
Test name
Test status
Simulation time 133401624 ps
CPU time 1.59 seconds
Started Mar 21 01:03:06 PM PDT 24
Finished Mar 21 01:03:08 PM PDT 24
Peak memory 212172 kb
Host smart-c95f384e-6da5-4305-b758-0d41f6ad688e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516212415 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.3516212415
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.49562830
Short name T900
Test name
Test status
Simulation time 56161694 ps
CPU time 0.91 seconds
Started Mar 21 01:03:08 PM PDT 24
Finished Mar 21 01:03:09 PM PDT 24
Peak memory 202456 kb
Host smart-4d95211a-3dd3-4171-bb31-85c12421e76b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49562830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.49562830
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4132312242
Short name T80
Test name
Test status
Simulation time 77016128 ps
CPU time 1 seconds
Started Mar 21 01:02:58 PM PDT 24
Finished Mar 21 01:03:00 PM PDT 24
Peak memory 202476 kb
Host smart-45d81d04-a09a-4c07-bd19-3c358a33bbe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132312242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.4132312242
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1985480239
Short name T881
Test name
Test status
Simulation time 66718735 ps
CPU time 2.06 seconds
Started Mar 21 01:02:48 PM PDT 24
Finished Mar 21 01:02:50 PM PDT 24
Peak memory 202364 kb
Host smart-32379855-be62-44c3-a711-5c0a2aee6cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1985480239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1985480239
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1479447581
Short name T191
Test name
Test status
Simulation time 212770566 ps
CPU time 2.09 seconds
Started Mar 21 01:02:56 PM PDT 24
Finished Mar 21 01:02:59 PM PDT 24
Peak memory 202444 kb
Host smart-847a2fb4-9daa-4b6e-9777-e459c4eeaea2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1479447581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1479447581
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3983741195
Short name T867
Test name
Test status
Simulation time 76800872 ps
CPU time 2.45 seconds
Started Mar 21 01:03:00 PM PDT 24
Finished Mar 21 01:03:03 PM PDT 24
Peak memory 210672 kb
Host smart-cd867c4a-4522-468a-b038-d1b9a621b0e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983741195 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3983741195
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3272412006
Short name T78
Test name
Test status
Simulation time 50829643 ps
CPU time 0.98 seconds
Started Mar 21 01:03:04 PM PDT 24
Finished Mar 21 01:03:05 PM PDT 24
Peak memory 202472 kb
Host smart-f04ccfca-068b-4a95-bc64-a81b296f455b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272412006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3272412006
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2523672468
Short name T248
Test name
Test status
Simulation time 28864113 ps
CPU time 0.65 seconds
Started Mar 21 01:02:58 PM PDT 24
Finished Mar 21 01:02:59 PM PDT 24
Peak memory 202160 kb
Host smart-1e2b9aec-8b37-46f7-998b-d04c8e387885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2523672468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2523672468
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3085030113
Short name T928
Test name
Test status
Simulation time 41625163 ps
CPU time 1.01 seconds
Started Mar 21 01:02:58 PM PDT 24
Finished Mar 21 01:03:00 PM PDT 24
Peak memory 202436 kb
Host smart-c349e384-ed6b-4970-bf5e-23d5a7283de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085030113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.3085030113
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3358605687
Short name T238
Test name
Test status
Simulation time 262980547 ps
CPU time 2.85 seconds
Started Mar 21 01:02:58 PM PDT 24
Finished Mar 21 01:03:00 PM PDT 24
Peak memory 202420 kb
Host smart-9270c0de-1dba-4754-8af0-957fb3ee795f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3358605687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3358605687
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1999696304
Short name T905
Test name
Test status
Simulation time 213446655 ps
CPU time 2.24 seconds
Started Mar 21 01:03:15 PM PDT 24
Finished Mar 21 01:03:17 PM PDT 24
Peak memory 202484 kb
Host smart-0f947c40-349d-402a-9e5f-55076105955f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1999696304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1999696304
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.159069124
Short name T906
Test name
Test status
Simulation time 148507391 ps
CPU time 1.92 seconds
Started Mar 21 01:02:58 PM PDT 24
Finished Mar 21 01:03:01 PM PDT 24
Peak memory 210768 kb
Host smart-20d81ec2-2d6a-4611-ab6b-b5bd8f9fcf82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159069124 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.159069124
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.19321198
Short name T79
Test name
Test status
Simulation time 55493245 ps
CPU time 0.88 seconds
Started Mar 21 01:02:58 PM PDT 24
Finished Mar 21 01:03:00 PM PDT 24
Peak memory 202352 kb
Host smart-c899d645-d735-4f92-a0db-1f57f0d433ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19321198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.19321198
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1085078606
Short name T252
Test name
Test status
Simulation time 18956032 ps
CPU time 0.64 seconds
Started Mar 21 01:03:05 PM PDT 24
Finished Mar 21 01:03:06 PM PDT 24
Peak memory 202104 kb
Host smart-cf4aad87-9bca-4404-b543-391d2ab7077c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1085078606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1085078606
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.989482401
Short name T918
Test name
Test status
Simulation time 81613431 ps
CPU time 0.98 seconds
Started Mar 21 01:02:56 PM PDT 24
Finished Mar 21 01:02:57 PM PDT 24
Peak memory 202412 kb
Host smart-b4bb38ae-6ba1-4003-bb66-9d438035f3ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989482401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_cs
r_outstanding.989482401
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3273603733
Short name T237
Test name
Test status
Simulation time 125649633 ps
CPU time 1.55 seconds
Started Mar 21 01:03:07 PM PDT 24
Finished Mar 21 01:03:08 PM PDT 24
Peak memory 202580 kb
Host smart-ae562f70-71d1-436a-bde0-ec88d523f624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3273603733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3273603733
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1392526751
Short name T244
Test name
Test status
Simulation time 133570056 ps
CPU time 1.76 seconds
Started Mar 21 01:02:59 PM PDT 24
Finished Mar 21 01:03:01 PM PDT 24
Peak memory 210748 kb
Host smart-ac131cd8-919d-4467-882e-6ef52064cc41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392526751 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.1392526751
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1030102341
Short name T55
Test name
Test status
Simulation time 45832725 ps
CPU time 0.88 seconds
Started Mar 21 01:03:00 PM PDT 24
Finished Mar 21 01:03:01 PM PDT 24
Peak memory 202428 kb
Host smart-f5f2ab78-562f-427a-a6dc-7f16866983e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030102341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1030102341
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2782620358
Short name T910
Test name
Test status
Simulation time 63231044 ps
CPU time 0.98 seconds
Started Mar 21 01:02:59 PM PDT 24
Finished Mar 21 01:03:00 PM PDT 24
Peak memory 202388 kb
Host smart-f6beee41-609b-41eb-9151-c80203e2fc44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782620358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.2782620358
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1661523040
Short name T187
Test name
Test status
Simulation time 108933137 ps
CPU time 1.48 seconds
Started Mar 21 01:03:05 PM PDT 24
Finished Mar 21 01:03:06 PM PDT 24
Peak memory 202472 kb
Host smart-74e53bbe-f370-4030-a907-3acfe3286150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1661523040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1661523040
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3664269660
Short name T929
Test name
Test status
Simulation time 428877457 ps
CPU time 3.92 seconds
Started Mar 21 01:02:59 PM PDT 24
Finished Mar 21 01:03:03 PM PDT 24
Peak memory 202516 kb
Host smart-1039adc4-6ec9-4252-9d19-72834186d394
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3664269660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3664269660
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2965030024
Short name T241
Test name
Test status
Simulation time 51842109 ps
CPU time 1.53 seconds
Started Mar 21 01:02:58 PM PDT 24
Finished Mar 21 01:03:00 PM PDT 24
Peak memory 210700 kb
Host smart-1ac489c6-7377-4384-b7e3-d4b6240af9e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965030024 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2965030024
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3661932700
Short name T203
Test name
Test status
Simulation time 52608072 ps
CPU time 0.87 seconds
Started Mar 21 01:03:15 PM PDT 24
Finished Mar 21 01:03:16 PM PDT 24
Peak memory 202492 kb
Host smart-4a3243b4-4ee3-4bf4-9ab0-ffbef620c0f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661932700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3661932700
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.841002513
Short name T908
Test name
Test status
Simulation time 52748186 ps
CPU time 1.34 seconds
Started Mar 21 01:03:00 PM PDT 24
Finished Mar 21 01:03:02 PM PDT 24
Peak memory 202424 kb
Host smart-4eefa600-9805-43c5-b128-fd51298d38f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841002513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_cs
r_outstanding.841002513
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4097849254
Short name T184
Test name
Test status
Simulation time 46546258 ps
CPU time 1.56 seconds
Started Mar 21 01:03:00 PM PDT 24
Finished Mar 21 01:03:02 PM PDT 24
Peak memory 202452 kb
Host smart-2efadd62-b89f-4b15-9013-70ffcb936a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4097849254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4097849254
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.325879044
Short name T261
Test name
Test status
Simulation time 460321109 ps
CPU time 4.05 seconds
Started Mar 21 01:03:16 PM PDT 24
Finished Mar 21 01:03:20 PM PDT 24
Peak memory 201920 kb
Host smart-57cf7c53-04b7-4c5c-9bb5-fe00c0b5bac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=325879044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.325879044
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1168793562
Short name T514
Test name
Test status
Simulation time 8370925173 ps
CPU time 9.6 seconds
Started Mar 21 01:22:43 PM PDT 24
Finished Mar 21 01:22:53 PM PDT 24
Peak memory 203460 kb
Host smart-d1305b13-a292-4b77-9f8e-fe9570813a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11687
93562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1168793562
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.3990831605
Short name T235
Test name
Test status
Simulation time 8372140678 ps
CPU time 7.14 seconds
Started Mar 21 01:22:41 PM PDT 24
Finished Mar 21 01:22:48 PM PDT 24
Peak memory 203448 kb
Host smart-83635c5c-2b81-43d9-b18e-f87551bf9f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39908
31605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3990831605
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3850112864
Short name T691
Test name
Test status
Simulation time 168779111 ps
CPU time 1.49 seconds
Started Mar 21 01:22:44 PM PDT 24
Finished Mar 21 01:22:47 PM PDT 24
Peak memory 203524 kb
Host smart-53d55683-1fee-4dfd-bd21-6441184eb1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38501
12864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3850112864
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1283198676
Short name T418
Test name
Test status
Simulation time 8362152111 ps
CPU time 6.83 seconds
Started Mar 21 01:22:41 PM PDT 24
Finished Mar 21 01:22:48 PM PDT 24
Peak memory 203468 kb
Host smart-4a6ebeed-b100-4ccd-ae63-3e165cb72848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12831
98676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1283198676
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1899532647
Short name T568
Test name
Test status
Simulation time 8405805893 ps
CPU time 7.95 seconds
Started Mar 21 01:22:46 PM PDT 24
Finished Mar 21 01:22:54 PM PDT 24
Peak memory 203472 kb
Host smart-acae3f83-c8ad-4778-8b09-4067a627fd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18995
32647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1899532647
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3450139030
Short name T745
Test name
Test status
Simulation time 8410968465 ps
CPU time 7.81 seconds
Started Mar 21 01:22:49 PM PDT 24
Finished Mar 21 01:22:57 PM PDT 24
Peak memory 203564 kb
Host smart-d8d1b158-7dc6-4ed2-b01d-4546552e9aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34501
39030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3450139030
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.4141225526
Short name T30
Test name
Test status
Simulation time 8369245027 ps
CPU time 8.85 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:23:04 PM PDT 24
Peak memory 203280 kb
Host smart-c10bc208-e833-4f7e-9842-3cd839d64c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41412
25526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.4141225526
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3576392817
Short name T849
Test name
Test status
Simulation time 8404009504 ps
CPU time 7.62 seconds
Started Mar 21 01:22:49 PM PDT 24
Finished Mar 21 01:22:57 PM PDT 24
Peak memory 203336 kb
Host smart-07a2d8ff-fbcc-43b4-acb1-d485b2064a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35763
92817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3576392817
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2353625434
Short name T789
Test name
Test status
Simulation time 8385628121 ps
CPU time 7.28 seconds
Started Mar 21 01:22:44 PM PDT 24
Finished Mar 21 01:22:52 PM PDT 24
Peak memory 203264 kb
Host smart-57ce111b-9ed6-4f93-b208-3c908e8dfba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23536
25434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2353625434
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1188069317
Short name T32
Test name
Test status
Simulation time 25649175 ps
CPU time 0.64 seconds
Started Mar 21 01:22:51 PM PDT 24
Finished Mar 21 01:22:52 PM PDT 24
Peak memory 202900 kb
Host smart-5dcd2995-de40-40b5-8207-af196ce605ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11880
69317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1188069317
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2217627043
Short name T840
Test name
Test status
Simulation time 8382521699 ps
CPU time 8.13 seconds
Started Mar 21 01:22:52 PM PDT 24
Finished Mar 21 01:23:00 PM PDT 24
Peak memory 203540 kb
Host smart-5afa898c-cc9b-484c-ab13-a98f9f4ad1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22176
27043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2217627043
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1713828814
Short name T585
Test name
Test status
Simulation time 8443768945 ps
CPU time 8.66 seconds
Started Mar 21 01:22:46 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 203428 kb
Host smart-bdae4860-1b14-4ffe-af0d-02cc613ebec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17138
28814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1713828814
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.4091404219
Short name T476
Test name
Test status
Simulation time 8386162123 ps
CPU time 7.85 seconds
Started Mar 21 01:22:51 PM PDT 24
Finished Mar 21 01:22:59 PM PDT 24
Peak memory 203552 kb
Host smart-c4a09e70-0c9a-4014-8c3f-5b12e64b3a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40914
04219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.4091404219
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3027750562
Short name T64
Test name
Test status
Simulation time 85001900 ps
CPU time 0.87 seconds
Started Mar 21 01:22:50 PM PDT 24
Finished Mar 21 01:22:51 PM PDT 24
Peak memory 219164 kb
Host smart-79f23e69-b0d6-4c84-8a5a-567c243c0f6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3027750562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3027750562
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1236522707
Short name T541
Test name
Test status
Simulation time 8355704808 ps
CPU time 9.13 seconds
Started Mar 21 01:22:47 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 203428 kb
Host smart-5acaab1f-babd-4c90-8f47-593ebc914d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12365
22707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1236522707
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1110337867
Short name T681
Test name
Test status
Simulation time 8475072899 ps
CPU time 7.79 seconds
Started Mar 21 01:22:43 PM PDT 24
Finished Mar 21 01:22:52 PM PDT 24
Peak memory 203632 kb
Host smart-ef22b306-4589-4adc-9799-3954e36b4ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11103
37867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1110337867
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.89980367
Short name T643
Test name
Test status
Simulation time 8367214861 ps
CPU time 7.61 seconds
Started Mar 21 01:22:38 PM PDT 24
Finished Mar 21 01:22:46 PM PDT 24
Peak memory 203512 kb
Host smart-7f11d6ae-d766-42c9-9175-f9639ac0fe48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89980
367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.89980367
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_enable.2299552386
Short name T772
Test name
Test status
Simulation time 8375413380 ps
CPU time 7.17 seconds
Started Mar 21 01:22:45 PM PDT 24
Finished Mar 21 01:22:52 PM PDT 24
Peak memory 203464 kb
Host smart-5b3f302d-0bbe-47c8-8c22-b628c90a679c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22995
52386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2299552386
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1434386781
Short name T216
Test name
Test status
Simulation time 75989197 ps
CPU time 1.11 seconds
Started Mar 21 01:22:39 PM PDT 24
Finished Mar 21 01:22:40 PM PDT 24
Peak memory 203412 kb
Host smart-67c69aac-4205-45ba-a546-4db05bdc72ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14343
86781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1434386781
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1074365199
Short name T777
Test name
Test status
Simulation time 8413062358 ps
CPU time 9.44 seconds
Started Mar 21 01:22:40 PM PDT 24
Finished Mar 21 01:22:50 PM PDT 24
Peak memory 203452 kb
Host smart-3f144153-82df-4344-a2f2-06f377d7e134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10743
65199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1074365199
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.4025788354
Short name T347
Test name
Test status
Simulation time 8362141554 ps
CPU time 7.65 seconds
Started Mar 21 01:22:50 PM PDT 24
Finished Mar 21 01:22:57 PM PDT 24
Peak memory 203388 kb
Host smart-a3be4619-ca2b-4761-8100-bdebfbcb6c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40257
88354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.4025788354
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.941526752
Short name T589
Test name
Test status
Simulation time 8398037562 ps
CPU time 7.53 seconds
Started Mar 21 01:22:41 PM PDT 24
Finished Mar 21 01:22:49 PM PDT 24
Peak memory 203248 kb
Host smart-2e2f9355-69fb-4e22-a91f-c7d8e6dd7870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94152
6752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.941526752
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.497414659
Short name T754
Test name
Test status
Simulation time 8372369119 ps
CPU time 7.18 seconds
Started Mar 21 01:22:41 PM PDT 24
Finished Mar 21 01:22:49 PM PDT 24
Peak memory 203376 kb
Host smart-b93c4381-9654-4da8-9f23-9e0065e9208a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49741
4659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.497414659
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3142154335
Short name T3
Test name
Test status
Simulation time 25339006 ps
CPU time 0.64 seconds
Started Mar 21 01:22:47 PM PDT 24
Finished Mar 21 01:22:48 PM PDT 24
Peak memory 202840 kb
Host smart-d71c0b3f-934e-4f20-be9e-af9eed4d390e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31421
54335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3142154335
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.4094446833
Short name T408
Test name
Test status
Simulation time 8405709785 ps
CPU time 7.78 seconds
Started Mar 21 01:22:42 PM PDT 24
Finished Mar 21 01:22:50 PM PDT 24
Peak memory 203528 kb
Host smart-e51be783-9551-4f65-957c-5f8e393f9953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
46833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.4094446833
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2413219061
Short name T778
Test name
Test status
Simulation time 8386673778 ps
CPU time 6.94 seconds
Started Mar 21 01:22:52 PM PDT 24
Finished Mar 21 01:22:59 PM PDT 24
Peak memory 203504 kb
Host smart-a849d88a-90ac-4a72-bad0-70a32f06edf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24132
19061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2413219061
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.3442421703
Short name T366
Test name
Test status
Simulation time 8408572478 ps
CPU time 7.56 seconds
Started Mar 21 01:22:47 PM PDT 24
Finished Mar 21 01:22:55 PM PDT 24
Peak memory 203420 kb
Host smart-5150b719-a073-408a-bf0e-2d7998e14217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
21703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.3442421703
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2121705898
Short name T591
Test name
Test status
Simulation time 8369081033 ps
CPU time 8.82 seconds
Started Mar 21 01:23:44 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203520 kb
Host smart-d1cd833e-e5cc-494a-9ab4-244d27a8d707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
05898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2121705898
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.1118722961
Short name T509
Test name
Test status
Simulation time 8371538520 ps
CPU time 7.81 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203456 kb
Host smart-52dccbd6-0d27-405e-8c90-91b797261d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11187
22961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1118722961
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3978012410
Short name T770
Test name
Test status
Simulation time 124508225 ps
CPU time 1.2 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:40 PM PDT 24
Peak memory 203208 kb
Host smart-7d17b856-d158-48c9-8766-0785a81d27ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39780
12410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3978012410
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2476365733
Short name T733
Test name
Test status
Simulation time 8376061046 ps
CPU time 8.78 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203432 kb
Host smart-09506723-5a80-4368-9774-cc5b36233e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24763
65733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2476365733
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1515837873
Short name T560
Test name
Test status
Simulation time 8409026100 ps
CPU time 8.53 seconds
Started Mar 21 01:23:36 PM PDT 24
Finished Mar 21 01:23:45 PM PDT 24
Peak memory 203468 kb
Host smart-3f20e4d7-5e8a-43e9-8fb2-9c4f5c9d85e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15158
37873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1515837873
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3576739938
Short name T339
Test name
Test status
Simulation time 8362353676 ps
CPU time 7.13 seconds
Started Mar 21 01:23:41 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203384 kb
Host smart-8d337535-d203-4e28-82c6-a843ddbfbaf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767
39938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3576739938
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1087707691
Short name T99
Test name
Test status
Simulation time 8442927782 ps
CPU time 7.5 seconds
Started Mar 21 01:23:45 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203512 kb
Host smart-8a377bd9-c3fb-469e-a6b9-a8c0f5544d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10877
07691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1087707691
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2126482131
Short name T798
Test name
Test status
Simulation time 8395212184 ps
CPU time 7.39 seconds
Started Mar 21 01:23:42 PM PDT 24
Finished Mar 21 01:23:49 PM PDT 24
Peak memory 203236 kb
Host smart-8e97d7b9-a84a-4f83-ba10-fc0eb5714589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21264
82131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2126482131
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2771744011
Short name T290
Test name
Test status
Simulation time 8390551522 ps
CPU time 9.49 seconds
Started Mar 21 01:23:39 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203300 kb
Host smart-91c29cd2-7e2b-4d6f-903c-ef3fa4031dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27717
44011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2771744011
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.4176960648
Short name T820
Test name
Test status
Simulation time 24952370 ps
CPU time 0.63 seconds
Started Mar 21 01:23:41 PM PDT 24
Finished Mar 21 01:23:41 PM PDT 24
Peak memory 202960 kb
Host smart-a45d74b5-c122-4f11-9815-8d1ba2cfb67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41769
60648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.4176960648
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2823502657
Short name T617
Test name
Test status
Simulation time 8404562967 ps
CPU time 7.6 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203464 kb
Host smart-65db41be-8945-4e88-95a8-c10aa2d070a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28235
02657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2823502657
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.502652217
Short name T112
Test name
Test status
Simulation time 8430116417 ps
CPU time 7.17 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:45 PM PDT 24
Peak memory 203480 kb
Host smart-97f5e43c-a3ca-4637-b3f1-d07fa67dc093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50265
2217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.502652217
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2235648470
Short name T573
Test name
Test status
Simulation time 8377559366 ps
CPU time 6.96 seconds
Started Mar 21 01:23:42 PM PDT 24
Finished Mar 21 01:23:49 PM PDT 24
Peak memory 203560 kb
Host smart-adc4cb90-8ad3-4061-8411-dcdb8a8d7a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22356
48470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2235648470
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1931245803
Short name T587
Test name
Test status
Simulation time 8356181439 ps
CPU time 8.14 seconds
Started Mar 21 01:23:36 PM PDT 24
Finished Mar 21 01:23:44 PM PDT 24
Peak memory 203368 kb
Host smart-0be7397e-6a98-4d41-b55f-0f3eda7893bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19312
45803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1931245803
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3162801138
Short name T635
Test name
Test status
Simulation time 8475147999 ps
CPU time 7.15 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:45 PM PDT 24
Peak memory 203580 kb
Host smart-87ca3ac9-3920-4455-9f3b-31fc8c950b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31628
01138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3162801138
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1360541768
Short name T685
Test name
Test status
Simulation time 8367921639 ps
CPU time 8.84 seconds
Started Mar 21 01:23:41 PM PDT 24
Finished Mar 21 01:23:50 PM PDT 24
Peak memory 203532 kb
Host smart-54bf7eb0-edd7-4a4f-9ff8-8818b5c0983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13605
41768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1360541768
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.608626666
Short name T858
Test name
Test status
Simulation time 8370519859 ps
CPU time 7.29 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203528 kb
Host smart-f8058f64-79ec-4fb4-bce4-e3f0063310a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60862
6666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.608626666
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2609664006
Short name T554
Test name
Test status
Simulation time 85126399 ps
CPU time 1.19 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203280 kb
Host smart-bdeb7804-219e-4e8d-ab96-972360a8251d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26096
64006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2609664006
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3970918794
Short name T539
Test name
Test status
Simulation time 8363398718 ps
CPU time 8 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:23 PM PDT 24
Peak memory 203268 kb
Host smart-d88ac5be-05c4-478e-b8c1-105851a1b4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39709
18794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3970918794
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.4216188046
Short name T780
Test name
Test status
Simulation time 8417934155 ps
CPU time 7.29 seconds
Started Mar 21 01:23:40 PM PDT 24
Finished Mar 21 01:23:47 PM PDT 24
Peak memory 203488 kb
Host smart-bb31de78-ac40-46d3-acc4-f3feda3f0028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42161
88046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.4216188046
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1412680448
Short name T575
Test name
Test status
Simulation time 8410198946 ps
CPU time 9.64 seconds
Started Mar 21 01:24:03 PM PDT 24
Finished Mar 21 01:24:13 PM PDT 24
Peak memory 203544 kb
Host smart-e282682a-90ae-468f-bfe9-a3f2129def00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14126
80448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1412680448
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2630311692
Short name T332
Test name
Test status
Simulation time 8365622879 ps
CPU time 7.29 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203248 kb
Host smart-172c49b7-b451-4e13-bfed-4f0b919490f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26303
11692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2630311692
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1486410996
Short name T9
Test name
Test status
Simulation time 8395227429 ps
CPU time 7.19 seconds
Started Mar 21 01:23:45 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203420 kb
Host smart-f715e856-27e8-4bee-84eb-84eac623b237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14864
10996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1486410996
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2375621140
Short name T453
Test name
Test status
Simulation time 8400192489 ps
CPU time 8.85 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203196 kb
Host smart-740f6d0a-15fe-445e-b703-7f50c8464629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23756
21140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2375621140
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.981361935
Short name T781
Test name
Test status
Simulation time 29176656 ps
CPU time 0.65 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:47 PM PDT 24
Peak memory 202992 kb
Host smart-f33c0248-b8c2-4b3a-ab1d-1005abeec6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98136
1935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.981361935
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3987287334
Short name T308
Test name
Test status
Simulation time 8391285878 ps
CPU time 6.84 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203504 kb
Host smart-29d0f229-eabb-4d63-8f29-21cf815f362d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39872
87334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3987287334
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2381876804
Short name T128
Test name
Test status
Simulation time 8442894081 ps
CPU time 7.53 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203504 kb
Host smart-eecd7eab-c42f-492c-b82d-d60f01c5e607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23818
76804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2381876804
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.1466311603
Short name T755
Test name
Test status
Simulation time 8370207413 ps
CPU time 7.14 seconds
Started Mar 21 01:23:53 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203320 kb
Host smart-578ea3fd-3c3c-4358-a812-8cae9e378514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14663
11603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.1466311603
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.161556928
Short name T436
Test name
Test status
Simulation time 8357430974 ps
CPU time 6.97 seconds
Started Mar 21 01:23:56 PM PDT 24
Finished Mar 21 01:24:04 PM PDT 24
Peak memory 203268 kb
Host smart-6505d00a-f043-46a1-aa32-8060547148a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16155
6928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.161556928
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3026054266
Short name T336
Test name
Test status
Simulation time 8371793876 ps
CPU time 9.4 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203420 kb
Host smart-965f8c6e-2106-42a8-af2e-8d18a827d4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30260
54266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3026054266
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.3865859303
Short name T674
Test name
Test status
Simulation time 8369842310 ps
CPU time 7.53 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203512 kb
Host smart-45e64fa5-a6e1-492e-a88e-db47e5677383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38658
59303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3865859303
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3041889075
Short name T224
Test name
Test status
Simulation time 179979105 ps
CPU time 1.9 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203524 kb
Host smart-efacd180-02d2-40d5-815d-7b66712e745e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30418
89075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3041889075
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.271292558
Short name T592
Test name
Test status
Simulation time 8405397963 ps
CPU time 7.82 seconds
Started Mar 21 01:23:42 PM PDT 24
Finished Mar 21 01:23:49 PM PDT 24
Peak memory 203356 kb
Host smart-dd02cab8-59c5-48ad-aa1e-f57361b9f185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27129
2558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.271292558
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.745559290
Short name T534
Test name
Test status
Simulation time 8409264676 ps
CPU time 7.69 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203572 kb
Host smart-0d474e83-21e2-4075-b03f-1804d4462001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74555
9290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.745559290
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2906562619
Short name T818
Test name
Test status
Simulation time 8366778184 ps
CPU time 7.64 seconds
Started Mar 21 01:23:53 PM PDT 24
Finished Mar 21 01:24:01 PM PDT 24
Peak memory 203296 kb
Host smart-bcf05c5f-0028-4083-90d2-9f5bc6af62bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
62619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2906562619
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.642079900
Short name T716
Test name
Test status
Simulation time 8378461108 ps
CPU time 7.51 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203248 kb
Host smart-71fa6bfb-8cd3-43db-83fa-34f21bead4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64207
9900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.642079900
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2285642821
Short name T356
Test name
Test status
Simulation time 8392449531 ps
CPU time 7.44 seconds
Started Mar 21 01:23:57 PM PDT 24
Finished Mar 21 01:24:05 PM PDT 24
Peak memory 203432 kb
Host smart-5dca01f9-af4b-42ee-ab1e-22ec62da9f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22856
42821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2285642821
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3975058655
Short name T374
Test name
Test status
Simulation time 8398678446 ps
CPU time 7.02 seconds
Started Mar 21 01:23:45 PM PDT 24
Finished Mar 21 01:23:52 PM PDT 24
Peak memory 203456 kb
Host smart-25343b7a-bef3-4b48-81dc-109240d65810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39750
58655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3975058655
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1386017822
Short name T590
Test name
Test status
Simulation time 8373638143 ps
CPU time 7.53 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203588 kb
Host smart-51e037ef-826f-46c7-9a25-24d8ecacc97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
17822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1386017822
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.431162298
Short name T406
Test name
Test status
Simulation time 8355501071 ps
CPU time 7.23 seconds
Started Mar 21 01:23:58 PM PDT 24
Finished Mar 21 01:24:05 PM PDT 24
Peak memory 203376 kb
Host smart-d1e2531c-93e5-4417-ac80-d95fa3946cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43116
2298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.431162298
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.4045897015
Short name T660
Test name
Test status
Simulation time 8476095935 ps
CPU time 7.72 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203568 kb
Host smart-ba13f593-1e23-48d2-9062-bc352625e987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40458
97015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.4045897015
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1492914636
Short name T650
Test name
Test status
Simulation time 8373605614 ps
CPU time 7.53 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203576 kb
Host smart-01185f1f-7554-4a11-975d-571ea3e5a16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14929
14636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1492914636
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.1122354894
Short name T228
Test name
Test status
Simulation time 8369856272 ps
CPU time 7.18 seconds
Started Mar 21 01:23:56 PM PDT 24
Finished Mar 21 01:24:03 PM PDT 24
Peak memory 203520 kb
Host smart-dbfbd605-284d-41c2-bcef-ca3ab475a667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11223
54894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1122354894
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.297091418
Short name T412
Test name
Test status
Simulation time 158170494 ps
CPU time 1.79 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:52 PM PDT 24
Peak memory 203452 kb
Host smart-d8574ce2-df7c-4165-bb1c-4ac04ced28f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29709
1418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.297091418
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.573290171
Short name T154
Test name
Test status
Simulation time 8363093292 ps
CPU time 7.51 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203264 kb
Host smart-1200fc87-6538-4971-a56f-11f97e7da55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57329
0171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.573290171
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3982883090
Short name T850
Test name
Test status
Simulation time 8406473349 ps
CPU time 7.21 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203516 kb
Host smart-064493b8-5b9f-457b-8951-a88abbc9bf96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39828
83090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3982883090
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3350957343
Short name T711
Test name
Test status
Simulation time 8407606373 ps
CPU time 7.37 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203544 kb
Host smart-efa8bdf1-e647-40c6-9245-f1f02c3ad4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33509
57343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3350957343
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1771443049
Short name T416
Test name
Test status
Simulation time 8364443363 ps
CPU time 7.42 seconds
Started Mar 21 01:24:09 PM PDT 24
Finished Mar 21 01:24:17 PM PDT 24
Peak memory 203264 kb
Host smart-12cf03bc-9901-498b-82ec-2bb8e431c057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714
43049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1771443049
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.127368764
Short name T614
Test name
Test status
Simulation time 8435019279 ps
CPU time 7.39 seconds
Started Mar 21 01:23:41 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203424 kb
Host smart-54f1ca88-f01b-4924-aa6f-d7af56c5e073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12736
8764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.127368764
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.898148093
Short name T491
Test name
Test status
Simulation time 8393603509 ps
CPU time 7.65 seconds
Started Mar 21 01:23:45 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203276 kb
Host smart-d32f084e-11f6-4e98-b441-d2f97d6a6163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89814
8093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.898148093
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.951972146
Short name T561
Test name
Test status
Simulation time 8393803758 ps
CPU time 10.03 seconds
Started Mar 21 01:23:59 PM PDT 24
Finished Mar 21 01:24:09 PM PDT 24
Peak memory 203364 kb
Host smart-c590f9a9-02de-4590-8b41-c48392eb67fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95197
2146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.951972146
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.788103496
Short name T847
Test name
Test status
Simulation time 28803567 ps
CPU time 0.65 seconds
Started Mar 21 01:24:18 PM PDT 24
Finished Mar 21 01:24:19 PM PDT 24
Peak memory 202952 kb
Host smart-6d0f8301-2993-4c43-9dc4-8f4cf8e26f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78810
3496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.788103496
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3772781378
Short name T767
Test name
Test status
Simulation time 8373669253 ps
CPU time 7.71 seconds
Started Mar 21 01:23:44 PM PDT 24
Finished Mar 21 01:23:52 PM PDT 24
Peak memory 203420 kb
Host smart-9556df58-214e-49d3-b8fe-1445185bcb3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37727
81378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3772781378
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1022384853
Short name T625
Test name
Test status
Simulation time 8428739715 ps
CPU time 7.25 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203432 kb
Host smart-88bfadc7-df5e-42ad-86f9-654f6df85113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10223
84853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1022384853
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.1144238208
Short name T717
Test name
Test status
Simulation time 8381038489 ps
CPU time 7.13 seconds
Started Mar 21 01:23:44 PM PDT 24
Finished Mar 21 01:23:51 PM PDT 24
Peak memory 203440 kb
Host smart-f724eaa6-e35d-43d8-ba84-39d843639e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11442
38208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.1144238208
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.3968475274
Short name T816
Test name
Test status
Simulation time 8361003208 ps
CPU time 7.66 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203420 kb
Host smart-ae69361a-7614-4d44-9978-d34884f50210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39684
75274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.3968475274
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.116423286
Short name T357
Test name
Test status
Simulation time 8369523551 ps
CPU time 7.3 seconds
Started Mar 21 01:23:53 PM PDT 24
Finished Mar 21 01:24:05 PM PDT 24
Peak memory 203496 kb
Host smart-12b51608-4966-47b7-8b18-04aa6f1c0954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642
3286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.116423286
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.585497907
Short name T225
Test name
Test status
Simulation time 8367176357 ps
CPU time 7.32 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203492 kb
Host smart-83724cd0-b2e7-4f6b-b19f-ff716f120b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58549
7907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.585497907
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3008194797
Short name T562
Test name
Test status
Simulation time 195047772 ps
CPU time 2 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:50 PM PDT 24
Peak memory 203452 kb
Host smart-74ebdd25-e2e0-46a9-ac55-6e678f237ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30081
94797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3008194797
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1578460699
Short name T793
Test name
Test status
Simulation time 8443015954 ps
CPU time 7.82 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203424 kb
Host smart-46045b41-ce09-4458-9fcf-d7e57d380ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15784
60699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1578460699
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.749852993
Short name T698
Test name
Test status
Simulation time 8407140744 ps
CPU time 9.36 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:24 PM PDT 24
Peak memory 203540 kb
Host smart-ea21fe9b-0490-4f0d-bd9c-c66581b6e49c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74985
2993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.749852993
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2934990065
Short name T264
Test name
Test status
Simulation time 8363830009 ps
CPU time 7.7 seconds
Started Mar 21 01:23:45 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203264 kb
Host smart-e285b6c2-df64-4a48-9ee7-c5f8527f9ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29349
90065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2934990065
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1899682997
Short name T721
Test name
Test status
Simulation time 8403980488 ps
CPU time 9.15 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203276 kb
Host smart-4c1f767f-8e8c-4c2e-80d8-204c314aec95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18996
82997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1899682997
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.3408938388
Short name T342
Test name
Test status
Simulation time 8393981693 ps
CPU time 7.12 seconds
Started Mar 21 01:23:59 PM PDT 24
Finished Mar 21 01:24:06 PM PDT 24
Peak memory 203228 kb
Host smart-0df30c1e-7bab-4c99-9598-99ec749348bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34089
38388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.3408938388
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2517542217
Short name T338
Test name
Test status
Simulation time 29052357 ps
CPU time 0.61 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:52 PM PDT 24
Peak memory 202892 kb
Host smart-f98d7aef-edce-4bea-bc05-bcacce8de5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25175
42217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2517542217
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3713455538
Short name T679
Test name
Test status
Simulation time 8407825147 ps
CPU time 7.9 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203516 kb
Host smart-7ee6ca61-81bf-45f7-ad5b-06e45acd7f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37134
55538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3713455538
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.966598500
Short name T622
Test name
Test status
Simulation time 8408986993 ps
CPU time 7.36 seconds
Started Mar 21 01:23:43 PM PDT 24
Finished Mar 21 01:23:50 PM PDT 24
Peak memory 203448 kb
Host smart-93189a98-e249-4c52-a004-bc97e4fb7545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96659
8500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.966598500
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.3556992351
Short name T41
Test name
Test status
Simulation time 8389490905 ps
CPU time 8.16 seconds
Started Mar 21 01:24:04 PM PDT 24
Finished Mar 21 01:24:12 PM PDT 24
Peak memory 203440 kb
Host smart-7e97ba34-4b7f-42ad-a96d-7b7c1d728327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35569
92351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.3556992351
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.4193453705
Short name T475
Test name
Test status
Simulation time 8360142265 ps
CPU time 8.83 seconds
Started Mar 21 01:24:11 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203424 kb
Host smart-5c7f7c21-c514-441e-8e47-df8a6f872978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41934
53705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.4193453705
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1625719700
Short name T69
Test name
Test status
Simulation time 8483803470 ps
CPU time 7.13 seconds
Started Mar 21 01:23:58 PM PDT 24
Finished Mar 21 01:24:06 PM PDT 24
Peak memory 203460 kb
Host smart-8d93ccff-b27d-4b9e-a9b5-c68abf1a23fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16257
19700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1625719700
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3921717979
Short name T714
Test name
Test status
Simulation time 8368494144 ps
CPU time 8.4 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203468 kb
Host smart-444639f7-6ea0-487a-9a95-861d5186da6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39217
17979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3921717979
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.4174970735
Short name T215
Test name
Test status
Simulation time 37311398 ps
CPU time 0.97 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203300 kb
Host smart-5fd6ea4f-4641-475b-9db1-f7f291971c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41749
70735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.4174970735
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.4057845043
Short name T172
Test name
Test status
Simulation time 8362724448 ps
CPU time 7.16 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203252 kb
Host smart-490307af-5779-430a-b657-3287002685f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40578
45043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.4057845043
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3566857614
Short name T442
Test name
Test status
Simulation time 8442748274 ps
CPU time 7.36 seconds
Started Mar 21 01:24:26 PM PDT 24
Finished Mar 21 01:24:34 PM PDT 24
Peak memory 203436 kb
Host smart-8480522a-86de-480f-a8bf-6706dbd3ba4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35668
57614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3566857614
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.731035027
Short name T361
Test name
Test status
Simulation time 8408868731 ps
CPU time 8.11 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203508 kb
Host smart-d9ca867d-22cc-4a38-a28a-4b338808703b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73103
5027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.731035027
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.102606121
Short name T301
Test name
Test status
Simulation time 8366913499 ps
CPU time 10.38 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203448 kb
Host smart-0d4c6468-5428-4cac-b82f-69d2270872e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10260
6121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.102606121
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1832807123
Short name T502
Test name
Test status
Simulation time 8398213576 ps
CPU time 7.6 seconds
Started Mar 21 01:24:09 PM PDT 24
Finished Mar 21 01:24:17 PM PDT 24
Peak memory 203364 kb
Host smart-52c1972b-19cd-42f3-a5bb-8e5468dff917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18328
07123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1832807123
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3420615958
Short name T571
Test name
Test status
Simulation time 8388471915 ps
CPU time 7.72 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 203484 kb
Host smart-3dc9630a-0e46-4ec1-baf4-16cb5c51b012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34206
15958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3420615958
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3456592083
Short name T727
Test name
Test status
Simulation time 26032180 ps
CPU time 0.64 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:51 PM PDT 24
Peak memory 202920 kb
Host smart-2a9258c9-bd15-4d49-bce4-e5a804435135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34565
92083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3456592083
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2798739309
Short name T365
Test name
Test status
Simulation time 8368580088 ps
CPU time 7.96 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 203568 kb
Host smart-f885b40e-cb69-4edf-8825-2b8a9a0f7592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27987
39309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2798739309
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1484584474
Short name T719
Test name
Test status
Simulation time 8429260246 ps
CPU time 7.16 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203428 kb
Host smart-efd536d8-df92-42c7-8b08-bff3e1ac8813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14845
84474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1484584474
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.1562573086
Short name T375
Test name
Test status
Simulation time 8365023597 ps
CPU time 7.82 seconds
Started Mar 21 01:24:11 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 203324 kb
Host smart-6eec351e-e06b-4b03-8ad8-4b1905f2f5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15625
73086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.1562573086
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.496960918
Short name T16
Test name
Test status
Simulation time 8356527212 ps
CPU time 8.76 seconds
Started Mar 21 01:24:04 PM PDT 24
Finished Mar 21 01:24:13 PM PDT 24
Peak memory 203488 kb
Host smart-e174ce09-ccc4-4954-a0b3-995120cf08cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49696
0918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.496960918
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3328866149
Short name T558
Test name
Test status
Simulation time 8372201836 ps
CPU time 7.98 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203576 kb
Host smart-4bff9403-af72-4d1d-9ebd-be097d660128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33288
66149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3328866149
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.3553232936
Short name T461
Test name
Test status
Simulation time 8371819759 ps
CPU time 8.58 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:21 PM PDT 24
Peak memory 203532 kb
Host smart-b8c078ec-9698-45f3-a8c4-4029b5b72915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35532
32936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3553232936
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3023169271
Short name T817
Test name
Test status
Simulation time 258354229 ps
CPU time 1.97 seconds
Started Mar 21 01:24:11 PM PDT 24
Finished Mar 21 01:24:13 PM PDT 24
Peak memory 203436 kb
Host smart-cdc86ca8-3dd0-4083-bc3f-508ae4008ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30231
69271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3023169271
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3683314937
Short name T709
Test name
Test status
Simulation time 8359990349 ps
CPU time 6.85 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203512 kb
Host smart-6c4bf998-15af-4397-9c49-42c0f58954f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36833
14937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3683314937
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1275656683
Short name T805
Test name
Test status
Simulation time 8398032993 ps
CPU time 8.41 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203432 kb
Host smart-55a98360-8b6d-4da3-89a9-c7ed12196b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12756
56683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1275656683
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1212093360
Short name T682
Test name
Test status
Simulation time 8413412838 ps
CPU time 8.34 seconds
Started Mar 21 01:24:01 PM PDT 24
Finished Mar 21 01:24:09 PM PDT 24
Peak memory 203456 kb
Host smart-9eaac521-3611-4c8e-957b-a298f0c1cec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12120
93360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1212093360
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2502632696
Short name T369
Test name
Test status
Simulation time 8367621428 ps
CPU time 9.45 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203432 kb
Host smart-255f93b0-55b5-4992-88c7-94ff06060b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25026
32696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2502632696
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.861041303
Short name T425
Test name
Test status
Simulation time 8385650756 ps
CPU time 7.08 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203344 kb
Host smart-f4951e9d-1137-4b97-9587-4dd7a29fa167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86104
1303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.861041303
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1785066506
Short name T441
Test name
Test status
Simulation time 8374600631 ps
CPU time 7.5 seconds
Started Mar 21 01:24:09 PM PDT 24
Finished Mar 21 01:24:17 PM PDT 24
Peak memory 203552 kb
Host smart-3ae0ee3a-e6ae-432f-9614-b8b16da7d567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17850
66506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1785066506
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1018835157
Short name T349
Test name
Test status
Simulation time 28508049 ps
CPU time 0.64 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 202900 kb
Host smart-33fb1f5f-6336-4097-8dab-516d877af9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10188
35157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1018835157
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.786813341
Short name T300
Test name
Test status
Simulation time 8377953297 ps
CPU time 8.18 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:19 PM PDT 24
Peak memory 203536 kb
Host smart-d5d1b81c-03ec-47ac-9e5e-d1f0413f9d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78681
3341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.786813341
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.900940989
Short name T326
Test name
Test status
Simulation time 8367678572 ps
CPU time 7.42 seconds
Started Mar 21 01:24:23 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203528 kb
Host smart-a13eefb4-28f0-48d3-a6f9-7aad48fc6c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90094
0989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.900940989
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2226766537
Short name T549
Test name
Test status
Simulation time 8355972618 ps
CPU time 9.31 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203372 kb
Host smart-b068fba9-59cd-45e8-81ed-743bd5c31c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22267
66537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2226766537
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1984076738
Short name T142
Test name
Test status
Simulation time 8471278456 ps
CPU time 7.43 seconds
Started Mar 21 01:23:53 PM PDT 24
Finished Mar 21 01:24:05 PM PDT 24
Peak memory 203460 kb
Host smart-4c0bdd77-cca4-4afc-860d-d6a2ef6bac77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19840
76738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1984076738
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.192355945
Short name T538
Test name
Test status
Simulation time 8373487755 ps
CPU time 7.66 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203576 kb
Host smart-2e14fa6f-88ca-42a7-83f6-db97a72f1cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
5945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.192355945
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.2739169777
Short name T275
Test name
Test status
Simulation time 8368710182 ps
CPU time 9.8 seconds
Started Mar 21 01:24:04 PM PDT 24
Finished Mar 21 01:24:14 PM PDT 24
Peak memory 203604 kb
Host smart-fc9e8d10-c011-4139-aa0f-8dc4165477e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27391
69777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2739169777
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1728749254
Short name T282
Test name
Test status
Simulation time 37866873 ps
CPU time 1.02 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:49 PM PDT 24
Peak memory 203444 kb
Host smart-68132927-df18-4db3-8b7a-1c897fdb2539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
49254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1728749254
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3312270554
Short name T183
Test name
Test status
Simulation time 8360981460 ps
CPU time 8.04 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203236 kb
Host smart-27f5c0b7-860c-428d-805b-8067e2a8a973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33122
70554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3312270554
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.610401175
Short name T633
Test name
Test status
Simulation time 8400145934 ps
CPU time 7.44 seconds
Started Mar 21 01:23:43 PM PDT 24
Finished Mar 21 01:23:50 PM PDT 24
Peak memory 203380 kb
Host smart-14a585a5-1eb0-4360-b574-acadb6272dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61040
1175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.610401175
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.488612344
Short name T20
Test name
Test status
Simulation time 8414173810 ps
CPU time 8.24 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203572 kb
Host smart-c55d4346-c6c4-415e-8fbf-cec2e59970f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48861
2344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.488612344
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1592650200
Short name T316
Test name
Test status
Simulation time 8363209908 ps
CPU time 7.12 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203336 kb
Host smart-67dc110f-debf-4517-a4ce-0c172a901811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15926
50200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1592650200
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.896838517
Short name T100
Test name
Test status
Simulation time 8423875267 ps
CPU time 7.53 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203420 kb
Host smart-edf49368-5c06-45cf-b7a7-d6c33658a6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89683
8517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.896838517
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.830288009
Short name T464
Test name
Test status
Simulation time 8378543601 ps
CPU time 8.35 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203352 kb
Host smart-525c1692-f136-46af-adf2-c77aa239fa27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83028
8009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.830288009
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.967598492
Short name T330
Test name
Test status
Simulation time 8379232486 ps
CPU time 8.1 seconds
Started Mar 21 01:23:53 PM PDT 24
Finished Mar 21 01:24:01 PM PDT 24
Peak memory 203348 kb
Host smart-9cb59fa0-9308-4877-9bb2-37f4a75e589c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96759
8492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.967598492
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.653522793
Short name T27
Test name
Test status
Simulation time 22263787 ps
CPU time 0.62 seconds
Started Mar 21 01:23:53 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 202992 kb
Host smart-c86a5455-253a-4735-890d-847d567695d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65352
2793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.653522793
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.240673814
Short name T310
Test name
Test status
Simulation time 8381291892 ps
CPU time 7.15 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203432 kb
Host smart-beb3c791-75ae-43f0-9dbb-982df1070588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24067
3814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.240673814
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.3326003925
Short name T743
Test name
Test status
Simulation time 8393827112 ps
CPU time 8.45 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203456 kb
Host smart-2756b397-0776-4d10-9fb4-39bf3a0ec66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33260
03925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.3326003925
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1457329199
Short name T532
Test name
Test status
Simulation time 8358286462 ps
CPU time 7.07 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203512 kb
Host smart-d8025a5c-a67c-479f-b886-13c6b30e5d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14573
29199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1457329199
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2472273751
Short name T471
Test name
Test status
Simulation time 8479597860 ps
CPU time 8.35 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:24:02 PM PDT 24
Peak memory 203548 kb
Host smart-4a102b31-1148-4285-a0a1-759d74563b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24722
73751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2472273751
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3005121894
Short name T299
Test name
Test status
Simulation time 8370146130 ps
CPU time 7.55 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203552 kb
Host smart-34e06fec-60ee-4699-ab1e-4c5298194404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051
21894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3005121894
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.2064895870
Short name T359
Test name
Test status
Simulation time 8370242774 ps
CPU time 6.87 seconds
Started Mar 21 01:24:09 PM PDT 24
Finished Mar 21 01:24:16 PM PDT 24
Peak memory 203572 kb
Host smart-c47a1e47-d5c1-4e4e-9c2d-017046b938ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20648
95870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2064895870
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.945220952
Short name T648
Test name
Test status
Simulation time 179206880 ps
CPU time 1.58 seconds
Started Mar 21 01:23:59 PM PDT 24
Finished Mar 21 01:24:01 PM PDT 24
Peak memory 203244 kb
Host smart-f0a83ab5-3036-48ff-a545-ab17e0f7dc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94522
0952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.945220952
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2685506056
Short name T121
Test name
Test status
Simulation time 8381991216 ps
CPU time 7.71 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203452 kb
Host smart-6683a973-441c-43c6-b04f-8d966759f5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26855
06056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2685506056
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.534158444
Short name T814
Test name
Test status
Simulation time 8412453684 ps
CPU time 9.81 seconds
Started Mar 21 01:23:55 PM PDT 24
Finished Mar 21 01:24:05 PM PDT 24
Peak memory 203636 kb
Host smart-b1e89db8-8f04-4e91-9fc5-b36ff01cc869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53415
8444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.534158444
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2472402748
Short name T758
Test name
Test status
Simulation time 8364081636 ps
CPU time 7.58 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203268 kb
Host smart-1501ad1b-9c5b-424f-b0c2-ac8e3e44764a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24724
02748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2472402748
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2833679705
Short name T480
Test name
Test status
Simulation time 8418724778 ps
CPU time 7.32 seconds
Started Mar 21 01:23:45 PM PDT 24
Finished Mar 21 01:23:53 PM PDT 24
Peak memory 203440 kb
Host smart-aaf4e7a6-ab09-43a7-b107-aa7e969a05e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28336
79705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2833679705
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3224019388
Short name T530
Test name
Test status
Simulation time 8382986048 ps
CPU time 9.19 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203376 kb
Host smart-09e09a24-c3b5-460b-9b3f-0cf4cf2f7a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32240
19388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3224019388
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1365630426
Short name T641
Test name
Test status
Simulation time 8380555904 ps
CPU time 8.39 seconds
Started Mar 21 01:24:03 PM PDT 24
Finished Mar 21 01:24:11 PM PDT 24
Peak memory 203376 kb
Host smart-694fade0-99ca-4849-bc6b-aa260a590f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13656
30426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1365630426
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1545935160
Short name T550
Test name
Test status
Simulation time 27584781 ps
CPU time 0.63 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 202952 kb
Host smart-7195d435-553b-48f5-a5cf-1e2689a9280f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15459
35160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1545935160
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2110342759
Short name T555
Test name
Test status
Simulation time 8385267326 ps
CPU time 7.1 seconds
Started Mar 21 01:24:11 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 203452 kb
Host smart-daa54780-e237-4faa-aacd-5814dd325a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21103
42759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2110342759
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2959121845
Short name T576
Test name
Test status
Simulation time 8421832074 ps
CPU time 7.46 seconds
Started Mar 21 01:23:53 PM PDT 24
Finished Mar 21 01:24:01 PM PDT 24
Peak memory 203424 kb
Host smart-95bbfab2-100e-4301-8bf9-91b8395856a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29591
21845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2959121845
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.3039163241
Short name T567
Test name
Test status
Simulation time 8374748431 ps
CPU time 8.77 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203480 kb
Host smart-53095cd6-c92e-4140-92fc-355053c084ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30391
63241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.3039163241
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2984788519
Short name T452
Test name
Test status
Simulation time 8360142091 ps
CPU time 7.46 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203352 kb
Host smart-f9c9c034-580f-40cc-b337-18496ea7beac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29847
88519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2984788519
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3366682860
Short name T380
Test name
Test status
Simulation time 8372797909 ps
CPU time 8.54 seconds
Started Mar 21 01:24:11 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203540 kb
Host smart-b2da6902-6c5f-4b0b-ab1c-58adcf5d0676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33666
82860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3366682860
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.1445798648
Short name T757
Test name
Test status
Simulation time 8370977488 ps
CPU time 8.73 seconds
Started Mar 21 01:24:07 PM PDT 24
Finished Mar 21 01:24:16 PM PDT 24
Peak memory 203496 kb
Host smart-484a5200-9f81-412e-b592-ec8d087c88e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14457
98648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1445798648
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1125580364
Short name T232
Test name
Test status
Simulation time 219164249 ps
CPU time 1.88 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:21 PM PDT 24
Peak memory 203520 kb
Host smart-435148cf-18fc-4054-a590-d82a66a6d9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11255
80364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1125580364
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1412283342
Short name T671
Test name
Test status
Simulation time 8395094134 ps
CPU time 7.22 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203484 kb
Host smart-715844ed-8450-4bf3-b134-23e44987d5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14122
83342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1412283342
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2792696871
Short name T413
Test name
Test status
Simulation time 8411152278 ps
CPU time 8.07 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203476 kb
Host smart-eeb28865-01f3-412a-88ae-01b0c0a36ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27926
96871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2792696871
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.4172999236
Short name T437
Test name
Test status
Simulation time 8370109137 ps
CPU time 7.55 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203380 kb
Host smart-7e09c195-1f64-4b34-82f3-45d98f88c070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41729
99236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.4172999236
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1614137375
Short name T89
Test name
Test status
Simulation time 8419934055 ps
CPU time 8.25 seconds
Started Mar 21 01:24:09 PM PDT 24
Finished Mar 21 01:24:17 PM PDT 24
Peak memory 203380 kb
Host smart-258839db-3ab6-46d0-bc78-1a49645e9993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141
37375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1614137375
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1378483520
Short name T21
Test name
Test status
Simulation time 8392098790 ps
CPU time 7.36 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203504 kb
Host smart-7170a8b7-b935-41b7-ac81-a134d0eed9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
83520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1378483520
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3623544212
Short name T352
Test name
Test status
Simulation time 8372176805 ps
CPU time 7.67 seconds
Started Mar 21 01:23:43 PM PDT 24
Finished Mar 21 01:23:51 PM PDT 24
Peak memory 203260 kb
Host smart-df7d1b22-eebc-47e0-9533-c292a585137b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36235
44212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3623544212
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1984162744
Short name T602
Test name
Test status
Simulation time 30795947 ps
CPU time 0.64 seconds
Started Mar 21 01:23:57 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 202936 kb
Host smart-7c9641c6-23a2-4d3c-973a-f0119156b8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19841
62744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1984162744
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.789771561
Short name T499
Test name
Test status
Simulation time 8409796690 ps
CPU time 7.16 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203544 kb
Host smart-66c42cfa-c58d-4c0e-a8c9-3d99c60268b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78977
1561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.789771561
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2492634095
Short name T815
Test name
Test status
Simulation time 8458700959 ps
CPU time 7.42 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203384 kb
Host smart-2563546e-4d44-4374-8594-628cdb6cc593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24926
34095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2492634095
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.4055609743
Short name T676
Test name
Test status
Simulation time 8394030750 ps
CPU time 9.14 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203452 kb
Host smart-9b0cce37-fd85-4ea1-a096-e132e5c737d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40556
09743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.4055609743
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1652923659
Short name T477
Test name
Test status
Simulation time 8362205749 ps
CPU time 7.17 seconds
Started Mar 21 01:24:08 PM PDT 24
Finished Mar 21 01:24:15 PM PDT 24
Peak memory 203236 kb
Host smart-cfd6d029-8d4b-4a02-ad9a-5a51555fbcd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16529
23659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1652923659
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2670723438
Short name T277
Test name
Test status
Simulation time 8367475977 ps
CPU time 8.92 seconds
Started Mar 21 01:22:45 PM PDT 24
Finished Mar 21 01:22:55 PM PDT 24
Peak memory 203500 kb
Host smart-791a6cb4-52d0-45d5-8194-aada5830ef72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26707
23438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2670723438
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.3596030828
Short name T728
Test name
Test status
Simulation time 8370567996 ps
CPU time 7.91 seconds
Started Mar 21 01:22:50 PM PDT 24
Finished Mar 21 01:22:58 PM PDT 24
Peak memory 203444 kb
Host smart-0493a103-f86d-408a-989d-c823f5668b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35960
30828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3596030828
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.826311713
Short name T474
Test name
Test status
Simulation time 66713206 ps
CPU time 1.86 seconds
Started Mar 21 01:22:54 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 203512 kb
Host smart-21d61944-3ae7-4379-9e5f-da0333cda2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82631
1713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.826311713
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.288332661
Short name T161
Test name
Test status
Simulation time 8358776423 ps
CPU time 7.51 seconds
Started Mar 21 01:22:42 PM PDT 24
Finished Mar 21 01:22:51 PM PDT 24
Peak memory 203240 kb
Host smart-149f37d8-646d-48fc-881e-b9b2c18bbe57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28833
2661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.288332661
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1530403592
Short name T856
Test name
Test status
Simulation time 8433688911 ps
CPU time 7.27 seconds
Started Mar 21 01:22:48 PM PDT 24
Finished Mar 21 01:22:55 PM PDT 24
Peak memory 203424 kb
Host smart-d530cb34-252a-4b60-b193-6670ab89dd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15304
03592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1530403592
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1048568643
Short name T799
Test name
Test status
Simulation time 8409507604 ps
CPU time 7.35 seconds
Started Mar 21 01:22:53 PM PDT 24
Finished Mar 21 01:23:01 PM PDT 24
Peak memory 203544 kb
Host smart-89137d9c-3f37-432a-9ce3-386015534a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10485
68643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1048568643
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3828115628
Short name T703
Test name
Test status
Simulation time 8363391014 ps
CPU time 8.85 seconds
Started Mar 21 01:22:44 PM PDT 24
Finished Mar 21 01:22:54 PM PDT 24
Peak memory 203248 kb
Host smart-b9d81df6-7330-4b76-be2e-f923ab28d945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38281
15628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3828115628
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1020478827
Short name T111
Test name
Test status
Simulation time 8387483560 ps
CPU time 7.39 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:23:02 PM PDT 24
Peak memory 203016 kb
Host smart-dfd3d558-a430-4d78-964d-3ef47dcd5808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
78827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1020478827
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.596571
Short name T328
Test name
Test status
Simulation time 8359959588 ps
CPU time 6.96 seconds
Started Mar 21 01:22:49 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 203256 kb
Host smart-14f6ed6c-958a-4870-b828-2c90f9a39525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59657
1 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.596571
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.4132659762
Short name T677
Test name
Test status
Simulation time 8393201506 ps
CPU time 9.68 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:23:04 PM PDT 24
Peak memory 203244 kb
Host smart-37b3bf43-1903-4a75-ad75-920b2cc4b046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41326
59762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.4132659762
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2341366974
Short name T775
Test name
Test status
Simulation time 27948892 ps
CPU time 0.65 seconds
Started Mar 21 01:22:51 PM PDT 24
Finished Mar 21 01:22:52 PM PDT 24
Peak memory 202856 kb
Host smart-bb9e91a5-4abb-4d32-bcd3-824d056343c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
66974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2341366974
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.866972081
Short name T512
Test name
Test status
Simulation time 8403395660 ps
CPU time 9.92 seconds
Started Mar 21 01:22:48 PM PDT 24
Finished Mar 21 01:22:58 PM PDT 24
Peak memory 203460 kb
Host smart-24212eeb-9562-4b85-9a6c-816666abd237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86697
2081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.866972081
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3783933584
Short name T792
Test name
Test status
Simulation time 8407211298 ps
CPU time 7.51 seconds
Started Mar 21 01:22:47 PM PDT 24
Finished Mar 21 01:22:55 PM PDT 24
Peak memory 203392 kb
Host smart-87174c06-2e28-4398-911c-3e9ccb2645c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37839
33584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3783933584
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1573479380
Short name T472
Test name
Test status
Simulation time 8395518568 ps
CPU time 7.63 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:23:02 PM PDT 24
Peak memory 203568 kb
Host smart-6b844d9e-ad92-4b55-aedf-74fea0afec4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15734
79380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1573479380
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.977818185
Short name T50
Test name
Test status
Simulation time 89703546 ps
CPU time 0.92 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 218756 kb
Host smart-47cc25ed-1fb9-4ebe-bc94-35608e4dcd9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=977818185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.977818185
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2607562779
Short name T623
Test name
Test status
Simulation time 8357650184 ps
CPU time 9.8 seconds
Started Mar 21 01:22:52 PM PDT 24
Finished Mar 21 01:23:02 PM PDT 24
Peak memory 203252 kb
Host smart-a13d0108-411f-4fd3-81b2-0763783a6c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26075
62779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2607562779
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1219091749
Short name T409
Test name
Test status
Simulation time 8475942831 ps
CPU time 10.17 seconds
Started Mar 21 01:22:49 PM PDT 24
Finished Mar 21 01:22:59 PM PDT 24
Peak memory 203488 kb
Host smart-c20edcf8-bfc2-4de4-bdf0-adcb319196c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12190
91749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1219091749
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_enable.286499388
Short name T333
Test name
Test status
Simulation time 8365680763 ps
CPU time 7.49 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203480 kb
Host smart-2f1ca29a-9f1c-47b7-b116-9fd855e72858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28649
9388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.286499388
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1904813119
Short name T795
Test name
Test status
Simulation time 151903404 ps
CPU time 1.73 seconds
Started Mar 21 01:23:42 PM PDT 24
Finished Mar 21 01:23:44 PM PDT 24
Peak memory 203464 kb
Host smart-e992506a-3061-4864-ac44-142b782d69b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19048
13119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1904813119
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1203441507
Short name T182
Test name
Test status
Simulation time 8362836547 ps
CPU time 7.67 seconds
Started Mar 21 01:23:56 PM PDT 24
Finished Mar 21 01:24:04 PM PDT 24
Peak memory 203252 kb
Host smart-b21336f0-a316-4a44-8b26-f7fc9fa5e65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12034
41507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1203441507
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1836253700
Short name T372
Test name
Test status
Simulation time 8382241724 ps
CPU time 7.86 seconds
Started Mar 21 01:24:00 PM PDT 24
Finished Mar 21 01:24:08 PM PDT 24
Peak memory 203372 kb
Host smart-137ba335-7ee0-4578-ac05-78837fd5392e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18362
53700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1836253700
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2940342495
Short name T626
Test name
Test status
Simulation time 8409466002 ps
CPU time 7.06 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203440 kb
Host smart-6cb44693-fe4d-41d4-b5a8-9de1dd80c6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29403
42495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2940342495
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.4286239648
Short name T487
Test name
Test status
Simulation time 8363970833 ps
CPU time 9.65 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:27 PM PDT 24
Peak memory 203308 kb
Host smart-98b5ace7-5df1-448a-8545-3da26cec9c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42862
39648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4286239648
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2304957832
Short name T91
Test name
Test status
Simulation time 8417663045 ps
CPU time 6.95 seconds
Started Mar 21 01:24:28 PM PDT 24
Finished Mar 21 01:24:35 PM PDT 24
Peak memory 203476 kb
Host smart-9c4e3f43-3eb2-4918-b66b-423dcc8be2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23049
57832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2304957832
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1354402413
Short name T732
Test name
Test status
Simulation time 8380007490 ps
CPU time 9.06 seconds
Started Mar 21 01:24:01 PM PDT 24
Finished Mar 21 01:24:10 PM PDT 24
Peak memory 203392 kb
Host smart-a3812b53-96ac-4b14-b3ba-44ce6399ee09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
02413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1354402413
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.9792398
Short name T327
Test name
Test status
Simulation time 8365272257 ps
CPU time 7.19 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 203172 kb
Host smart-3186d71c-cb78-4a35-9e0b-895890976ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97923
98 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.9792398
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1479815890
Short name T750
Test name
Test status
Simulation time 26409369 ps
CPU time 0.62 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:13 PM PDT 24
Peak memory 202968 kb
Host smart-73464323-e48e-4438-b837-fabc2e9fbe95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14798
15890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1479815890
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.728075307
Short name T688
Test name
Test status
Simulation time 8405627301 ps
CPU time 7.34 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203536 kb
Host smart-9ea04d65-4f33-48e6-a87a-a9a420bdea19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72807
5307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.728075307
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1302974577
Short name T466
Test name
Test status
Simulation time 8431418922 ps
CPU time 8 seconds
Started Mar 21 01:24:07 PM PDT 24
Finished Mar 21 01:24:15 PM PDT 24
Peak memory 203436 kb
Host smart-690030f0-7d63-4d94-b514-aeb21dafaf88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13029
74577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1302974577
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.2718254953
Short name T621
Test name
Test status
Simulation time 8370006611 ps
CPU time 7.84 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203432 kb
Host smart-d728c713-b27f-4a08-9ade-8dea11962943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27182
54953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.2718254953
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3251711840
Short name T731
Test name
Test status
Simulation time 8355183289 ps
CPU time 9.69 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:25 PM PDT 24
Peak memory 203428 kb
Host smart-b9573e85-0144-4b49-be52-bec85f957c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32517
11840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3251711840
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1167504822
Short name T141
Test name
Test status
Simulation time 8474145197 ps
CPU time 7.72 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203444 kb
Host smart-fc399663-0a42-4a16-b00b-22e4d8e69d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11675
04822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1167504822
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2514193297
Short name T687
Test name
Test status
Simulation time 8373017327 ps
CPU time 9.66 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203424 kb
Host smart-53c4b383-475f-43dd-8e40-e83836d197f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25141
93297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2514193297
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.3013586949
Short name T834
Test name
Test status
Simulation time 8373021576 ps
CPU time 7.29 seconds
Started Mar 21 01:24:16 PM PDT 24
Finished Mar 21 01:24:24 PM PDT 24
Peak memory 203420 kb
Host smart-23eb88c2-c7dd-48ca-be02-f2d8854a7b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30135
86949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3013586949
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.206845799
Short name T44
Test name
Test status
Simulation time 130933671 ps
CPU time 1.52 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:51 PM PDT 24
Peak memory 203288 kb
Host smart-2d3ce240-798b-488c-ac2e-4d5cae881630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20684
5799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.206845799
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.808924116
Short name T66
Test name
Test status
Simulation time 8363161351 ps
CPU time 7.09 seconds
Started Mar 21 01:24:06 PM PDT 24
Finished Mar 21 01:24:13 PM PDT 24
Peak memory 203204 kb
Host smart-0d09a862-09b8-42a8-8aab-b370705ed7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80892
4116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.808924116
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1414323023
Short name T445
Test name
Test status
Simulation time 8432783766 ps
CPU time 7.52 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:21 PM PDT 24
Peak memory 203488 kb
Host smart-2544d765-91c7-4bd2-9fe6-4e11a5b4869b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14143
23023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1414323023
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2642738184
Short name T564
Test name
Test status
Simulation time 8414681744 ps
CPU time 7.39 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203572 kb
Host smart-8e2ec790-2cb1-4b79-b2dd-e19d0ab35873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26427
38184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2642738184
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3732559012
Short name T73
Test name
Test status
Simulation time 8363181557 ps
CPU time 7.28 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203328 kb
Host smart-b207904c-6690-4f7d-9b42-752f72b2ad05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
59012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3732559012
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1341942160
Short name T110
Test name
Test status
Simulation time 8431659257 ps
CPU time 7.27 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203376 kb
Host smart-97f59aa5-4812-4de6-9707-06af61d6bbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13419
42160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1341942160
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1549773340
Short name T547
Test name
Test status
Simulation time 8386929850 ps
CPU time 8.41 seconds
Started Mar 21 01:24:18 PM PDT 24
Finished Mar 21 01:24:27 PM PDT 24
Peak memory 203464 kb
Host smart-9f8918ea-dbbc-48b1-a668-ada10eb58548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15497
73340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1549773340
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1266458654
Short name T702
Test name
Test status
Simulation time 8398531446 ps
CPU time 7.94 seconds
Started Mar 21 01:24:02 PM PDT 24
Finished Mar 21 01:24:10 PM PDT 24
Peak memory 203260 kb
Host smart-90b51c97-8d4a-4621-86d4-61a9b7b3758b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12664
58654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1266458654
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2007931491
Short name T371
Test name
Test status
Simulation time 26304764 ps
CPU time 0.62 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 202964 kb
Host smart-898712fd-886f-4d43-aa65-860588bcf2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20079
31491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2007931491
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.329660307
Short name T213
Test name
Test status
Simulation time 8377289586 ps
CPU time 8.52 seconds
Started Mar 21 01:24:15 PM PDT 24
Finished Mar 21 01:24:24 PM PDT 24
Peak memory 203440 kb
Host smart-9cceb498-6385-4193-b81f-6c2064557f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32966
0307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.329660307
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2983592045
Short name T133
Test name
Test status
Simulation time 8433528550 ps
CPU time 7.41 seconds
Started Mar 21 01:24:09 PM PDT 24
Finished Mar 21 01:24:17 PM PDT 24
Peak memory 203508 kb
Host smart-6f6c818c-5d3c-4789-8ba1-b7d4e3ba52aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29835
92045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2983592045
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.890388721
Short name T779
Test name
Test status
Simulation time 8381682286 ps
CPU time 7.87 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203596 kb
Host smart-1f7f48c0-1175-4e8a-bd4c-04e120e34d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89038
8721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.890388721
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1909696975
Short name T710
Test name
Test status
Simulation time 8361455557 ps
CPU time 7.16 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203496 kb
Host smart-b1be5e7d-ca6d-4df0-9445-0fbae999d786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19096
96975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1909696975
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1788239481
Short name T120
Test name
Test status
Simulation time 8476825761 ps
CPU time 9.77 seconds
Started Mar 21 01:23:48 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203540 kb
Host smart-7b5fceed-1247-42ec-ad2e-e33b27c99e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17882
39481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1788239481
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.4287311972
Short name T481
Test name
Test status
Simulation time 8367002170 ps
CPU time 7.58 seconds
Started Mar 21 01:24:03 PM PDT 24
Finished Mar 21 01:24:11 PM PDT 24
Peak memory 203452 kb
Host smart-5d0ef4bf-04c8-4d9d-8548-e238af9d392f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42873
11972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.4287311972
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.2995818473
Short name T544
Test name
Test status
Simulation time 8369710639 ps
CPU time 7.87 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203564 kb
Host smart-033620ff-bfcd-4476-b2e8-3368ccf6e65c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29958
18473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2995818473
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2766935050
Short name T594
Test name
Test status
Simulation time 8355785168 ps
CPU time 9.91 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:22 PM PDT 24
Peak memory 203224 kb
Host smart-8b0d9390-ba16-4c10-9e51-32f33e2371ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27669
35050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2766935050
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1784989359
Short name T811
Test name
Test status
Simulation time 8429650585 ps
CPU time 7.63 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:58 PM PDT 24
Peak memory 203428 kb
Host smart-49ea852b-988c-4530-8fd5-77a7d487e993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17849
89359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1784989359
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.715646607
Short name T287
Test name
Test status
Simulation time 8415424106 ps
CPU time 7.07 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203484 kb
Host smart-3d6b5729-c623-4449-98cd-f93887ec7c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71564
6607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.715646607
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.59161427
Short name T353
Test name
Test status
Simulation time 8365214694 ps
CPU time 7.89 seconds
Started Mar 21 01:24:03 PM PDT 24
Finished Mar 21 01:24:11 PM PDT 24
Peak memory 203316 kb
Host smart-739fd8ae-fa7c-4029-8ff7-9d4617c3fae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59161
427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.59161427
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3780770011
Short name T766
Test name
Test status
Simulation time 8385637611 ps
CPU time 9.73 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:22 PM PDT 24
Peak memory 203472 kb
Host smart-2e79ac61-2ad1-4673-a0d4-fffec55db835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37807
70011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3780770011
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1462142352
Short name T303
Test name
Test status
Simulation time 8382702616 ps
CPU time 7.8 seconds
Started Mar 21 01:24:06 PM PDT 24
Finished Mar 21 01:24:14 PM PDT 24
Peak memory 203304 kb
Host smart-da76167f-bcae-49fa-856b-68d649e25449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14621
42352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1462142352
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2211503176
Short name T663
Test name
Test status
Simulation time 27316078 ps
CPU time 0.64 seconds
Started Mar 21 01:24:16 PM PDT 24
Finished Mar 21 01:24:17 PM PDT 24
Peak memory 202924 kb
Host smart-01ec22e9-b45b-4c7e-b03b-f98ad829a7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22115
03176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2211503176
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1498971691
Short name T618
Test name
Test status
Simulation time 8396936539 ps
CPU time 9.51 seconds
Started Mar 21 01:24:26 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 203544 kb
Host smart-fc726bed-f53f-45ca-859a-99f9572dc96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14989
71691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1498971691
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.982832908
Short name T482
Test name
Test status
Simulation time 8377531821 ps
CPU time 7.23 seconds
Started Mar 21 01:24:04 PM PDT 24
Finished Mar 21 01:24:11 PM PDT 24
Peak memory 203492 kb
Host smart-e1fb037a-dfbf-4b94-b9b8-d964424e09ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98283
2908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.982832908
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2545347721
Short name T341
Test name
Test status
Simulation time 8403638564 ps
CPU time 7.82 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203572 kb
Host smart-5214079f-eed5-47e8-92cc-a95125ada6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25453
47721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2545347721
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1240721679
Short name T304
Test name
Test status
Simulation time 8359301234 ps
CPU time 7.3 seconds
Started Mar 21 01:23:54 PM PDT 24
Finished Mar 21 01:24:01 PM PDT 24
Peak memory 203424 kb
Host smart-7022b50a-d6d3-459f-b848-4ac9c004275c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12407
21679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1240721679
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.824153449
Short name T270
Test name
Test status
Simulation time 8371490201 ps
CPU time 7.7 seconds
Started Mar 21 01:24:09 PM PDT 24
Finished Mar 21 01:24:17 PM PDT 24
Peak memory 203512 kb
Host smart-f87aef93-10b9-482b-8969-3f428b9e0c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82415
3449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.824153449
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.2808556712
Short name T495
Test name
Test status
Simulation time 8371304801 ps
CPU time 7.44 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 203440 kb
Host smart-8406122e-7e46-4774-8f4d-6752644afffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28085
56712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2808556712
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2071320015
Short name T220
Test name
Test status
Simulation time 129440286 ps
CPU time 1.53 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:14 PM PDT 24
Peak memory 203348 kb
Host smart-af2d37ab-1261-49e1-8577-48811945a8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20713
20015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2071320015
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3161864794
Short name T114
Test name
Test status
Simulation time 8402547484 ps
CPU time 7.72 seconds
Started Mar 21 01:24:15 PM PDT 24
Finished Mar 21 01:24:23 PM PDT 24
Peak memory 203480 kb
Host smart-925ad835-d857-439d-b865-915c2b5c7ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31618
64794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3161864794
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2036657859
Short name T511
Test name
Test status
Simulation time 8407127051 ps
CPU time 9.33 seconds
Started Mar 21 01:23:53 PM PDT 24
Finished Mar 21 01:24:02 PM PDT 24
Peak memory 203548 kb
Host smart-74abc6d8-63fd-4c58-ac9f-47a7273cbb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
57859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2036657859
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3415035191
Short name T578
Test name
Test status
Simulation time 8366823801 ps
CPU time 7.36 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:22 PM PDT 24
Peak memory 203436 kb
Host smart-70529aa8-469c-401c-b4d0-999b8ab419e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
35191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3415035191
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.632002319
Short name T629
Test name
Test status
Simulation time 8398274554 ps
CPU time 7.03 seconds
Started Mar 21 01:24:20 PM PDT 24
Finished Mar 21 01:24:27 PM PDT 24
Peak memory 203488 kb
Host smart-19689deb-0135-46cc-afc7-ae0c144f1ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63200
2319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.632002319
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1125879264
Short name T318
Test name
Test status
Simulation time 8408141832 ps
CPU time 7.9 seconds
Started Mar 21 01:24:03 PM PDT 24
Finished Mar 21 01:24:11 PM PDT 24
Peak memory 203292 kb
Host smart-3709de7d-58e0-422d-a983-392aba8540e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11258
79264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1125879264
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.139763298
Short name T694
Test name
Test status
Simulation time 8393296737 ps
CPU time 7.32 seconds
Started Mar 21 01:24:02 PM PDT 24
Finished Mar 21 01:24:10 PM PDT 24
Peak memory 203284 kb
Host smart-88203c2d-3e3e-4b90-be6b-065b808ba366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13976
3298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.139763298
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1866225384
Short name T35
Test name
Test status
Simulation time 25151843 ps
CPU time 0.63 seconds
Started Mar 21 01:23:54 PM PDT 24
Finished Mar 21 01:23:55 PM PDT 24
Peak memory 202976 kb
Host smart-78adb525-f8dd-47ac-91b2-df9fb8c6981b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
25384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1866225384
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3228472997
Short name T473
Test name
Test status
Simulation time 8397878822 ps
CPU time 7.47 seconds
Started Mar 21 01:23:50 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203464 kb
Host smart-0638fdb7-ed5b-4c32-be72-c7b480df6bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32284
72997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3228472997
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2212558853
Short name T632
Test name
Test status
Simulation time 8389453052 ps
CPU time 7.46 seconds
Started Mar 21 01:23:56 PM PDT 24
Finished Mar 21 01:24:08 PM PDT 24
Peak memory 203484 kb
Host smart-3b526f2b-e1e1-4c68-b99c-36e6f9193a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22125
58853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2212558853
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.3895031664
Short name T510
Test name
Test status
Simulation time 8404246355 ps
CPU time 7.7 seconds
Started Mar 21 01:24:13 PM PDT 24
Finished Mar 21 01:24:21 PM PDT 24
Peak memory 203544 kb
Host smart-682e0c46-6397-4b24-8831-9e2a9a7af8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38950
31664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.3895031664
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.4195990847
Short name T855
Test name
Test status
Simulation time 8359800397 ps
CPU time 8.08 seconds
Started Mar 21 01:23:51 PM PDT 24
Finished Mar 21 01:23:59 PM PDT 24
Peak memory 203500 kb
Host smart-91984bc0-9725-4d97-9326-faea95afba68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41959
90847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.4195990847
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2448646358
Short name T218
Test name
Test status
Simulation time 8368476699 ps
CPU time 7.28 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:25 PM PDT 24
Peak memory 203464 kb
Host smart-3d187215-8362-4f84-84b4-1dfcb849d64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24486
46358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2448646358
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.2955931087
Short name T768
Test name
Test status
Simulation time 8371260815 ps
CPU time 7.94 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:22 PM PDT 24
Peak memory 203532 kb
Host smart-ca559419-5e33-4ad5-8adf-75b45bbf44e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29559
31087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2955931087
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.762217442
Short name T551
Test name
Test status
Simulation time 67704511 ps
CPU time 1.76 seconds
Started Mar 21 01:24:28 PM PDT 24
Finished Mar 21 01:24:30 PM PDT 24
Peak memory 203544 kb
Host smart-5efc6af3-e507-4abd-8f02-f5c2cd10bdd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76221
7442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.762217442
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3522461330
Short name T169
Test name
Test status
Simulation time 8362948612 ps
CPU time 7.09 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 203256 kb
Host smart-429aeed3-e12e-4ddc-8ca9-286ce3d80f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35224
61330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3522461330
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.4043572151
Short name T113
Test name
Test status
Simulation time 8431962127 ps
CPU time 7.52 seconds
Started Mar 21 01:23:56 PM PDT 24
Finished Mar 21 01:24:04 PM PDT 24
Peak memory 203412 kb
Host smart-b15c4d33-c96a-4fb6-95d2-5b9408965f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
72151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.4043572151
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.3933532840
Short name T440
Test name
Test status
Simulation time 8405788024 ps
CPU time 7.9 seconds
Started Mar 21 01:24:10 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 203508 kb
Host smart-a1386d6f-1eed-4cf4-ad70-914c505911ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39335
32840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.3933532840
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3409299555
Short name T683
Test name
Test status
Simulation time 8367307236 ps
CPU time 7.53 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 203272 kb
Host smart-05ebdec1-412c-47f7-9ff9-2cc7c83f473a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34092
99555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3409299555
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.676112235
Short name T649
Test name
Test status
Simulation time 8439563002 ps
CPU time 7.27 seconds
Started Mar 21 01:24:13 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203464 kb
Host smart-7dc5e69e-f6eb-402f-a173-7f1450740cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67611
2235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.676112235
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2848957030
Short name T377
Test name
Test status
Simulation time 8397396612 ps
CPU time 7.65 seconds
Started Mar 21 01:23:56 PM PDT 24
Finished Mar 21 01:24:09 PM PDT 24
Peak memory 203340 kb
Host smart-2f02f60e-1464-4bd0-8158-0fda99dfd0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28489
57030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2848957030
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.298677730
Short name T696
Test name
Test status
Simulation time 27006508 ps
CPU time 0.66 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:15 PM PDT 24
Peak memory 202892 kb
Host smart-533633e2-fe20-41f4-9109-9b7247e7e46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867
7730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.298677730
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.375734981
Short name T42
Test name
Test status
Simulation time 8399607146 ps
CPU time 7.33 seconds
Started Mar 21 01:24:23 PM PDT 24
Finished Mar 21 01:24:30 PM PDT 24
Peak memory 203508 kb
Host smart-53340290-e3bf-4657-9113-5ccb518cfa32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37573
4981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.375734981
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.505643825
Short name T118
Test name
Test status
Simulation time 8384251870 ps
CPU time 7.83 seconds
Started Mar 21 01:24:25 PM PDT 24
Finished Mar 21 01:24:33 PM PDT 24
Peak memory 203392 kb
Host smart-3390109a-8ee6-41b3-a807-3083657b4701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50564
3825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.505643825
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.3166010932
Short name T725
Test name
Test status
Simulation time 8391423250 ps
CPU time 8.28 seconds
Started Mar 21 01:24:04 PM PDT 24
Finished Mar 21 01:24:12 PM PDT 24
Peak memory 203596 kb
Host smart-1d16b06d-217d-4a34-aae1-17495a15ab57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660
10932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.3166010932
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3877029255
Short name T498
Test name
Test status
Simulation time 8362565222 ps
CPU time 7.46 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:25 PM PDT 24
Peak memory 203380 kb
Host smart-0ee0e67a-1473-45b4-973e-87342c6fad30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38770
29255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3877029255
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3316710285
Short name T126
Test name
Test status
Simulation time 8477376727 ps
CPU time 7.14 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:25 PM PDT 24
Peak memory 203460 kb
Host smart-f84f5172-b6f4-465f-9e21-771120dfa126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33167
10285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3316710285
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.679347972
Short name T360
Test name
Test status
Simulation time 8373271460 ps
CPU time 7.34 seconds
Started Mar 21 01:24:08 PM PDT 24
Finished Mar 21 01:24:16 PM PDT 24
Peak memory 203516 kb
Host smart-a9abd776-2eb3-41af-aa8a-f016d181c3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67934
7972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.679347972
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.4252418441
Short name T810
Test name
Test status
Simulation time 8370576832 ps
CPU time 7.33 seconds
Started Mar 21 01:24:19 PM PDT 24
Finished Mar 21 01:24:26 PM PDT 24
Peak memory 203416 kb
Host smart-903a6209-9a7d-43d5-88af-a945545b931a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42524
18441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.4252418441
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2991716270
Short name T45
Test name
Test status
Simulation time 162382031 ps
CPU time 1.94 seconds
Started Mar 21 01:24:28 PM PDT 24
Finished Mar 21 01:24:30 PM PDT 24
Peak memory 203456 kb
Host smart-4d7e5dca-712e-47e8-9daa-38b0453a4b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29917
16270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2991716270
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.397131144
Short name T166
Test name
Test status
Simulation time 8364814206 ps
CPU time 8.48 seconds
Started Mar 21 01:24:26 PM PDT 24
Finished Mar 21 01:24:35 PM PDT 24
Peak memory 203180 kb
Host smart-cac64971-cc95-41ba-b27c-db3acffe5cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
1144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.397131144
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.2539357606
Short name T545
Test name
Test status
Simulation time 8403501262 ps
CPU time 8.12 seconds
Started Mar 21 01:24:25 PM PDT 24
Finished Mar 21 01:24:33 PM PDT 24
Peak memory 203420 kb
Host smart-47374f79-a48f-4bc3-95b7-225faf196c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25393
57606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.2539357606
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1604597642
Short name T833
Test name
Test status
Simulation time 8360792236 ps
CPU time 8.07 seconds
Started Mar 21 01:24:24 PM PDT 24
Finished Mar 21 01:24:32 PM PDT 24
Peak memory 203396 kb
Host smart-7714738b-f92a-426f-866d-126a84da900c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16045
97642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1604597642
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.4015499405
Short name T794
Test name
Test status
Simulation time 8384621342 ps
CPU time 8.28 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203416 kb
Host smart-bc3cadaf-daa1-4e19-9d02-3b8ba77f5678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
99405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.4015499405
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1808417681
Short name T493
Test name
Test status
Simulation time 8388094861 ps
CPU time 9.36 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:22 PM PDT 24
Peak memory 203256 kb
Host smart-76db0e21-2512-4031-b9a1-df42f0baae5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18084
17681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1808417681
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3987290496
Short name T601
Test name
Test status
Simulation time 8401262197 ps
CPU time 7.69 seconds
Started Mar 21 01:24:08 PM PDT 24
Finished Mar 21 01:24:16 PM PDT 24
Peak memory 203344 kb
Host smart-a0584847-f06d-42c9-9304-c206c00ed229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39872
90496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3987290496
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1341329764
Short name T455
Test name
Test status
Simulation time 29899232 ps
CPU time 0.64 seconds
Started Mar 21 01:24:08 PM PDT 24
Finished Mar 21 01:24:08 PM PDT 24
Peak memory 202896 kb
Host smart-7629b691-4979-4146-a320-ca56154cf163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13413
29764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1341329764
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1589287059
Short name T804
Test name
Test status
Simulation time 8406034650 ps
CPU time 9.35 seconds
Started Mar 21 01:24:20 PM PDT 24
Finished Mar 21 01:24:35 PM PDT 24
Peak memory 203596 kb
Host smart-3f10522e-e638-454f-8e1b-f1a88e9cfd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15892
87059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1589287059
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1541468268
Short name T292
Test name
Test status
Simulation time 8386838531 ps
CPU time 7.1 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:24 PM PDT 24
Peak memory 203456 kb
Host smart-e6fed8f8-dd8a-49b8-a964-685ba112f170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15414
68268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1541468268
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.3028713039
Short name T667
Test name
Test status
Simulation time 8380240754 ps
CPU time 9.27 seconds
Started Mar 21 01:24:15 PM PDT 24
Finished Mar 21 01:24:25 PM PDT 24
Peak memory 203436 kb
Host smart-7260f9d4-191e-4940-8dcc-46e891b1515f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30287
13039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.3028713039
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.4056912604
Short name T323
Test name
Test status
Simulation time 8360144850 ps
CPU time 8.48 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:23 PM PDT 24
Peak memory 203372 kb
Host smart-6fd4144e-ea38-41e8-a3ba-dc646ae3a007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40569
12604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.4056912604
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1675112892
Short name T147
Test name
Test status
Simulation time 8475878026 ps
CPU time 8.09 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:21 PM PDT 24
Peak memory 203456 kb
Host smart-10f2cec1-1ae2-4ac7-8a7f-6910acf9f2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16751
12892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1675112892
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.236814317
Short name T411
Test name
Test status
Simulation time 8372246017 ps
CPU time 7.06 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:24 PM PDT 24
Peak memory 203520 kb
Host smart-572574c8-9905-4fbc-9ddf-b9991fed5e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23681
4317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.236814317
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.1132840953
Short name T527
Test name
Test status
Simulation time 8369152240 ps
CPU time 7.26 seconds
Started Mar 21 01:24:15 PM PDT 24
Finished Mar 21 01:24:22 PM PDT 24
Peak memory 203564 kb
Host smart-ebb5e43c-7150-4e38-9657-5c8f4169615b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11328
40953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1132840953
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1313054464
Short name T598
Test name
Test status
Simulation time 101117735 ps
CPU time 1.2 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 203492 kb
Host smart-312caaea-b079-4005-ab5a-f73ccb909e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13130
54464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1313054464
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1066905423
Short name T181
Test name
Test status
Simulation time 8360082113 ps
CPU time 7.73 seconds
Started Mar 21 01:24:14 PM PDT 24
Finished Mar 21 01:24:21 PM PDT 24
Peak memory 203176 kb
Host smart-7f2390fb-2707-4149-aad4-981c242726d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10669
05423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1066905423
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3837955317
Short name T134
Test name
Test status
Simulation time 8426029760 ps
CPU time 7.81 seconds
Started Mar 21 01:24:12 PM PDT 24
Finished Mar 21 01:24:20 PM PDT 24
Peak memory 203572 kb
Host smart-248066b8-a5d5-48e9-9866-cca5d2487d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38379
55317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3837955317
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3212607037
Short name T497
Test name
Test status
Simulation time 8409963760 ps
CPU time 8.86 seconds
Started Mar 21 01:24:18 PM PDT 24
Finished Mar 21 01:24:27 PM PDT 24
Peak memory 203420 kb
Host smart-33620f4f-31b6-48b9-829d-0d212c46734a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32126
07037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3212607037
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2708486145
Short name T492
Test name
Test status
Simulation time 8363930226 ps
CPU time 7.79 seconds
Started Mar 21 01:24:25 PM PDT 24
Finished Mar 21 01:24:33 PM PDT 24
Peak memory 203356 kb
Host smart-e3d124d9-6725-4b80-8861-75460606962c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27084
86145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2708486145
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3681171867
Short name T628
Test name
Test status
Simulation time 8372121251 ps
CPU time 7.62 seconds
Started Mar 21 01:24:20 PM PDT 24
Finished Mar 21 01:24:28 PM PDT 24
Peak memory 203368 kb
Host smart-b26cb16b-9da2-49f5-9711-188f64dc53fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811
71867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3681171867
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1006441848
Short name T529
Test name
Test status
Simulation time 8395134780 ps
CPU time 7.45 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203336 kb
Host smart-75e9b2e2-face-4cd0-87c9-5ebc124d8bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10064
41848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1006441848
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3653295127
Short name T572
Test name
Test status
Simulation time 30155351 ps
CPU time 0.62 seconds
Started Mar 21 01:24:18 PM PDT 24
Finished Mar 21 01:24:19 PM PDT 24
Peak memory 202852 kb
Host smart-876e8946-eb5e-4556-8f2a-4cb5485ca98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36532
95127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3653295127
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.192569696
Short name T489
Test name
Test status
Simulation time 8386249720 ps
CPU time 7.69 seconds
Started Mar 21 01:23:56 PM PDT 24
Finished Mar 21 01:24:04 PM PDT 24
Peak memory 203452 kb
Host smart-d1131878-ca4f-4a45-b918-c63a8b170b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19256
9696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.192569696
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3796617972
Short name T722
Test name
Test status
Simulation time 8420808564 ps
CPU time 8.91 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:38 PM PDT 24
Peak memory 203424 kb
Host smart-4bbda806-5c4c-4a73-9736-40e927f961b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37966
17972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3796617972
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.2608307726
Short name T28
Test name
Test status
Simulation time 8401310467 ps
CPU time 7.28 seconds
Started Mar 21 01:24:24 PM PDT 24
Finished Mar 21 01:24:32 PM PDT 24
Peak memory 203424 kb
Host smart-84a66fc4-4787-409e-a571-99d6b3502389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26083
07726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.2608307726
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.338090554
Short name T615
Test name
Test status
Simulation time 8360147349 ps
CPU time 8.65 seconds
Started Mar 21 01:24:22 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203288 kb
Host smart-0cfef563-8d17-49eb-9a18-96c768302245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33809
0554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.338090554
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1464650663
Short name T153
Test name
Test status
Simulation time 8482032543 ps
CPU time 7.8 seconds
Started Mar 21 01:24:11 PM PDT 24
Finished Mar 21 01:24:19 PM PDT 24
Peak memory 203572 kb
Host smart-e6563509-460f-43eb-8693-6994e7f1c1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14646
50663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1464650663
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.45986584
Short name T647
Test name
Test status
Simulation time 8373273453 ps
CPU time 7.62 seconds
Started Mar 21 01:24:24 PM PDT 24
Finished Mar 21 01:24:32 PM PDT 24
Peak memory 203580 kb
Host smart-c7f41069-e0bc-4c78-9298-5a307ce0f4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45986
584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.45986584
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.3717511075
Short name T653
Test name
Test status
Simulation time 8369403329 ps
CPU time 8 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203468 kb
Host smart-3c3eafa7-8170-46b1-9d55-0080f237702b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37175
11075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3717511075
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.552905636
Short name T624
Test name
Test status
Simulation time 74248652 ps
CPU time 1.85 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203372 kb
Host smart-91fe800c-2050-473d-b002-0995d18b2f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55290
5636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.552905636
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.937202214
Short name T174
Test name
Test status
Simulation time 8362906225 ps
CPU time 8.09 seconds
Started Mar 21 01:24:23 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203244 kb
Host smart-223cd885-9d81-4731-bd9a-d46562eb5634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93720
2214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.937202214
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2979525738
Short name T460
Test name
Test status
Simulation time 8376815701 ps
CPU time 7.14 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:45 PM PDT 24
Peak memory 203464 kb
Host smart-6eb54762-41fa-4c13-bc41-bbae3bfe65e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
25738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2979525738
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1682066368
Short name T523
Test name
Test status
Simulation time 8402720450 ps
CPU time 7.94 seconds
Started Mar 21 01:24:22 PM PDT 24
Finished Mar 21 01:24:30 PM PDT 24
Peak memory 203484 kb
Host smart-d61b1f4a-7f4c-4323-b140-01894e90d74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16820
66368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1682066368
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3017833912
Short name T570
Test name
Test status
Simulation time 8363791756 ps
CPU time 7.7 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:38 PM PDT 24
Peak memory 203400 kb
Host smart-8fa1c81e-1347-496f-934b-075769ea574c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30178
33912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3017833912
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2181389665
Short name T102
Test name
Test status
Simulation time 8399043303 ps
CPU time 7.51 seconds
Started Mar 21 01:24:16 PM PDT 24
Finished Mar 21 01:24:24 PM PDT 24
Peak memory 203516 kb
Host smart-1bbe37cd-d3ee-42f2-a262-728f4e87f781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21813
89665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2181389665
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3577646984
Short name T825
Test name
Test status
Simulation time 8408657903 ps
CPU time 7.65 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203284 kb
Host smart-9f6903fa-6b0c-4314-8250-6a6364cc953a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35776
46984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3577646984
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.741397695
Short name T419
Test name
Test status
Simulation time 8390974879 ps
CPU time 7.24 seconds
Started Mar 21 01:24:28 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 203340 kb
Host smart-c32c12db-4c4e-402c-9399-40c37fd94e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74139
7695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.741397695
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1231920519
Short name T504
Test name
Test status
Simulation time 27948378 ps
CPU time 0.66 seconds
Started Mar 21 01:24:20 PM PDT 24
Finished Mar 21 01:24:21 PM PDT 24
Peak memory 202924 kb
Host smart-87f7027b-e3e3-4898-8214-e0812f8143cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12319
20519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1231920519
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.997130679
Short name T431
Test name
Test status
Simulation time 8367288727 ps
CPU time 7.32 seconds
Started Mar 21 01:24:24 PM PDT 24
Finished Mar 21 01:24:32 PM PDT 24
Peak memory 203548 kb
Host smart-9cd1271f-a373-407f-a946-5335c794b86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99713
0679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.997130679
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3448657658
Short name T130
Test name
Test status
Simulation time 8455257408 ps
CPU time 7.67 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:25 PM PDT 24
Peak memory 203380 kb
Host smart-f41d43b1-2796-433b-b700-5279029007e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34486
57658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3448657658
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.3918090790
Short name T233
Test name
Test status
Simulation time 8384178882 ps
CPU time 7.92 seconds
Started Mar 21 01:24:27 PM PDT 24
Finished Mar 21 01:24:35 PM PDT 24
Peak memory 203544 kb
Host smart-dd4562ce-a1d1-4ffc-b54e-5ed2b07e74d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39180
90790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.3918090790
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2606548439
Short name T582
Test name
Test status
Simulation time 8360594308 ps
CPU time 7.18 seconds
Started Mar 21 01:24:26 PM PDT 24
Finished Mar 21 01:24:34 PM PDT 24
Peak memory 203492 kb
Host smart-e16b3377-414d-4e04-8930-ad8dd6782a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26065
48439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2606548439
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3366635216
Short name T67
Test name
Test status
Simulation time 8475673705 ps
CPU time 7.3 seconds
Started Mar 21 01:24:23 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203608 kb
Host smart-e6e626bc-db84-478f-8d9f-7fc7b2d37529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33666
35216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3366635216
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.4032743662
Short name T450
Test name
Test status
Simulation time 8369750192 ps
CPU time 10.18 seconds
Started Mar 21 01:24:15 PM PDT 24
Finished Mar 21 01:24:26 PM PDT 24
Peak memory 203540 kb
Host smart-5e146014-9167-4d3f-a53d-b6e181b5b8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40327
43662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.4032743662
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.1666959055
Short name T479
Test name
Test status
Simulation time 8370976222 ps
CPU time 7.17 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:45 PM PDT 24
Peak memory 203480 kb
Host smart-4b9e1154-6a47-434d-8042-b44cca541d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16669
59055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1666959055
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2853282046
Short name T517
Test name
Test status
Simulation time 151867190 ps
CPU time 1.78 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:32 PM PDT 24
Peak memory 203320 kb
Host smart-e6ad8150-fcce-4afa-8f32-d890b01c0f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28532
82046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2853282046
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1026958185
Short name T163
Test name
Test status
Simulation time 8358000992 ps
CPU time 7.18 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203296 kb
Host smart-50fb0600-6ea2-4056-a11c-51bb99ecf772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10269
58185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1026958185
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.15985901
Short name T741
Test name
Test status
Simulation time 8410687276 ps
CPU time 7.78 seconds
Started Mar 21 01:24:33 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 203488 kb
Host smart-425211ec-0ad1-4fe7-bc25-df36025316a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15985
901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.15985901
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1815716906
Short name T673
Test name
Test status
Simulation time 8414647471 ps
CPU time 7.35 seconds
Started Mar 21 01:24:26 PM PDT 24
Finished Mar 21 01:24:34 PM PDT 24
Peak memory 203408 kb
Host smart-73c30780-776e-4f05-8552-af281d84191f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18157
16906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1815716906
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.763835132
Short name T724
Test name
Test status
Simulation time 8362411266 ps
CPU time 7.39 seconds
Started Mar 21 01:24:20 PM PDT 24
Finished Mar 21 01:24:27 PM PDT 24
Peak memory 203228 kb
Host smart-0095e38c-1b46-41e5-9011-bbdf461aa522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76383
5132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.763835132
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1337909877
Short name T797
Test name
Test status
Simulation time 8373005864 ps
CPU time 7.25 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 203292 kb
Host smart-97282174-56be-4ed7-8824-15545e13a756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13379
09877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1337909877
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3615108877
Short name T746
Test name
Test status
Simulation time 8405162684 ps
CPU time 8.18 seconds
Started Mar 21 01:24:23 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203332 kb
Host smart-ba4bc5c3-7f2f-4f5f-b0f9-89d6c3fad3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36151
08877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3615108877
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.391985825
Short name T723
Test name
Test status
Simulation time 24322876 ps
CPU time 0.64 seconds
Started Mar 21 01:24:17 PM PDT 24
Finished Mar 21 01:24:18 PM PDT 24
Peak memory 202908 kb
Host smart-3981ba27-991b-4857-9c58-e3d74543b486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39198
5825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.391985825
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2479856377
Short name T521
Test name
Test status
Simulation time 8396769298 ps
CPU time 8.91 seconds
Started Mar 21 01:24:28 PM PDT 24
Finished Mar 21 01:24:37 PM PDT 24
Peak memory 203536 kb
Host smart-b1de18ff-0abb-432f-951d-b3d9d3c133dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
56377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2479856377
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.3863617309
Short name T832
Test name
Test status
Simulation time 8407511395 ps
CPU time 8.28 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203388 kb
Host smart-52163ded-7fcb-45c0-8462-98c851d0e9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38636
17309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3863617309
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.2099816009
Short name T520
Test name
Test status
Simulation time 8388937396 ps
CPU time 7.5 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 203544 kb
Host smart-09d04458-085a-443f-be0b-278e8e5202f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20998
16009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.2099816009
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1907465546
Short name T399
Test name
Test status
Simulation time 8357442107 ps
CPU time 7.79 seconds
Started Mar 21 01:24:25 PM PDT 24
Finished Mar 21 01:24:33 PM PDT 24
Peak memory 203316 kb
Host smart-e8ad4cd8-87e0-4f87-bf3e-e178348bf6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19074
65546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1907465546
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.4158195317
Short name T424
Test name
Test status
Simulation time 8371876712 ps
CPU time 9.16 seconds
Started Mar 21 01:24:22 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203444 kb
Host smart-47f0df92-bf90-4cfb-be7b-9af4aa01b168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41581
95317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4158195317
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.627953126
Short name T421
Test name
Test status
Simulation time 8367447502 ps
CPU time 7.39 seconds
Started Mar 21 01:24:21 PM PDT 24
Finished Mar 21 01:24:29 PM PDT 24
Peak memory 203308 kb
Host smart-b3e6bc2a-17cd-4291-b5d9-c8d178ed8b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62795
3126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.627953126
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.4019953124
Short name T535
Test name
Test status
Simulation time 70548909 ps
CPU time 1.78 seconds
Started Mar 21 01:24:27 PM PDT 24
Finished Mar 21 01:24:29 PM PDT 24
Peak memory 203248 kb
Host smart-ebd479e1-161b-4218-a893-4cc92ca94054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40199
53124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.4019953124
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.96385490
Short name T176
Test name
Test status
Simulation time 8358614833 ps
CPU time 7.28 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203212 kb
Host smart-43f7a0a7-02e6-4b40-b364-333f22810178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96385
490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.96385490
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2925116152
Short name T675
Test name
Test status
Simulation time 8403683407 ps
CPU time 7.21 seconds
Started Mar 21 01:24:34 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 203412 kb
Host smart-c33facce-f4f0-4e3c-b438-9d53d021db28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29251
16152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2925116152
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1687972408
Short name T764
Test name
Test status
Simulation time 8410457910 ps
CPU time 8.45 seconds
Started Mar 21 01:24:21 PM PDT 24
Finished Mar 21 01:24:30 PM PDT 24
Peak memory 203296 kb
Host smart-bbff7079-094e-42cb-ab18-4e4c6ab96695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16879
72408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1687972408
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.729390231
Short name T286
Test name
Test status
Simulation time 8363137627 ps
CPU time 7.18 seconds
Started Mar 21 01:24:34 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203220 kb
Host smart-aa24b6a7-3422-42b5-aa20-4c6d5110367a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72939
0231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.729390231
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.282548474
Short name T87
Test name
Test status
Simulation time 8414940927 ps
CPU time 7.64 seconds
Started Mar 21 01:24:20 PM PDT 24
Finished Mar 21 01:24:28 PM PDT 24
Peak memory 203412 kb
Host smart-755e3640-54b9-4371-95f0-ac79c3897233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28254
8474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.282548474
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3693930036
Short name T737
Test name
Test status
Simulation time 8388037737 ps
CPU time 8.93 seconds
Started Mar 21 01:24:18 PM PDT 24
Finished Mar 21 01:24:27 PM PDT 24
Peak memory 203228 kb
Host smart-a038e949-915f-4fec-b387-60e8fe9d8b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36939
30036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3693930036
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3623943230
Short name T314
Test name
Test status
Simulation time 8377876140 ps
CPU time 7.13 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:38 PM PDT 24
Peak memory 203292 kb
Host smart-ea36222e-9329-4523-8400-65bd31228335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36239
43230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3623943230
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3788649280
Short name T345
Test name
Test status
Simulation time 24538118 ps
CPU time 0.63 seconds
Started Mar 21 01:24:44 PM PDT 24
Finished Mar 21 01:24:45 PM PDT 24
Peak memory 202972 kb
Host smart-0c64e657-aa3c-4a47-98ae-5112200599ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37886
49280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3788649280
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1773603435
Short name T715
Test name
Test status
Simulation time 8390407549 ps
CPU time 8.1 seconds
Started Mar 21 01:24:24 PM PDT 24
Finished Mar 21 01:24:32 PM PDT 24
Peak memory 203440 kb
Host smart-8b75de2c-dcec-42c7-b2cb-46d2b75df351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17736
03435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1773603435
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.978796559
Short name T383
Test name
Test status
Simulation time 8403441159 ps
CPU time 8.1 seconds
Started Mar 21 01:24:20 PM PDT 24
Finished Mar 21 01:24:28 PM PDT 24
Peak memory 203448 kb
Host smart-5cf0611a-7879-4eab-98d1-404d08974166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97879
6559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.978796559
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.2727505916
Short name T309
Test name
Test status
Simulation time 8365275110 ps
CPU time 7.13 seconds
Started Mar 21 01:24:24 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203456 kb
Host smart-79882e27-65be-4e00-a721-8ab6c4bafde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27275
05916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.2727505916
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.522645841
Short name T857
Test name
Test status
Simulation time 8357086882 ps
CPU time 9.55 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203308 kb
Host smart-ca5c090a-1d90-411d-a470-765ff0a030a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52264
5841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.522645841
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3543118685
Short name T313
Test name
Test status
Simulation time 8365576344 ps
CPU time 7.41 seconds
Started Mar 21 01:22:53 PM PDT 24
Finished Mar 21 01:23:01 PM PDT 24
Peak memory 203556 kb
Host smart-e00b8055-6e19-4ec0-b851-a0e62f759084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35431
18685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3543118685
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.1910650979
Short name T295
Test name
Test status
Simulation time 8366669968 ps
CPU time 6.94 seconds
Started Mar 21 01:22:49 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 203456 kb
Host smart-68e80d93-0a2f-4548-a4aa-a683076a8989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19106
50979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1910650979
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1108128898
Short name T370
Test name
Test status
Simulation time 260089969 ps
CPU time 2.11 seconds
Started Mar 21 01:22:58 PM PDT 24
Finished Mar 21 01:23:00 PM PDT 24
Peak memory 203524 kb
Host smart-23a75241-f717-40d1-8c1a-833f3cfa01da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11081
28898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1108128898
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3914485255
Short name T405
Test name
Test status
Simulation time 8421812028 ps
CPU time 7.34 seconds
Started Mar 21 01:22:47 PM PDT 24
Finished Mar 21 01:22:55 PM PDT 24
Peak memory 203392 kb
Host smart-479e2e7d-810b-47a0-8815-e097eeef7913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39144
85255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3914485255
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.4238934088
Short name T263
Test name
Test status
Simulation time 8408988214 ps
CPU time 7.11 seconds
Started Mar 21 01:22:50 PM PDT 24
Finished Mar 21 01:22:57 PM PDT 24
Peak memory 203444 kb
Host smart-d45e67ef-6245-4b25-8dc1-38923af18e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
34088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4238934088
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.461918527
Short name T848
Test name
Test status
Simulation time 8366408816 ps
CPU time 7.91 seconds
Started Mar 21 01:22:50 PM PDT 24
Finished Mar 21 01:22:59 PM PDT 24
Peak memory 203212 kb
Host smart-de31336c-52f2-4fe2-8a61-0bd8d71db618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46191
8527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.461918527
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.4080123636
Short name T84
Test name
Test status
Simulation time 8393547928 ps
CPU time 9.02 seconds
Started Mar 21 01:22:51 PM PDT 24
Finished Mar 21 01:23:00 PM PDT 24
Peak memory 203400 kb
Host smart-a4581106-505d-45e2-9290-a5fdaac21387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40801
23636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.4080123636
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3262263624
Short name T280
Test name
Test status
Simulation time 8397318987 ps
CPU time 7.84 seconds
Started Mar 21 01:22:48 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 203284 kb
Host smart-56bc3be7-bb3e-4d4e-a473-04d7d56f4aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32622
63624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3262263624
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1929931856
Short name T428
Test name
Test status
Simulation time 8406427624 ps
CPU time 7.95 seconds
Started Mar 21 01:22:40 PM PDT 24
Finished Mar 21 01:22:48 PM PDT 24
Peak memory 203336 kb
Host smart-18c9bbd4-88a3-4c6a-a5c7-a0bd1bc71d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19299
31856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1929931856
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1095167011
Short name T388
Test name
Test status
Simulation time 26853437 ps
CPU time 0.65 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 202904 kb
Host smart-d7b27d46-762c-4566-91ad-ace4a40c134f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10951
67011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1095167011
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3174164006
Short name T501
Test name
Test status
Simulation time 8369890940 ps
CPU time 7.88 seconds
Started Mar 21 01:22:53 PM PDT 24
Finished Mar 21 01:23:02 PM PDT 24
Peak memory 203896 kb
Host smart-2c1adc8e-58e1-405a-8bc4-dcd400d388b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31741
64006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3174164006
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.367313501
Short name T131
Test name
Test status
Simulation time 8435723268 ps
CPU time 8.3 seconds
Started Mar 21 01:22:54 PM PDT 24
Finished Mar 21 01:23:07 PM PDT 24
Peak memory 203484 kb
Host smart-5c94bcac-2dfd-4c53-9959-5d70876e2d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36731
3501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.367313501
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3840855078
Short name T478
Test name
Test status
Simulation time 8377873343 ps
CPU time 7.32 seconds
Started Mar 21 01:23:02 PM PDT 24
Finished Mar 21 01:23:09 PM PDT 24
Peak memory 203560 kb
Host smart-aa3678fa-db22-4053-9987-31b9f5682e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38408
55078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3840855078
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.19412504
Short name T52
Test name
Test status
Simulation time 102506094 ps
CPU time 0.92 seconds
Started Mar 21 01:22:57 PM PDT 24
Finished Mar 21 01:22:58 PM PDT 24
Peak memory 219140 kb
Host smart-f32a7045-b738-4d2d-9a85-2e9d854a0d9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=19412504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.19412504
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1611604686
Short name T268
Test name
Test status
Simulation time 8360177084 ps
CPU time 8.21 seconds
Started Mar 21 01:22:51 PM PDT 24
Finished Mar 21 01:23:00 PM PDT 24
Peak memory 203424 kb
Host smart-21a3a702-c0e0-4dd9-991a-419dfe5da6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16116
04686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1611604686
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2481943554
Short name T813
Test name
Test status
Simulation time 8468553121 ps
CPU time 7.59 seconds
Started Mar 21 01:22:49 PM PDT 24
Finished Mar 21 01:22:57 PM PDT 24
Peak memory 203552 kb
Host smart-7573ab44-0373-49db-9ee8-580447642d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24819
43554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2481943554
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2065601748
Short name T584
Test name
Test status
Simulation time 8373345404 ps
CPU time 7.48 seconds
Started Mar 21 01:24:58 PM PDT 24
Finished Mar 21 01:25:05 PM PDT 24
Peak memory 203520 kb
Host smart-bb52008f-da04-4a9c-afb7-ba1b29f46fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20656
01748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2065601748
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_enable.2875190191
Short name T612
Test name
Test status
Simulation time 8364977159 ps
CPU time 7.35 seconds
Started Mar 21 01:24:33 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 203576 kb
Host smart-c56e9da7-90ba-4466-aa4b-fd184a3a541d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751
90191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2875190191
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.237802452
Short name T788
Test name
Test status
Simulation time 93322324 ps
CPU time 1.09 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203448 kb
Host smart-e38f454b-9952-4b88-ad1a-87fe74de799e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23780
2452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.237802452
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2639594852
Short name T119
Test name
Test status
Simulation time 8416669325 ps
CPU time 7.56 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:37 PM PDT 24
Peak memory 203360 kb
Host smart-254cc3b1-d63b-45bf-8e53-bae65e9d677e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26395
94852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2639594852
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4012194069
Short name T801
Test name
Test status
Simulation time 8410544315 ps
CPU time 7.42 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203468 kb
Host smart-be21d00e-0203-49f8-af75-b1b4c09aa6e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
94069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4012194069
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3560932757
Short name T842
Test name
Test status
Simulation time 8366219682 ps
CPU time 7.04 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203404 kb
Host smart-ab591422-c42d-4c3c-a689-35594f58267b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35609
32757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3560932757
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3847525
Short name T713
Test name
Test status
Simulation time 8427484222 ps
CPU time 7.55 seconds
Started Mar 21 01:24:57 PM PDT 24
Finished Mar 21 01:25:05 PM PDT 24
Peak memory 203460 kb
Host smart-68bbe78f-49cb-49c3-882b-8dd8013ac90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38475
25 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3847525
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2810800985
Short name T657
Test name
Test status
Simulation time 8370606278 ps
CPU time 9.04 seconds
Started Mar 21 01:24:33 PM PDT 24
Finished Mar 21 01:24:42 PM PDT 24
Peak memory 203328 kb
Host smart-47e10a3e-28dc-4188-9576-d38caf920df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28108
00985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2810800985
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3323169983
Short name T652
Test name
Test status
Simulation time 8389692203 ps
CPU time 7.36 seconds
Started Mar 21 01:24:36 PM PDT 24
Finished Mar 21 01:24:44 PM PDT 24
Peak memory 203460 kb
Host smart-3da78f06-7939-486b-92e5-7da4b5894ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33231
69983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3323169983
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1800293873
Short name T808
Test name
Test status
Simulation time 29605817 ps
CPU time 0.7 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203028 kb
Host smart-3fb60968-ca6a-4d5c-ad01-4a8e9f840d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
93873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1800293873
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1388225056
Short name T446
Test name
Test status
Simulation time 8398281232 ps
CPU time 7.31 seconds
Started Mar 21 01:24:27 PM PDT 24
Finished Mar 21 01:24:35 PM PDT 24
Peak memory 203424 kb
Host smart-cb56d92e-020a-486e-aa7c-0368ce9fd2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13882
25056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1388225056
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3092357469
Short name T588
Test name
Test status
Simulation time 8374520601 ps
CPU time 7.47 seconds
Started Mar 21 01:24:54 PM PDT 24
Finished Mar 21 01:25:02 PM PDT 24
Peak memory 203364 kb
Host smart-c82b26b4-935d-41fc-826b-078f725e7235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30923
57469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3092357469
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.1421115672
Short name T320
Test name
Test status
Simulation time 8409687583 ps
CPU time 7.57 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 203508 kb
Host smart-be2fff5c-d11d-4ef8-8d20-f28bd8adc761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14211
15672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.1421115672
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1435303844
Short name T684
Test name
Test status
Simulation time 8360601858 ps
CPU time 9 seconds
Started Mar 21 01:24:26 PM PDT 24
Finished Mar 21 01:24:35 PM PDT 24
Peak memory 203464 kb
Host smart-d72e2d7d-665c-4d70-b9be-8d3199e3a296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
03844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1435303844
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2545058156
Short name T152
Test name
Test status
Simulation time 8481443890 ps
CPU time 7.62 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203488 kb
Host smart-0d273e29-a680-4c1f-b01b-4036587ab6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25450
58156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2545058156
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.511938348
Short name T749
Test name
Test status
Simulation time 8367511838 ps
CPU time 7.97 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:48 PM PDT 24
Peak memory 203580 kb
Host smart-e4d9c555-5b82-4faa-b898-edbc979dcd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51193
8348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.511938348
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.2279699445
Short name T668
Test name
Test status
Simulation time 8366236882 ps
CPU time 8.26 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203416 kb
Host smart-89ed064d-2d17-4de4-9614-460936f77662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22796
99445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2279699445
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.806111241
Short name T209
Test name
Test status
Simulation time 73640751 ps
CPU time 1.93 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 203324 kb
Host smart-60f002c9-c7ff-44c5-b2b1-4025532182cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80611
1241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.806111241
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.692741825
Short name T178
Test name
Test status
Simulation time 8363846632 ps
CPU time 7.45 seconds
Started Mar 21 01:24:44 PM PDT 24
Finished Mar 21 01:24:52 PM PDT 24
Peak memory 203220 kb
Host smart-c1412006-5b31-4272-b4d5-9598912862cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69274
1825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.692741825
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3988925564
Short name T600
Test name
Test status
Simulation time 8444273956 ps
CPU time 8.6 seconds
Started Mar 21 01:24:59 PM PDT 24
Finished Mar 21 01:25:08 PM PDT 24
Peak memory 203492 kb
Host smart-f8de6690-0d3c-42bf-9fa8-dd174aef9f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39889
25564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3988925564
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2005155167
Short name T211
Test name
Test status
Simulation time 8413557742 ps
CPU time 7.12 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:38 PM PDT 24
Peak memory 203544 kb
Host smart-e18a885e-1aea-4f67-91f3-fcbe3aad8a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20051
55167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2005155167
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3719013103
Short name T490
Test name
Test status
Simulation time 8362460862 ps
CPU time 9.15 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203328 kb
Host smart-d883e20f-9db7-4553-bd1d-bef06eef5bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
13103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3719013103
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3858279115
Short name T109
Test name
Test status
Simulation time 8402803720 ps
CPU time 7.31 seconds
Started Mar 21 01:24:27 PM PDT 24
Finished Mar 21 01:24:35 PM PDT 24
Peak memory 203496 kb
Host smart-2ca12012-e3d8-405e-9b80-097a60153e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582
79115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3858279115
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3537507425
Short name T639
Test name
Test status
Simulation time 8409693634 ps
CPU time 7.17 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203436 kb
Host smart-c8f5dde4-5c12-4b6e-b1b9-10a97e2e06de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
07425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3537507425
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2058714040
Short name T381
Test name
Test status
Simulation time 8399648048 ps
CPU time 9.09 seconds
Started Mar 21 01:24:28 PM PDT 24
Finished Mar 21 01:24:37 PM PDT 24
Peak memory 203452 kb
Host smart-e8b33d65-8400-4f75-8bdc-4fef081bc7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20587
14040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2058714040
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.644738756
Short name T34
Test name
Test status
Simulation time 30075299 ps
CPU time 0.65 seconds
Started Mar 21 01:24:28 PM PDT 24
Finished Mar 21 01:24:29 PM PDT 24
Peak memory 202948 kb
Host smart-0490843c-8ac0-41ce-8509-2318e6e00cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64473
8756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.644738756
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1949806592
Short name T806
Test name
Test status
Simulation time 8391229031 ps
CPU time 6.99 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 203508 kb
Host smart-25efba63-dbce-444b-bb2c-e304ebfedca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19498
06592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1949806592
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1515583478
Short name T552
Test name
Test status
Simulation time 8454319321 ps
CPU time 7.24 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:44 PM PDT 24
Peak memory 203452 kb
Host smart-be49c689-5dc6-4161-b932-25a6b3f961c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15155
83478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1515583478
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.239501986
Short name T402
Test name
Test status
Simulation time 8388197153 ps
CPU time 8.83 seconds
Started Mar 21 01:24:28 PM PDT 24
Finished Mar 21 01:24:37 PM PDT 24
Peak memory 203552 kb
Host smart-5843f925-10b0-449f-909a-dbbfb1076773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23950
1986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.239501986
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3069441605
Short name T559
Test name
Test status
Simulation time 8362699327 ps
CPU time 8.53 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:48 PM PDT 24
Peak memory 203364 kb
Host smart-5d1e56eb-047c-469b-b9b5-a5fc783b0056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30694
41605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3069441605
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.228708518
Short name T785
Test name
Test status
Simulation time 8475619587 ps
CPU time 8.36 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:48 PM PDT 24
Peak memory 203580 kb
Host smart-57ddf6f7-8313-411b-8ac2-9bfe69637ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22870
8518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.228708518
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1680413797
Short name T831
Test name
Test status
Simulation time 8364512870 ps
CPU time 7.57 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:38 PM PDT 24
Peak memory 203424 kb
Host smart-c72897e5-6eb2-43a3-882f-1d3139329ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16804
13797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1680413797
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.4248642048
Short name T826
Test name
Test status
Simulation time 8370464195 ps
CPU time 7.42 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:36 PM PDT 24
Peak memory 203548 kb
Host smart-646736c8-f81a-43ab-91a4-9fbf4012c4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42486
42048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.4248642048
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.431757562
Short name T656
Test name
Test status
Simulation time 40643840 ps
CPU time 0.98 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:31 PM PDT 24
Peak memory 203196 kb
Host smart-4c3cd4c9-646d-419f-ba09-17fe3ebc9616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43175
7562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.431757562
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.4235329285
Short name T665
Test name
Test status
Simulation time 8362942842 ps
CPU time 8.14 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203300 kb
Host smart-13f8f9fc-0022-4fb3-8f6f-c3cf30d3617d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42353
29285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.4235329285
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.143157799
Short name T284
Test name
Test status
Simulation time 8393436334 ps
CPU time 8.83 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203364 kb
Host smart-90bd183d-f0d7-4a2b-8b8f-246e488b5a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315
7799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.143157799
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1407034365
Short name T401
Test name
Test status
Simulation time 8410635152 ps
CPU time 8.97 seconds
Started Mar 21 01:24:36 PM PDT 24
Finished Mar 21 01:24:45 PM PDT 24
Peak memory 203576 kb
Host smart-d036949c-4aa3-4ece-b3c6-3ce39f5d4292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14070
34365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1407034365
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.452989687
Short name T760
Test name
Test status
Simulation time 8362944516 ps
CPU time 7.48 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:45 PM PDT 24
Peak memory 203468 kb
Host smart-453c8f6b-cfab-4e8a-abd3-31ad1d78e984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45298
9687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.452989687
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.258092837
Short name T451
Test name
Test status
Simulation time 8404554428 ps
CPU time 7.52 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:38 PM PDT 24
Peak memory 203308 kb
Host smart-78810009-daaa-4535-a1c9-1ef2022a19bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25809
2837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.258092837
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.281329142
Short name T354
Test name
Test status
Simulation time 8398544737 ps
CPU time 7.33 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203464 kb
Host smart-18762202-dbc6-41f5-b97d-c0b705e1c30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28132
9142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.281329142
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1150541390
Short name T404
Test name
Test status
Simulation time 23891120 ps
CPU time 0.64 seconds
Started Mar 21 01:24:27 PM PDT 24
Finished Mar 21 01:24:28 PM PDT 24
Peak memory 202852 kb
Host smart-89adddb8-6f21-44da-8b6e-5c20890da962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
41390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1150541390
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2079748967
Short name T734
Test name
Test status
Simulation time 8395581974 ps
CPU time 8.99 seconds
Started Mar 21 01:24:34 PM PDT 24
Finished Mar 21 01:24:43 PM PDT 24
Peak memory 203456 kb
Host smart-cf1a02c7-81c3-417b-bb6e-03b958b8f277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
48967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2079748967
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.316813114
Short name T689
Test name
Test status
Simulation time 8417082919 ps
CPU time 7.94 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203408 kb
Host smart-613a55ed-31c2-498b-955e-36ab78a07a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31681
3114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.316813114
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2474873053
Short name T610
Test name
Test status
Simulation time 8371067707 ps
CPU time 7.87 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203496 kb
Host smart-45a8671e-1a50-4742-a852-87704a4d1c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24748
73053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2474873053
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.196647496
Short name T72
Test name
Test status
Simulation time 8356226081 ps
CPU time 7.17 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203352 kb
Host smart-5445f8d4-3104-4691-b837-cf75d00ade38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19664
7496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.196647496
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.4110643764
Short name T613
Test name
Test status
Simulation time 8478817180 ps
CPU time 7.63 seconds
Started Mar 21 01:25:00 PM PDT 24
Finished Mar 21 01:25:08 PM PDT 24
Peak memory 203476 kb
Host smart-a4e894fa-6953-4baa-9a3f-34bae53c6b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41106
43764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.4110643764
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4036500215
Short name T448
Test name
Test status
Simulation time 8373530641 ps
CPU time 7.3 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203496 kb
Host smart-523dd8be-fe2a-4d57-bb36-4b72508662e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40365
00215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4036500215
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.4003360779
Short name T646
Test name
Test status
Simulation time 8366773228 ps
CPU time 7.57 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203484 kb
Host smart-8b557fa1-eb44-41ad-a890-6e496c90018b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
60779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.4003360779
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3092005493
Short name T46
Test name
Test status
Simulation time 47083537 ps
CPU time 1.17 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:42 PM PDT 24
Peak memory 203196 kb
Host smart-1b50bc88-8031-4e75-8dd1-9d4b6899ef74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30920
05493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3092005493
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.187891399
Short name T704
Test name
Test status
Simulation time 8363410598 ps
CPU time 8.04 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203196 kb
Host smart-414fd56f-d46f-4466-9b71-d4c08ba45a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
1399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.187891399
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3471758962
Short name T736
Test name
Test status
Simulation time 8414501447 ps
CPU time 7.13 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203548 kb
Host smart-e2a15247-221f-4de5-bedb-2db9f8984c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34717
58962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3471758962
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.4032547922
Short name T222
Test name
Test status
Simulation time 8363492342 ps
CPU time 6.91 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:25:57 PM PDT 24
Peak memory 201012 kb
Host smart-0d6d2560-6908-4c98-bd19-3b10ec15a68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40325
47922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.4032547922
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3043907353
Short name T739
Test name
Test status
Simulation time 8367698935 ps
CPU time 7.55 seconds
Started Mar 21 01:25:02 PM PDT 24
Finished Mar 21 01:25:15 PM PDT 24
Peak memory 203328 kb
Host smart-9ef2aa17-3db5-490b-ad65-f692962c36aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30439
07353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3043907353
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2670872402
Short name T812
Test name
Test status
Simulation time 8388361251 ps
CPU time 7.44 seconds
Started Mar 21 01:24:36 PM PDT 24
Finished Mar 21 01:24:44 PM PDT 24
Peak memory 203340 kb
Host smart-342a1e67-c1a1-4461-ae20-c299e7c22f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26708
72402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2670872402
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1466858178
Short name T376
Test name
Test status
Simulation time 31279981 ps
CPU time 0.64 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 202916 kb
Host smart-efcd3095-6c02-490c-a57c-2a6827d43ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14668
58178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1466858178
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3814787156
Short name T430
Test name
Test status
Simulation time 8398049439 ps
CPU time 8.3 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:48 PM PDT 24
Peak memory 203424 kb
Host smart-f9ac1fa5-e605-453a-8803-4fb21615a1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38147
87156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3814787156
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3571295755
Short name T638
Test name
Test status
Simulation time 8435139416 ps
CPU time 8.27 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:26:02 PM PDT 24
Peak memory 202784 kb
Host smart-2f3b9f17-ffaf-41b1-9e81-65b1287c18b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
95755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3571295755
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1961328007
Short name T844
Test name
Test status
Simulation time 8411138121 ps
CPU time 7.72 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203456 kb
Host smart-ead7360f-d655-402d-952d-0a450d638536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19613
28007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1961328007
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1416856577
Short name T695
Test name
Test status
Simulation time 8363545762 ps
CPU time 8.62 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 203448 kb
Host smart-d9668208-6364-49d9-a701-1ce533de5755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14168
56577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1416856577
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2736888331
Short name T640
Test name
Test status
Simulation time 8475932127 ps
CPU time 7.98 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203540 kb
Host smart-4ce77eb1-fb22-431c-b20e-481f247236dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27368
88331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2736888331
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2814004570
Short name T557
Test name
Test status
Simulation time 8371470054 ps
CPU time 8.01 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203508 kb
Host smart-a45b8ed8-5e66-4728-a637-3b0f032451ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
04570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2814004570
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.74958927
Short name T500
Test name
Test status
Simulation time 8371834566 ps
CPU time 9.35 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203540 kb
Host smart-f270b27c-c718-4d20-ab98-f2b26d33a31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74958
927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.74958927
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1550152575
Short name T180
Test name
Test status
Simulation time 8358553242 ps
CPU time 8.09 seconds
Started Mar 21 01:24:59 PM PDT 24
Finished Mar 21 01:25:07 PM PDT 24
Peak memory 203268 kb
Host smart-1a48f99a-5c18-4bd1-a6da-6bd9d1d6600f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15501
52575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1550152575
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.4034680976
Short name T556
Test name
Test status
Simulation time 8409582606 ps
CPU time 7.44 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:38 PM PDT 24
Peak memory 203440 kb
Host smart-4d8cad05-3012-4024-a9dc-210b0030c33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40346
80976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.4034680976
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4275574448
Short name T655
Test name
Test status
Simulation time 8368940265 ps
CPU time 7.57 seconds
Started Mar 21 01:24:29 PM PDT 24
Finished Mar 21 01:24:37 PM PDT 24
Peak memory 203244 kb
Host smart-ceb5ed19-5188-4108-ba7e-323527c8900c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42755
74448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4275574448
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1209774438
Short name T5
Test name
Test status
Simulation time 8420641195 ps
CPU time 9.13 seconds
Started Mar 21 01:24:36 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203440 kb
Host smart-712e6f2c-47f4-4169-9e9a-416c71f9918b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12097
74438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1209774438
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.4096075059
Short name T279
Test name
Test status
Simulation time 8390644632 ps
CPU time 7.33 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203500 kb
Host smart-5a6b6e1c-4347-45ea-a1af-7b9c0ce87454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40960
75059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.4096075059
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3844184795
Short name T846
Test name
Test status
Simulation time 8393225404 ps
CPU time 7.16 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203392 kb
Host smart-0b6339b7-882b-4b92-9a1f-4918f05f1d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38441
84795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3844184795
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3360859458
Short name T414
Test name
Test status
Simulation time 22540337 ps
CPU time 0.7 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:25:50 PM PDT 24
Peak memory 200564 kb
Host smart-aff89080-5356-4675-8d31-8ada66912de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33608
59458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3360859458
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1603707664
Short name T680
Test name
Test status
Simulation time 8379192747 ps
CPU time 9.35 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203536 kb
Host smart-a457934f-6eed-423e-b733-bdc50156a14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16037
07664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1603707664
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2384230442
Short name T776
Test name
Test status
Simulation time 8448178989 ps
CPU time 7.28 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203480 kb
Host smart-276b840f-fac5-422d-97ad-63c08b2d86d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23842
30442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2384230442
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.1919698320
Short name T334
Test name
Test status
Simulation time 8362477587 ps
CPU time 6.9 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203368 kb
Host smart-ef518212-ea6c-4b3f-ac49-c2081d6a816d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19196
98320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.1919698320
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2802323314
Short name T651
Test name
Test status
Simulation time 8356182809 ps
CPU time 7.5 seconds
Started Mar 21 01:24:48 PM PDT 24
Finished Mar 21 01:24:56 PM PDT 24
Peak memory 203444 kb
Host smart-65cb8aab-c525-4332-b69d-453b16452edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28023
23314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2802323314
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1652443654
Short name T603
Test name
Test status
Simulation time 8474993790 ps
CPU time 8.02 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203500 kb
Host smart-d88c52b6-7844-4946-92d7-569eddddb3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16524
43654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1652443654
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1046176526
Short name T729
Test name
Test status
Simulation time 8370684910 ps
CPU time 8.43 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203512 kb
Host smart-d2f2a691-81d5-4a27-878b-4b0fb97a6085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10461
76526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1046176526
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.2103714044
Short name T802
Test name
Test status
Simulation time 8369006981 ps
CPU time 8.46 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:25:58 PM PDT 24
Peak memory 200764 kb
Host smart-75ac181c-6e6d-4737-bdb0-44bf7ea1005f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21037
14044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2103714044
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1109001190
Short name T835
Test name
Test status
Simulation time 292692840 ps
CPU time 2.31 seconds
Started Mar 21 01:24:27 PM PDT 24
Finished Mar 21 01:24:29 PM PDT 24
Peak memory 203520 kb
Host smart-22caf39d-ed5e-4ddc-bacb-afae9edcafb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11090
01190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1109001190
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3326419940
Short name T157
Test name
Test status
Simulation time 8363549277 ps
CPU time 8.7 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203248 kb
Host smart-b4faddd2-3f91-4efe-8e68-2474d2a3cf6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33264
19940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3326419940
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3486577061
Short name T116
Test name
Test status
Simulation time 8414615903 ps
CPU time 9.06 seconds
Started Mar 21 01:24:42 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203392 kb
Host smart-b4f3567a-7ab1-4895-bf15-6530815ff765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865
77061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3486577061
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3195103935
Short name T800
Test name
Test status
Simulation time 8409758831 ps
CPU time 7.12 seconds
Started Mar 21 01:25:50 PM PDT 24
Finished Mar 21 01:25:57 PM PDT 24
Peak memory 202644 kb
Host smart-b5019665-0e37-40da-9824-7db8c039b1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31951
03935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3195103935
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1913455609
Short name T294
Test name
Test status
Simulation time 8365725772 ps
CPU time 7.17 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203428 kb
Host smart-1ef49637-3a03-495c-821d-0cf455355c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19134
55609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1913455609
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2850354746
Short name T362
Test name
Test status
Simulation time 8401765417 ps
CPU time 7.3 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:43 PM PDT 24
Peak memory 203308 kb
Host smart-e9b2b295-74ea-4780-b2d1-81a2cc5c082c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28503
54746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2850354746
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3041517776
Short name T468
Test name
Test status
Simulation time 8390428100 ps
CPU time 7.08 seconds
Started Mar 21 01:24:47 PM PDT 24
Finished Mar 21 01:25:00 PM PDT 24
Peak memory 203452 kb
Host smart-d4fe99f6-8436-4bd7-af44-918db22cb277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30415
17776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3041517776
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2336376169
Short name T524
Test name
Test status
Simulation time 29524570 ps
CPU time 0.6 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 202912 kb
Host smart-30e0ad4f-ee71-41f7-87a2-dac337de4ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23363
76169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2336376169
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3878200296
Short name T661
Test name
Test status
Simulation time 8394874528 ps
CPU time 7.63 seconds
Started Mar 21 01:24:31 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203540 kb
Host smart-456c893f-ab92-4700-a459-0b8033546d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38782
00296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3878200296
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2708062632
Short name T565
Test name
Test status
Simulation time 8438258694 ps
CPU time 7.63 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:25:57 PM PDT 24
Peak memory 200944 kb
Host smart-0591a2f2-4e27-46a4-b900-25f382d90e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080
62632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2708062632
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.1705278917
Short name T467
Test name
Test status
Simulation time 8394800174 ps
CPU time 8.47 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203488 kb
Host smart-6dcc2cce-b5e0-4fe0-982b-3330d6b1546c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17052
78917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.1705278917
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2087166384
Short name T735
Test name
Test status
Simulation time 8355598494 ps
CPU time 7.55 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203384 kb
Host smart-091c41fc-0103-4fd7-967d-5334b7f09660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20871
66384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2087166384
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.27786381
Short name T205
Test name
Test status
Simulation time 8365180855 ps
CPU time 6.91 seconds
Started Mar 21 01:24:36 PM PDT 24
Finished Mar 21 01:24:43 PM PDT 24
Peak memory 203576 kb
Host smart-82ba5aa2-5d27-46f1-9517-77e115fcb189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.27786381
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.1146129444
Short name T281
Test name
Test status
Simulation time 8371327974 ps
CPU time 8.52 seconds
Started Mar 21 01:25:49 PM PDT 24
Finished Mar 21 01:25:58 PM PDT 24
Peak memory 201808 kb
Host smart-c76d5408-acd5-465d-bbff-a5266c1ddb8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11461
29444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1146129444
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3136850219
Short name T226
Test name
Test status
Simulation time 172824012 ps
CPU time 1.48 seconds
Started Mar 21 01:26:01 PM PDT 24
Finished Mar 21 01:26:02 PM PDT 24
Peak memory 203320 kb
Host smart-88765b31-2509-4145-be0b-391250cbf039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31368
50219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3136850219
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.855709130
Short name T692
Test name
Test status
Simulation time 8358351932 ps
CPU time 9.28 seconds
Started Mar 21 01:24:42 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203216 kb
Host smart-da7b4557-92b5-454e-8898-b0c0ceaae08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85570
9130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.855709130
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2214645667
Short name T132
Test name
Test status
Simulation time 8387281223 ps
CPU time 7.22 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:44 PM PDT 24
Peak memory 203516 kb
Host smart-cbc591d7-14df-40f3-8727-38007c67bc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22146
45667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2214645667
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2976205828
Short name T40
Test name
Test status
Simulation time 8413432894 ps
CPU time 7.51 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203468 kb
Host smart-c287833d-3966-4a02-b14e-4639db9eb1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29762
05828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2976205828
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.202074133
Short name T454
Test name
Test status
Simulation time 8363310657 ps
CPU time 7.09 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203272 kb
Host smart-f23e9ff7-4780-4c2a-bd71-c00edbd31fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20207
4133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.202074133
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3576535062
Short name T221
Test name
Test status
Simulation time 8424817186 ps
CPU time 7.45 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:37 PM PDT 24
Peak memory 203404 kb
Host smart-2c424986-392f-4c84-a846-d0cf0dba12ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35765
35062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3576535062
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.598679142
Short name T488
Test name
Test status
Simulation time 8375685122 ps
CPU time 7.02 seconds
Started Mar 21 01:24:44 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203308 kb
Host smart-6c69f880-7a13-4558-89d4-a9e669477a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59867
9142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.598679142
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3371077108
Short name T751
Test name
Test status
Simulation time 8371477058 ps
CPU time 8.03 seconds
Started Mar 21 01:24:30 PM PDT 24
Finished Mar 21 01:24:39 PM PDT 24
Peak memory 203212 kb
Host smart-ee96db6a-639f-4349-96fa-d1b938a8e2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33710
77108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3371077108
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.4293865880
Short name T36
Test name
Test status
Simulation time 24704772 ps
CPU time 0.64 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 202984 kb
Host smart-da7c97f4-03dc-44aa-8816-56ee781722ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938
65880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.4293865880
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3400353002
Short name T841
Test name
Test status
Simulation time 8376246548 ps
CPU time 8.8 seconds
Started Mar 21 01:24:33 PM PDT 24
Finished Mar 21 01:24:42 PM PDT 24
Peak memory 203516 kb
Host smart-a3401a80-d3d0-489d-9192-335bd8e6f3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34003
53002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3400353002
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.4073011778
Short name T422
Test name
Test status
Simulation time 8383711920 ps
CPU time 7.31 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203480 kb
Host smart-6142b9d3-5df1-48b0-8555-bd2da88f9042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40730
11778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.4073011778
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2171882202
Short name T15
Test name
Test status
Simulation time 8357673122 ps
CPU time 7.01 seconds
Started Mar 21 01:24:33 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203556 kb
Host smart-eae4e31e-8824-4972-884e-c5a8b1fc34e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21718
82202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2171882202
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2587839007
Short name T137
Test name
Test status
Simulation time 8474984709 ps
CPU time 8.42 seconds
Started Mar 21 01:24:33 PM PDT 24
Finished Mar 21 01:24:42 PM PDT 24
Peak memory 203568 kb
Host smart-fd410e47-5ce4-45fb-85c8-c5818e8b6ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25878
39007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2587839007
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.959215928
Short name T693
Test name
Test status
Simulation time 8370631626 ps
CPU time 8.36 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203576 kb
Host smart-9a329bc0-e86a-4cc2-b379-feeff2993688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95921
5928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.959215928
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.213263286
Short name T74
Test name
Test status
Simulation time 8369385446 ps
CPU time 7.42 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203468 kb
Host smart-317b21e1-3a15-410a-ad4d-b7f34ed1bdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21326
3286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.213263286
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3187925484
Short name T706
Test name
Test status
Simulation time 243028140 ps
CPU time 1.9 seconds
Started Mar 21 01:25:01 PM PDT 24
Finished Mar 21 01:25:03 PM PDT 24
Peak memory 203228 kb
Host smart-06e09836-6e87-49d4-b9e4-0978ad6b10ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31879
25484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3187925484
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3467322312
Short name T720
Test name
Test status
Simulation time 8361823620 ps
CPU time 7 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:45 PM PDT 24
Peak memory 203344 kb
Host smart-d6b41f02-cd68-467e-81f3-c0050a29b106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34673
22312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3467322312
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.200375465
Short name T223
Test name
Test status
Simulation time 8420527638 ps
CPU time 7.05 seconds
Started Mar 21 01:24:32 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 203452 kb
Host smart-1fd654d7-0fcd-4b98-aa06-f00f2c36e053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20037
5465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.200375465
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2254335110
Short name T266
Test name
Test status
Simulation time 8411727092 ps
CPU time 7.67 seconds
Started Mar 21 01:24:55 PM PDT 24
Finished Mar 21 01:25:04 PM PDT 24
Peak memory 203452 kb
Host smart-f53e3dec-88b8-4de4-b51d-4135dbc7996e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22543
35110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2254335110
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.926775968
Short name T771
Test name
Test status
Simulation time 8368775174 ps
CPU time 7.32 seconds
Started Mar 21 01:24:47 PM PDT 24
Finished Mar 21 01:24:55 PM PDT 24
Peak memory 203256 kb
Host smart-e38bfafa-eda3-4bb6-a5b8-435edd3eba6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92677
5968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.926775968
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3850568500
Short name T761
Test name
Test status
Simulation time 8404875110 ps
CPU time 7.08 seconds
Started Mar 21 01:24:36 PM PDT 24
Finished Mar 21 01:24:44 PM PDT 24
Peak memory 203444 kb
Host smart-f998e767-6f63-452c-9511-31fc5b3f731a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38505
68500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3850568500
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2200370543
Short name T827
Test name
Test status
Simulation time 8372744735 ps
CPU time 7.17 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203272 kb
Host smart-d739602b-b48b-489e-a892-c2d3609976fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
70543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2200370543
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3909320979
Short name T784
Test name
Test status
Simulation time 8383770126 ps
CPU time 7.52 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203376 kb
Host smart-2f8ace1f-c0dc-45e0-9c0f-ab91cfac76f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39093
20979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3909320979
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1343429301
Short name T447
Test name
Test status
Simulation time 24165673 ps
CPU time 0.65 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:40 PM PDT 24
Peak memory 202900 kb
Host smart-8a10a57c-7a0b-44ab-9900-dc743585e293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13434
29301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1343429301
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.200024660
Short name T536
Test name
Test status
Simulation time 8389407820 ps
CPU time 7.04 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:50 PM PDT 24
Peak memory 203424 kb
Host smart-0272c6f9-2818-4948-a7ce-05ffb81cf2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20002
4660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.200024660
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.4110554255
Short name T373
Test name
Test status
Simulation time 8391436100 ps
CPU time 7.78 seconds
Started Mar 21 01:24:59 PM PDT 24
Finished Mar 21 01:25:07 PM PDT 24
Peak memory 203392 kb
Host smart-0b1f7617-26f8-4cbb-9efd-e01bd421eb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41105
54255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.4110554255
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.2575341337
Short name T540
Test name
Test status
Simulation time 8394876037 ps
CPU time 9.53 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:55 PM PDT 24
Peak memory 203568 kb
Host smart-ec3fbf95-e95a-4ab3-9f89-a80b67872f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25753
41337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.2575341337
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.544221614
Short name T803
Test name
Test status
Simulation time 8361066303 ps
CPU time 6.92 seconds
Started Mar 21 01:24:44 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203368 kb
Host smart-d58efb9f-9a07-4545-8065-c64de07f2c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54422
1614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.544221614
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.719292129
Short name T574
Test name
Test status
Simulation time 8476376497 ps
CPU time 7.81 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203584 kb
Host smart-0b476802-a870-4ebf-8038-6619f29bf810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71929
2129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.719292129
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1446786206
Short name T291
Test name
Test status
Simulation time 8366350853 ps
CPU time 7.15 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:44 PM PDT 24
Peak memory 203512 kb
Host smart-33abd969-727c-47d5-9a2e-737e25822b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14467
86206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1446786206
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.2010163600
Short name T642
Test name
Test status
Simulation time 8369121661 ps
CPU time 7.19 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:50 PM PDT 24
Peak memory 203444 kb
Host smart-b832e9f6-9d10-463f-a0b8-d479869849cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20101
63600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2010163600
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2487318943
Short name T459
Test name
Test status
Simulation time 138957212 ps
CPU time 1.66 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 203400 kb
Host smart-3d6f6302-2053-4363-923b-83e02a5d71a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24873
18943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2487318943
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3860242900
Short name T822
Test name
Test status
Simulation time 8362089792 ps
CPU time 8.62 seconds
Started Mar 21 01:24:59 PM PDT 24
Finished Mar 21 01:25:08 PM PDT 24
Peak memory 203176 kb
Host smart-d9338ada-870b-4cdd-9666-755a8ac4e0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
42900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3860242900
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.639117929
Short name T122
Test name
Test status
Simulation time 8391830888 ps
CPU time 8.75 seconds
Started Mar 21 01:24:56 PM PDT 24
Finished Mar 21 01:25:05 PM PDT 24
Peak memory 203404 kb
Host smart-b0d4556b-983a-410f-bb18-5ee4e11979da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63911
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.639117929
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3777941180
Short name T519
Test name
Test status
Simulation time 8411691123 ps
CPU time 7.36 seconds
Started Mar 21 01:24:42 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203508 kb
Host smart-d7a9a85c-7c4b-4a55-9ffb-edf90289e288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37779
41180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3777941180
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2042352304
Short name T644
Test name
Test status
Simulation time 8366046409 ps
CPU time 9.42 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:50 PM PDT 24
Peak memory 203260 kb
Host smart-78f60928-931f-4717-a124-7ebb8c935520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20423
52304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2042352304
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3828720489
Short name T90
Test name
Test status
Simulation time 8390371790 ps
CPU time 7.74 seconds
Started Mar 21 01:24:49 PM PDT 24
Finished Mar 21 01:24:58 PM PDT 24
Peak memory 203440 kb
Host smart-96995e67-06d9-42ae-904c-d3021b698dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38287
20489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3828720489
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2854125933
Short name T707
Test name
Test status
Simulation time 8360635265 ps
CPU time 7.69 seconds
Started Mar 21 01:24:48 PM PDT 24
Finished Mar 21 01:25:01 PM PDT 24
Peak memory 203296 kb
Host smart-985353a9-71f9-47c7-b006-6c19f1706139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28541
25933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2854125933
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.932804504
Short name T231
Test name
Test status
Simulation time 8379560643 ps
CPU time 7.41 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:48 PM PDT 24
Peak memory 203380 kb
Host smart-545ae9e9-98d2-41be-a506-a0b1400903bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93280
4504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.932804504
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.979105038
Short name T496
Test name
Test status
Simulation time 27057962 ps
CPU time 0.61 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 202712 kb
Host smart-50b77102-df83-4a51-8ca4-d090bf50566e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97910
5038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.979105038
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3823252095
Short name T597
Test name
Test status
Simulation time 8405093549 ps
CPU time 7.18 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203544 kb
Host smart-feb0b074-64a6-4a3f-92af-a6b7aeded1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38232
52095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3823252095
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.576355972
Short name T738
Test name
Test status
Simulation time 8424409800 ps
CPU time 9.54 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:55 PM PDT 24
Peak memory 203360 kb
Host smart-79de0317-819f-4f05-9293-dbfa9c40a9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57635
5972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.576355972
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.2271571003
Short name T666
Test name
Test status
Simulation time 8394603828 ps
CPU time 8.1 seconds
Started Mar 21 01:24:33 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 203492 kb
Host smart-74ce90b6-fd55-4c6b-bf27-5edf43fc71f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22715
71003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.2271571003
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1756238903
Short name T595
Test name
Test status
Simulation time 8360846838 ps
CPU time 7.54 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:53 PM PDT 24
Peak memory 203220 kb
Host smart-d4d2bf69-8971-451a-95de-05c2f795f584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17562
38903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1756238903
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2060577879
Short name T145
Test name
Test status
Simulation time 8471397905 ps
CPU time 7.01 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:44 PM PDT 24
Peak memory 203576 kb
Host smart-14039332-7963-4f3f-845f-aa6f18e83dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20605
77879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2060577879
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2855660169
Short name T276
Test name
Test status
Simulation time 8373302190 ps
CPU time 8.13 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:55 PM PDT 24
Peak memory 203568 kb
Host smart-947312a2-68be-4995-b586-25e8b06b1fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28556
60169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2855660169
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.3482534920
Short name T845
Test name
Test status
Simulation time 8368068276 ps
CPU time 9.72 seconds
Started Mar 21 01:24:37 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203568 kb
Host smart-8b05e01f-13a5-4e30-97cc-ee424ccdd68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825
34920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3482534920
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2712361243
Short name T379
Test name
Test status
Simulation time 52040890 ps
CPU time 1.57 seconds
Started Mar 21 01:25:07 PM PDT 24
Finished Mar 21 01:25:09 PM PDT 24
Peak memory 203536 kb
Host smart-23ed32f6-d6e0-49d5-a524-d102c5070cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27123
61243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2712361243
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1685194456
Short name T158
Test name
Test status
Simulation time 8357723962 ps
CPU time 7.18 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:25:22 PM PDT 24
Peak memory 203324 kb
Host smart-c510d88f-5948-4770-b119-27d5a3344267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16851
94456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1685194456
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2607631181
Short name T605
Test name
Test status
Simulation time 8372456706 ps
CPU time 9.42 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:55 PM PDT 24
Peak memory 203272 kb
Host smart-b38f03a8-7994-40d6-ac8e-694b275c43c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
31181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2607631181
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1710947165
Short name T329
Test name
Test status
Simulation time 8411974350 ps
CPU time 7.43 seconds
Started Mar 21 01:25:07 PM PDT 24
Finished Mar 21 01:25:14 PM PDT 24
Peak memory 203532 kb
Host smart-dc1d11e4-922e-4769-9843-c9c489cf6139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17109
47165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1710947165
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3566872413
Short name T563
Test name
Test status
Simulation time 8369358765 ps
CPU time 7.02 seconds
Started Mar 21 01:25:11 PM PDT 24
Finished Mar 21 01:25:19 PM PDT 24
Peak memory 203308 kb
Host smart-00047ef4-a158-4792-932f-74c8042830d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35668
72413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3566872413
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1297181580
Short name T104
Test name
Test status
Simulation time 8438746425 ps
CPU time 9.44 seconds
Started Mar 21 01:24:55 PM PDT 24
Finished Mar 21 01:25:04 PM PDT 24
Peak memory 203380 kb
Host smart-be541373-8e25-46e2-88e6-a5ea5b86a4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
81580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1297181580
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.444013426
Short name T307
Test name
Test status
Simulation time 8405279171 ps
CPU time 7.71 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:16 PM PDT 24
Peak memory 203340 kb
Host smart-dbcd6f9c-35db-45bc-b66f-1011a5557471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44401
3426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.444013426
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2033949724
Short name T433
Test name
Test status
Simulation time 8399509822 ps
CPU time 7.39 seconds
Started Mar 21 01:24:38 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203252 kb
Host smart-7c510f9e-a652-4bac-9eb9-301d42d64b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20339
49724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2033949724
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.285810963
Short name T463
Test name
Test status
Simulation time 27791644 ps
CPU time 0.63 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 202964 kb
Host smart-d55e2fbc-63b9-4c54-aa4c-d97d02b86e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28581
0963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.285810963
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2273823326
Short name T599
Test name
Test status
Simulation time 8367018390 ps
CPU time 7.27 seconds
Started Mar 21 01:25:04 PM PDT 24
Finished Mar 21 01:25:12 PM PDT 24
Peak memory 203536 kb
Host smart-00fa3cca-47af-4493-8561-f5355491f9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22738
23326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2273823326
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1028818392
Short name T700
Test name
Test status
Simulation time 8445355922 ps
CPU time 7.84 seconds
Started Mar 21 01:25:06 PM PDT 24
Finished Mar 21 01:25:14 PM PDT 24
Peak memory 203248 kb
Host smart-5302e28e-9b36-4a0e-852c-d8c50b72f91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10288
18392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1028818392
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2071757307
Short name T611
Test name
Test status
Simulation time 8406810049 ps
CPU time 7.31 seconds
Started Mar 21 01:24:40 PM PDT 24
Finished Mar 21 01:24:47 PM PDT 24
Peak memory 203484 kb
Host smart-516aac43-9d65-4813-b62a-1bc4f8fa592b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20717
57307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2071757307
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1471268685
Short name T391
Test name
Test status
Simulation time 8358218590 ps
CPU time 9.64 seconds
Started Mar 21 01:24:36 PM PDT 24
Finished Mar 21 01:24:46 PM PDT 24
Peak memory 203428 kb
Host smart-5cd33baa-523e-440a-b4e3-ac4fc4981475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712
68685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1471268685
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2583488411
Short name T77
Test name
Test status
Simulation time 8476105824 ps
CPU time 10.19 seconds
Started Mar 21 01:24:47 PM PDT 24
Finished Mar 21 01:24:58 PM PDT 24
Peak memory 203488 kb
Host smart-cf51d3e4-3301-4d79-b8ed-877095211b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25834
88411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2583488411
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3105130288
Short name T730
Test name
Test status
Simulation time 8371319098 ps
CPU time 7.15 seconds
Started Mar 21 01:22:58 PM PDT 24
Finished Mar 21 01:23:06 PM PDT 24
Peak memory 203456 kb
Host smart-b793c8fa-ae42-47f7-b8f9-c1b59c35667d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31051
30288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3105130288
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.2171138280
Short name T31
Test name
Test status
Simulation time 8365014560 ps
CPU time 7.57 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:23:03 PM PDT 24
Peak memory 203616 kb
Host smart-5ab5b744-e0e0-4c0d-9a7a-5400b34b3784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21711
38280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2171138280
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3251293642
Short name T384
Test name
Test status
Simulation time 63971410 ps
CPU time 1.03 seconds
Started Mar 21 01:23:06 PM PDT 24
Finished Mar 21 01:23:07 PM PDT 24
Peak memory 203232 kb
Host smart-2c51167c-7405-4ab1-bfd4-967b72fa92ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32512
93642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3251293642
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.652615304
Short name T159
Test name
Test status
Simulation time 8359678487 ps
CPU time 7.21 seconds
Started Mar 21 01:23:07 PM PDT 24
Finished Mar 21 01:23:14 PM PDT 24
Peak memory 203140 kb
Host smart-f3bf185d-4673-4257-8276-f93913cb156c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65261
5304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.652615304
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1223014291
Short name T645
Test name
Test status
Simulation time 8380863988 ps
CPU time 7.46 seconds
Started Mar 21 01:23:01 PM PDT 24
Finished Mar 21 01:23:09 PM PDT 24
Peak memory 203448 kb
Host smart-14f4a9ae-82fb-4a1e-817d-67b4f1cf51ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12230
14291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1223014291
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2385568529
Short name T71
Test name
Test status
Simulation time 8409038598 ps
CPU time 8.69 seconds
Started Mar 21 01:22:58 PM PDT 24
Finished Mar 21 01:23:07 PM PDT 24
Peak memory 203564 kb
Host smart-aa5c4539-f253-482a-bbd4-dc456af9081c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23855
68529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2385568529
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1643202135
Short name T444
Test name
Test status
Simulation time 8361807620 ps
CPU time 9 seconds
Started Mar 21 01:22:56 PM PDT 24
Finished Mar 21 01:23:06 PM PDT 24
Peak memory 203180 kb
Host smart-526805a4-50d9-4405-837a-16af5c6ad98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16432
02135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1643202135
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.4037991694
Short name T636
Test name
Test status
Simulation time 8433641598 ps
CPU time 7.8 seconds
Started Mar 21 01:22:57 PM PDT 24
Finished Mar 21 01:23:05 PM PDT 24
Peak memory 203448 kb
Host smart-1fae5be2-44c4-469d-9ca2-886a46c13ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40379
91694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.4037991694
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1266887452
Short name T824
Test name
Test status
Simulation time 8377892804 ps
CPU time 7.69 seconds
Started Mar 21 01:23:04 PM PDT 24
Finished Mar 21 01:23:12 PM PDT 24
Peak memory 203280 kb
Host smart-ac9b3f04-dd89-4cd1-bfe1-d97e270b469a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12668
87452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1266887452
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3883349323
Short name T378
Test name
Test status
Simulation time 8368774948 ps
CPU time 7.21 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:23:03 PM PDT 24
Peak memory 203232 kb
Host smart-cdac8006-1290-4d2a-a281-96e68dc5521e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38833
49323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3883349323
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1708329404
Short name T70
Test name
Test status
Simulation time 27871832 ps
CPU time 0.65 seconds
Started Mar 21 01:23:08 PM PDT 24
Finished Mar 21 01:23:09 PM PDT 24
Peak memory 202904 kb
Host smart-c2fc3bba-3221-4468-8554-fb95336582ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17083
29404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1708329404
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3224120482
Short name T1
Test name
Test status
Simulation time 8398346477 ps
CPU time 7.75 seconds
Started Mar 21 01:22:55 PM PDT 24
Finished Mar 21 01:23:03 PM PDT 24
Peak memory 203544 kb
Host smart-2bba4fb4-fe1e-463a-ad8d-893d2b638106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32241
20482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3224120482
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1070290842
Short name T434
Test name
Test status
Simulation time 8401626100 ps
CPU time 8 seconds
Started Mar 21 01:23:01 PM PDT 24
Finished Mar 21 01:23:09 PM PDT 24
Peak memory 203484 kb
Host smart-1bd95351-abed-4091-86e0-dda3cbe83f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
90842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1070290842
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.3669266554
Short name T669
Test name
Test status
Simulation time 8404184803 ps
CPU time 9.18 seconds
Started Mar 21 01:23:18 PM PDT 24
Finished Mar 21 01:23:29 PM PDT 24
Peak memory 203552 kb
Host smart-f050870c-a9e0-489e-8368-0b80cf6bd30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36692
66554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.3669266554
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3910617574
Short name T65
Test name
Test status
Simulation time 77531917 ps
CPU time 0.89 seconds
Started Mar 21 01:23:24 PM PDT 24
Finished Mar 21 01:23:25 PM PDT 24
Peak memory 219208 kb
Host smart-6749bc60-c2fa-400d-95ed-cfc32a2237c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3910617574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3910617574
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2370341404
Short name T678
Test name
Test status
Simulation time 8363145320 ps
CPU time 8.38 seconds
Started Mar 21 01:23:16 PM PDT 24
Finished Mar 21 01:23:25 PM PDT 24
Peak memory 203452 kb
Host smart-5b9075a5-edb2-43e4-b3bc-b56ba411575b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23703
41404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2370341404
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2094337997
Short name T150
Test name
Test status
Simulation time 8479083529 ps
CPU time 7.53 seconds
Started Mar 21 01:23:00 PM PDT 24
Finished Mar 21 01:23:08 PM PDT 24
Peak memory 203500 kb
Host smart-da13fdff-1830-4924-b53a-547a87db6803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20943
37997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2094337997
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1107733449
Short name T505
Test name
Test status
Simulation time 8372838523 ps
CPU time 7.5 seconds
Started Mar 21 01:24:42 PM PDT 24
Finished Mar 21 01:24:50 PM PDT 24
Peak memory 203468 kb
Host smart-7062f8a3-1a94-45e5-a7e5-0fadde278507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11077
33449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1107733449
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.4028054688
Short name T518
Test name
Test status
Simulation time 8368168465 ps
CPU time 7.65 seconds
Started Mar 21 01:24:52 PM PDT 24
Finished Mar 21 01:25:01 PM PDT 24
Peak memory 203452 kb
Host smart-b27654df-ae06-41b2-bbd7-49176e489fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
54688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.4028054688
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2513126208
Short name T606
Test name
Test status
Simulation time 105291989 ps
CPU time 1.32 seconds
Started Mar 21 01:24:39 PM PDT 24
Finished Mar 21 01:24:41 PM PDT 24
Peak memory 203304 kb
Host smart-868d2978-c95f-464e-bed4-92f94f6fd010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25131
26208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2513126208
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2346998789
Short name T175
Test name
Test status
Simulation time 8363905766 ps
CPU time 7.49 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203296 kb
Host smart-f77ade46-5ece-4a29-9c37-3f24b2fb14ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23469
98789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2346998789
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.632967757
Short name T387
Test name
Test status
Simulation time 8419932536 ps
CPU time 7.26 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203396 kb
Host smart-0a5ddb39-334d-4588-bf38-92b28b9898a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63296
7757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.632967757
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2240666222
Short name T533
Test name
Test status
Simulation time 8405132062 ps
CPU time 7.07 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:48 PM PDT 24
Peak memory 203492 kb
Host smart-5f14cfc7-dc64-434a-aca4-0f14205a33df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22406
66222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2240666222
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2569290026
Short name T396
Test name
Test status
Simulation time 8362805597 ps
CPU time 9.17 seconds
Started Mar 21 01:24:44 PM PDT 24
Finished Mar 21 01:24:53 PM PDT 24
Peak memory 203456 kb
Host smart-00069566-3fdc-4bd8-a5b3-cbde7ca2dc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25692
90026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2569290026
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2902201480
Short name T579
Test name
Test status
Simulation time 8377966105 ps
CPU time 9.74 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203284 kb
Host smart-790add7a-e244-4fa2-9f12-ce57401a7784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29022
01480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2902201480
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.442517016
Short name T747
Test name
Test status
Simulation time 8383083253 ps
CPU time 6.93 seconds
Started Mar 21 01:24:42 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203488 kb
Host smart-ca7758d2-7ee1-4cbe-93c1-e8143ab5c812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44251
7016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.442517016
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.903686263
Short name T791
Test name
Test status
Simulation time 29150390 ps
CPU time 0.65 seconds
Started Mar 21 01:25:03 PM PDT 24
Finished Mar 21 01:25:04 PM PDT 24
Peak memory 202988 kb
Host smart-43b0ab23-ef1a-4ef9-87a3-ac0693ad864c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90368
6263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.903686263
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2368990805
Short name T742
Test name
Test status
Simulation time 8388139470 ps
CPU time 7.14 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:52 PM PDT 24
Peak memory 203548 kb
Host smart-d7ccae5e-a82e-4632-8fdb-0faeaddca339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23689
90805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2368990805
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1094872695
Short name T783
Test name
Test status
Simulation time 8414688236 ps
CPU time 7.4 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203540 kb
Host smart-2bd66774-d650-4fb3-9315-e20bd7a553bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10948
72695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1094872695
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1738351821
Short name T718
Test name
Test status
Simulation time 8388451684 ps
CPU time 8.67 seconds
Started Mar 21 01:24:44 PM PDT 24
Finished Mar 21 01:24:53 PM PDT 24
Peak memory 203436 kb
Host smart-11db9e38-23fd-4400-9ff3-85c66cd83c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17383
51821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1738351821
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.962909680
Short name T823
Test name
Test status
Simulation time 8357625174 ps
CPU time 7.49 seconds
Started Mar 21 01:24:46 PM PDT 24
Finished Mar 21 01:24:53 PM PDT 24
Peak memory 203292 kb
Host smart-ba827711-50bf-40b0-b3e6-c590247c85cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96290
9680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.962909680
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1252840531
Short name T14
Test name
Test status
Simulation time 8471502199 ps
CPU time 7.79 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203480 kb
Host smart-25491242-6682-47c8-9442-7c0027380d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12528
40531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1252840531
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.34341508
Short name T427
Test name
Test status
Simulation time 8372924667 ps
CPU time 7.43 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203492 kb
Host smart-bb954ec9-e37e-468d-b928-beae1f55e68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34341
508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.34341508
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.3444956772
Short name T616
Test name
Test status
Simulation time 8367209593 ps
CPU time 8.38 seconds
Started Mar 21 01:25:11 PM PDT 24
Finished Mar 21 01:25:19 PM PDT 24
Peak memory 203460 kb
Host smart-50cf78af-fd8c-4653-9f11-050d04500d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34449
56772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3444956772
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.626808954
Short name T528
Test name
Test status
Simulation time 250663671 ps
CPU time 2.01 seconds
Started Mar 21 01:24:51 PM PDT 24
Finished Mar 21 01:24:53 PM PDT 24
Peak memory 203444 kb
Host smart-e362933b-f159-492a-9a54-d9722fd9723a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62680
8954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.626808954
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.672047504
Short name T569
Test name
Test status
Simulation time 8356420063 ps
CPU time 7.8 seconds
Started Mar 21 01:25:00 PM PDT 24
Finished Mar 21 01:25:08 PM PDT 24
Peak memory 203336 kb
Host smart-dfefc2a1-d3dd-4077-ad37-1e3a1203052f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67204
7504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.672047504
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1795772947
Short name T769
Test name
Test status
Simulation time 8384879001 ps
CPU time 7.84 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203512 kb
Host smart-29c1aee1-4e18-410f-aad4-a7b991b3fd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17957
72947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1795772947
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2936438017
Short name T860
Test name
Test status
Simulation time 8406203002 ps
CPU time 7.19 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:53 PM PDT 24
Peak memory 203420 kb
Host smart-13ab8672-6a92-4190-8a6b-f5aa84bf45a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29364
38017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2936438017
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4166586191
Short name T787
Test name
Test status
Simulation time 8361936266 ps
CPU time 7.56 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203352 kb
Host smart-77e4211b-e40f-4910-bb74-1e5d904a1a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41665
86191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4166586191
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3896915429
Short name T513
Test name
Test status
Simulation time 8419504623 ps
CPU time 9.2 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:54 PM PDT 24
Peak memory 203440 kb
Host smart-59cc5347-9822-4cfa-ae8b-2cfc1b63e7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38969
15429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3896915429
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3032159454
Short name T494
Test name
Test status
Simulation time 8387225539 ps
CPU time 7.99 seconds
Started Mar 21 01:24:46 PM PDT 24
Finished Mar 21 01:24:55 PM PDT 24
Peak memory 203372 kb
Host smart-85ba7d3c-5928-44da-ac3a-602919e5b8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30321
59454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3032159454
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3452955335
Short name T390
Test name
Test status
Simulation time 8381263627 ps
CPU time 7.13 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:53 PM PDT 24
Peak memory 203316 kb
Host smart-2899d31b-a17e-4eac-bec9-87ca36d6002d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
55335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3452955335
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.1501392555
Short name T712
Test name
Test status
Simulation time 25663904 ps
CPU time 0.65 seconds
Started Mar 21 01:24:42 PM PDT 24
Finished Mar 21 01:24:43 PM PDT 24
Peak memory 203044 kb
Host smart-a1953109-c68e-4e76-9e41-e080a216fb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15013
92555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.1501392555
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1453299342
Short name T285
Test name
Test status
Simulation time 8398319033 ps
CPU time 7.56 seconds
Started Mar 21 01:24:53 PM PDT 24
Finished Mar 21 01:25:01 PM PDT 24
Peak memory 203536 kb
Host smart-b8ebcce0-30d1-476e-b2e1-19fa3b978122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14532
99342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1453299342
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.545902550
Short name T312
Test name
Test status
Simulation time 8379738328 ps
CPU time 7.51 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203452 kb
Host smart-b38541cf-2c7c-489f-8b8c-5119e661f675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54590
2550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.545902550
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1818804403
Short name T293
Test name
Test status
Simulation time 8365884241 ps
CPU time 8.67 seconds
Started Mar 21 01:25:04 PM PDT 24
Finished Mar 21 01:25:13 PM PDT 24
Peak memory 203504 kb
Host smart-d0e9e99b-2c35-4c5f-bf14-d9c07691e578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18188
04403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1818804403
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.4043900381
Short name T462
Test name
Test status
Simulation time 8359150654 ps
CPU time 7.06 seconds
Started Mar 21 01:24:50 PM PDT 24
Finished Mar 21 01:24:57 PM PDT 24
Peak memory 203420 kb
Host smart-9a5f46ca-dd86-4509-b10b-28ce6e006e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439
00381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.4043900381
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3053307751
Short name T146
Test name
Test status
Simulation time 8475364007 ps
CPU time 6.99 seconds
Started Mar 21 01:24:42 PM PDT 24
Finished Mar 21 01:24:49 PM PDT 24
Peak memory 203488 kb
Host smart-b0ee6ecc-43db-49fe-86fb-b6665ac48d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30533
07751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3053307751
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2615340509
Short name T288
Test name
Test status
Simulation time 8372441771 ps
CPU time 7.25 seconds
Started Mar 21 01:24:56 PM PDT 24
Finished Mar 21 01:25:03 PM PDT 24
Peak memory 203508 kb
Host smart-120cb616-17e8-4cd8-af71-1b122d6ba23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26153
40509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2615340509
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.314934870
Short name T631
Test name
Test status
Simulation time 8368878002 ps
CPU time 7.72 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:16 PM PDT 24
Peak memory 203492 kb
Host smart-59960af1-7a6b-4ffd-9bd9-aa7f425d1d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31493
4870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.314934870
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2045574173
Short name T443
Test name
Test status
Simulation time 60084805 ps
CPU time 1.61 seconds
Started Mar 21 01:25:20 PM PDT 24
Finished Mar 21 01:25:22 PM PDT 24
Peak memory 203448 kb
Host smart-11dd3f6a-cbd5-4a32-8b38-989ec193a405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20455
74173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2045574173
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.515238484
Short name T173
Test name
Test status
Simulation time 8357905469 ps
CPU time 7.06 seconds
Started Mar 21 01:24:44 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203300 kb
Host smart-3f05cb43-4ac1-4637-8fbd-3105ccc369d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51523
8484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.515238484
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1093431552
Short name T830
Test name
Test status
Simulation time 8452377249 ps
CPU time 7.7 seconds
Started Mar 21 01:24:42 PM PDT 24
Finished Mar 21 01:24:50 PM PDT 24
Peak memory 203380 kb
Host smart-465f8f79-dd99-43ef-a9d9-58cdcdb342fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10934
31552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1093431552
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1824564115
Short name T670
Test name
Test status
Simulation time 8416475001 ps
CPU time 8.1 seconds
Started Mar 21 01:25:02 PM PDT 24
Finished Mar 21 01:25:10 PM PDT 24
Peak memory 203452 kb
Host smart-aad1ad40-4b54-4dc0-a991-4d9dd140f081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18245
64115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1824564115
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1412153631
Short name T325
Test name
Test status
Simulation time 8367897695 ps
CPU time 7.06 seconds
Started Mar 21 01:25:09 PM PDT 24
Finished Mar 21 01:25:16 PM PDT 24
Peak memory 203360 kb
Host smart-2f4efb33-6213-44cd-9da7-aff64d70fca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14121
53631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1412153631
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3223815878
Short name T690
Test name
Test status
Simulation time 8389637416 ps
CPU time 9.66 seconds
Started Mar 21 01:24:52 PM PDT 24
Finished Mar 21 01:25:03 PM PDT 24
Peak memory 203516 kb
Host smart-e73ab65a-0a39-4357-9e9e-0ecfddcf211d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238
15878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3223815878
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.4218203276
Short name T542
Test name
Test status
Simulation time 8373272826 ps
CPU time 7.97 seconds
Started Mar 21 01:25:09 PM PDT 24
Finished Mar 21 01:25:18 PM PDT 24
Peak memory 203320 kb
Host smart-9004f9ec-7361-4ff3-8d60-f203c21b9294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42182
03276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.4218203276
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2033271274
Short name T283
Test name
Test status
Simulation time 8374235705 ps
CPU time 8.33 seconds
Started Mar 21 01:25:13 PM PDT 24
Finished Mar 21 01:25:21 PM PDT 24
Peak memory 203472 kb
Host smart-d57aa899-259d-472c-b4d4-dc97295be712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20332
71274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2033271274
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1535822756
Short name T765
Test name
Test status
Simulation time 29184368 ps
CPU time 0.61 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:44 PM PDT 24
Peak memory 202932 kb
Host smart-1a263c55-3d63-45e5-a228-d94cc3441b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15358
22756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1535822756
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1773933564
Short name T274
Test name
Test status
Simulation time 8367733174 ps
CPU time 7.8 seconds
Started Mar 21 01:24:50 PM PDT 24
Finished Mar 21 01:24:58 PM PDT 24
Peak memory 203492 kb
Host smart-55a1e5d8-3f88-4987-a690-b34905ea779a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
33564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1773933564
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1691477117
Short name T756
Test name
Test status
Simulation time 8373560298 ps
CPU time 7.31 seconds
Started Mar 21 01:25:03 PM PDT 24
Finished Mar 21 01:25:10 PM PDT 24
Peak memory 203436 kb
Host smart-cd8451c1-f4c7-4925-b560-769a490ee7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16914
77117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1691477117
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.561903996
Short name T4
Test name
Test status
Simulation time 8369109761 ps
CPU time 7.55 seconds
Started Mar 21 01:25:04 PM PDT 24
Finished Mar 21 01:25:11 PM PDT 24
Peak memory 203224 kb
Host smart-fb1fa334-72e8-4285-933d-1b1bbf49a324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56190
3996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.561903996
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3173708122
Short name T350
Test name
Test status
Simulation time 8359106431 ps
CPU time 9.51 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:25:25 PM PDT 24
Peak memory 203468 kb
Host smart-50a6d53a-28ec-4c82-88bf-f3c8293218e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31737
08122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3173708122
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.634685278
Short name T125
Test name
Test status
Simulation time 8478397488 ps
CPU time 7.97 seconds
Started Mar 21 01:25:05 PM PDT 24
Finished Mar 21 01:25:13 PM PDT 24
Peak memory 203592 kb
Host smart-182913a8-4af8-4846-b13a-459d5ea8b5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63468
5278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.634685278
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3097228128
Short name T439
Test name
Test status
Simulation time 8373084781 ps
CPU time 7.68 seconds
Started Mar 21 01:24:41 PM PDT 24
Finished Mar 21 01:24:48 PM PDT 24
Peak memory 203492 kb
Host smart-31143611-9848-47bf-8dc1-499fa0ae1730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30972
28128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3097228128
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.1701967934
Short name T458
Test name
Test status
Simulation time 8368710028 ps
CPU time 9.56 seconds
Started Mar 21 01:25:04 PM PDT 24
Finished Mar 21 01:25:14 PM PDT 24
Peak memory 203528 kb
Host smart-473a23d5-24b1-4fc8-9541-87cf89498610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019
67934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1701967934
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1441241051
Short name T852
Test name
Test status
Simulation time 81959905 ps
CPU time 1.07 seconds
Started Mar 21 01:25:00 PM PDT 24
Finished Mar 21 01:25:01 PM PDT 24
Peak memory 203512 kb
Host smart-17aee9d6-43e3-4539-969e-0dd2b41fe75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14412
41051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1441241051
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3508619782
Short name T705
Test name
Test status
Simulation time 8360347845 ps
CPU time 7.16 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:16 PM PDT 24
Peak memory 203380 kb
Host smart-61cf2b0c-38bc-46fd-9134-072c11b215f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35086
19782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3508619782
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3222800161
Short name T697
Test name
Test status
Simulation time 8438670229 ps
CPU time 7.25 seconds
Started Mar 21 01:25:09 PM PDT 24
Finished Mar 21 01:25:16 PM PDT 24
Peak memory 203348 kb
Host smart-06e87147-bae3-4dc3-bdc9-97d3c3894618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32228
00161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3222800161
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1824867600
Short name T854
Test name
Test status
Simulation time 8412894079 ps
CPU time 7.27 seconds
Started Mar 21 01:24:57 PM PDT 24
Finished Mar 21 01:25:04 PM PDT 24
Peak memory 203508 kb
Host smart-3c24796a-c258-4dc2-82d1-381edaee1000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18248
67600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1824867600
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2421070152
Short name T407
Test name
Test status
Simulation time 8363392548 ps
CPU time 7.82 seconds
Started Mar 21 01:25:03 PM PDT 24
Finished Mar 21 01:25:11 PM PDT 24
Peak memory 203392 kb
Host smart-11051212-4a77-4975-b8d2-90f1c050143d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24210
70152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2421070152
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2892577740
Short name T18
Test name
Test status
Simulation time 8418284339 ps
CPU time 7.37 seconds
Started Mar 21 01:24:53 PM PDT 24
Finished Mar 21 01:25:00 PM PDT 24
Peak memory 203384 kb
Host smart-0ed34fe3-1940-4204-bf23-b3f801175828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28925
77740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2892577740
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1051678668
Short name T507
Test name
Test status
Simulation time 8370838804 ps
CPU time 8.64 seconds
Started Mar 21 01:25:04 PM PDT 24
Finished Mar 21 01:25:12 PM PDT 24
Peak memory 203284 kb
Host smart-c3c6fb07-d6b5-42ae-a0ce-c774683e38b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10516
78668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1051678668
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.71767668
Short name T420
Test name
Test status
Simulation time 8400380350 ps
CPU time 7.44 seconds
Started Mar 21 01:24:52 PM PDT 24
Finished Mar 21 01:25:00 PM PDT 24
Peak memory 203264 kb
Host smart-42924c2a-5710-4224-81bd-27e10f8de5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71767
668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.71767668
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.33706159
Short name T608
Test name
Test status
Simulation time 29573408 ps
CPU time 0.65 seconds
Started Mar 21 01:25:02 PM PDT 24
Finished Mar 21 01:25:03 PM PDT 24
Peak memory 202968 kb
Host smart-6c3bca95-b79b-4580-8cdf-2de2246cea6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33706
159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.33706159
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2500391640
Short name T321
Test name
Test status
Simulation time 8380393350 ps
CPU time 8 seconds
Started Mar 21 01:24:57 PM PDT 24
Finished Mar 21 01:25:05 PM PDT 24
Peak memory 203448 kb
Host smart-cdb10687-cb35-4570-9409-dcc6317307ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003
91640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2500391640
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3250913205
Short name T619
Test name
Test status
Simulation time 8405358040 ps
CPU time 7.01 seconds
Started Mar 21 01:25:03 PM PDT 24
Finished Mar 21 01:25:10 PM PDT 24
Peak memory 203452 kb
Host smart-a1aedd9c-3832-4238-b262-9c515709414c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32509
13205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3250913205
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3124428147
Short name T367
Test name
Test status
Simulation time 8362917232 ps
CPU time 10.16 seconds
Started Mar 21 01:24:59 PM PDT 24
Finished Mar 21 01:25:15 PM PDT 24
Peak memory 203412 kb
Host smart-28fa2557-0ca8-4213-91f8-e617e4bc152a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31244
28147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3124428147
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3142503141
Short name T392
Test name
Test status
Simulation time 8473406049 ps
CPU time 9.35 seconds
Started Mar 21 01:24:47 PM PDT 24
Finished Mar 21 01:24:57 PM PDT 24
Peak memory 203512 kb
Host smart-b3048dad-a711-489e-a7bc-0167b42e56a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31425
03141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3142503141
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3275036219
Short name T457
Test name
Test status
Simulation time 8369424741 ps
CPU time 9.01 seconds
Started Mar 21 01:25:02 PM PDT 24
Finished Mar 21 01:25:11 PM PDT 24
Peak memory 203496 kb
Host smart-c8a36528-fe42-4a3e-8cf6-16cff6afe72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32750
36219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3275036219
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.683397611
Short name T553
Test name
Test status
Simulation time 8365537670 ps
CPU time 9.44 seconds
Started Mar 21 01:25:10 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203492 kb
Host smart-7130b066-d119-48ba-b53f-49beb6f5f30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68339
7611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.683397611
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.70406307
Short name T227
Test name
Test status
Simulation time 156905161 ps
CPU time 1.45 seconds
Started Mar 21 01:24:52 PM PDT 24
Finished Mar 21 01:24:54 PM PDT 24
Peak memory 203440 kb
Host smart-dad4731e-36bf-4c79-a697-d5defd37a56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70406
307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.70406307
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.256101085
Short name T838
Test name
Test status
Simulation time 8359329807 ps
CPU time 7.22 seconds
Started Mar 21 01:24:44 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203328 kb
Host smart-2bf2544d-88e6-4a02-86af-653030715f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25610
1085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.256101085
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1606637211
Short name T117
Test name
Test status
Simulation time 8419067250 ps
CPU time 7.89 seconds
Started Mar 21 01:24:49 PM PDT 24
Finished Mar 21 01:24:57 PM PDT 24
Peak memory 203492 kb
Host smart-1289877a-9584-4803-9c1c-abb5ef3b7ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16066
37211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1606637211
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.152768893
Short name T271
Test name
Test status
Simulation time 8405172898 ps
CPU time 7.86 seconds
Started Mar 21 01:25:01 PM PDT 24
Finished Mar 21 01:25:09 PM PDT 24
Peak memory 203548 kb
Host smart-17a7f662-9464-42b4-9fae-31b6a30850dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
8893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.152768893
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2014766587
Short name T566
Test name
Test status
Simulation time 8366526940 ps
CPU time 8.39 seconds
Started Mar 21 01:24:46 PM PDT 24
Finished Mar 21 01:24:56 PM PDT 24
Peak memory 203468 kb
Host smart-df726b15-a851-44dd-9086-8cbd5f2bda82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20147
66587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2014766587
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1046209397
Short name T839
Test name
Test status
Simulation time 8405263665 ps
CPU time 7.7 seconds
Started Mar 21 01:24:58 PM PDT 24
Finished Mar 21 01:25:06 PM PDT 24
Peak memory 203480 kb
Host smart-27d9431d-4df0-4faf-af0b-b30adccde198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10462
09397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1046209397
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3774431758
Short name T415
Test name
Test status
Simulation time 8405869356 ps
CPU time 7.91 seconds
Started Mar 21 01:25:02 PM PDT 24
Finished Mar 21 01:25:10 PM PDT 24
Peak memory 203336 kb
Host smart-4fa31379-078f-4053-b16d-09edd8879a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37744
31758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3774431758
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3638034948
Short name T515
Test name
Test status
Simulation time 8389331189 ps
CPU time 8.44 seconds
Started Mar 21 01:24:47 PM PDT 24
Finished Mar 21 01:24:56 PM PDT 24
Peak memory 203472 kb
Host smart-f728acc3-bed9-44d6-a7d8-2c4da154a3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36380
34948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3638034948
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1051344520
Short name T33
Test name
Test status
Simulation time 29421268 ps
CPU time 0.64 seconds
Started Mar 21 01:25:07 PM PDT 24
Finished Mar 21 01:25:08 PM PDT 24
Peak memory 202956 kb
Host smart-4566674f-d22c-480d-960b-1a7526e18f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10513
44520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1051344520
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.7063093
Short name T265
Test name
Test status
Simulation time 8407742689 ps
CPU time 7.22 seconds
Started Mar 21 01:24:43 PM PDT 24
Finished Mar 21 01:24:51 PM PDT 24
Peak memory 203544 kb
Host smart-550c3115-5af6-4156-90e1-edc8cc90f585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70630
93 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.7063093
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2629273243
Short name T449
Test name
Test status
Simulation time 8380165133 ps
CPU time 7.89 seconds
Started Mar 21 01:24:55 PM PDT 24
Finished Mar 21 01:25:03 PM PDT 24
Peak memory 203456 kb
Host smart-152081e7-7466-4686-ad28-48e795b133fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26292
73243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2629273243
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2635320584
Short name T207
Test name
Test status
Simulation time 8387651620 ps
CPU time 7.56 seconds
Started Mar 21 01:25:06 PM PDT 24
Finished Mar 21 01:25:14 PM PDT 24
Peak memory 203208 kb
Host smart-2e92ffba-f2fb-49c4-864f-b49e12bb29b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26353
20584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2635320584
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3345272355
Short name T324
Test name
Test status
Simulation time 8363924258 ps
CPU time 7.39 seconds
Started Mar 21 01:25:03 PM PDT 24
Finished Mar 21 01:25:11 PM PDT 24
Peak memory 203444 kb
Host smart-dc9c22e7-7e34-44e8-aa96-3426d31dca66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33452
72355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3345272355
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.4101683510
Short name T139
Test name
Test status
Simulation time 8472663462 ps
CPU time 8.91 seconds
Started Mar 21 01:24:57 PM PDT 24
Finished Mar 21 01:25:06 PM PDT 24
Peak memory 203500 kb
Host smart-d90eb7c0-8fd7-4a1c-a240-b28446f77d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41016
83510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4101683510
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.670332876
Short name T39
Test name
Test status
Simulation time 8366515057 ps
CPU time 7.74 seconds
Started Mar 21 01:25:12 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203512 kb
Host smart-8572ccfb-33de-4529-88fe-dc15e865d701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67033
2876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.670332876
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.1017286066
Short name T417
Test name
Test status
Simulation time 8369059505 ps
CPU time 8.9 seconds
Started Mar 21 01:25:09 PM PDT 24
Finished Mar 21 01:25:19 PM PDT 24
Peak memory 203572 kb
Host smart-e9331d8b-0bcf-4a02-861f-3340e9c6803f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10172
86066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1017286066
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2856565840
Short name T395
Test name
Test status
Simulation time 184090380 ps
CPU time 2.07 seconds
Started Mar 21 01:25:09 PM PDT 24
Finished Mar 21 01:25:11 PM PDT 24
Peak memory 203420 kb
Host smart-e936e9d5-285e-4dd1-ba27-63df40ee8723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28565
65840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2856565840
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1958769978
Short name T837
Test name
Test status
Simulation time 8362302839 ps
CPU time 8.26 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:17 PM PDT 24
Peak memory 203328 kb
Host smart-68feeb36-d3e0-4c93-831c-fde81aea190e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19587
69978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1958769978
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2309947353
Short name T548
Test name
Test status
Simulation time 8375905679 ps
CPU time 7.4 seconds
Started Mar 21 01:25:06 PM PDT 24
Finished Mar 21 01:25:13 PM PDT 24
Peak memory 203396 kb
Host smart-9a7da42c-2236-4360-a18e-54c8ae9f679a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099
47353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2309947353
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.223811822
Short name T773
Test name
Test status
Simulation time 8416501287 ps
CPU time 7.87 seconds
Started Mar 21 01:25:04 PM PDT 24
Finished Mar 21 01:25:12 PM PDT 24
Peak memory 203448 kb
Host smart-6a965b45-0906-4f5d-9448-2d2baf834ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22381
1822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.223811822
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3823909732
Short name T219
Test name
Test status
Simulation time 8364524524 ps
CPU time 9.62 seconds
Started Mar 21 01:25:09 PM PDT 24
Finished Mar 21 01:25:19 PM PDT 24
Peak memory 203444 kb
Host smart-dfa32fdf-e448-4b72-b2a2-94397b155e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38239
09732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3823909732
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.272640737
Short name T101
Test name
Test status
Simulation time 8428431871 ps
CPU time 7.47 seconds
Started Mar 21 01:25:09 PM PDT 24
Finished Mar 21 01:25:17 PM PDT 24
Peak memory 203380 kb
Host smart-90e1639a-078c-4807-bc5f-9f7c6fe1c41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27264
0737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.272640737
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1693090667
Short name T759
Test name
Test status
Simulation time 8363847637 ps
CPU time 6.86 seconds
Started Mar 21 01:25:10 PM PDT 24
Finished Mar 21 01:25:17 PM PDT 24
Peak memory 203572 kb
Host smart-110c5073-91de-44b5-95a5-da0217b9cea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16930
90667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1693090667
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.523335156
Short name T298
Test name
Test status
Simulation time 8402214777 ps
CPU time 7.95 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:25:32 PM PDT 24
Peak memory 203296 kb
Host smart-9977d522-40d1-4a9a-bc36-2b5270dd9a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52333
5156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.523335156
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.468830909
Short name T217
Test name
Test status
Simulation time 28283556 ps
CPU time 0.62 seconds
Started Mar 21 01:25:11 PM PDT 24
Finished Mar 21 01:25:12 PM PDT 24
Peak memory 202928 kb
Host smart-8be51c5c-a285-46e3-bce5-86bffdf57479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46883
0909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.468830909
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.617129900
Short name T726
Test name
Test status
Simulation time 8363972314 ps
CPU time 7.17 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:25:21 PM PDT 24
Peak memory 203428 kb
Host smart-063fd1e8-bcca-459d-aa78-d7ad7a6227d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61712
9900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.617129900
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2060972003
Short name T485
Test name
Test status
Simulation time 8408029211 ps
CPU time 7.97 seconds
Started Mar 21 01:25:12 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203380 kb
Host smart-dec0f169-7980-46ca-ac02-4a89f19881b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20609
72003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2060972003
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1593360463
Short name T809
Test name
Test status
Simulation time 8387597260 ps
CPU time 8.06 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:25:23 PM PDT 24
Peak memory 203488 kb
Host smart-0589007d-6880-4eea-b6b9-93303231f16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15933
60463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1593360463
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3743604019
Short name T394
Test name
Test status
Simulation time 8360085666 ps
CPU time 9.37 seconds
Started Mar 21 01:25:12 PM PDT 24
Finished Mar 21 01:25:22 PM PDT 24
Peak memory 203284 kb
Host smart-fe027add-1591-49e5-8105-e928c2557313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37436
04019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3743604019
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3206496887
Short name T144
Test name
Test status
Simulation time 8473520064 ps
CPU time 7.89 seconds
Started Mar 21 01:24:45 PM PDT 24
Finished Mar 21 01:24:54 PM PDT 24
Peak memory 203304 kb
Host smart-ec2cf783-ea54-4270-9d7c-0aca56089d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064
96887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3206496887
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.770486546
Short name T43
Test name
Test status
Simulation time 8367886434 ps
CPU time 9.39 seconds
Started Mar 21 01:25:10 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203548 kb
Host smart-908964f5-3fbb-4708-91b6-02f3fbd3491d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77048
6546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.770486546
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.3377233392
Short name T456
Test name
Test status
Simulation time 8365719604 ps
CPU time 8.35 seconds
Started Mar 21 01:25:12 PM PDT 24
Finished Mar 21 01:25:21 PM PDT 24
Peak memory 203508 kb
Host smart-026916bf-1094-4c8d-96b4-929ab90a4adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33772
33392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3377233392
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3296305518
Short name T156
Test name
Test status
Simulation time 8356928976 ps
CPU time 7.42 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:25:30 PM PDT 24
Peak memory 203336 kb
Host smart-bbc88ecb-5f1f-439b-97a9-7c33484d66c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32963
05518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3296305518
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1926554393
Short name T637
Test name
Test status
Simulation time 8432096465 ps
CPU time 7.36 seconds
Started Mar 21 01:25:16 PM PDT 24
Finished Mar 21 01:25:24 PM PDT 24
Peak memory 203544 kb
Host smart-990dd4bb-de03-41a5-be9e-bc96a2c1c584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19265
54393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1926554393
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3390625474
Short name T752
Test name
Test status
Simulation time 8409286025 ps
CPU time 7.82 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 203568 kb
Host smart-4ae5566c-62d3-4acd-8ec9-07aeb9e560d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33906
25474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3390625474
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3314559764
Short name T634
Test name
Test status
Simulation time 8367275890 ps
CPU time 7.9 seconds
Started Mar 21 01:25:16 PM PDT 24
Finished Mar 21 01:25:24 PM PDT 24
Peak memory 203372 kb
Host smart-7c10c896-52c1-46a1-b1da-0a81c0c8262b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145
59764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3314559764
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1043627547
Short name T98
Test name
Test status
Simulation time 8438468282 ps
CPU time 7.64 seconds
Started Mar 21 01:25:12 PM PDT 24
Finished Mar 21 01:25:19 PM PDT 24
Peak memory 203404 kb
Host smart-2660b0d5-1980-4b22-9cfe-f5cc727740e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10436
27547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1043627547
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2797457195
Short name T740
Test name
Test status
Simulation time 8372903655 ps
CPU time 7.72 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:16 PM PDT 24
Peak memory 203228 kb
Host smart-816c8d93-9682-407d-be98-b1c8e70f4bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974
57195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2797457195
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.155095094
Short name T393
Test name
Test status
Simulation time 8379285076 ps
CPU time 7.19 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:25:31 PM PDT 24
Peak memory 203380 kb
Host smart-14129602-9193-482b-aef1-78cb1bdfdf3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15509
5094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.155095094
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.364460145
Short name T435
Test name
Test status
Simulation time 28797451 ps
CPU time 0.65 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:09 PM PDT 24
Peak memory 202904 kb
Host smart-cdee49d5-bf9f-47a5-88a7-4f3ef350b6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36446
0145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.364460145
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3956524674
Short name T829
Test name
Test status
Simulation time 8409159252 ps
CPU time 8.87 seconds
Started Mar 21 01:25:11 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203548 kb
Host smart-48caaaee-b449-4363-b758-b0dfd981f0c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39565
24674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3956524674
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4120144558
Short name T12
Test name
Test status
Simulation time 8428314685 ps
CPU time 8.83 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:17 PM PDT 24
Peak memory 203512 kb
Host smart-3efd1cfd-77ba-44df-b77e-51295fcc4c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41201
44558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4120144558
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3840580058
Short name T343
Test name
Test status
Simulation time 8403052788 ps
CPU time 9.15 seconds
Started Mar 21 01:25:11 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203548 kb
Host smart-1163bf6e-40d9-407f-9e6c-26d4b1d18190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38405
80058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3840580058
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3910198370
Short name T385
Test name
Test status
Simulation time 8356837654 ps
CPU time 7.49 seconds
Started Mar 21 01:24:54 PM PDT 24
Finished Mar 21 01:25:02 PM PDT 24
Peak memory 203504 kb
Host smart-e0b4dbb0-a658-42cc-84c7-0081ea6cce9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39101
98370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3910198370
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1279753669
Short name T382
Test name
Test status
Simulation time 8470469508 ps
CPU time 7.11 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:25:21 PM PDT 24
Peak memory 203516 kb
Host smart-c5e5f204-6262-49eb-85c8-18cda830d78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12797
53669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1279753669
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3585482964
Short name T296
Test name
Test status
Simulation time 8371256264 ps
CPU time 7.86 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 203444 kb
Host smart-2f9b32a4-7045-47e1-bff9-3f3b64c05290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35854
82964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3585482964
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.196910711
Short name T486
Test name
Test status
Simulation time 8372481551 ps
CPU time 9.48 seconds
Started Mar 21 01:25:24 PM PDT 24
Finished Mar 21 01:25:34 PM PDT 24
Peak memory 203540 kb
Host smart-51992af5-2466-4fad-afe7-59dee45de54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19691
0711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.196910711
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.4074839430
Short name T748
Test name
Test status
Simulation time 197218231 ps
CPU time 1.75 seconds
Started Mar 21 01:25:02 PM PDT 24
Finished Mar 21 01:25:04 PM PDT 24
Peak memory 203548 kb
Host smart-71a492cf-3981-4773-b0ea-021d8b8aaa88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40748
39430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.4074839430
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3581181055
Short name T537
Test name
Test status
Simulation time 8360632766 ps
CPU time 8.89 seconds
Started Mar 21 01:25:12 PM PDT 24
Finished Mar 21 01:25:21 PM PDT 24
Peak memory 203168 kb
Host smart-35ed3a35-8526-4df4-b1cd-1cd2038d29ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35811
81055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3581181055
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3445252351
Short name T127
Test name
Test status
Simulation time 8434604962 ps
CPU time 8.7 seconds
Started Mar 21 01:25:07 PM PDT 24
Finished Mar 21 01:25:17 PM PDT 24
Peak memory 203512 kb
Host smart-15ee6269-c7fe-4e20-a7c0-2a489511818e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34452
52351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3445252351
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.4054278827
Short name T630
Test name
Test status
Simulation time 8406155155 ps
CPU time 7.65 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:25:23 PM PDT 24
Peak memory 203568 kb
Host smart-f00aaa6d-4865-48b4-9a22-2562d6a4716c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40542
78827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.4054278827
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.306847266
Short name T355
Test name
Test status
Simulation time 8360173837 ps
CPU time 7.75 seconds
Started Mar 21 01:25:19 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 203440 kb
Host smart-72e18597-b98f-49a8-9f7a-fdae89769cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30684
7266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.306847266
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.324446869
Short name T94
Test name
Test status
Simulation time 8435779117 ps
CPU time 7.1 seconds
Started Mar 21 01:25:20 PM PDT 24
Finished Mar 21 01:25:27 PM PDT 24
Peak memory 203436 kb
Host smart-1a7ed69d-27bc-43bd-b6ad-3c9f5b9cbf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32444
6869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.324446869
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.119954170
Short name T429
Test name
Test status
Simulation time 8375132907 ps
CPU time 7.33 seconds
Started Mar 21 01:25:20 PM PDT 24
Finished Mar 21 01:25:28 PM PDT 24
Peak memory 203424 kb
Host smart-4df236dc-806f-4db5-962f-39b94766b2a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11995
4170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.119954170
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1113191447
Short name T364
Test name
Test status
Simulation time 8378685614 ps
CPU time 7.31 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:25:21 PM PDT 24
Peak memory 203316 kb
Host smart-c0aacd47-7257-40cf-823a-dfec002f20ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11131
91447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1113191447
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1231544193
Short name T351
Test name
Test status
Simulation time 23243663 ps
CPU time 0.63 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:25:22 PM PDT 24
Peak memory 202964 kb
Host smart-c9ad83d0-7f83-4ca4-ab73-98bef15bf599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
44193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1231544193
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3920800523
Short name T483
Test name
Test status
Simulation time 8397533871 ps
CPU time 6.95 seconds
Started Mar 21 01:25:13 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203448 kb
Host smart-1f27dc3f-65b7-4785-b68d-6eb52f501a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39208
00523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3920800523
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2451424461
Short name T335
Test name
Test status
Simulation time 8433160797 ps
CPU time 7.17 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:25:31 PM PDT 24
Peak memory 203380 kb
Host smart-1b01bd02-6fde-4c38-a724-22cc07c205a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24514
24461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2451424461
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.2655577731
Short name T331
Test name
Test status
Simulation time 8406337438 ps
CPU time 7.46 seconds
Started Mar 21 01:25:08 PM PDT 24
Finished Mar 21 01:25:15 PM PDT 24
Peak memory 203464 kb
Host smart-88aac3c3-f129-4a78-892d-d6dc517798da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26555
77731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.2655577731
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.711555992
Short name T306
Test name
Test status
Simulation time 8361361117 ps
CPU time 7.46 seconds
Started Mar 21 01:25:16 PM PDT 24
Finished Mar 21 01:25:23 PM PDT 24
Peak memory 203232 kb
Host smart-68546f75-50fb-4972-a10a-8df320c62fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71155
5992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.711555992
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.213049430
Short name T609
Test name
Test status
Simulation time 8478416576 ps
CPU time 8.48 seconds
Started Mar 21 01:25:02 PM PDT 24
Finished Mar 21 01:25:10 PM PDT 24
Peak memory 203484 kb
Host smart-df681b65-dd7a-419f-b7c2-cf0e423c4f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304
9430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.213049430
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.799680588
Short name T607
Test name
Test status
Simulation time 8374087992 ps
CPU time 7.34 seconds
Started Mar 21 01:25:17 PM PDT 24
Finished Mar 21 01:25:25 PM PDT 24
Peak memory 203576 kb
Host smart-50a9e62d-6398-49a9-b3de-0bab68cb5d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79968
0588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.799680588
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.1895847276
Short name T269
Test name
Test status
Simulation time 8368573095 ps
CPU time 7.08 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 203544 kb
Host smart-fe30fb62-aca2-46a0-9b4b-2c764728cfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18958
47276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1895847276
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3704497522
Short name T525
Test name
Test status
Simulation time 109460953 ps
CPU time 1.36 seconds
Started Mar 21 01:25:17 PM PDT 24
Finished Mar 21 01:25:19 PM PDT 24
Peak memory 203596 kb
Host smart-02d473d1-ee14-4dc7-94a6-0f0aadc269a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37044
97522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3704497522
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1909963230
Short name T170
Test name
Test status
Simulation time 8361926512 ps
CPU time 7.29 seconds
Started Mar 21 01:25:10 PM PDT 24
Finished Mar 21 01:25:18 PM PDT 24
Peak memory 203364 kb
Host smart-88e81214-1905-45f9-a29c-20a65be6fbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099
63230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1909963230
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3571786675
Short name T708
Test name
Test status
Simulation time 8435708915 ps
CPU time 9.2 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:25:24 PM PDT 24
Peak memory 203440 kb
Host smart-42cc4693-9de3-40ce-9026-5b976b11e3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35717
86675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3571786675
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2931925316
Short name T762
Test name
Test status
Simulation time 8407373567 ps
CPU time 9.43 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:25:25 PM PDT 24
Peak memory 203548 kb
Host smart-6a1ddfb9-a595-4616-bd3e-2f5f6d1500fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29319
25316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2931925316
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3612601752
Short name T543
Test name
Test status
Simulation time 8363410410 ps
CPU time 8.75 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:25:22 PM PDT 24
Peak memory 203248 kb
Host smart-75b88c5d-ab86-4e8b-824d-60b6964af848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36126
01752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3612601752
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2598386596
Short name T627
Test name
Test status
Simulation time 8386060197 ps
CPU time 8.41 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:25:23 PM PDT 24
Peak memory 203292 kb
Host smart-c457cc84-44e1-4129-9ac7-d305694d0b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
86596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2598386596
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.632827267
Short name T315
Test name
Test status
Simulation time 8389094772 ps
CPU time 7.56 seconds
Started Mar 21 01:25:13 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203256 kb
Host smart-ebf234f2-6482-45b3-8983-b3a85d9406db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63282
7267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.632827267
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.391460239
Short name T786
Test name
Test status
Simulation time 30431508 ps
CPU time 0.65 seconds
Started Mar 21 01:25:17 PM PDT 24
Finished Mar 21 01:25:18 PM PDT 24
Peak memory 202928 kb
Host smart-ad9e8bf8-f579-473d-91fb-0e3de5fbdad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39146
0239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.391460239
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1661592253
Short name T368
Test name
Test status
Simulation time 8396470211 ps
CPU time 7.62 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 203508 kb
Host smart-6fe2d65c-91f8-44b1-8d3d-15ec0282dd2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16615
92253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1661592253
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3661471570
Short name T659
Test name
Test status
Simulation time 8403739956 ps
CPU time 7.43 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:25:23 PM PDT 24
Peak memory 203436 kb
Host smart-e2360eda-f3c9-4021-8ea8-5e0cb69688b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36614
71570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3661471570
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.4197018206
Short name T851
Test name
Test status
Simulation time 8408707095 ps
CPU time 8.39 seconds
Started Mar 21 01:25:19 PM PDT 24
Finished Mar 21 01:25:27 PM PDT 24
Peak memory 203552 kb
Host smart-239a7daa-f489-4c0a-b8b7-bba892662fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41970
18206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.4197018206
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.4253504241
Short name T348
Test name
Test status
Simulation time 8362094062 ps
CPU time 7.4 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:25:29 PM PDT 24
Peak memory 203304 kb
Host smart-069924df-ddc0-4606-bb0c-0d3b0be1d19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42535
04241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.4253504241
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3704299900
Short name T289
Test name
Test status
Simulation time 8367413305 ps
CPU time 7.12 seconds
Started Mar 21 01:25:21 PM PDT 24
Finished Mar 21 01:25:28 PM PDT 24
Peak memory 203540 kb
Host smart-3612a9e8-3dbf-4ecc-a6ea-36e43a68ceed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37042
99900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3704299900
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.673529001
Short name T272
Test name
Test status
Simulation time 8367445525 ps
CPU time 8.21 seconds
Started Mar 21 01:25:05 PM PDT 24
Finished Mar 21 01:25:13 PM PDT 24
Peak memory 203488 kb
Host smart-0e31f3b7-fb8f-4757-a9b8-d78100096f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67352
9001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.673529001
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3453078615
Short name T503
Test name
Test status
Simulation time 50923925 ps
CPU time 1.39 seconds
Started Mar 21 01:25:23 PM PDT 24
Finished Mar 21 01:25:25 PM PDT 24
Peak memory 203176 kb
Host smart-34b26039-9fae-493a-8863-560fcf1b36a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34530
78615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3453078615
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2392512116
Short name T26
Test name
Test status
Simulation time 8357125480 ps
CPU time 7.16 seconds
Started Mar 21 01:25:33 PM PDT 24
Finished Mar 21 01:25:40 PM PDT 24
Peak memory 203244 kb
Host smart-6a9e7e79-0e3b-4c12-8500-e5767e5be400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23925
12116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2392512116
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.621690410
Short name T596
Test name
Test status
Simulation time 8387056943 ps
CPU time 7.61 seconds
Started Mar 21 01:25:10 PM PDT 24
Finished Mar 21 01:25:18 PM PDT 24
Peak memory 203384 kb
Host smart-1135cc55-4e56-489e-bb96-516b1c3c8226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62169
0410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.621690410
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2596905164
Short name T654
Test name
Test status
Simulation time 8410645887 ps
CPU time 7.62 seconds
Started Mar 21 01:25:13 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 203508 kb
Host smart-ecb11c74-2ba2-43e0-9de7-70230d1343b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25969
05164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2596905164
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1477860803
Short name T828
Test name
Test status
Simulation time 8360190984 ps
CPU time 7.84 seconds
Started Mar 21 01:25:17 PM PDT 24
Finished Mar 21 01:25:25 PM PDT 24
Peak memory 203368 kb
Host smart-57d3c9c9-3534-4758-899d-13a5ec9c5bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778
60803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1477860803
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.353737588
Short name T410
Test name
Test status
Simulation time 8374429120 ps
CPU time 8.57 seconds
Started Mar 21 01:25:17 PM PDT 24
Finished Mar 21 01:25:26 PM PDT 24
Peak memory 203308 kb
Host smart-f7af6ec4-b210-4575-9f21-6c0656f4077f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35373
7588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.353737588
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1438749378
Short name T701
Test name
Test status
Simulation time 8392430622 ps
CPU time 8.65 seconds
Started Mar 21 01:25:12 PM PDT 24
Finished Mar 21 01:25:21 PM PDT 24
Peak memory 203288 kb
Host smart-79970265-1210-4b5a-8ccf-72ef8b15c7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
49378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1438749378
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.4047496782
Short name T426
Test name
Test status
Simulation time 27076749 ps
CPU time 0.65 seconds
Started Mar 21 01:25:18 PM PDT 24
Finished Mar 21 01:25:20 PM PDT 24
Peak memory 202952 kb
Host smart-d732a03f-aa5f-4dc7-9912-31aac83b1c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40474
96782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4047496782
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1918984396
Short name T662
Test name
Test status
Simulation time 8396557946 ps
CPU time 7.12 seconds
Started Mar 21 01:25:22 PM PDT 24
Finished Mar 21 01:25:29 PM PDT 24
Peak memory 203440 kb
Host smart-d91e39b9-1ac4-45b6-9169-2506d1361d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19189
84396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1918984396
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.216857206
Short name T577
Test name
Test status
Simulation time 8455570824 ps
CPU time 7.49 seconds
Started Mar 21 01:25:14 PM PDT 24
Finished Mar 21 01:25:22 PM PDT 24
Peak memory 203448 kb
Host smart-c2fbe97f-d098-4b09-b931-720cffd39372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21685
7206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.216857206
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3386454032
Short name T398
Test name
Test status
Simulation time 8389246651 ps
CPU time 7.65 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:25:23 PM PDT 24
Peak memory 203484 kb
Host smart-53e527b0-45fe-4ee5-86b9-dea6fc16f928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33864
54032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3386454032
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1562387766
Short name T821
Test name
Test status
Simulation time 8361149033 ps
CPU time 7.32 seconds
Started Mar 21 01:25:25 PM PDT 24
Finished Mar 21 01:25:32 PM PDT 24
Peak memory 203376 kb
Host smart-78fa0389-eb2c-456a-ab76-f1cc2752f7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15623
87766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1562387766
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1179362912
Short name T861
Test name
Test status
Simulation time 8475941274 ps
CPU time 7.54 seconds
Started Mar 21 01:25:15 PM PDT 24
Finished Mar 21 01:25:23 PM PDT 24
Peak memory 203548 kb
Host smart-28d2ae62-53c4-4275-aba5-bddf744d691c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11793
62912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1179362912
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1609546014
Short name T397
Test name
Test status
Simulation time 8369438679 ps
CPU time 7.09 seconds
Started Mar 21 01:23:04 PM PDT 24
Finished Mar 21 01:23:11 PM PDT 24
Peak memory 203576 kb
Host smart-54abcf94-4ad0-4283-b017-7d917b265bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16095
46014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1609546014
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.401346073
Short name T699
Test name
Test status
Simulation time 8372587915 ps
CPU time 8.91 seconds
Started Mar 21 01:23:03 PM PDT 24
Finished Mar 21 01:23:12 PM PDT 24
Peak memory 203496 kb
Host smart-5e314439-5508-4e80-b068-41fe7b297ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40134
6073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.401346073
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3190611603
Short name T469
Test name
Test status
Simulation time 246817523 ps
CPU time 2.03 seconds
Started Mar 21 01:23:19 PM PDT 24
Finished Mar 21 01:23:22 PM PDT 24
Peak memory 203460 kb
Host smart-6ba0aff2-c380-46d6-9104-f6e0b8ceabaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31906
11603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3190611603
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3890512379
Short name T177
Test name
Test status
Simulation time 8362989545 ps
CPU time 7.75 seconds
Started Mar 21 01:23:14 PM PDT 24
Finished Mar 21 01:23:23 PM PDT 24
Peak memory 203212 kb
Host smart-55e337dc-40f5-42f3-848d-2f10175a4667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38905
12379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3890512379
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3657251969
Short name T302
Test name
Test status
Simulation time 8409607922 ps
CPU time 8.56 seconds
Started Mar 21 01:23:04 PM PDT 24
Finished Mar 21 01:23:13 PM PDT 24
Peak memory 203452 kb
Host smart-203cf160-116c-4890-8bb4-bf4d89ca7678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36572
51969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3657251969
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2650154770
Short name T432
Test name
Test status
Simulation time 8406672492 ps
CPU time 7.66 seconds
Started Mar 21 01:23:24 PM PDT 24
Finished Mar 21 01:23:32 PM PDT 24
Peak memory 203572 kb
Host smart-52923c5c-d319-41e8-885e-bdae61c3e1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26501
54770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2650154770
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3399951722
Short name T796
Test name
Test status
Simulation time 8361366711 ps
CPU time 7.26 seconds
Started Mar 21 01:23:04 PM PDT 24
Finished Mar 21 01:23:11 PM PDT 24
Peak memory 203340 kb
Host smart-f643b6bb-81c3-4f5a-a404-5a0861fc433c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33999
51722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3399951722
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.66247984
Short name T96
Test name
Test status
Simulation time 8402402400 ps
CPU time 7.42 seconds
Started Mar 21 01:23:04 PM PDT 24
Finished Mar 21 01:23:12 PM PDT 24
Peak memory 203424 kb
Host smart-aaa16a34-1764-4779-9dc9-b14a8ff2c1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66247
984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.66247984
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3800951066
Short name T438
Test name
Test status
Simulation time 8370692473 ps
CPU time 7.25 seconds
Started Mar 21 01:23:12 PM PDT 24
Finished Mar 21 01:23:21 PM PDT 24
Peak memory 203300 kb
Host smart-1635b57e-bf47-47fb-a518-6ed03b08c667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
51066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3800951066
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.639671730
Short name T526
Test name
Test status
Simulation time 8386633836 ps
CPU time 10.01 seconds
Started Mar 21 01:23:18 PM PDT 24
Finished Mar 21 01:23:29 PM PDT 24
Peak memory 203260 kb
Host smart-b47e3451-29b5-45d3-b285-c3260a7b7db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63967
1730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.639671730
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3754992490
Short name T819
Test name
Test status
Simulation time 8371374573 ps
CPU time 8.94 seconds
Started Mar 21 01:23:12 PM PDT 24
Finished Mar 21 01:23:22 PM PDT 24
Peak memory 203500 kb
Host smart-417769d4-0b80-44b7-997c-e4c2bf2e2fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37549
92490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3754992490
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2935861261
Short name T664
Test name
Test status
Simulation time 8395297992 ps
CPU time 7.23 seconds
Started Mar 21 01:23:06 PM PDT 24
Finished Mar 21 01:23:13 PM PDT 24
Peak memory 203380 kb
Host smart-9380d99c-6589-4e53-8ec3-7506800acc3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29358
61261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2935861261
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.3171730015
Short name T580
Test name
Test status
Simulation time 8379579159 ps
CPU time 7.41 seconds
Started Mar 21 01:23:20 PM PDT 24
Finished Mar 21 01:23:28 PM PDT 24
Peak memory 203452 kb
Host smart-8be4caae-a2ae-44ed-acf1-bc074e75bc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31717
30015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.3171730015
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.500810695
Short name T586
Test name
Test status
Simulation time 8360325317 ps
CPU time 9.3 seconds
Started Mar 21 01:23:18 PM PDT 24
Finished Mar 21 01:23:29 PM PDT 24
Peak memory 203452 kb
Host smart-b36bff5c-3bf2-4b4f-a0b5-3236ce7fdccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50081
0695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.500810695
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.574728258
Short name T140
Test name
Test status
Simulation time 8478743898 ps
CPU time 9.34 seconds
Started Mar 21 01:23:10 PM PDT 24
Finished Mar 21 01:23:20 PM PDT 24
Peak memory 203596 kb
Host smart-b418ac93-4931-4a10-b07e-d80d68282393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57472
8258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.574728258
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1001775948
Short name T273
Test name
Test status
Simulation time 8371495971 ps
CPU time 8.5 seconds
Started Mar 21 01:23:19 PM PDT 24
Finished Mar 21 01:23:29 PM PDT 24
Peak memory 203512 kb
Host smart-d441e2b5-a721-43b9-81ac-1189fa7d375b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10017
75948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1001775948
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.3941672411
Short name T389
Test name
Test status
Simulation time 8371445171 ps
CPU time 7.87 seconds
Started Mar 21 01:23:07 PM PDT 24
Finished Mar 21 01:23:15 PM PDT 24
Peak memory 203576 kb
Host smart-a2b1eaad-b535-4245-893d-366467a31848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39416
72411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3941672411
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1003267519
Short name T229
Test name
Test status
Simulation time 70024962 ps
CPU time 1.92 seconds
Started Mar 21 01:23:17 PM PDT 24
Finished Mar 21 01:23:20 PM PDT 24
Peak memory 203536 kb
Host smart-b7e78081-b26e-4e11-bd2d-8a768ec21753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10032
67519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1003267519
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.506112135
Short name T836
Test name
Test status
Simulation time 8361331682 ps
CPU time 7.11 seconds
Started Mar 21 01:23:03 PM PDT 24
Finished Mar 21 01:23:11 PM PDT 24
Peak memory 203308 kb
Host smart-69416206-3c86-42bb-8087-e3fd78c7ebd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50611
2135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.506112135
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2742012849
Short name T135
Test name
Test status
Simulation time 8386244395 ps
CPU time 7.25 seconds
Started Mar 21 01:23:13 PM PDT 24
Finished Mar 21 01:23:21 PM PDT 24
Peak memory 203432 kb
Host smart-d3705367-f9b9-4227-961b-b3a87581ddd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27420
12849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2742012849
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2316260621
Short name T278
Test name
Test status
Simulation time 8414279560 ps
CPU time 8.64 seconds
Started Mar 21 01:23:26 PM PDT 24
Finished Mar 21 01:23:35 PM PDT 24
Peak memory 203440 kb
Host smart-99e7556b-2b7e-44b5-b4ac-712a3eca03df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23162
60621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2316260621
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2386733263
Short name T423
Test name
Test status
Simulation time 8360431056 ps
CPU time 7.71 seconds
Started Mar 21 01:23:12 PM PDT 24
Finished Mar 21 01:23:21 PM PDT 24
Peak memory 203204 kb
Host smart-02d038a8-9364-4721-9ed4-59bbdd76258a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23867
33263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2386733263
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1859832315
Short name T108
Test name
Test status
Simulation time 8401010138 ps
CPU time 7.75 seconds
Started Mar 21 01:23:15 PM PDT 24
Finished Mar 21 01:23:24 PM PDT 24
Peak memory 203436 kb
Host smart-716ebd53-f264-4518-a351-e2dbdd27d765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18598
32315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1859832315
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3636074068
Short name T546
Test name
Test status
Simulation time 8389113032 ps
CPU time 8.54 seconds
Started Mar 21 01:23:23 PM PDT 24
Finished Mar 21 01:23:32 PM PDT 24
Peak memory 203308 kb
Host smart-1c2129ea-06ba-4e72-8268-9800213f8ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36360
74068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3636074068
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3493782766
Short name T672
Test name
Test status
Simulation time 8391078023 ps
CPU time 6.9 seconds
Started Mar 21 01:23:07 PM PDT 24
Finished Mar 21 01:23:14 PM PDT 24
Peak memory 203248 kb
Host smart-3587bf8d-6e63-45cc-8727-c068056b66b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34937
82766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3493782766
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.17531168
Short name T522
Test name
Test status
Simulation time 27840635 ps
CPU time 0.63 seconds
Started Mar 21 01:23:05 PM PDT 24
Finished Mar 21 01:23:05 PM PDT 24
Peak memory 203008 kb
Host smart-2167d76e-1dac-4601-8256-8a446379bfc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17531
168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.17531168
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3889577773
Short name T506
Test name
Test status
Simulation time 8382661614 ps
CPU time 7.3 seconds
Started Mar 21 01:23:20 PM PDT 24
Finished Mar 21 01:23:28 PM PDT 24
Peak memory 203448 kb
Host smart-078a6ed3-2743-4cdd-bc2e-f56d380cd39c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38895
77773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3889577773
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.1149791808
Short name T319
Test name
Test status
Simulation time 8364923882 ps
CPU time 7.92 seconds
Started Mar 21 01:23:10 PM PDT 24
Finished Mar 21 01:23:19 PM PDT 24
Peak memory 203216 kb
Host smart-3ebd270b-518e-4ade-b0ea-f9323f332a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11497
91808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.1149791808
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2202423586
Short name T340
Test name
Test status
Simulation time 8359105668 ps
CPU time 7.76 seconds
Started Mar 21 01:23:29 PM PDT 24
Finished Mar 21 01:23:37 PM PDT 24
Peak memory 203236 kb
Host smart-7060951d-7c21-4d2b-beda-16fc1efc0abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22024
23586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2202423586
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3114339133
Short name T620
Test name
Test status
Simulation time 8472871530 ps
CPU time 8.93 seconds
Started Mar 21 01:23:12 PM PDT 24
Finished Mar 21 01:23:22 PM PDT 24
Peak memory 203552 kb
Host smart-1ced9be0-0caf-4132-887a-b0123438ceee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31143
39133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3114339133
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3397717597
Short name T386
Test name
Test status
Simulation time 8365333577 ps
CPU time 8.81 seconds
Started Mar 21 01:23:29 PM PDT 24
Finished Mar 21 01:23:38 PM PDT 24
Peak memory 203488 kb
Host smart-1ecc1cb4-0a56-4b24-a5e3-956472fcf0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
17597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3397717597
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.2334117495
Short name T508
Test name
Test status
Simulation time 8370670160 ps
CPU time 8.07 seconds
Started Mar 21 01:23:31 PM PDT 24
Finished Mar 21 01:23:40 PM PDT 24
Peak memory 203504 kb
Host smart-e6eb7c23-dfc0-4f93-bded-f79d1e4d93bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23341
17495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2334117495
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.4104021139
Short name T214
Test name
Test status
Simulation time 178254074 ps
CPU time 1.88 seconds
Started Mar 21 01:23:27 PM PDT 24
Finished Mar 21 01:23:29 PM PDT 24
Peak memory 203524 kb
Host smart-e9e3d208-bd12-4e0e-9082-a4c848ee39dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41040
21139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.4104021139
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2242861523
Short name T165
Test name
Test status
Simulation time 8358407297 ps
CPU time 8.46 seconds
Started Mar 21 01:23:36 PM PDT 24
Finished Mar 21 01:23:45 PM PDT 24
Peak memory 203220 kb
Host smart-8af1cd63-78f0-40ac-8671-51f70299c754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22428
61523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2242861523
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3341337346
Short name T744
Test name
Test status
Simulation time 8396917624 ps
CPU time 7 seconds
Started Mar 21 01:23:31 PM PDT 24
Finished Mar 21 01:23:39 PM PDT 24
Peak memory 203400 kb
Host smart-5cb3e1b2-b5de-48c6-9e95-e6a51b96a9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413
37346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3341337346
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1978843268
Short name T344
Test name
Test status
Simulation time 8416588297 ps
CPU time 7.65 seconds
Started Mar 21 01:23:25 PM PDT 24
Finished Mar 21 01:23:33 PM PDT 24
Peak memory 203424 kb
Host smart-6b5c8a06-7382-472e-9aa9-212d14fdc531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19788
43268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1978843268
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.92844056
Short name T484
Test name
Test status
Simulation time 8361235211 ps
CPU time 8.33 seconds
Started Mar 21 01:23:21 PM PDT 24
Finished Mar 21 01:23:29 PM PDT 24
Peak memory 203272 kb
Host smart-f908bdf9-9b52-4d01-b2ba-e98dd6649cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92844
056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.92844056
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1500488251
Short name T107
Test name
Test status
Simulation time 8399428458 ps
CPU time 7.48 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:46 PM PDT 24
Peak memory 203500 kb
Host smart-668d7302-80f6-4f98-9bd4-9ea0afde2ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15004
88251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1500488251
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.556742192
Short name T267
Test name
Test status
Simulation time 8364390597 ps
CPU time 7.73 seconds
Started Mar 21 01:23:31 PM PDT 24
Finished Mar 21 01:23:39 PM PDT 24
Peak memory 203440 kb
Host smart-5cbeec68-9a73-49af-8b4f-1e6740213d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55674
2192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.556742192
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.486118322
Short name T604
Test name
Test status
Simulation time 8384252355 ps
CPU time 8.02 seconds
Started Mar 21 01:23:20 PM PDT 24
Finished Mar 21 01:23:29 PM PDT 24
Peak memory 203400 kb
Host smart-ed3a3aa6-10d3-4cda-b38b-acdb0e4e3217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48611
8322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.486118322
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1228989355
Short name T853
Test name
Test status
Simulation time 23505439 ps
CPU time 0.65 seconds
Started Mar 21 01:23:21 PM PDT 24
Finished Mar 21 01:23:22 PM PDT 24
Peak memory 202936 kb
Host smart-34cc0488-039e-4f6d-876f-e9c445f71d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12289
89355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1228989355
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3975113753
Short name T753
Test name
Test status
Simulation time 8384411066 ps
CPU time 9.29 seconds
Started Mar 21 01:23:28 PM PDT 24
Finished Mar 21 01:23:38 PM PDT 24
Peak memory 203508 kb
Host smart-45d75477-9275-4c8a-b5ca-0e385220501e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751
13753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3975113753
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4013736103
Short name T807
Test name
Test status
Simulation time 8427590867 ps
CPU time 9.41 seconds
Started Mar 21 01:23:33 PM PDT 24
Finished Mar 21 01:23:44 PM PDT 24
Peak memory 203452 kb
Host smart-2025a74c-f064-4fb5-9b91-e89cd2105984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40137
36103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4013736103
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1975997229
Short name T516
Test name
Test status
Simulation time 8370524641 ps
CPU time 7.94 seconds
Started Mar 21 01:23:25 PM PDT 24
Finished Mar 21 01:23:33 PM PDT 24
Peak memory 203528 kb
Host smart-2a934e95-b032-412e-ad2c-08a6ae902140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19759
97229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1975997229
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.1036020702
Short name T363
Test name
Test status
Simulation time 8358102211 ps
CPU time 7.48 seconds
Started Mar 21 01:23:31 PM PDT 24
Finished Mar 21 01:23:39 PM PDT 24
Peak memory 203336 kb
Host smart-06250e6b-c89d-47cc-9833-74822daa122c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10360
20702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.1036020702
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3397734566
Short name T75
Test name
Test status
Simulation time 8473008732 ps
CPU time 9.6 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203544 kb
Host smart-17ea2026-10b2-4c7d-8ff7-a221dd23248b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
34566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3397734566
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.815294702
Short name T8
Test name
Test status
Simulation time 8367746805 ps
CPU time 8.9 seconds
Started Mar 21 01:23:27 PM PDT 24
Finished Mar 21 01:23:36 PM PDT 24
Peak memory 203580 kb
Host smart-69f5df48-09ea-44a7-9f8b-a894c262648a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81529
4702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.815294702
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.1187692471
Short name T6
Test name
Test status
Simulation time 8371734010 ps
CPU time 7.16 seconds
Started Mar 21 01:23:25 PM PDT 24
Finished Mar 21 01:23:32 PM PDT 24
Peak memory 203488 kb
Host smart-83143aa3-9775-4f5f-a909-fdc10f08d464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11876
92471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1187692471
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1685891721
Short name T403
Test name
Test status
Simulation time 182197939 ps
CPU time 2.02 seconds
Started Mar 21 01:23:21 PM PDT 24
Finished Mar 21 01:23:23 PM PDT 24
Peak memory 203364 kb
Host smart-fdaecc1f-cd90-4d00-a5a8-252a8f57d6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16858
91721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1685891721
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2444011150
Short name T168
Test name
Test status
Simulation time 8361004049 ps
CPU time 7.36 seconds
Started Mar 21 01:23:44 PM PDT 24
Finished Mar 21 01:23:51 PM PDT 24
Peak memory 203244 kb
Host smart-9837c7f8-5bc4-4083-8e09-f11f1c3c36e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24440
11150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2444011150
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2401597486
Short name T686
Test name
Test status
Simulation time 8453072276 ps
CPU time 7.47 seconds
Started Mar 21 01:23:39 PM PDT 24
Finished Mar 21 01:23:46 PM PDT 24
Peak memory 203480 kb
Host smart-ebc89486-cb99-441c-9b10-c69a466112d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24015
97486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2401597486
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3824772869
Short name T658
Test name
Test status
Simulation time 8403438877 ps
CPU time 7.14 seconds
Started Mar 21 01:23:34 PM PDT 24
Finished Mar 21 01:23:42 PM PDT 24
Peak memory 203572 kb
Host smart-c48d5ebc-0413-49e7-b70a-dccd2ee1739c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
72869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3824772869
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2675911435
Short name T470
Test name
Test status
Simulation time 8368628373 ps
CPU time 7.76 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:46 PM PDT 24
Peak memory 203308 kb
Host smart-934bd76b-35c2-4f65-96c8-15d3c20fc1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26759
11435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2675911435
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3606957540
Short name T86
Test name
Test status
Simulation time 8422709159 ps
CPU time 7.74 seconds
Started Mar 21 01:23:24 PM PDT 24
Finished Mar 21 01:23:32 PM PDT 24
Peak memory 203476 kb
Host smart-0c818f3b-5d7a-4af2-961b-abc573fb3614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36069
57540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3606957540
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1913274617
Short name T22
Test name
Test status
Simulation time 8365402140 ps
CPU time 7.11 seconds
Started Mar 21 01:23:31 PM PDT 24
Finished Mar 21 01:23:38 PM PDT 24
Peak memory 203416 kb
Host smart-e7799207-bda2-42b5-964f-9ef6cc0efd99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19132
74617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1913274617
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2148385386
Short name T531
Test name
Test status
Simulation time 8391086782 ps
CPU time 7.07 seconds
Started Mar 21 01:23:37 PM PDT 24
Finished Mar 21 01:23:44 PM PDT 24
Peak memory 203188 kb
Host smart-6cf4e2f6-0369-4b80-8216-ebbee19634b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21483
85386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2148385386
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.80742643
Short name T465
Test name
Test status
Simulation time 26538590 ps
CPU time 0.62 seconds
Started Mar 21 01:23:34 PM PDT 24
Finished Mar 21 01:23:35 PM PDT 24
Peak memory 202840 kb
Host smart-61c77cd3-dd61-4d67-805c-ea4875472905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80742
643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.80742643
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.442535772
Short name T843
Test name
Test status
Simulation time 8359659464 ps
CPU time 7.4 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:56 PM PDT 24
Peak memory 203364 kb
Host smart-993584c5-dd3a-4ccb-9616-82bef123138b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44253
5772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.442535772
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3562763869
Short name T346
Test name
Test status
Simulation time 8430047953 ps
CPU time 7.82 seconds
Started Mar 21 01:23:39 PM PDT 24
Finished Mar 21 01:23:47 PM PDT 24
Peak memory 203440 kb
Host smart-dfc21e7a-f555-424d-a076-6b496a2e800e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35627
63869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3562763869
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.1637939967
Short name T322
Test name
Test status
Simulation time 8394302523 ps
CPU time 7.6 seconds
Started Mar 21 01:23:46 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203416 kb
Host smart-6fc26522-3d65-43f7-a307-35dd6e25848d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16379
39967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.1637939967
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1239747371
Short name T790
Test name
Test status
Simulation time 8358443755 ps
CPU time 7.42 seconds
Started Mar 21 01:23:34 PM PDT 24
Finished Mar 21 01:23:42 PM PDT 24
Peak memory 203380 kb
Host smart-48372c31-0633-4fe7-8af0-f50e8d2916a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397
47371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1239747371
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.588379330
Short name T581
Test name
Test status
Simulation time 8472935690 ps
CPU time 7.75 seconds
Started Mar 21 01:23:29 PM PDT 24
Finished Mar 21 01:23:37 PM PDT 24
Peak memory 203516 kb
Host smart-0e938b33-dde1-46b0-873a-a999dfe43ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58837
9330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.588379330
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.661784988
Short name T400
Test name
Test status
Simulation time 8369017635 ps
CPU time 7.31 seconds
Started Mar 21 01:23:41 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203500 kb
Host smart-6a852185-d206-464f-9265-d3ed6412e773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66178
4988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.661784988
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.3351411251
Short name T774
Test name
Test status
Simulation time 8370529799 ps
CPU time 8.21 seconds
Started Mar 21 01:23:45 PM PDT 24
Finished Mar 21 01:23:54 PM PDT 24
Peak memory 203572 kb
Host smart-2c1de2b0-c610-4b29-9141-04f5f97f580f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33514
11251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3351411251
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3411632843
Short name T358
Test name
Test status
Simulation time 62373238 ps
CPU time 1.57 seconds
Started Mar 21 01:23:35 PM PDT 24
Finished Mar 21 01:23:37 PM PDT 24
Peak memory 203248 kb
Host smart-4875a6ed-41c6-425b-bb7a-2d49fab64a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34116
32843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3411632843
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1854391628
Short name T583
Test name
Test status
Simulation time 8361455416 ps
CPU time 7.81 seconds
Started Mar 21 01:23:44 PM PDT 24
Finished Mar 21 01:23:52 PM PDT 24
Peak memory 203252 kb
Host smart-096364c6-bf20-49d2-9608-9d81924d58fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18543
91628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1854391628
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.958071527
Short name T124
Test name
Test status
Simulation time 8380129578 ps
CPU time 7.6 seconds
Started Mar 21 01:23:44 PM PDT 24
Finished Mar 21 01:23:52 PM PDT 24
Peak memory 203536 kb
Host smart-4c1e074d-525a-4251-aceb-13a3921b8744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95807
1527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.958071527
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3529857216
Short name T234
Test name
Test status
Simulation time 8407828615 ps
CPU time 7.49 seconds
Started Mar 21 01:23:49 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203484 kb
Host smart-60328729-d4e8-4c3a-a852-a8c97c317dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35298
57216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3529857216
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2330848638
Short name T317
Test name
Test status
Simulation time 8364274717 ps
CPU time 7.1 seconds
Started Mar 21 01:23:41 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203436 kb
Host smart-d3376e72-0de4-4af9-a18b-15a8ff162cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23308
48638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2330848638
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2837119020
Short name T93
Test name
Test status
Simulation time 8436357127 ps
CPU time 7.33 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:46 PM PDT 24
Peak memory 203556 kb
Host smart-1e9a207e-4b17-4a34-9015-4e5ea998194b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28371
19020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2837119020
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2401562183
Short name T297
Test name
Test status
Simulation time 8370175986 ps
CPU time 8.56 seconds
Started Mar 21 01:23:44 PM PDT 24
Finished Mar 21 01:23:52 PM PDT 24
Peak memory 203552 kb
Host smart-243a6080-2ad1-4681-a27b-a9423568fc4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24015
62183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2401562183
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3695345678
Short name T305
Test name
Test status
Simulation time 8394532393 ps
CPU time 9.26 seconds
Started Mar 21 01:23:38 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203244 kb
Host smart-65b54f61-63af-4a70-97df-758bd4df3ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36953
45678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3695345678
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1856427105
Short name T37
Test name
Test status
Simulation time 28964746 ps
CPU time 0.65 seconds
Started Mar 21 01:23:39 PM PDT 24
Finished Mar 21 01:23:40 PM PDT 24
Peak memory 202948 kb
Host smart-5256a3ed-e8db-4e89-98e2-0c0348f664fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18564
27105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1856427105
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1475141628
Short name T311
Test name
Test status
Simulation time 8366775015 ps
CPU time 9.61 seconds
Started Mar 21 01:23:40 PM PDT 24
Finished Mar 21 01:23:50 PM PDT 24
Peak memory 203532 kb
Host smart-2342946e-9a2f-46a6-ae19-471cca692868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14751
41628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1475141628
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.1207299237
Short name T129
Test name
Test status
Simulation time 8409540092 ps
CPU time 7.28 seconds
Started Mar 21 01:23:52 PM PDT 24
Finished Mar 21 01:24:00 PM PDT 24
Peak memory 203392 kb
Host smart-87b319c2-f3e8-4c54-a6d0-28c5a14b9cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12072
99237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1207299237
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.2408941618
Short name T68
Test name
Test status
Simulation time 8369327361 ps
CPU time 8.97 seconds
Started Mar 21 01:23:39 PM PDT 24
Finished Mar 21 01:23:48 PM PDT 24
Peak memory 203452 kb
Host smart-f18972e9-7583-4783-b44d-207aa441c36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24089
41618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.2408941618
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4254502212
Short name T782
Test name
Test status
Simulation time 8361205982 ps
CPU time 9.4 seconds
Started Mar 21 01:23:32 PM PDT 24
Finished Mar 21 01:23:42 PM PDT 24
Peak memory 203312 kb
Host smart-8ceaa8c8-3a8d-4ced-baad-1d5a58e6f3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42545
02212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4254502212
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2695681878
Short name T763
Test name
Test status
Simulation time 8479385550 ps
CPU time 10.57 seconds
Started Mar 21 01:23:47 PM PDT 24
Finished Mar 21 01:23:57 PM PDT 24
Peak memory 203584 kb
Host smart-8077666b-cff4-4e4d-ad3f-b5569ad69cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26956
81878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2695681878
Directory /workspace/9.usbdev_smoke/latest
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