Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2850	1		T1	4		T2	2		T3	4
all_values[1]	2850	1		T1	4		T2	2		T3	4
all_values[2]	2850	1		T1	4		T2	2		T3	4
all_values[3]	2850	1		T1	4		T2	2		T3	4
all_values[4]	2850	1		T1	4		T2	2		T3	4
all_values[5]	2850	1		T1	4		T2	2		T3	4
all_values[6]	2850	1		T1	4		T2	2		T3	4
all_values[7]	2850	1		T1	4		T2	2		T3	4
all_values[8]	2850	1		T1	4		T2	2		T3	4
all_values[9]	2850	1		T1	4		T2	2		T3	4
all_values[10]	2850	1		T1	4		T2	2		T3	4
all_values[11]	2850	1		T1	4		T2	2		T3	4
all_values[12]	2850	1		T1	4		T2	2		T3	4
all_values[13]	2850	1		T1	4		T2	2		T3	4
all_values[14]	2850	1		T1	4		T2	2		T3	4
all_values[15]	2850	1		T1	4		T2	2		T3	4
all_values[16]	2850	1		T1	4		T2	2		T3	4
all_values[17]	2850	1		T1	4		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	48476	1		T1	68		T2	36		T3	68
auto[1]	2824	1		T1	4		T3	4		T13	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	48024	1		T1	72		T2	36		T3	72
auto[1]	3276	1		T67	123		T69	75		T70	116

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1999	1		T2	2		T11	2		T8	3
all_values[0]	auto[0]	auto[1]	86	1		T67	2		T69	4		T71	4
all_values[0]	auto[1]	auto[0]	666	1		T1	4		T3	4		T13	4
all_values[0]	auto[1]	auto[1]	99	1		T67	4		T69	1		T71	1
all_values[1]	auto[0]	auto[0]	2348	1		T1	4		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	100	1		T67	3		T69	2		T70	3
all_values[1]	auto[1]	auto[0]	312	1		T14	3		T28	3		T29	3
all_values[1]	auto[1]	auto[1]	90	1		T67	5		T69	3		T70	4
all_values[2]	auto[0]	auto[0]	2649	1		T1	4		T2	2		T3	4
all_values[2]	auto[0]	auto[1]	102	1		T67	7		T69	3		T70	6
all_values[2]	auto[1]	auto[0]	13	1		T72	1		T254	2		T255	1
all_values[2]	auto[1]	auto[1]	86	1		T67	1		T69	2		T70	2
all_values[3]	auto[0]	auto[0]	2644	1		T1	4		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	115	1		T67	6		T69	4		T70	3
all_values[3]	auto[1]	auto[0]	14	1		T70	1		T71	1		T256	4
all_values[3]	auto[1]	auto[1]	77	1		T67	2		T69	1		T70	4
all_values[4]	auto[0]	auto[0]	2653	1		T1	4		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	103	1		T67	6		T70	6		T72	4
all_values[4]	auto[1]	auto[0]	11	1		T69	1		T73	2		T257	1
all_values[4]	auto[1]	auto[1]	83	1		T67	1		T70	2		T71	3
all_values[5]	auto[0]	auto[0]	2658	1		T1	4		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	75	1		T67	6		T70	4		T73	2
all_values[5]	auto[1]	auto[0]	20	1		T72	2		T73	2		T258	1
all_values[5]	auto[1]	auto[1]	97	1		T67	2		T69	5		T70	4
all_values[6]	auto[0]	auto[0]	2662	1		T1	4		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	96	1		T69	5		T70	7		T72	6
all_values[6]	auto[1]	auto[0]	21	1		T253	1		T259	1		T254	2
all_values[6]	auto[1]	auto[1]	71	1		T67	6		T70	1		T71	5
all_values[7]	auto[0]	auto[0]	2646	1		T1	4		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	105	1		T67	2		T69	3		T70	3
all_values[7]	auto[1]	auto[0]	18	1		T67	2		T69	1		T71	1
all_values[7]	auto[1]	auto[1]	81	1		T67	3		T70	5		T72	2
all_values[8]	auto[0]	auto[0]	2648	1		T1	4		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	97	1		T70	6		T72	4		T73	3
all_values[8]	auto[1]	auto[0]	15	1		T69	4		T259	1		T256	1
all_values[8]	auto[1]	auto[1]	90	1		T67	8		T70	1		T71	3
all_values[9]	auto[0]	auto[0]	2660	1		T1	4		T2	2		T3	4
all_values[9]	auto[0]	auto[1]	91	1		T67	1		T69	2		T70	3
all_values[9]	auto[1]	auto[0]	16	1		T67	1		T71	1		T73	1
all_values[9]	auto[1]	auto[1]	83	1		T67	6		T69	3		T70	4
all_values[10]	auto[0]	auto[0]	2650	1		T1	4		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	82	1		T70	3		T73	6		T260	5
all_values[10]	auto[1]	auto[0]	19	1		T71	4		T72	1		T259	1
all_values[10]	auto[1]	auto[1]	99	1		T67	8		T69	5		T70	5
all_values[11]	auto[0]	auto[0]	2661	1		T1	4		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	94	1		T67	2		T69	1		T70	2
all_values[11]	auto[1]	auto[0]	14	1		T67	1		T254	1		T256	1
all_values[11]	auto[1]	auto[1]	81	1		T67	4		T69	4		T70	6
all_values[12]	auto[0]	auto[0]	2646	1		T1	4		T2	2		T3	4
all_values[12]	auto[0]	auto[1]	102	1		T67	4		T70	7		T71	1
all_values[12]	auto[1]	auto[0]	13	1		T69	1		T73	1		T260	1
all_values[12]	auto[1]	auto[1]	89	1		T67	2		T69	4		T70	1
all_values[13]	auto[0]	auto[0]	2650	1		T1	4		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	88	1		T67	4		T69	1		T70	7
all_values[13]	auto[1]	auto[0]	19	1		T67	3		T260	1		T253	1
all_values[13]	auto[1]	auto[1]	93	1		T69	4		T70	1		T71	5
all_values[14]	auto[0]	auto[0]	2656	1		T1	4		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	91	1		T67	1		T69	1		T70	3
all_values[14]	auto[1]	auto[0]	18	1		T70	1		T73	2		T260	1
all_values[14]	auto[1]	auto[1]	85	1		T67	7		T69	4		T70	1
all_values[15]	auto[0]	auto[0]	2653	1		T1	4		T2	2		T3	4
all_values[15]	auto[0]	auto[1]	89	1		T69	1		T71	5		T72	6
all_values[15]	auto[1]	auto[0]	14	1		T67	3		T69	1		T70	1
all_values[15]	auto[1]	auto[1]	94	1		T67	4		T69	3		T72	2
all_values[16]	auto[0]	auto[0]	2655	1		T1	4		T2	2		T3	4
all_values[16]	auto[0]	auto[1]	80	1		T67	3		T69	4		T70	5
all_values[16]	auto[1]	auto[0]	18	1		T70	1		T253	1		T259	4
all_values[16]	auto[1]	auto[1]	97	1		T67	5		T70	1		T72	2
all_values[17]	auto[0]	auto[0]	2655	1		T1	4		T2	2		T3	4
all_values[17]	auto[0]	auto[1]	87	1		T67	3		T69	2		T70	3
all_values[17]	auto[1]	auto[0]	10	1		T70	1		T255	1		T258	1
all_values[17]	auto[1]	auto[1]	98	1		T67	5		T69	3		T70	3