Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2850	1		T1	4		T2	2		T3	4
all_pins[1]	2850	1		T1	4		T2	2		T3	4
all_pins[2]	2850	1		T1	4		T2	2		T3	4
all_pins[3]	2850	1		T1	4		T2	2		T3	4
all_pins[4]	2850	1		T1	4		T2	2		T3	4
all_pins[5]	2850	1		T1	4		T2	2		T3	4
all_pins[6]	2850	1		T1	4		T2	2		T3	4
all_pins[7]	2850	1		T1	4		T2	2		T3	4
all_pins[8]	2850	1		T1	4		T2	2		T3	4
all_pins[9]	2850	1		T1	4		T2	2		T3	4
all_pins[10]	2850	1		T1	4		T2	2		T3	4
all_pins[11]	2850	1		T1	4		T2	2		T3	4
all_pins[12]	2850	1		T1	4		T2	2		T3	4
all_pins[13]	2850	1		T1	4		T2	2		T3	4
all_pins[14]	2850	1		T1	4		T2	2		T3	4
all_pins[15]	2850	1		T1	4		T2	2		T3	4
all_pins[16]	2850	1		T1	4		T2	2		T3	4
all_pins[17]	2850	1		T1	4		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	50342	1		T1	71		T2	36		T3	71
values[0x1]	958	1		T1	1		T3	1		T13	1
transitions[0x0=>0x1]	767	1		T1	1		T3	1		T13	1
transitions[0x1=>0x0]	772	1		T1	1		T3	1		T13	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2704	1		T1	3		T2	2		T3	3
all_pins[0]	values[0x1]	146	1		T1	1		T3	1		T13	1
all_pins[0]	transitions[0x0=>0x1]	134	1		T1	1		T3	1		T13	1
all_pins[0]	transitions[0x1=>0x0]	128	1		T14	1		T28	1		T29	1
all_pins[1]	values[0x0]	2710	1		T1	4		T2	2		T3	4
all_pins[1]	values[0x1]	140	1		T14	1		T28	1		T29	1
all_pins[1]	transitions[0x0=>0x1]	130	1		T14	1		T28	1		T29	1
all_pins[1]	transitions[0x1=>0x0]	40	1		T69	2		T70	2		T71	3
all_pins[2]	values[0x0]	2800	1		T1	4		T2	2		T3	4
all_pins[2]	values[0x1]	50	1		T67	1		T69	2		T70	2
all_pins[2]	transitions[0x0=>0x1]	41	1		T69	1		T70	2		T71	4
all_pins[2]	transitions[0x1=>0x0]	30	1		T67	1		T70	1		T72	2
all_pins[3]	values[0x0]	2811	1		T1	4		T2	2		T3	4
all_pins[3]	values[0x1]	39	1		T67	2		T69	1		T70	1
all_pins[3]	transitions[0x0=>0x1]	27	1		T67	2		T69	1		T70	1
all_pins[3]	transitions[0x1=>0x0]	33	1		T70	1		T71	2		T72	2
all_pins[4]	values[0x0]	2805	1		T1	4		T2	2		T3	4
all_pins[4]	values[0x1]	45	1		T70	1		T71	2		T72	2
all_pins[4]	transitions[0x0=>0x1]	29	1		T71	2		T73	2		T260	2
all_pins[4]	transitions[0x1=>0x0]	33	1		T67	1		T69	4		T70	2
all_pins[5]	values[0x0]	2801	1		T1	4		T2	2		T3	4
all_pins[5]	values[0x1]	49	1		T67	1		T69	4		T70	3
all_pins[5]	transitions[0x0=>0x1]	36	1		T67	1		T69	4		T70	3
all_pins[5]	transitions[0x1=>0x0]	24	1		T67	4		T71	1		T72	1
all_pins[6]	values[0x0]	2813	1		T1	4		T2	2		T3	4
all_pins[6]	values[0x1]	37	1		T67	4		T71	1		T72	2
all_pins[6]	transitions[0x0=>0x1]	29	1		T67	3		T71	1		T72	2
all_pins[6]	transitions[0x1=>0x0]	25	1		T70	2		T72	1		T73	1
all_pins[7]	values[0x0]	2817	1		T1	4		T2	2		T3	4
all_pins[7]	values[0x1]	33	1		T67	1		T70	2		T72	1
all_pins[7]	transitions[0x0=>0x1]	31	1		T67	1		T70	2		T72	1
all_pins[7]	transitions[0x1=>0x0]	32	1		T67	4		T70	1		T71	1
all_pins[8]	values[0x0]	2816	1		T1	4		T2	2		T3	4
all_pins[8]	values[0x1]	34	1		T67	4		T70	1		T71	1
all_pins[8]	transitions[0x0=>0x1]	27	1		T67	3		T70	1		T71	1
all_pins[8]	transitions[0x1=>0x0]	24	1		T67	2		T72	2		T260	3
all_pins[9]	values[0x0]	2819	1		T1	4		T2	2		T3	4
all_pins[9]	values[0x1]	31	1		T67	3		T72	2		T73	1
all_pins[9]	transitions[0x0=>0x1]	19	1		T67	1		T73	1		T260	3
all_pins[9]	transitions[0x1=>0x0]	33	1		T67	2		T69	2		T70	2
all_pins[10]	values[0x0]	2805	1		T1	4		T2	2		T3	4
all_pins[10]	values[0x1]	45	1		T67	4		T69	2		T70	2
all_pins[10]	transitions[0x0=>0x1]	32	1		T67	2		T72	4		T260	1
all_pins[10]	transitions[0x1=>0x0]	27	1		T67	1		T69	1		T70	2
all_pins[11]	values[0x0]	2810	1		T1	4		T2	2		T3	4
all_pins[11]	values[0x1]	40	1		T67	3		T69	3		T70	4
all_pins[11]	transitions[0x0=>0x1]	36	1		T67	3		T69	2		T70	4
all_pins[11]	transitions[0x1=>0x0]	42	1		T67	1		T70	1		T71	1
all_pins[12]	values[0x0]	2804	1		T1	4		T2	2		T3	4
all_pins[12]	values[0x1]	46	1		T67	1		T69	1		T70	1
all_pins[12]	transitions[0x0=>0x1]	33	1		T67	1		T70	1		T72	2
all_pins[12]	transitions[0x1=>0x0]	33	1		T69	2		T70	1		T71	2
all_pins[13]	values[0x0]	2804	1		T1	4		T2	2		T3	4
all_pins[13]	values[0x1]	46	1		T69	3		T70	1		T71	3
all_pins[13]	transitions[0x0=>0x1]	38	1		T69	3		T70	1		T71	3
all_pins[13]	transitions[0x1=>0x0]	36	1		T67	6		T70	1		T71	1
all_pins[14]	values[0x0]	2806	1		T1	4		T2	2		T3	4
all_pins[14]	values[0x1]	44	1		T67	6		T70	1		T71	1
all_pins[14]	transitions[0x0=>0x1]	30	1		T67	3		T70	1		T71	1
all_pins[14]	transitions[0x1=>0x0]	37	1		T72	1		T73	4		T260	1
all_pins[15]	values[0x0]	2799	1		T1	4		T2	2		T3	4
all_pins[15]	values[0x1]	51	1		T67	3		T72	2		T73	4
all_pins[15]	transitions[0x0=>0x1]	34	1		T67	1		T73	2		T260	4
all_pins[15]	transitions[0x1=>0x0]	31	1		T67	2		T73	1		T253	4
all_pins[16]	values[0x0]	2802	1		T1	4		T2	2		T3	4
all_pins[16]	values[0x1]	48	1		T67	4		T72	2		T73	3
all_pins[16]	transitions[0x0=>0x1]	42	1		T67	4		T72	2		T73	3
all_pins[16]	transitions[0x1=>0x0]	28	1		T67	1		T70	2		T71	1
all_pins[17]	values[0x0]	2816	1		T1	4		T2	2		T3	4
all_pins[17]	values[0x1]	34	1		T67	1		T70	2		T71	1
all_pins[17]	transitions[0x0=>0x1]	19	1		T70	2		T72	2		T260	1
all_pins[17]	transitions[0x1=>0x0]	136	1		T1	1		T3	1		T13	1