Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	182	1		T67	7		T69	4		T70	7
all_values[1]	182	1		T67	7		T69	4		T70	7
all_values[2]	182	1		T67	7		T69	4		T70	7
all_values[3]	182	1		T67	7		T69	4		T70	7
all_values[4]	182	1		T67	7		T69	4		T70	7
all_values[5]	182	1		T67	7		T69	4		T70	7
all_values[6]	182	1		T67	7		T69	4		T70	7
all_values[7]	182	1		T67	7		T69	4		T70	7
all_values[8]	182	1		T67	7		T69	4		T70	7
all_values[9]	182	1		T67	7		T69	4		T70	7
all_values[10]	182	1		T67	7		T69	4		T70	7
all_values[11]	182	1		T67	7		T69	4		T70	7
all_values[12]	182	1		T67	7		T69	4		T70	7
all_values[13]	182	1		T67	7		T69	4		T70	7
all_values[14]	182	1		T67	7		T69	4		T70	7
all_values[15]	182	1		T67	7		T69	4		T70	7
all_values[16]	182	1		T67	7		T69	4		T70	7
all_values[17]	182	1		T67	7		T69	4		T70	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1840	1		T67	64		T69	39		T70	79
auto[1]	1436	1		T67	62		T69	33		T70	47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	542	1		T67	21		T69	13		T70	26
auto[1]	2734	1		T67	105		T69	59		T70	100

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1919	1		T67	76		T69	42		T70	77
auto[1]	1357	1		T67	50		T69	30		T70	49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	13	1		T67	1		T70	2		T73	2
all_values[0]	auto[0]	auto[0]	auto[1]	36	1		T67	1		T69	1		T71	2
all_values[0]	auto[0]	auto[1]	auto[0]	14	1		T67	1		T70	5		T73	2
all_values[0]	auto[0]	auto[1]	auto[1]	40	1		T67	2		T72	1		T260	4
all_values[0]	auto[1]	auto[0]	auto[1]	43	1		T67	2		T69	1		T71	2
all_values[0]	auto[1]	auto[1]	auto[1]	36	1		T69	2		T72	3		T253	1
all_values[1]	auto[0]	auto[0]	auto[0]	14	1		T70	1		T72	1		T73	1
all_values[1]	auto[0]	auto[0]	auto[1]	44	1		T67	2		T69	1		T70	1
all_values[1]	auto[0]	auto[1]	auto[0]	9	1		T72	2		T73	1		T255	3
all_values[1]	auto[0]	auto[1]	auto[1]	36	1		T67	3		T69	1		T70	2
all_values[1]	auto[1]	auto[0]	auto[1]	40	1		T67	1		T69	2		T70	3
all_values[1]	auto[1]	auto[1]	auto[1]	39	1		T67	1		T71	1		T72	3
all_values[2]	auto[0]	auto[0]	auto[0]	18	1		T72	1		T73	2		T253	1
all_values[2]	auto[0]	auto[0]	auto[1]	37	1		T67	3		T69	1		T70	2
all_values[2]	auto[0]	auto[1]	auto[0]	8	1		T72	1		T254	1		T261	3
all_values[2]	auto[0]	auto[1]	auto[1]	29	1		T67	1		T70	1		T71	2
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T67	3		T69	1		T70	2
all_values[2]	auto[1]	auto[1]	auto[1]	30	1		T69	2		T70	2		T71	2
all_values[3]	auto[0]	auto[0]	auto[0]	11	1		T71	2		T256	1		T255	2
all_values[3]	auto[0]	auto[0]	auto[1]	47	1		T67	3		T69	1		T70	2
all_values[3]	auto[0]	auto[1]	auto[0]	9	1		T70	1		T256	3		T255	2
all_values[3]	auto[0]	auto[1]	auto[1]	42	1		T69	1		T70	3		T72	1
all_values[3]	auto[1]	auto[0]	auto[1]	50	1		T67	3		T69	1		T71	1
all_values[3]	auto[1]	auto[1]	auto[1]	23	1		T67	1		T69	1		T70	1
all_values[4]	auto[0]	auto[0]	auto[0]	18	1		T67	1		T69	2		T71	2
all_values[4]	auto[0]	auto[0]	auto[1]	44	1		T67	3		T70	2		T72	1
all_values[4]	auto[0]	auto[1]	auto[0]	8	1		T69	2		T73	1		T262	1
all_values[4]	auto[0]	auto[1]	auto[1]	43	1		T67	1		T70	1		T71	1
all_values[4]	auto[1]	auto[0]	auto[1]	45	1		T67	2		T70	3		T72	4
all_values[4]	auto[1]	auto[1]	auto[1]	24	1		T70	1		T71	1		T73	1
all_values[5]	auto[0]	auto[0]	auto[0]	24	1		T71	4		T72	2		T73	1
all_values[5]	auto[0]	auto[0]	auto[1]	35	1		T67	1		T70	2		T73	2
all_values[5]	auto[0]	auto[1]	auto[0]	15	1		T72	2		T73	1		T258	1
all_values[5]	auto[0]	auto[1]	auto[1]	35	1		T67	1		T69	2		T70	1
all_values[5]	auto[1]	auto[0]	auto[1]	34	1		T67	4		T69	1		T73	1
all_values[5]	auto[1]	auto[1]	auto[1]	39	1		T67	1		T69	1		T70	4
all_values[6]	auto[0]	auto[0]	auto[0]	28	1		T67	2		T253	1		T259	1
all_values[6]	auto[0]	auto[0]	auto[1]	46	1		T69	3		T70	2		T72	3
all_values[6]	auto[0]	auto[1]	auto[0]	15	1		T253	1		T259	1		T254	1
all_values[6]	auto[0]	auto[1]	auto[1]	23	1		T67	1		T71	2		T72	1
all_values[6]	auto[1]	auto[0]	auto[1]	40	1		T67	1		T69	1		T70	5
all_values[6]	auto[1]	auto[1]	auto[1]	30	1		T67	3		T71	2		T72	1
all_values[7]	auto[0]	auto[0]	auto[0]	13	1		T67	2		T69	1		T73	1
all_values[7]	auto[0]	auto[0]	auto[1]	44	1		T69	1		T70	1		T71	1
all_values[7]	auto[0]	auto[1]	auto[0]	15	1		T67	1		T69	1		T71	1
all_values[7]	auto[0]	auto[1]	auto[1]	35	1		T67	1		T70	2		T72	2
all_values[7]	auto[1]	auto[0]	auto[1]	44	1		T67	2		T70	2		T71	1
all_values[7]	auto[1]	auto[1]	auto[1]	31	1		T67	1		T69	1		T70	2
all_values[8]	auto[0]	auto[0]	auto[0]	15	1		T69	1		T70	1		T71	2
all_values[8]	auto[0]	auto[0]	auto[1]	38	1		T70	3		T72	2		T253	3
all_values[8]	auto[0]	auto[1]	auto[0]	11	1		T69	3		T259	1		T261	1
all_values[8]	auto[0]	auto[1]	auto[1]	39	1		T67	3		T71	1		T72	1
all_values[8]	auto[1]	auto[0]	auto[1]	47	1		T67	1		T70	1		T72	4
all_values[8]	auto[1]	auto[1]	auto[1]	32	1		T67	3		T70	2		T71	1
all_values[9]	auto[0]	auto[0]	auto[0]	26	1		T67	1		T70	1		T73	1
all_values[9]	auto[0]	auto[0]	auto[1]	45	1		T69	1		T70	2		T72	2
all_values[9]	auto[0]	auto[1]	auto[0]	10	1		T71	1		T73	1		T263	1
all_values[9]	auto[0]	auto[1]	auto[1]	39	1		T67	3		T69	1		T70	2
all_values[9]	auto[1]	auto[0]	auto[1]	37	1		T67	1		T69	2		T70	2
all_values[9]	auto[1]	auto[1]	auto[1]	25	1		T67	2		T71	1		T72	1
all_values[10]	auto[0]	auto[0]	auto[0]	17	1		T254	4		T263	1		T261	3
all_values[10]	auto[0]	auto[0]	auto[1]	41	1		T70	3		T73	1		T260	1
all_values[10]	auto[0]	auto[1]	auto[0]	13	1		T71	4		T72	1		T259	1
all_values[10]	auto[0]	auto[1]	auto[1]	39	1		T67	5		T69	2		T70	1
all_values[10]	auto[1]	auto[0]	auto[1]	39	1		T67	1		T69	1		T70	1
all_values[10]	auto[1]	auto[1]	auto[1]	33	1		T67	1		T69	1		T70	2
all_values[11]	auto[0]	auto[0]	auto[0]	28	1		T67	2		T71	1		T253	2
all_values[11]	auto[0]	auto[0]	auto[1]	36	1		T67	1		T71	2		T72	3
all_values[11]	auto[0]	auto[1]	auto[0]	8	1		T254	1		T257	3		T264	1
all_values[11]	auto[0]	auto[1]	auto[1]	31	1		T67	1		T69	2		T70	2
all_values[11]	auto[1]	auto[0]	auto[1]	48	1		T67	1		T69	1		T70	3
all_values[11]	auto[1]	auto[1]	auto[1]	31	1		T67	2		T69	1		T70	2
all_values[12]	auto[0]	auto[0]	auto[0]	15	1		T67	2		T69	1		T73	1
all_values[12]	auto[0]	auto[0]	auto[1]	41	1		T67	2		T70	6		T72	1
all_values[12]	auto[0]	auto[1]	auto[0]	8	1		T260	1		T253	3		T259	1
all_values[12]	auto[0]	auto[1]	auto[1]	42	1		T67	2		T69	1		T71	3
all_values[12]	auto[1]	auto[0]	auto[1]	46	1		T67	1		T70	1		T72	2
all_values[12]	auto[1]	auto[1]	auto[1]	30	1		T69	2		T71	1		T72	1
all_values[13]	auto[0]	auto[0]	auto[0]	16	1		T67	1		T253	1		T263	1
all_values[13]	auto[0]	auto[0]	auto[1]	41	1		T67	1		T70	2		T72	1
all_values[13]	auto[0]	auto[1]	auto[0]	15	1		T67	3		T260	1		T263	1
all_values[13]	auto[0]	auto[1]	auto[1]	36	1		T69	2		T70	1		T71	1
all_values[13]	auto[1]	auto[0]	auto[1]	37	1		T67	2		T69	1		T70	3
all_values[13]	auto[1]	auto[1]	auto[1]	37	1		T69	1		T70	1		T71	3
all_values[14]	auto[0]	auto[0]	auto[0]	27	1		T70	3		T71	1		T73	1
all_values[14]	auto[0]	auto[0]	auto[1]	38	1		T70	2		T71	2		T72	1
all_values[14]	auto[0]	auto[1]	auto[0]	10	1		T70	1		T73	2		T253	1
all_values[14]	auto[0]	auto[1]	auto[1]	35	1		T67	4		T69	1		T72	3
all_values[14]	auto[1]	auto[0]	auto[1]	43	1		T67	2		T69	3		T71	1
all_values[14]	auto[1]	auto[1]	auto[1]	29	1		T67	1		T70	1		T72	3
all_values[15]	auto[0]	auto[0]	auto[0]	15	1		T67	2		T69	1		T70	5
all_values[15]	auto[0]	auto[0]	auto[1]	34	1		T69	1		T71	1		T72	3
all_values[15]	auto[0]	auto[1]	auto[0]	13	1		T67	2		T70	2		T253	3
all_values[15]	auto[0]	auto[1]	auto[1]	38	1		T67	1		T69	1		T72	2
all_values[15]	auto[1]	auto[0]	auto[1]	38	1		T69	1		T71	3		T72	1
all_values[15]	auto[1]	auto[1]	auto[1]	44	1		T67	2		T72	1		T73	2
all_values[16]	auto[0]	auto[0]	auto[0]	23	1		T69	1		T70	1		T253	1
all_values[16]	auto[0]	auto[0]	auto[1]	29	1		T67	2		T69	2		T70	3
all_values[16]	auto[0]	auto[1]	auto[0]	12	1		T70	1		T259	4		T257	3
all_values[16]	auto[0]	auto[1]	auto[1]	41	1		T67	3		T72	1		T73	1
all_values[16]	auto[1]	auto[0]	auto[1]	45	1		T67	1		T69	1		T70	2
all_values[16]	auto[1]	auto[1]	auto[1]	32	1		T67	1		T72	2		T73	4
all_values[17]	auto[0]	auto[0]	auto[0]	22	1		T70	1		T72	1		T259	1
all_values[17]	auto[0]	auto[0]	auto[1]	36	1		T67	1		T69	2		T70	1
all_values[17]	auto[0]	auto[1]	auto[0]	6	1		T70	1		T258	1		T264	2
all_values[17]	auto[0]	auto[1]	auto[1]	42	1		T67	3		T69	1		T70	1
all_values[17]	auto[1]	auto[0]	auto[1]	49	1		T67	2		T69	1		T70	2
all_values[17]	auto[1]	auto[1]	auto[1]	27	1		T67	1		T70	1		T71	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal