Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.91 96.13 87.92 97.19 46.88 93.35 97.36 96.58


Total test records in report: 955
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T831 /workspace/coverage/default/1.usbdev_random_length_out_trans.1252959851 Mar 24 02:40:48 PM PDT 24 Mar 24 02:40:55 PM PDT 24 8363053585 ps
T832 /workspace/coverage/default/10.usbdev_enable.2277332888 Mar 24 02:41:18 PM PDT 24 Mar 24 02:41:26 PM PDT 24 8370726731 ps
T157 /workspace/coverage/default/26.usbdev_smoke.2599709156 Mar 24 02:42:04 PM PDT 24 Mar 24 02:42:13 PM PDT 24 8474666801 ps
T833 /workspace/coverage/default/29.usbdev_out_trans_nak.1782729683 Mar 24 02:42:16 PM PDT 24 Mar 24 02:42:26 PM PDT 24 8368012066 ps
T162 /workspace/coverage/default/46.usbdev_in_stall.1984025067 Mar 24 02:43:00 PM PDT 24 Mar 24 02:43:08 PM PDT 24 8358779490 ps
T834 /workspace/coverage/default/32.usbdev_out_trans_nak.3061773626 Mar 24 02:42:34 PM PDT 24 Mar 24 02:42:42 PM PDT 24 8395188857 ps
T835 /workspace/coverage/default/8.usbdev_setup_trans_ignored.2198325711 Mar 24 02:41:14 PM PDT 24 Mar 24 02:41:21 PM PDT 24 8362850542 ps
T836 /workspace/coverage/default/21.usbdev_fifo_rst.1434970992 Mar 24 02:41:50 PM PDT 24 Mar 24 02:41:52 PM PDT 24 72444078 ps
T837 /workspace/coverage/default/13.usbdev_min_length_out_transaction.1372705725 Mar 24 02:41:27 PM PDT 24 Mar 24 02:41:35 PM PDT 24 8368244900 ps
T838 /workspace/coverage/default/47.usbdev_min_length_out_transaction.4242501950 Mar 24 02:43:06 PM PDT 24 Mar 24 02:43:15 PM PDT 24 8367463887 ps
T839 /workspace/coverage/default/40.usbdev_enable.19822977 Mar 24 02:42:44 PM PDT 24 Mar 24 02:42:52 PM PDT 24 8368251560 ps
T840 /workspace/coverage/default/43.usbdev_setup_trans_ignored.4045237609 Mar 24 02:42:48 PM PDT 24 Mar 24 02:42:56 PM PDT 24 8361619014 ps
T841 /workspace/coverage/default/35.usbdev_random_length_out_trans.1322196320 Mar 24 02:42:27 PM PDT 24 Mar 24 02:42:36 PM PDT 24 8378801867 ps
T842 /workspace/coverage/default/26.usbdev_pkt_received.140516134 Mar 24 02:42:10 PM PDT 24 Mar 24 02:42:18 PM PDT 24 8384917134 ps
T843 /workspace/coverage/default/13.usbdev_pkt_received.2623525050 Mar 24 02:41:29 PM PDT 24 Mar 24 02:41:40 PM PDT 24 8392257869 ps
T844 /workspace/coverage/default/4.usbdev_av_buffer.2342650065 Mar 24 02:40:57 PM PDT 24 Mar 24 02:41:06 PM PDT 24 8373902197 ps
T845 /workspace/coverage/default/46.usbdev_pkt_received.1848535943 Mar 24 02:42:59 PM PDT 24 Mar 24 02:43:07 PM PDT 24 8388384236 ps
T846 /workspace/coverage/default/28.usbdev_smoke.3963073301 Mar 24 02:42:12 PM PDT 24 Mar 24 02:42:20 PM PDT 24 8478059542 ps
T847 /workspace/coverage/default/7.usbdev_out_trans_nak.359204201 Mar 24 02:41:07 PM PDT 24 Mar 24 02:41:14 PM PDT 24 8403921315 ps
T848 /workspace/coverage/default/33.usbdev_enable.2439263352 Mar 24 02:42:25 PM PDT 24 Mar 24 02:42:33 PM PDT 24 8366873848 ps
T849 /workspace/coverage/default/23.usbdev_in_stall.2386337484 Mar 24 02:42:00 PM PDT 24 Mar 24 02:42:08 PM PDT 24 8365308134 ps
T850 /workspace/coverage/default/46.usbdev_enable.2816092664 Mar 24 02:43:01 PM PDT 24 Mar 24 02:43:08 PM PDT 24 8369720442 ps
T851 /workspace/coverage/default/14.usbdev_min_length_out_transaction.1871906744 Mar 24 02:41:33 PM PDT 24 Mar 24 02:41:41 PM PDT 24 8365186899 ps
T852 /workspace/coverage/default/10.usbdev_fifo_rst.3858094364 Mar 24 02:41:18 PM PDT 24 Mar 24 02:41:21 PM PDT 24 202841631 ps
T853 /workspace/coverage/default/28.usbdev_in_stall.1009544306 Mar 24 02:42:17 PM PDT 24 Mar 24 02:42:26 PM PDT 24 8362713700 ps
T854 /workspace/coverage/default/32.usbdev_min_length_out_transaction.2844095846 Mar 24 02:42:20 PM PDT 24 Mar 24 02:42:27 PM PDT 24 8361587356 ps
T855 /workspace/coverage/default/12.usbdev_av_buffer.2254423344 Mar 24 02:41:32 PM PDT 24 Mar 24 02:41:42 PM PDT 24 8370458517 ps
T856 /workspace/coverage/default/12.usbdev_smoke.4096333800 Mar 24 02:41:28 PM PDT 24 Mar 24 02:41:35 PM PDT 24 8476827168 ps
T857 /workspace/coverage/default/37.usbdev_av_buffer.4052781927 Mar 24 02:42:38 PM PDT 24 Mar 24 02:42:48 PM PDT 24 8368582921 ps
T236 /workspace/coverage/default/3.usbdev_av_buffer.3047836175 Mar 24 02:40:56 PM PDT 24 Mar 24 02:41:04 PM PDT 24 8372507425 ps
T858 /workspace/coverage/default/18.usbdev_out_stall.35943297 Mar 24 02:41:48 PM PDT 24 Mar 24 02:41:56 PM PDT 24 8396854820 ps
T859 /workspace/coverage/default/28.usbdev_pkt_received.2115032618 Mar 24 02:42:14 PM PDT 24 Mar 24 02:42:22 PM PDT 24 8393536926 ps
T860 /workspace/coverage/default/39.usbdev_min_length_out_transaction.1039959386 Mar 24 02:42:42 PM PDT 24 Mar 24 02:42:50 PM PDT 24 8364543888 ps
T861 /workspace/coverage/default/4.usbdev_in_trans.2214575356 Mar 24 02:40:56 PM PDT 24 Mar 24 02:41:03 PM PDT 24 8438451777 ps
T862 /workspace/coverage/default/6.usbdev_av_buffer.1333062121 Mar 24 02:41:02 PM PDT 24 Mar 24 02:41:09 PM PDT 24 8365773242 ps
T863 /workspace/coverage/default/35.usbdev_fifo_rst.1252760236 Mar 24 02:42:31 PM PDT 24 Mar 24 02:42:33 PM PDT 24 264035976 ps
T864 /workspace/coverage/default/15.usbdev_setup_trans_ignored.1742854548 Mar 24 02:41:41 PM PDT 24 Mar 24 02:41:49 PM PDT 24 8355348300 ps
T865 /workspace/coverage/default/39.usbdev_max_length_out_transaction.1558481291 Mar 24 02:42:45 PM PDT 24 Mar 24 02:42:54 PM PDT 24 8413518900 ps
T866 /workspace/coverage/default/29.usbdev_enable.2427666346 Mar 24 02:42:19 PM PDT 24 Mar 24 02:42:27 PM PDT 24 8369009372 ps
T867 /workspace/coverage/default/16.usbdev_av_buffer.1722466748 Mar 24 02:41:38 PM PDT 24 Mar 24 02:41:47 PM PDT 24 8373268477 ps
T868 /workspace/coverage/default/3.usbdev_out_stall.4134212579 Mar 24 02:40:57 PM PDT 24 Mar 24 02:41:04 PM PDT 24 8382542904 ps
T869 /workspace/coverage/default/11.usbdev_enable.3435960184 Mar 24 02:41:24 PM PDT 24 Mar 24 02:41:32 PM PDT 24 8371970309 ps
T870 /workspace/coverage/default/46.usbdev_nak_trans.1481517176 Mar 24 02:43:01 PM PDT 24 Mar 24 02:43:12 PM PDT 24 8443531671 ps
T871 /workspace/coverage/default/10.usbdev_out_trans_nak.1075345992 Mar 24 02:41:20 PM PDT 24 Mar 24 02:41:28 PM PDT 24 8376298376 ps
T241 /workspace/coverage/default/3.usbdev_fifo_rst.528598031 Mar 24 02:40:51 PM PDT 24 Mar 24 02:40:52 PM PDT 24 54868373 ps
T872 /workspace/coverage/default/44.usbdev_in_stall.2170529492 Mar 24 02:42:53 PM PDT 24 Mar 24 02:43:01 PM PDT 24 8356531086 ps
T873 /workspace/coverage/default/48.usbdev_enable.1282541573 Mar 24 02:43:07 PM PDT 24 Mar 24 02:43:16 PM PDT 24 8368116234 ps
T874 /workspace/coverage/default/38.usbdev_av_buffer.4112328607 Mar 24 02:42:35 PM PDT 24 Mar 24 02:42:44 PM PDT 24 8366776917 ps
T875 /workspace/coverage/default/36.usbdev_in_stall.1111672410 Mar 24 02:42:45 PM PDT 24 Mar 24 02:42:54 PM PDT 24 8360192268 ps
T876 /workspace/coverage/default/38.usbdev_fifo_rst.3721682841 Mar 24 02:42:41 PM PDT 24 Mar 24 02:42:44 PM PDT 24 137595759 ps
T877 /workspace/coverage/default/42.usbdev_pkt_received.130127459 Mar 24 02:43:10 PM PDT 24 Mar 24 02:43:20 PM PDT 24 8374648913 ps
T878 /workspace/coverage/default/17.usbdev_pkt_sent.1384051916 Mar 24 02:41:54 PM PDT 24 Mar 24 02:42:02 PM PDT 24 8454280388 ps
T879 /workspace/coverage/default/31.usbdev_phy_pins_sense.155475104 Mar 24 02:42:29 PM PDT 24 Mar 24 02:42:30 PM PDT 24 27579603 ps
T239 /workspace/coverage/default/44.usbdev_in_trans.1314435121 Mar 24 02:43:08 PM PDT 24 Mar 24 02:43:17 PM PDT 24 8434341624 ps
T62 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2165520184 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:02 PM PDT 24 59802686 ps
T52 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2888669511 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:03 PM PDT 24 90340650 ps
T67 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3399819821 Mar 24 12:42:55 PM PDT 24 Mar 24 12:42:56 PM PDT 24 21007265 ps
T69 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2643585659 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:17 PM PDT 24 25492518 ps
T66 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2148037338 Mar 24 12:43:14 PM PDT 24 Mar 24 12:43:15 PM PDT 24 30150901 ps
T53 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1569942552 Mar 24 12:43:08 PM PDT 24 Mar 24 12:43:09 PM PDT 24 37155056 ps
T54 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3576553614 Mar 24 12:43:10 PM PDT 24 Mar 24 12:43:13 PM PDT 24 115699671 ps
T70 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4167434210 Mar 24 12:43:08 PM PDT 24 Mar 24 12:43:09 PM PDT 24 31368659 ps
T63 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2463028877 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:01 PM PDT 24 63322913 ps
T68 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3634955631 Mar 24 12:43:14 PM PDT 24 Mar 24 12:43:16 PM PDT 24 37827188 ps
T60 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4191175049 Mar 24 12:43:09 PM PDT 24 Mar 24 12:43:13 PM PDT 24 151207666 ps
T61 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1946565403 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:04 PM PDT 24 111848044 ps
T80 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4055348644 Mar 24 12:43:10 PM PDT 24 Mar 24 12:43:12 PM PDT 24 120026685 ps
T192 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3575357549 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:24 PM PDT 24 132555820 ps
T193 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3373598786 Mar 24 12:43:08 PM PDT 24 Mar 24 12:43:11 PM PDT 24 95551085 ps
T81 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1738839071 Mar 24 12:42:53 PM PDT 24 Mar 24 12:42:54 PM PDT 24 22922373 ps
T82 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2915232004 Mar 24 12:43:11 PM PDT 24 Mar 24 12:43:13 PM PDT 24 91002140 ps
T198 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3208795394 Mar 24 12:43:08 PM PDT 24 Mar 24 12:43:15 PM PDT 24 273394095 ps
T880 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2940876630 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:17 PM PDT 24 470691175 ps
T210 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1257663107 Mar 24 12:42:56 PM PDT 24 Mar 24 12:42:58 PM PDT 24 56536128 ps
T211 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.682360367 Mar 24 12:43:14 PM PDT 24 Mar 24 12:43:15 PM PDT 24 34871707 ps
T194 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.669717216 Mar 24 12:43:13 PM PDT 24 Mar 24 12:43:17 PM PDT 24 217847957 ps
T71 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1227165144 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:03 PM PDT 24 25197482 ps
T57 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.350597779 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:13 PM PDT 24 50931553 ps
T199 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3316352003 Mar 24 12:42:55 PM PDT 24 Mar 24 12:42:56 PM PDT 24 35943285 ps
T212 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.7150949 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:13 PM PDT 24 56314333 ps
T72 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.679543212 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:16 PM PDT 24 23571712 ps
T195 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.859566053 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:02 PM PDT 24 84752674 ps
T196 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1457132150 Mar 24 12:42:49 PM PDT 24 Mar 24 12:42:52 PM PDT 24 81652091 ps
T213 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2825887710 Mar 24 12:43:05 PM PDT 24 Mar 24 12:43:06 PM PDT 24 68233752 ps
T246 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.530188073 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:07 PM PDT 24 266130147 ps
T73 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4064697752 Mar 24 12:43:06 PM PDT 24 Mar 24 12:43:06 PM PDT 24 24302055 ps
T200 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3514437726 Mar 24 12:42:51 PM PDT 24 Mar 24 12:42:53 PM PDT 24 38305779 ps
T197 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3862660023 Mar 24 12:43:13 PM PDT 24 Mar 24 12:43:17 PM PDT 24 424327494 ps
T242 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.886364960 Mar 24 12:43:04 PM PDT 24 Mar 24 12:43:06 PM PDT 24 67485582 ps
T245 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2569502675 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:04 PM PDT 24 319117308 ps
T243 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2703885492 Mar 24 12:43:10 PM PDT 24 Mar 24 12:43:12 PM PDT 24 83279074 ps
T201 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2064673649 Mar 24 12:43:09 PM PDT 24 Mar 24 12:43:10 PM PDT 24 27596403 ps
T881 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.420873 Mar 24 12:43:14 PM PDT 24 Mar 24 12:43:16 PM PDT 24 44275798 ps
T202 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3621283123 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:16 PM PDT 24 65609042 ps
T247 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1361145073 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:20 PM PDT 24 338821362 ps
T244 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2605471500 Mar 24 12:43:27 PM PDT 24 Mar 24 12:43:29 PM PDT 24 124989880 ps
T882 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1425352834 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:00 PM PDT 24 88673629 ps
T260 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.287490929 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:00 PM PDT 24 24355229 ps
T253 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3541534580 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:16 PM PDT 24 27346526 ps
T883 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.480148557 Mar 24 12:43:18 PM PDT 24 Mar 24 12:43:19 PM PDT 24 71842496 ps
T64 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1216958765 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:01 PM PDT 24 33991768 ps
T884 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1240924830 Mar 24 12:43:05 PM PDT 24 Mar 24 12:43:07 PM PDT 24 55181487 ps
T885 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1118931989 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:06 PM PDT 24 79178053 ps
T265 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2625169751 Mar 24 12:43:05 PM PDT 24 Mar 24 12:43:09 PM PDT 24 449590668 ps
T248 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3407265047 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:18 PM PDT 24 45642475 ps
T259 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.529857473 Mar 24 12:43:21 PM PDT 24 Mar 24 12:43:23 PM PDT 24 24883849 ps
T266 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.43548648 Mar 24 12:42:48 PM PDT 24 Mar 24 12:42:52 PM PDT 24 203453706 ps
T249 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.137830647 Mar 24 12:43:14 PM PDT 24 Mar 24 12:43:15 PM PDT 24 76853307 ps
T886 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.108014155 Mar 24 12:43:05 PM PDT 24 Mar 24 12:43:07 PM PDT 24 68269782 ps
T254 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.276541289 Mar 24 12:42:58 PM PDT 24 Mar 24 12:42:59 PM PDT 24 26101528 ps
T203 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3421533102 Mar 24 12:43:04 PM PDT 24 Mar 24 12:43:05 PM PDT 24 51340596 ps
T263 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3361287445 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:12 PM PDT 24 19685984 ps
T256 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3515650351 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:16 PM PDT 24 28575662 ps
T255 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4094464151 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:02 PM PDT 24 30434624 ps
T250 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1981231509 Mar 24 12:43:08 PM PDT 24 Mar 24 12:43:11 PM PDT 24 300358357 ps
T251 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.748165388 Mar 24 12:43:19 PM PDT 24 Mar 24 12:43:21 PM PDT 24 143749654 ps
T252 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3962820232 Mar 24 12:43:07 PM PDT 24 Mar 24 12:43:08 PM PDT 24 143173365 ps
T887 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.611018132 Mar 24 12:43:09 PM PDT 24 Mar 24 12:43:13 PM PDT 24 285860599 ps
T888 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2859710971 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:03 PM PDT 24 205908518 ps
T204 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.961207344 Mar 24 12:43:04 PM PDT 24 Mar 24 12:43:06 PM PDT 24 69774064 ps
T258 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1813158740 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:17 PM PDT 24 25016724 ps
T889 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1324282288 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:13 PM PDT 24 78165219 ps
T890 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.38099315 Mar 24 12:43:05 PM PDT 24 Mar 24 12:43:06 PM PDT 24 52837944 ps
T257 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3591512243 Mar 24 12:43:13 PM PDT 24 Mar 24 12:43:13 PM PDT 24 31214056 ps
T891 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1372528014 Mar 24 12:43:19 PM PDT 24 Mar 24 12:43:23 PM PDT 24 259215284 ps
T205 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3201036000 Mar 24 12:42:48 PM PDT 24 Mar 24 12:42:54 PM PDT 24 282200102 ps
T206 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2956475160 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:18 PM PDT 24 30136735 ps
T892 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2921478262 Mar 24 12:43:09 PM PDT 24 Mar 24 12:43:11 PM PDT 24 59933349 ps
T893 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.666236194 Mar 24 12:42:55 PM PDT 24 Mar 24 12:42:57 PM PDT 24 148623506 ps
T894 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2413485399 Mar 24 12:43:11 PM PDT 24 Mar 24 12:43:13 PM PDT 24 49739425 ps
T267 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2604445425 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:06 PM PDT 24 229934887 ps
T207 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.304631053 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:14 PM PDT 24 60886978 ps
T895 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1815186820 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:17 PM PDT 24 192274007 ps
T896 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3860500117 Mar 24 12:43:11 PM PDT 24 Mar 24 12:43:15 PM PDT 24 256918193 ps
T208 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3378242998 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:04 PM PDT 24 105543858 ps
T897 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1257006816 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:04 PM PDT 24 152972027 ps
T898 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2463387258 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:17 PM PDT 24 26288856 ps
T899 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.747018861 Mar 24 12:43:11 PM PDT 24 Mar 24 12:43:16 PM PDT 24 469752111 ps
T261 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.819792879 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:13 PM PDT 24 25592451 ps
T900 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3340650877 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:00 PM PDT 24 29533084 ps
T58 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.385766648 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:06 PM PDT 24 60554519 ps
T901 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2658849292 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:17 PM PDT 24 49534735 ps
T902 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3776265166 Mar 24 12:43:10 PM PDT 24 Mar 24 12:43:11 PM PDT 24 36818980 ps
T271 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2878298199 Mar 24 12:43:02 PM PDT 24 Mar 24 12:43:06 PM PDT 24 211254071 ps
T65 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1922886916 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:02 PM PDT 24 35518596 ps
T903 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1840147405 Mar 24 12:43:14 PM PDT 24 Mar 24 12:43:16 PM PDT 24 151371922 ps
T904 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2408862051 Mar 24 12:42:58 PM PDT 24 Mar 24 12:42:59 PM PDT 24 29269027 ps
T209 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1980012957 Mar 24 12:43:06 PM PDT 24 Mar 24 12:43:08 PM PDT 24 39182880 ps
T905 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.380812729 Mar 24 12:42:46 PM PDT 24 Mar 24 12:42:48 PM PDT 24 122180896 ps
T262 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1463209832 Mar 24 12:42:49 PM PDT 24 Mar 24 12:42:50 PM PDT 24 27394592 ps
T59 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3993117165 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:04 PM PDT 24 59485179 ps
T906 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1937254208 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:15 PM PDT 24 255366216 ps
T907 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4082098300 Mar 24 12:43:11 PM PDT 24 Mar 24 12:43:13 PM PDT 24 118229091 ps
T908 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2203039532 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:14 PM PDT 24 156054387 ps
T909 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1240956215 Mar 24 12:43:24 PM PDT 24 Mar 24 12:43:27 PM PDT 24 262252710 ps
T910 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2760711391 Mar 24 12:43:10 PM PDT 24 Mar 24 12:43:12 PM PDT 24 67767215 ps
T269 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2295184763 Mar 24 12:43:20 PM PDT 24 Mar 24 12:43:23 PM PDT 24 123084125 ps
T911 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2442425729 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:13 PM PDT 24 26382325 ps
T912 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2123912825 Mar 24 12:43:14 PM PDT 24 Mar 24 12:43:15 PM PDT 24 54993678 ps
T913 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1101767785 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:16 PM PDT 24 25488979 ps
T914 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2265877281 Mar 24 12:43:17 PM PDT 24 Mar 24 12:43:19 PM PDT 24 75988878 ps
T915 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4065175566 Mar 24 12:43:04 PM PDT 24 Mar 24 12:43:04 PM PDT 24 22573849 ps
T916 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.574461377 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:16 PM PDT 24 24536193 ps
T917 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3579677188 Mar 24 12:43:08 PM PDT 24 Mar 24 12:43:12 PM PDT 24 447860908 ps
T918 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1851681099 Mar 24 12:43:21 PM PDT 24 Mar 24 12:43:25 PM PDT 24 300736556 ps
T264 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2316383008 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:03 PM PDT 24 28005679 ps
T919 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1120895660 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:01 PM PDT 24 62826965 ps
T920 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1158377972 Mar 24 12:42:49 PM PDT 24 Mar 24 12:42:50 PM PDT 24 24400161 ps
T921 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1022218007 Mar 24 12:43:06 PM PDT 24 Mar 24 12:43:09 PM PDT 24 297066406 ps
T922 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2138990273 Mar 24 12:43:06 PM PDT 24 Mar 24 12:43:07 PM PDT 24 18013402 ps
T923 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2200465625 Mar 24 12:43:17 PM PDT 24 Mar 24 12:43:17 PM PDT 24 19479387 ps
T924 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.731465909 Mar 24 12:43:18 PM PDT 24 Mar 24 12:43:20 PM PDT 24 130548297 ps
T270 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.572980035 Mar 24 12:42:58 PM PDT 24 Mar 24 12:43:00 PM PDT 24 219805553 ps
T925 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3999108393 Mar 24 12:42:53 PM PDT 24 Mar 24 12:42:53 PM PDT 24 22945817 ps
T926 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.968203418 Mar 24 12:43:07 PM PDT 24 Mar 24 12:43:07 PM PDT 24 41278149 ps
T927 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.203096858 Mar 24 12:42:54 PM PDT 24 Mar 24 12:42:56 PM PDT 24 90378063 ps
T928 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1393309297 Mar 24 12:43:19 PM PDT 24 Mar 24 12:43:20 PM PDT 24 25998147 ps
T268 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2129613170 Mar 24 12:43:04 PM PDT 24 Mar 24 12:43:08 PM PDT 24 243753388 ps
T929 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3273636070 Mar 24 12:43:10 PM PDT 24 Mar 24 12:43:12 PM PDT 24 147756926 ps
T930 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.534539066 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:16 PM PDT 24 52134102 ps
T931 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3466756103 Mar 24 12:43:06 PM PDT 24 Mar 24 12:43:08 PM PDT 24 49605421 ps
T932 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.845191224 Mar 24 12:42:59 PM PDT 24 Mar 24 12:42:59 PM PDT 24 18271482 ps
T933 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4014044027 Mar 24 12:43:05 PM PDT 24 Mar 24 12:43:07 PM PDT 24 100136908 ps
T934 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.40580160 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:17 PM PDT 24 54877045 ps
T935 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.318058791 Mar 24 12:43:15 PM PDT 24 Mar 24 12:43:19 PM PDT 24 228993842 ps
T936 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1012231387 Mar 24 12:43:20 PM PDT 24 Mar 24 12:43:22 PM PDT 24 154391440 ps
T937 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.816748626 Mar 24 12:42:51 PM PDT 24 Mar 24 12:42:55 PM PDT 24 283248875 ps
T938 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4093387149 Mar 24 12:43:07 PM PDT 24 Mar 24 12:43:09 PM PDT 24 112381082 ps
T939 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1253039383 Mar 24 12:43:05 PM PDT 24 Mar 24 12:43:06 PM PDT 24 67116293 ps
T940 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.852422679 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:01 PM PDT 24 58500836 ps
T941 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2771776352 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:01 PM PDT 24 97088996 ps
T942 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2605020581 Mar 24 12:43:11 PM PDT 24 Mar 24 12:43:12 PM PDT 24 29929814 ps
T943 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2498936694 Mar 24 12:43:02 PM PDT 24 Mar 24 12:43:04 PM PDT 24 61529725 ps
T944 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1378933152 Mar 24 12:43:19 PM PDT 24 Mar 24 12:43:21 PM PDT 24 26874616 ps
T945 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1693758455 Mar 24 12:43:02 PM PDT 24 Mar 24 12:43:04 PM PDT 24 91702587 ps
T946 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.311376024 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:49 PM PDT 24 126754831 ps
T947 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3394104196 Mar 24 12:43:09 PM PDT 24 Mar 24 12:43:11 PM PDT 24 56856813 ps
T948 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1315330667 Mar 24 12:42:50 PM PDT 24 Mar 24 12:42:51 PM PDT 24 31732369 ps
T949 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.540227518 Mar 24 12:43:09 PM PDT 24 Mar 24 12:43:10 PM PDT 24 24348332 ps
T950 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.814283213 Mar 24 12:43:11 PM PDT 24 Mar 24 12:43:12 PM PDT 24 56046761 ps
T951 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.985202946 Mar 24 12:43:08 PM PDT 24 Mar 24 12:43:10 PM PDT 24 55437953 ps
T952 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2838556158 Mar 24 12:43:12 PM PDT 24 Mar 24 12:43:15 PM PDT 24 104328998 ps
T953 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2156436327 Mar 24 12:43:06 PM PDT 24 Mar 24 12:43:08 PM PDT 24 58569713 ps
T954 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1215546388 Mar 24 12:43:10 PM PDT 24 Mar 24 12:43:11 PM PDT 24 60837190 ps
T955 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2049539323 Mar 24 12:42:58 PM PDT 24 Mar 24 12:42:59 PM PDT 24 121577872 ps

Test location /workspace/coverage/default/30.usbdev_enable.3557258443
Short name T1
Test name
Test status
Simulation time 8368210225 ps
CPU time 8.89 seconds
Started Mar 24 02:42:24 PM PDT 24
Finished Mar 24 02:42:33 PM PDT 24
Peak memory 203568 kb
Host smart-81e8cb7f-e4e3-4cf7-8b90-73be45570b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35572
58443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3557258443
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4064697752
Short name T73
Test name
Test status
Simulation time 24302055 ps
CPU time 0.65 seconds
Started Mar 24 12:43:06 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203356 kb
Host smart-f1307c51-99aa-4d1f-bdbc-e9b970b3aa1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4064697752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4064697752
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2000410325
Short name T16
Test name
Test status
Simulation time 8475372103 ps
CPU time 8.4 seconds
Started Mar 24 02:41:57 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203592 kb
Host smart-0a6e5a82-e530-4aad-b3c7-cb528220d4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20004
10325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2000410325
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3576553614
Short name T54
Test name
Test status
Simulation time 115699671 ps
CPU time 2.27 seconds
Started Mar 24 12:43:10 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203664 kb
Host smart-e8b502df-2f2d-42d0-9255-0170370944a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3576553614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3576553614
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2971841593
Short name T76
Test name
Test status
Simulation time 65560081 ps
CPU time 1.89 seconds
Started Mar 24 02:42:27 PM PDT 24
Finished Mar 24 02:42:29 PM PDT 24
Peak memory 203620 kb
Host smart-7a124c1c-17db-41a1-af99-60711da865e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29718
41593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2971841593
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1574679817
Short name T4
Test name
Test status
Simulation time 8358647172 ps
CPU time 8.97 seconds
Started Mar 24 02:41:11 PM PDT 24
Finished Mar 24 02:41:21 PM PDT 24
Peak memory 203472 kb
Host smart-2baf4b9e-f82e-42d0-bf0b-3f0a92cda1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15746
79817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1574679817
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1525042142
Short name T12
Test name
Test status
Simulation time 106644126 ps
CPU time 0.88 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:40:53 PM PDT 24
Peak memory 219492 kb
Host smart-d45a22ac-a5d0-4a76-9dd4-3b126a0a2050
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1525042142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1525042142
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.332415771
Short name T18
Test name
Test status
Simulation time 8426130943 ps
CPU time 7.19 seconds
Started Mar 24 02:42:01 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 203568 kb
Host smart-babae8bf-8d13-41d7-bf22-602b4157a1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33241
5771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.332415771
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3541534580
Short name T253
Test name
Test status
Simulation time 27346526 ps
CPU time 0.65 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203344 kb
Host smart-6c3d3fd2-608e-497e-b6c8-a554b5a082f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3541534580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3541534580
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2888669511
Short name T52
Test name
Test status
Simulation time 90340650 ps
CPU time 2.97 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 203624 kb
Host smart-d67a30bc-b19d-4270-9fc2-fc6a8efc352a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2888669511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2888669511
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.300781624
Short name T32
Test name
Test status
Simulation time 22999374 ps
CPU time 0.63 seconds
Started Mar 24 02:41:51 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203440 kb
Host smart-75a725f4-b1b7-421f-acbc-feb8344a68d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30078
1624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.300781624
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1913534576
Short name T235
Test name
Test status
Simulation time 8380000575 ps
CPU time 8.86 seconds
Started Mar 24 02:40:57 PM PDT 24
Finished Mar 24 02:41:05 PM PDT 24
Peak memory 203568 kb
Host smart-809fde97-98a6-4f35-b0f9-0f5b7a2b7e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19135
34576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1913534576
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.1854016446
Short name T115
Test name
Test status
Simulation time 8432404876 ps
CPU time 7.76 seconds
Started Mar 24 02:41:47 PM PDT 24
Finished Mar 24 02:41:55 PM PDT 24
Peak memory 203564 kb
Host smart-ff8a5944-6778-41a1-9588-e3270d33dedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18540
16446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1854016446
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3316352003
Short name T199
Test name
Test status
Simulation time 35943285 ps
CPU time 0.75 seconds
Started Mar 24 12:42:55 PM PDT 24
Finished Mar 24 12:42:56 PM PDT 24
Peak memory 203340 kb
Host smart-ec436090-498e-4f94-a618-315458788069
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316352003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3316352003
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2382888319
Short name T78
Test name
Test status
Simulation time 120501164 ps
CPU time 1.26 seconds
Started Mar 24 02:41:56 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203588 kb
Host smart-a0372696-5e34-4280-bd56-7064a78baf5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23828
88319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2382888319
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.276541289
Short name T254
Test name
Test status
Simulation time 26101528 ps
CPU time 0.64 seconds
Started Mar 24 12:42:58 PM PDT 24
Finished Mar 24 12:42:59 PM PDT 24
Peak memory 203336 kb
Host smart-d56e924f-0380-4937-a860-951d0e665f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=276541289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.276541289
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2604445425
Short name T267
Test name
Test status
Simulation time 229934887 ps
CPU time 3.89 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203600 kb
Host smart-7b20f6d1-f609-4c09-b469-449d224f4a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2604445425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2604445425
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1813158740
Short name T258
Test name
Test status
Simulation time 25016724 ps
CPU time 0.66 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203184 kb
Host smart-492f9ee8-247c-4f3c-82ed-6df058e02bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1813158740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1813158740
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/default/33.usbdev_smoke.4242783581
Short name T126
Test name
Test status
Simulation time 8480367112 ps
CPU time 8.25 seconds
Started Mar 24 02:42:26 PM PDT 24
Finished Mar 24 02:42:35 PM PDT 24
Peak memory 203620 kb
Host smart-eea98041-efbc-4508-b4e9-5f1a7b214588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
83581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.4242783581
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1626743139
Short name T28
Test name
Test status
Simulation time 8406867215 ps
CPU time 8.85 seconds
Started Mar 24 02:42:34 PM PDT 24
Finished Mar 24 02:42:44 PM PDT 24
Peak memory 203484 kb
Host smart-5cec71fb-1c56-4fa8-b0bc-da6f85fc10f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16267
43139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1626743139
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3789633206
Short name T122
Test name
Test status
Simulation time 8476482740 ps
CPU time 7.42 seconds
Started Mar 24 02:41:52 PM PDT 24
Finished Mar 24 02:41:59 PM PDT 24
Peak memory 203580 kb
Host smart-d764302c-6747-41bf-a971-ce102393e6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37896
33206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3789633206
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3822101014
Short name T44
Test name
Test status
Simulation time 8477710412 ps
CPU time 8.79 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203608 kb
Host smart-24d00e43-deda-48f6-8e55-d4bf90e70c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38221
01014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3822101014
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_smoke.139669899
Short name T79
Test name
Test status
Simulation time 8472503457 ps
CPU time 7.95 seconds
Started Mar 24 02:42:36 PM PDT 24
Finished Mar 24 02:42:46 PM PDT 24
Peak memory 203576 kb
Host smart-e029db34-90e8-4659-9c7c-31fa8a381532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13966
9899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.139669899
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_smoke.681370461
Short name T496
Test name
Test status
Simulation time 8472762111 ps
CPU time 8.21 seconds
Started Mar 24 02:40:36 PM PDT 24
Finished Mar 24 02:40:44 PM PDT 24
Peak memory 203784 kb
Host smart-8f0f90d1-1cfc-43ee-b977-bdd79bff2e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68137
0461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.681370461
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_smoke.4184825064
Short name T784
Test name
Test status
Simulation time 8482382861 ps
CPU time 7.98 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:55 PM PDT 24
Peak memory 203584 kb
Host smart-d3139316-5fbb-4b03-bf43-6c4e98f62d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41848
25064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.4184825064
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1909029902
Short name T154
Test name
Test status
Simulation time 8475217922 ps
CPU time 8.84 seconds
Started Mar 24 02:41:47 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203568 kb
Host smart-78b4e8e8-717d-4f97-9d37-34374ae258dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19090
29902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1909029902
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3522382664
Short name T113
Test name
Test status
Simulation time 8388737460 ps
CPU time 8.61 seconds
Started Mar 24 02:40:53 PM PDT 24
Finished Mar 24 02:41:02 PM PDT 24
Peak memory 203568 kb
Host smart-45a1dfcf-81d1-4884-8ca1-6c882e7318ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35223
82664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3522382664
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.350597779
Short name T57
Test name
Test status
Simulation time 50931553 ps
CPU time 0.84 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203336 kb
Host smart-7998c95a-f23a-42cf-9623-706663e347b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350597779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.350597779
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4167434210
Short name T70
Test name
Test status
Simulation time 31368659 ps
CPU time 0.66 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 203276 kb
Host smart-2bfee140-e1f0-49d2-a79b-4239afc4ee2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4167434210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4167434210
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1922886916
Short name T65
Test name
Test status
Simulation time 35518596 ps
CPU time 0.85 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:02 PM PDT 24
Peak memory 203304 kb
Host smart-3df17faa-0fad-4b55-96da-4701e7605b53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922886916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1922886916
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1981231509
Short name T250
Test name
Test status
Simulation time 300358357 ps
CPU time 2.61 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 203604 kb
Host smart-61cd30b9-7a48-4da5-b911-30f08234acb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1981231509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1981231509
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.845191224
Short name T932
Test name
Test status
Simulation time 18271482 ps
CPU time 0.61 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:42:59 PM PDT 24
Peak memory 203192 kb
Host smart-f34d37e8-70cc-4915-aaeb-4369df37335a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=845191224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.845191224
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2295184763
Short name T269
Test name
Test status
Simulation time 123084125 ps
CPU time 2.36 seconds
Started Mar 24 12:43:20 PM PDT 24
Finished Mar 24 12:43:23 PM PDT 24
Peak memory 203560 kb
Host smart-3cb13ca3-0250-499e-ad5a-45adcd5e3eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2295184763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2295184763
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/1.usbdev_enable.3348258208
Short name T36
Test name
Test status
Simulation time 8370262628 ps
CPU time 8.41 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 203552 kb
Host smart-b5999dcb-350e-44c2-b9e2-3cf90cd6e147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33482
58208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3348258208
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_smoke.4096333800
Short name T856
Test name
Test status
Simulation time 8476827168 ps
CPU time 7.14 seconds
Started Mar 24 02:41:28 PM PDT 24
Finished Mar 24 02:41:35 PM PDT 24
Peak memory 203520 kb
Host smart-44bb45c9-9078-42d5-800a-993450dc9978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40963
33800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.4096333800
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3208795394
Short name T198
Test name
Test status
Simulation time 273394095 ps
CPU time 6.81 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 203476 kb
Host smart-984e7874-49cc-47e8-9b1e-7e8375c2450f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208795394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3208795394
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3759730601
Short name T234
Test name
Test status
Simulation time 55574951 ps
CPU time 1.59 seconds
Started Mar 24 02:42:19 PM PDT 24
Finished Mar 24 02:42:21 PM PDT 24
Peak memory 203664 kb
Host smart-db22e7a8-5b87-4081-908c-545feea84b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37597
30601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3759730601
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1372528014
Short name T891
Test name
Test status
Simulation time 259215284 ps
CPU time 2.93 seconds
Started Mar 24 12:43:19 PM PDT 24
Finished Mar 24 12:43:23 PM PDT 24
Peak memory 203556 kb
Host smart-09054756-f44f-4e1b-9072-aa87ada82abd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1372528014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1372528014
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2320549233
Short name T214
Test name
Test status
Simulation time 28327211 ps
CPU time 0.65 seconds
Started Mar 24 02:41:24 PM PDT 24
Finished Mar 24 02:41:25 PM PDT 24
Peak memory 203492 kb
Host smart-bb233e03-361f-4315-9d6e-40202f332574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
49233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2320549233
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_smoke.488546147
Short name T624
Test name
Test status
Simulation time 8476641625 ps
CPU time 9.2 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:32 PM PDT 24
Peak memory 203540 kb
Host smart-d85fedab-68f1-4bb1-b3fc-e89a63df9ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48854
6147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.488546147
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.622806942
Short name T230
Test name
Test status
Simulation time 8356639637 ps
CPU time 9.33 seconds
Started Mar 24 02:41:29 PM PDT 24
Finished Mar 24 02:41:39 PM PDT 24
Peak memory 203548 kb
Host smart-03656434-88e7-4678-b62d-fd8a95fa5150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62280
6942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.622806942
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2130055713
Short name T145
Test name
Test status
Simulation time 8473496693 ps
CPU time 8.44 seconds
Started Mar 24 02:41:28 PM PDT 24
Finished Mar 24 02:41:37 PM PDT 24
Peak memory 203604 kb
Host smart-b1d7f733-bded-4618-bc6a-9a303e0f8cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21300
55713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2130055713
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.4230595897
Short name T6
Test name
Test status
Simulation time 8408793222 ps
CPU time 7.5 seconds
Started Mar 24 02:41:38 PM PDT 24
Finished Mar 24 02:41:45 PM PDT 24
Peak memory 203588 kb
Host smart-ce6097e3-81c3-4084-8ef2-573da821fcdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42305
95897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.4230595897
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3022551438
Short name T140
Test name
Test status
Simulation time 8475122785 ps
CPU time 8.27 seconds
Started Mar 24 02:41:57 PM PDT 24
Finished Mar 24 02:42:05 PM PDT 24
Peak memory 203548 kb
Host smart-63295494-1e9c-4900-a5db-e334f9964bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30225
51438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3022551438
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3201036000
Short name T205
Test name
Test status
Simulation time 282200102 ps
CPU time 6.76 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 203456 kb
Host smart-1d5f9c5c-b4f5-48fc-915a-7d9fcc25f44a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201036000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3201036000
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1298526803
Short name T767
Test name
Test status
Simulation time 8361370644 ps
CPU time 8.51 seconds
Started Mar 24 02:40:42 PM PDT 24
Finished Mar 24 02:40:51 PM PDT 24
Peak memory 203496 kb
Host smart-180610fb-18d2-4877-bbf4-0f251b0de54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12985
26803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1298526803
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1200095655
Short name T728
Test name
Test status
Simulation time 8406461895 ps
CPU time 8.52 seconds
Started Mar 24 02:40:39 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 203552 kb
Host smart-5a83a64e-4e7f-4280-8805-4055706dd58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12000
95655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1200095655
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1911053827
Short name T2
Test name
Test status
Simulation time 8356376137 ps
CPU time 7.25 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:55 PM PDT 24
Peak memory 203544 kb
Host smart-f5f74d3f-c517-43d3-9fc4-05012d389852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110
53827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1911053827
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2130357086
Short name T725
Test name
Test status
Simulation time 8386022381 ps
CPU time 8.4 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:41:01 PM PDT 24
Peak memory 203552 kb
Host smart-bcec77d1-ca32-4757-a181-02897e4389ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21303
57086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2130357086
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3422657851
Short name T101
Test name
Test status
Simulation time 8404308353 ps
CPU time 8.73 seconds
Started Mar 24 02:41:20 PM PDT 24
Finished Mar 24 02:41:29 PM PDT 24
Peak memory 203556 kb
Host smart-71d7e19f-0541-4d36-b1e1-8da543231618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34226
57851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3422657851
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2654028641
Short name T164
Test name
Test status
Simulation time 8355997836 ps
CPU time 7.14 seconds
Started Mar 24 02:41:24 PM PDT 24
Finished Mar 24 02:41:31 PM PDT 24
Peak memory 203560 kb
Host smart-a2512d6b-a83a-4510-92e1-d9dfbb69404a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26540
28641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2654028641
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2052962421
Short name T825
Test name
Test status
Simulation time 8402019638 ps
CPU time 9.71 seconds
Started Mar 24 02:41:25 PM PDT 24
Finished Mar 24 02:41:35 PM PDT 24
Peak memory 203496 kb
Host smart-a8b3dd3c-0836-469d-9bc9-e08a12fec7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20529
62421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2052962421
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3500830627
Short name T669
Test name
Test status
Simulation time 8407919856 ps
CPU time 7.91 seconds
Started Mar 24 02:41:28 PM PDT 24
Finished Mar 24 02:41:37 PM PDT 24
Peak memory 203536 kb
Host smart-03cb15b0-50c5-4af8-b6e2-658341f016ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35008
30627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3500830627
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2839250205
Short name T176
Test name
Test status
Simulation time 8359520986 ps
CPU time 8.29 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:44 PM PDT 24
Peak memory 203496 kb
Host smart-416bad12-3d26-47a8-aee4-a5a127f2e75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28392
50205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2839250205
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.396228958
Short name T100
Test name
Test status
Simulation time 8386208360 ps
CPU time 7.78 seconds
Started Mar 24 02:41:36 PM PDT 24
Finished Mar 24 02:41:44 PM PDT 24
Peak memory 203552 kb
Host smart-e8cb19ad-0de6-4af4-af04-3af43fc41abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39622
8958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.396228958
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2806900521
Short name T104
Test name
Test status
Simulation time 8397135555 ps
CPU time 7.52 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203520 kb
Host smart-b99b2349-9a63-42fc-8522-c99a823aa449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
00521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2806900521
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.597334617
Short name T161
Test name
Test status
Simulation time 8362331085 ps
CPU time 7.22 seconds
Started Mar 24 02:41:48 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203532 kb
Host smart-cc26a54d-604c-4bdd-aef7-988674a2fe74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59733
4617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.597334617
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3205063510
Short name T90
Test name
Test status
Simulation time 8440229709 ps
CPU time 7.7 seconds
Started Mar 24 02:41:44 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203568 kb
Host smart-8395d9d6-e2e0-4418-b86c-fac561a7685d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32050
63510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3205063510
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3324218616
Short name T89
Test name
Test status
Simulation time 8432407441 ps
CPU time 7.27 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203536 kb
Host smart-209544e0-b6e5-4f4a-984d-e23ec35f3063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242
18616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3324218616
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1341134898
Short name T688
Test name
Test status
Simulation time 8456672896 ps
CPU time 8.48 seconds
Started Mar 24 02:42:02 PM PDT 24
Finished Mar 24 02:42:10 PM PDT 24
Peak memory 203540 kb
Host smart-fb9c6d50-06e5-48f2-9cea-24b670b5825f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13411
34898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1341134898
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2375717943
Short name T105
Test name
Test status
Simulation time 8414126775 ps
CPU time 6.86 seconds
Started Mar 24 02:42:13 PM PDT 24
Finished Mar 24 02:42:20 PM PDT 24
Peak memory 203556 kb
Host smart-ba612b35-00d6-4db3-a81f-736d2b78b7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23757
17943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2375717943
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1055402365
Short name T191
Test name
Test status
Simulation time 8363523800 ps
CPU time 7.41 seconds
Started Mar 24 02:42:36 PM PDT 24
Finished Mar 24 02:42:45 PM PDT 24
Peak memory 203556 kb
Host smart-3b85b008-b317-4484-b750-912694440852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554
02365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1055402365
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2463028877
Short name T63
Test name
Test status
Simulation time 63322913 ps
CPU time 1.87 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 203508 kb
Host smart-0fa55da9-9894-4fe2-948d-cd197f608f23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463028877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2463028877
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.385766648
Short name T58
Test name
Test status
Simulation time 60554519 ps
CPU time 0.91 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203320 kb
Host smart-5742aafd-08bf-48e0-aa9f-b9227d703cda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385766648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.385766648
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2703885492
Short name T243
Test name
Test status
Simulation time 83279074 ps
CPU time 2.58 seconds
Started Mar 24 12:43:10 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 211780 kb
Host smart-9ce90bde-d25e-4f23-8d51-91ce8d0fe1d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703885492 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2703885492
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2658849292
Short name T901
Test name
Test status
Simulation time 49534735 ps
CPU time 0.95 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203456 kb
Host smart-cf673c11-3ac9-4fb7-88b9-f1829e3b318f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658849292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2658849292
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1980012957
Short name T209
Test name
Test status
Simulation time 39182880 ps
CPU time 1.37 seconds
Started Mar 24 12:43:06 PM PDT 24
Finished Mar 24 12:43:08 PM PDT 24
Peak memory 203532 kb
Host smart-1e23ee19-b2f5-4970-b63d-197902c1e5d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1980012957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1980012957
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.747018861
Short name T899
Test name
Test status
Simulation time 469752111 ps
CPU time 4.39 seconds
Started Mar 24 12:43:11 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203452 kb
Host smart-ae97a831-0da4-4d80-b0a0-f200294d4298
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=747018861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.747018861
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2413485399
Short name T894
Test name
Test status
Simulation time 49739425 ps
CPU time 1.27 seconds
Started Mar 24 12:43:11 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203568 kb
Host smart-2b0e1a5d-6642-4dac-ab86-0240fa385995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413485399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c
sr_outstanding.2413485399
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2771776352
Short name T941
Test name
Test status
Simulation time 97088996 ps
CPU time 1.45 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 203576 kb
Host smart-7d387374-f504-4f92-ae7c-0c425ded66f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2771776352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2771776352
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.572980035
Short name T270
Test name
Test status
Simulation time 219805553 ps
CPU time 2.5 seconds
Started Mar 24 12:42:58 PM PDT 24
Finished Mar 24 12:43:00 PM PDT 24
Peak memory 203548 kb
Host smart-e4ab421a-1187-4d70-80b0-f66bc962c0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=572980035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.572980035
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3378242998
Short name T208
Test name
Test status
Simulation time 105543858 ps
CPU time 3.17 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 203496 kb
Host smart-d4d15bae-d8ab-4a45-8e03-9d12a38677c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378242998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3378242998
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4191175049
Short name T60
Test name
Test status
Simulation time 151207666 ps
CPU time 3.75 seconds
Started Mar 24 12:43:09 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203468 kb
Host smart-6a09f1c0-4ebd-41fa-a83d-3102633abf1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191175049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.4191175049
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1457132150
Short name T196
Test name
Test status
Simulation time 81652091 ps
CPU time 2.47 seconds
Started Mar 24 12:42:49 PM PDT 24
Finished Mar 24 12:42:52 PM PDT 24
Peak memory 211700 kb
Host smart-e3785a78-2556-4110-ae4b-4ffcfd8a456a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457132150 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.1457132150
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2165520184
Short name T62
Test name
Test status
Simulation time 59802686 ps
CPU time 1.03 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:02 PM PDT 24
Peak memory 203476 kb
Host smart-d12d9631-a723-40e8-8f1f-acf51a49605f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165520184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2165520184
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1227165144
Short name T71
Test name
Test status
Simulation time 25197482 ps
CPU time 0.69 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 203600 kb
Host smart-a544db9c-2c43-48b0-b29c-11e4aa5dc04b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1227165144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1227165144
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2760711391
Short name T910
Test name
Test status
Simulation time 67767215 ps
CPU time 2.01 seconds
Started Mar 24 12:43:10 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 203512 kb
Host smart-00bd53fd-5261-4b8e-9fb0-7787c4ab469c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2760711391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2760711391
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.311376024
Short name T946
Test name
Test status
Simulation time 126754831 ps
CPU time 1.48 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:49 PM PDT 24
Peak memory 203728 kb
Host smart-63b21d47-a95e-4fea-aa7f-0761ffb036d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311376024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_cs
r_outstanding.311376024
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2921478262
Short name T892
Test name
Test status
Simulation time 59933349 ps
CPU time 1.73 seconds
Started Mar 24 12:43:09 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 203596 kb
Host smart-b940e0d6-45ee-41a7-96ae-ecc4b5af7c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2921478262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2921478262
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3862660023
Short name T197
Test name
Test status
Simulation time 424327494 ps
CPU time 4.18 seconds
Started Mar 24 12:43:13 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203552 kb
Host smart-ee580260-49c2-4dac-9e8c-38ab2bd14982
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3862660023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3862660023
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.480148557
Short name T883
Test name
Test status
Simulation time 71842496 ps
CPU time 1.26 seconds
Started Mar 24 12:43:18 PM PDT 24
Finished Mar 24 12:43:19 PM PDT 24
Peak memory 211832 kb
Host smart-e7f45e01-e89a-45a2-9c19-efe4f9331450
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480148557 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.480148557
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.38099315
Short name T890
Test name
Test status
Simulation time 52837944 ps
CPU time 0.93 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203508 kb
Host smart-4907a72d-3328-49ff-b8ee-d64a0aa4e20b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38099315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.38099315
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2316383008
Short name T264
Test name
Test status
Simulation time 28005679 ps
CPU time 0.66 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 203276 kb
Host smart-045fdfbd-d084-4744-b195-0a8a7ca8c9a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2316383008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2316383008
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3621283123
Short name T202
Test name
Test status
Simulation time 65609042 ps
CPU time 1.09 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203844 kb
Host smart-ed8705df-5f21-4822-8888-4f2b14726324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621283123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.3621283123
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1118931989
Short name T885
Test name
Test status
Simulation time 79178053 ps
CPU time 2.46 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203684 kb
Host smart-b8033e87-47a7-4cfb-b52e-60960b7be4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118931989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1118931989
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3579677188
Short name T917
Test name
Test status
Simulation time 447860908 ps
CPU time 4.39 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 203500 kb
Host smart-bfe368bf-269c-45c6-a180-1d47fd4f4545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3579677188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3579677188
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.420873
Short name T881
Test name
Test status
Simulation time 44275798 ps
CPU time 1.43 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 211740 kb
Host smart-916ae56b-54d4-4ad4-80b3-e7fe9c2b19fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420873 -assert nopostproc +UVM_TESTNAME=usbdev_
base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.420873
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.852422679
Short name T940
Test name
Test status
Simulation time 58500836 ps
CPU time 0.88 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 203472 kb
Host smart-68150e28-8416-4c3d-b04d-6b5d35a04b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852422679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.852422679
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4094464151
Short name T255
Test name
Test status
Simulation time 30434624 ps
CPU time 0.66 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:02 PM PDT 24
Peak memory 203264 kb
Host smart-01b893d9-44a5-4042-85a6-66ac8e7b3432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4094464151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4094464151
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3962820232
Short name T252
Test name
Test status
Simulation time 143173365 ps
CPU time 1.52 seconds
Started Mar 24 12:43:07 PM PDT 24
Finished Mar 24 12:43:08 PM PDT 24
Peak memory 203472 kb
Host smart-f06511ba-eec8-4dab-87cf-45ab5463a2fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962820232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.3962820232
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1937254208
Short name T906
Test name
Test status
Simulation time 255366216 ps
CPU time 2.85 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 203712 kb
Host smart-2218ba97-f729-44cb-b0d9-933ce1367ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1937254208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1937254208
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4082098300
Short name T907
Test name
Test status
Simulation time 118229091 ps
CPU time 2.25 seconds
Started Mar 24 12:43:11 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203524 kb
Host smart-604a3ca2-edc9-47e0-bc5d-79628dcd4283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4082098300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4082098300
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3466756103
Short name T931
Test name
Test status
Simulation time 49605421 ps
CPU time 1.36 seconds
Started Mar 24 12:43:06 PM PDT 24
Finished Mar 24 12:43:08 PM PDT 24
Peak memory 211792 kb
Host smart-702a8184-20a9-4f4c-908d-f5625f5a61b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466756103 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.3466756103
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3340650877
Short name T900
Test name
Test status
Simulation time 29533084 ps
CPU time 0.78 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:00 PM PDT 24
Peak memory 203292 kb
Host smart-a4ef3d2a-e46e-4bbf-b926-27ad00147896
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340650877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3340650877
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1215546388
Short name T954
Test name
Test status
Simulation time 60837190 ps
CPU time 1.02 seconds
Started Mar 24 12:43:10 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 203576 kb
Host smart-6b3d5803-657a-46b7-8d60-574a1675d3d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215546388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.1215546388
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1815186820
Short name T895
Test name
Test status
Simulation time 192274007 ps
CPU time 2.55 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203612 kb
Host smart-d9dfc096-cd3c-430a-a997-2e19565d5b91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1815186820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1815186820
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.534539066
Short name T930
Test name
Test status
Simulation time 52134102 ps
CPU time 1.64 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 214148 kb
Host smart-4703be34-b12b-4b61-8892-5107af88954e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534539066 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.534539066
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2148037338
Short name T66
Test name
Test status
Simulation time 30150901 ps
CPU time 0.78 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 203264 kb
Host smart-04b322e4-cba7-4ab1-a760-f7909f00a6d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148037338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2148037338
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.287490929
Short name T260
Test name
Test status
Simulation time 24355229 ps
CPU time 0.68 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:00 PM PDT 24
Peak memory 203252 kb
Host smart-f5d5f5c2-1e75-4a4a-b701-0d7c70d77c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=287490929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.287490929
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3273636070
Short name T929
Test name
Test status
Simulation time 147756926 ps
CPU time 1.5 seconds
Started Mar 24 12:43:10 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 203588 kb
Host smart-718886cd-824e-43d2-857d-2aaf5d7e2952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273636070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.3273636070
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.666236194
Short name T893
Test name
Test status
Simulation time 148623506 ps
CPU time 1.78 seconds
Started Mar 24 12:42:55 PM PDT 24
Finished Mar 24 12:42:57 PM PDT 24
Peak memory 203472 kb
Host smart-d1333a7b-7c06-42da-b336-c48bda41788a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=666236194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.666236194
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.318058791
Short name T935
Test name
Test status
Simulation time 228993842 ps
CPU time 3.91 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:19 PM PDT 24
Peak memory 203536 kb
Host smart-b2a71847-a896-42b2-95d7-033c0f8fb22d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=318058791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.318058791
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.859566053
Short name T195
Test name
Test status
Simulation time 84752674 ps
CPU time 1.23 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:02 PM PDT 24
Peak memory 211768 kb
Host smart-af4e951c-7447-42a7-b8aa-34fb793347da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859566053 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.859566053
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.961207344
Short name T204
Test name
Test status
Simulation time 69774064 ps
CPU time 1.08 seconds
Started Mar 24 12:43:04 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203440 kb
Host smart-61b056b1-0b0c-4bf5-a4bd-1d2078b92bbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961207344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.961207344
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3515650351
Short name T256
Test name
Test status
Simulation time 28575662 ps
CPU time 0.63 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203276 kb
Host smart-19967111-e81b-43b0-80e1-ae60ba467ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3515650351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3515650351
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1324282288
Short name T889
Test name
Test status
Simulation time 78165219 ps
CPU time 1.03 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203528 kb
Host smart-7d16213c-7f81-4aae-94e0-b161f2cb2c45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324282288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.1324282288
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1851681099
Short name T918
Test name
Test status
Simulation time 300736556 ps
CPU time 3.12 seconds
Started Mar 24 12:43:21 PM PDT 24
Finished Mar 24 12:43:25 PM PDT 24
Peak memory 203640 kb
Host smart-945608ff-8da3-47aa-88e1-b8441b155a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1851681099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1851681099
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1240956215
Short name T909
Test name
Test status
Simulation time 262252710 ps
CPU time 2.71 seconds
Started Mar 24 12:43:24 PM PDT 24
Finished Mar 24 12:43:27 PM PDT 24
Peak memory 203628 kb
Host smart-bb696c3c-9c18-46a2-9714-37ee6e159227
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1240956215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1240956215
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1012231387
Short name T936
Test name
Test status
Simulation time 154391440 ps
CPU time 2.02 seconds
Started Mar 24 12:43:20 PM PDT 24
Finished Mar 24 12:43:22 PM PDT 24
Peak memory 211760 kb
Host smart-3ac7370f-f2a5-40fd-a8a2-ebcd1175f4aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012231387 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.1012231387
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3776265166
Short name T902
Test name
Test status
Simulation time 36818980 ps
CPU time 0.94 seconds
Started Mar 24 12:43:10 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 203440 kb
Host smart-d3ee76c8-61eb-4806-8182-392998cca09c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776265166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3776265166
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3634955631
Short name T68
Test name
Test status
Simulation time 37827188 ps
CPU time 1.01 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203592 kb
Host smart-16023916-32b6-4b61-8811-0f833a10f27f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634955631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.3634955631
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2605471500
Short name T244
Test name
Test status
Simulation time 124989880 ps
CPU time 1.68 seconds
Started Mar 24 12:43:27 PM PDT 24
Finished Mar 24 12:43:29 PM PDT 24
Peak memory 203524 kb
Host smart-906cfb5a-5c13-4917-930d-2de2eecbe369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2605471500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2605471500
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2915232004
Short name T82
Test name
Test status
Simulation time 91002140 ps
CPU time 1.38 seconds
Started Mar 24 12:43:11 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 211880 kb
Host smart-67e0e248-da83-4ead-927e-7d83a08864ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915232004 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2915232004
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.682360367
Short name T211
Test name
Test status
Simulation time 34871707 ps
CPU time 0.78 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 203428 kb
Host smart-f1ba7c81-ebe7-42e7-a2ac-eb45f390837d
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682360367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.682360367
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1393309297
Short name T928
Test name
Test status
Simulation time 25998147 ps
CPU time 0.64 seconds
Started Mar 24 12:43:19 PM PDT 24
Finished Mar 24 12:43:20 PM PDT 24
Peak memory 203260 kb
Host smart-dd6b4f5f-53e1-4e26-83cf-7c948da191ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1393309297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1393309297
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.40580160
Short name T934
Test name
Test status
Simulation time 54877045 ps
CPU time 1.34 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203548 kb
Host smart-01d86ac4-d7e8-4a7d-be32-c008f7588d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40580160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_cs
r_outstanding.40580160
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1569942552
Short name T53
Test name
Test status
Simulation time 37155056 ps
CPU time 1.31 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 203636 kb
Host smart-64ac215e-a6ce-4cb4-8850-8540fc21400c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1569942552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1569942552
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1022218007
Short name T921
Test name
Test status
Simulation time 297066406 ps
CPU time 2.68 seconds
Started Mar 24 12:43:06 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 203600 kb
Host smart-db16ad4b-eea4-4fac-a06f-9b589b1c4c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1022218007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1022218007
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.731465909
Short name T924
Test name
Test status
Simulation time 130548297 ps
CPU time 1.7 seconds
Started Mar 24 12:43:18 PM PDT 24
Finished Mar 24 12:43:20 PM PDT 24
Peak memory 216056 kb
Host smart-4d1f73ee-b435-4d5c-a0da-d18064de21cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731465909 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.731465909
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3407265047
Short name T248
Test name
Test status
Simulation time 45642475 ps
CPU time 0.89 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:18 PM PDT 24
Peak memory 203324 kb
Host smart-1cba80d5-d5d7-4177-91b6-eef3dce2a39d
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407265047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3407265047
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.540227518
Short name T949
Test name
Test status
Simulation time 24348332 ps
CPU time 0.66 seconds
Started Mar 24 12:43:09 PM PDT 24
Finished Mar 24 12:43:10 PM PDT 24
Peak memory 203260 kb
Host smart-3ad83b91-94d3-4c23-9682-c4c77e5d35d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=540227518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.540227518
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2156436327
Short name T953
Test name
Test status
Simulation time 58569713 ps
CPU time 1.42 seconds
Started Mar 24 12:43:06 PM PDT 24
Finished Mar 24 12:43:08 PM PDT 24
Peak memory 203556 kb
Host smart-f2330d55-e2a1-46ef-88ac-3064ee536ae6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156436327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.2156436327
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2569502675
Short name T245
Test name
Test status
Simulation time 319117308 ps
CPU time 3.31 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 203588 kb
Host smart-e9f60d72-e2b7-49d6-a152-0fd3a2cb7913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2569502675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2569502675
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1120895660
Short name T919
Test name
Test status
Simulation time 62826965 ps
CPU time 1.15 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 219476 kb
Host smart-2c241fc0-323a-4150-82ba-f6780616a8b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120895660 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.1120895660
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2956475160
Short name T206
Test name
Test status
Simulation time 30136735 ps
CPU time 0.96 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:18 PM PDT 24
Peak memory 203512 kb
Host smart-49abf734-08c9-4164-bcb5-e2425837a5a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956475160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2956475160
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.137830647
Short name T249
Test name
Test status
Simulation time 76853307 ps
CPU time 1.07 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 203540 kb
Host smart-2f50c1fb-38a3-415b-8a41-7e74719e9b3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137830647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_c
sr_outstanding.137830647
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2878298199
Short name T271
Test name
Test status
Simulation time 211254071 ps
CPU time 4.08 seconds
Started Mar 24 12:43:02 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203504 kb
Host smart-0aa50e61-f4d3-45b9-9ac4-bf8fe1443efc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2878298199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2878298199
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.4055348644
Short name T80
Test name
Test status
Simulation time 120026685 ps
CPU time 1.76 seconds
Started Mar 24 12:43:10 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 211860 kb
Host smart-b0d0e309-1626-486d-9cab-0c0cb600087d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055348644 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.4055348644
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.968203418
Short name T926
Test name
Test status
Simulation time 41278149 ps
CPU time 0.82 seconds
Started Mar 24 12:43:07 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 203332 kb
Host smart-9fd151c2-a0ae-49c9-87c2-7507bc938544
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968203418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.968203418
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.4065175566
Short name T915
Test name
Test status
Simulation time 22573849 ps
CPU time 0.64 seconds
Started Mar 24 12:43:04 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 203272 kb
Host smart-fded6557-0dd2-453e-ad21-d4cdff17f1a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4065175566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.4065175566
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.748165388
Short name T251
Test name
Test status
Simulation time 143749654 ps
CPU time 1.47 seconds
Started Mar 24 12:43:19 PM PDT 24
Finished Mar 24 12:43:21 PM PDT 24
Peak memory 203660 kb
Host smart-93576234-3810-4596-9a94-6b6d30e7cf6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748165388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_c
sr_outstanding.748165388
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3575357549
Short name T192
Test name
Test status
Simulation time 132555820 ps
CPU time 1.67 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:24 PM PDT 24
Peak memory 203652 kb
Host smart-b482ff34-16a5-4633-8231-ca369e3d09f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3575357549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3575357549
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.669717216
Short name T194
Test name
Test status
Simulation time 217847957 ps
CPU time 3.61 seconds
Started Mar 24 12:43:13 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203684 kb
Host smart-70e3ad9b-7f30-44f2-9196-f8979d59c862
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=669717216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.669717216
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2838556158
Short name T952
Test name
Test status
Simulation time 104328998 ps
CPU time 3.32 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 203780 kb
Host smart-435ac8bc-b74f-42af-b9d0-6448188617f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838556158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2838556158
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3993117165
Short name T59
Test name
Test status
Simulation time 59485179 ps
CPU time 0.86 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 203240 kb
Host smart-41a2c183-16aa-440e-bf5d-c48d967f9556
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993117165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3993117165
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1693758455
Short name T945
Test name
Test status
Simulation time 91702587 ps
CPU time 1.38 seconds
Started Mar 24 12:43:02 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 211752 kb
Host smart-932b1e98-9b90-468f-859e-7784f92d5e85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693758455 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.1693758455
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1257663107
Short name T210
Test name
Test status
Simulation time 56536128 ps
CPU time 0.97 seconds
Started Mar 24 12:42:56 PM PDT 24
Finished Mar 24 12:42:58 PM PDT 24
Peak memory 203764 kb
Host smart-f72359e7-7510-4977-92ad-f322ec990b34
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257663107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1257663107
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3399819821
Short name T67
Test name
Test status
Simulation time 21007265 ps
CPU time 0.67 seconds
Started Mar 24 12:42:55 PM PDT 24
Finished Mar 24 12:42:56 PM PDT 24
Peak memory 203232 kb
Host smart-a8f18d14-c1f6-486b-b161-589e7ca7f6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3399819821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3399819821
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.304631053
Short name T207
Test name
Test status
Simulation time 60886978 ps
CPU time 2.06 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:14 PM PDT 24
Peak memory 203544 kb
Host smart-7c61fd91-585d-4e45-8c58-5e342d92c6b4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=304631053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.304631053
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3394104196
Short name T947
Test name
Test status
Simulation time 56856813 ps
CPU time 0.99 seconds
Started Mar 24 12:43:09 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 203560 kb
Host smart-5fb93fd5-1fa7-479e-9907-89791edf78a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394104196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.3394104196
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.380812729
Short name T905
Test name
Test status
Simulation time 122180896 ps
CPU time 1.69 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 203552 kb
Host smart-1a8d5355-6ba9-4f7c-8f98-3d615d328775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=380812729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.380812729
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.43548648
Short name T266
Test name
Test status
Simulation time 203453706 ps
CPU time 3.76 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:52 PM PDT 24
Peak memory 203540 kb
Host smart-82544db5-3ceb-4fb7-97ef-11aac3d85dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=43548648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.43548648
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2442425729
Short name T911
Test name
Test status
Simulation time 26382325 ps
CPU time 0.63 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203304 kb
Host smart-b7fa5e35-8d9b-4c5c-bab1-10a6330e3747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2442425729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2442425729
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2605020581
Short name T942
Test name
Test status
Simulation time 29929814 ps
CPU time 0.69 seconds
Started Mar 24 12:43:11 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 203268 kb
Host smart-5ba732cd-7328-4056-90cb-954d6615ce06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2605020581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2605020581
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3591512243
Short name T257
Test name
Test status
Simulation time 31214056 ps
CPU time 0.65 seconds
Started Mar 24 12:43:13 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203272 kb
Host smart-f20c764e-be42-451c-8b11-53064da4309f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3591512243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3591512243
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3999108393
Short name T925
Test name
Test status
Simulation time 22945817 ps
CPU time 0.67 seconds
Started Mar 24 12:42:53 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 203228 kb
Host smart-5b8d49ee-b8e6-4263-9e1e-6141302597fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3999108393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3999108393
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3361287445
Short name T263
Test name
Test status
Simulation time 19685984 ps
CPU time 0.65 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 203268 kb
Host smart-9a144c82-4632-4e0a-b7ab-6a1819f72a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3361287445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3361287445
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.816748626
Short name T937
Test name
Test status
Simulation time 283248875 ps
CPU time 3.56 seconds
Started Mar 24 12:42:51 PM PDT 24
Finished Mar 24 12:42:55 PM PDT 24
Peak memory 203448 kb
Host smart-aee63316-8cd8-46c0-ae9a-a424c8e85bfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816748626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.816748626
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2049539323
Short name T955
Test name
Test status
Simulation time 121577872 ps
CPU time 1.74 seconds
Started Mar 24 12:42:58 PM PDT 24
Finished Mar 24 12:42:59 PM PDT 24
Peak memory 211764 kb
Host smart-7d556af9-5652-418b-979f-d99bb519a7b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049539323 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.2049539323
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1463209832
Short name T262
Test name
Test status
Simulation time 27394592 ps
CPU time 0.63 seconds
Started Mar 24 12:42:49 PM PDT 24
Finished Mar 24 12:42:50 PM PDT 24
Peak memory 203356 kb
Host smart-c7de627a-d2c0-45a3-9e74-a928c4ba936e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1463209832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1463209832
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3514437726
Short name T200
Test name
Test status
Simulation time 38305779 ps
CPU time 1.29 seconds
Started Mar 24 12:42:51 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 203532 kb
Host smart-847fdc4f-0829-41d6-bbfe-92538d62fd32
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3514437726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3514437726
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1257006816
Short name T897
Test name
Test status
Simulation time 152972027 ps
CPU time 4.06 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 203428 kb
Host smart-ee6c3908-aae1-4b5c-ae8f-8cfe42b80e9a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1257006816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1257006816
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2498936694
Short name T943
Test name
Test status
Simulation time 61529725 ps
CPU time 1.44 seconds
Started Mar 24 12:43:02 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 203572 kb
Host smart-bddd3f73-7bd5-457a-9b04-efdf722b5f21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498936694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.2498936694
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.611018132
Short name T887
Test name
Test status
Simulation time 285860599 ps
CPU time 3.35 seconds
Started Mar 24 12:43:09 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203636 kb
Host smart-edf36e83-825e-4d50-86fe-d996959d8d43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=611018132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.611018132
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2200465625
Short name T923
Test name
Test status
Simulation time 19479387 ps
CPU time 0.63 seconds
Started Mar 24 12:43:17 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203188 kb
Host smart-cd4fface-4d95-4c10-b8f0-9f72bbdbf3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2200465625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2200465625
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1101767785
Short name T913
Test name
Test status
Simulation time 25488979 ps
CPU time 0.63 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203232 kb
Host smart-5d7d4d74-590a-442e-ab38-ac7828f7483f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1101767785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1101767785
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1361145073
Short name T247
Test name
Test status
Simulation time 338821362 ps
CPU time 3.63 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:20 PM PDT 24
Peak memory 203432 kb
Host smart-20010eee-6fc8-4bab-b4a2-a7c8180ac546
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361145073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1361145073
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1216958765
Short name T64
Test name
Test status
Simulation time 33991768 ps
CPU time 0.76 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 203276 kb
Host smart-798bbe8c-e1da-4e17-a950-992f84253231
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216958765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1216958765
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2265877281
Short name T914
Test name
Test status
Simulation time 75988878 ps
CPU time 2.46 seconds
Started Mar 24 12:43:17 PM PDT 24
Finished Mar 24 12:43:19 PM PDT 24
Peak memory 211732 kb
Host smart-c786a2c5-22c7-4cac-b634-1d3fa887acf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265877281 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2265877281
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3421533102
Short name T203
Test name
Test status
Simulation time 51340596 ps
CPU time 1.03 seconds
Started Mar 24 12:43:04 PM PDT 24
Finished Mar 24 12:43:05 PM PDT 24
Peak memory 203456 kb
Host smart-143ad325-37b7-432f-ba32-598f3f522171
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421533102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3421533102
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4014044027
Short name T933
Test name
Test status
Simulation time 100136908 ps
CPU time 1.43 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 203660 kb
Host smart-f811f494-6dd8-496c-8d2b-e102f4b3d855
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4014044027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4014044027
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2940876630
Short name T880
Test name
Test status
Simulation time 470691175 ps
CPU time 4.36 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203784 kb
Host smart-4fffd5e1-fd9f-4bde-a9b8-62d0bfcd2eb8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2940876630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2940876630
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1253039383
Short name T939
Test name
Test status
Simulation time 67116293 ps
CPU time 1.04 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203572 kb
Host smart-4e8d7449-cde6-47f5-aec2-1412c9677767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253039383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.1253039383
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3860500117
Short name T896
Test name
Test status
Simulation time 256918193 ps
CPU time 3.12 seconds
Started Mar 24 12:43:11 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 203592 kb
Host smart-5a538257-3210-4a94-8450-03cc2fc02e24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3860500117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3860500117
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2129613170
Short name T268
Test name
Test status
Simulation time 243753388 ps
CPU time 4.03 seconds
Started Mar 24 12:43:04 PM PDT 24
Finished Mar 24 12:43:08 PM PDT 24
Peak memory 203564 kb
Host smart-16a01c33-b001-4d3f-8f6d-1e8214fd18ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2129613170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2129613170
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1158377972
Short name T920
Test name
Test status
Simulation time 24400161 ps
CPU time 0.66 seconds
Started Mar 24 12:42:49 PM PDT 24
Finished Mar 24 12:42:50 PM PDT 24
Peak memory 203236 kb
Host smart-2a231267-8be6-4f02-9579-a58af4a5aa70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1158377972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1158377972
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1378933152
Short name T944
Test name
Test status
Simulation time 26874616 ps
CPU time 0.63 seconds
Started Mar 24 12:43:19 PM PDT 24
Finished Mar 24 12:43:21 PM PDT 24
Peak memory 203272 kb
Host smart-a01dc7e8-1810-4973-97b1-d20963b1cbf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1378933152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1378933152
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.574461377
Short name T916
Test name
Test status
Simulation time 24536193 ps
CPU time 0.64 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203340 kb
Host smart-3fe21c57-485d-4bf9-8258-07f146a7192b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=574461377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.574461377
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.529857473
Short name T259
Test name
Test status
Simulation time 24883849 ps
CPU time 0.69 seconds
Started Mar 24 12:43:21 PM PDT 24
Finished Mar 24 12:43:23 PM PDT 24
Peak memory 203192 kb
Host smart-47a45fdb-d605-4b05-ab87-310f9c3b7285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=529857473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.529857473
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.819792879
Short name T261
Test name
Test status
Simulation time 25592451 ps
CPU time 0.7 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203272 kb
Host smart-e046de15-3f3c-4aea-a417-590809e8c8d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=819792879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.819792879
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2643585659
Short name T69
Test name
Test status
Simulation time 25492518 ps
CPU time 0.72 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203268 kb
Host smart-74a72ecf-891b-4567-a710-6a1de3a4035b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2643585659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2643585659
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1240924830
Short name T884
Test name
Test status
Simulation time 55181487 ps
CPU time 1.79 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 211728 kb
Host smart-4cf7a52b-29bb-409c-8827-0b493b793b18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240924830 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.1240924830
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1738839071
Short name T81
Test name
Test status
Simulation time 22922373 ps
CPU time 0.81 seconds
Started Mar 24 12:42:53 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 203420 kb
Host smart-183a3d90-bb21-49fb-a594-57601a4e77f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738839071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1738839071
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.679543212
Short name T72
Test name
Test status
Simulation time 23571712 ps
CPU time 0.64 seconds
Started Mar 24 12:43:15 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203220 kb
Host smart-2d684354-3838-4eb1-8ca0-7064d567d30d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=679543212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.679543212
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4093387149
Short name T938
Test name
Test status
Simulation time 112381082 ps
CPU time 1.38 seconds
Started Mar 24 12:43:07 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 203544 kb
Host smart-6ddecb2e-ca03-4703-9a6b-9ee89130797a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093387149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.4093387149
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1425352834
Short name T882
Test name
Test status
Simulation time 88673629 ps
CPU time 1.29 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:00 PM PDT 24
Peak memory 211784 kb
Host smart-6b96d1a3-fae2-4736-8fdb-375747340d8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425352834 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.1425352834
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2064673649
Short name T201
Test name
Test status
Simulation time 27596403 ps
CPU time 0.77 seconds
Started Mar 24 12:43:09 PM PDT 24
Finished Mar 24 12:43:10 PM PDT 24
Peak memory 203428 kb
Host smart-e3ee2ed2-2faa-4ceb-bf0e-bd7787ecf80b
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064673649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2064673649
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2825887710
Short name T213
Test name
Test status
Simulation time 68233752 ps
CPU time 1.12 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203568 kb
Host smart-5eeb00ad-1eed-4d05-a8f1-a6996c1863cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825887710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.2825887710
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3373598786
Short name T193
Test name
Test status
Simulation time 95551085 ps
CPU time 2.84 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 203684 kb
Host smart-93d4d811-ace9-4fcf-8f5e-a284c3ce7509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3373598786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3373598786
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1946565403
Short name T61
Test name
Test status
Simulation time 111848044 ps
CPU time 2.24 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 203568 kb
Host smart-fb1e4994-940a-4eef-b691-bdcd48fcf8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1946565403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1946565403
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.985202946
Short name T951
Test name
Test status
Simulation time 55437953 ps
CPU time 1.72 seconds
Started Mar 24 12:43:08 PM PDT 24
Finished Mar 24 12:43:10 PM PDT 24
Peak memory 214388 kb
Host smart-c245e301-757f-4681-9a08-c716727828c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985202946 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.985202946
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2408862051
Short name T904
Test name
Test status
Simulation time 29269027 ps
CPU time 0.89 seconds
Started Mar 24 12:42:58 PM PDT 24
Finished Mar 24 12:42:59 PM PDT 24
Peak memory 203476 kb
Host smart-fc3438ea-287e-47db-8763-3c7b31095eac
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408862051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2408862051
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2138990273
Short name T922
Test name
Test status
Simulation time 18013402 ps
CPU time 0.65 seconds
Started Mar 24 12:43:06 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 203272 kb
Host smart-c96947fc-fb91-43d4-8a15-9f4821463bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2138990273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2138990273
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1840147405
Short name T903
Test name
Test status
Simulation time 151371922 ps
CPU time 1.52 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 203580 kb
Host smart-77fac4d0-8fa9-4d72-991f-d76995cb18c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840147405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.1840147405
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2859710971
Short name T888
Test name
Test status
Simulation time 205908518 ps
CPU time 2.71 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 203608 kb
Host smart-493e4659-d7d8-4cb1-b123-9a829e806f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2859710971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2859710971
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.108014155
Short name T886
Test name
Test status
Simulation time 68269782 ps
CPU time 2.03 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 211796 kb
Host smart-c23fe2c1-9a4f-4c64-a012-fea514e034d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108014155 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.108014155
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1315330667
Short name T948
Test name
Test status
Simulation time 31732369 ps
CPU time 0.99 seconds
Started Mar 24 12:42:50 PM PDT 24
Finished Mar 24 12:42:51 PM PDT 24
Peak memory 203376 kb
Host smart-31547831-0937-4bd9-83b0-516841c5cf4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315330667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1315330667
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.203096858
Short name T927
Test name
Test status
Simulation time 90378063 ps
CPU time 1.13 seconds
Started Mar 24 12:42:54 PM PDT 24
Finished Mar 24 12:42:56 PM PDT 24
Peak memory 203556 kb
Host smart-306a7cd7-92f2-4ec4-8f3b-952effa03ecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203096858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_cs
r_outstanding.203096858
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2203039532
Short name T908
Test name
Test status
Simulation time 156054387 ps
CPU time 2.24 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:14 PM PDT 24
Peak memory 203644 kb
Host smart-975625b3-1b32-491d-9c34-d95338871205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2203039532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2203039532
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.530188073
Short name T246
Test name
Test status
Simulation time 266130147 ps
CPU time 2.36 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 203600 kb
Host smart-f6b19937-9466-4e6d-afef-806ac9f19654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=530188073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.530188073
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.814283213
Short name T950
Test name
Test status
Simulation time 56046761 ps
CPU time 1.7 seconds
Started Mar 24 12:43:11 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 211820 kb
Host smart-f7124d64-9da1-4e4b-900b-dac74aa555ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814283213 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.814283213
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2123912825
Short name T912
Test name
Test status
Simulation time 54993678 ps
CPU time 0.95 seconds
Started Mar 24 12:43:14 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 203508 kb
Host smart-b887fe2e-81fb-4496-b0f3-589953c56f11
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123912825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2123912825
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2463387258
Short name T898
Test name
Test status
Simulation time 26288856 ps
CPU time 0.66 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 203268 kb
Host smart-b6350811-94c7-4f9d-bde6-cba6b6dc8d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2463387258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2463387258
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.7150949
Short name T212
Test name
Test status
Simulation time 56314333 ps
CPU time 1.33 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:43:13 PM PDT 24
Peak memory 203592 kb
Host smart-b145b05a-b013-417b-a360-019a289b2871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7150949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_
outstanding.7150949
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.886364960
Short name T242
Test name
Test status
Simulation time 67485582 ps
CPU time 2.01 seconds
Started Mar 24 12:43:04 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 203640 kb
Host smart-c29cfd6d-4f8f-4d73-9146-b68b0c68b2dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=886364960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.886364960
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2625169751
Short name T265
Test name
Test status
Simulation time 449590668 ps
CPU time 4.51 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 203568 kb
Host smart-6411a164-e28b-49f2-9a94-d66de145800b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2625169751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2625169751
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2822194461
Short name T713
Test name
Test status
Simulation time 8372198219 ps
CPU time 9.43 seconds
Started Mar 24 02:40:38 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 203552 kb
Host smart-f561cf41-a0ed-4aef-becb-b47ad4481b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28221
94461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2822194461
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_enable.1068885733
Short name T240
Test name
Test status
Simulation time 8372621432 ps
CPU time 8.79 seconds
Started Mar 24 02:40:39 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 203572 kb
Host smart-03f334bb-c0a9-48e5-98e7-68f91c2ba4d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
85733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1068885733
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3389327373
Short name T782
Test name
Test status
Simulation time 134162051 ps
CPU time 1.69 seconds
Started Mar 24 02:40:37 PM PDT 24
Finished Mar 24 02:40:39 PM PDT 24
Peak memory 203636 kb
Host smart-1ab4ea28-769e-498d-886c-8c9bdb0badea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33893
27373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3389327373
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.417782113
Short name T544
Test name
Test status
Simulation time 8398903271 ps
CPU time 7.9 seconds
Started Mar 24 02:40:38 PM PDT 24
Finished Mar 24 02:40:46 PM PDT 24
Peak memory 203488 kb
Host smart-133fb67d-2c8d-4759-bb02-bf50bbd36928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41778
2113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.417782113
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1076564939
Short name T758
Test name
Test status
Simulation time 8413974923 ps
CPU time 7.74 seconds
Started Mar 24 02:40:39 PM PDT 24
Finished Mar 24 02:40:47 PM PDT 24
Peak memory 203576 kb
Host smart-04882ab4-17af-424a-80ae-de5678f35d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10765
64939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1076564939
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1823682910
Short name T807
Test name
Test status
Simulation time 8365122496 ps
CPU time 8.58 seconds
Started Mar 24 02:40:34 PM PDT 24
Finished Mar 24 02:40:43 PM PDT 24
Peak memory 203548 kb
Host smart-cca280cd-cdd2-4586-92a2-c5a3ee823a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
82910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1823682910
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2223028534
Short name T221
Test name
Test status
Simulation time 8373958153 ps
CPU time 7.38 seconds
Started Mar 24 02:40:40 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 203536 kb
Host smart-adaf5442-7e5e-41b0-99b6-094e9e94388e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22230
28534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2223028534
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3596035961
Short name T791
Test name
Test status
Simulation time 8380307158 ps
CPU time 7.56 seconds
Started Mar 24 02:40:40 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 203604 kb
Host smart-eb5942ef-9025-4631-a786-1a673a2baf31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35960
35961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3596035961
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1768465688
Short name T489
Test name
Test status
Simulation time 25973483 ps
CPU time 0.67 seconds
Started Mar 24 02:40:41 PM PDT 24
Finished Mar 24 02:40:42 PM PDT 24
Peak memory 203392 kb
Host smart-29090124-a0ba-41fe-bbc0-446c9536af4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
65688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1768465688
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3181192688
Short name T707
Test name
Test status
Simulation time 8385436115 ps
CPU time 7.55 seconds
Started Mar 24 02:40:42 PM PDT 24
Finished Mar 24 02:40:50 PM PDT 24
Peak memory 203568 kb
Host smart-aa9eca92-a9ee-4eac-bc0d-f48ada5443d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31811
92688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3181192688
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3892899400
Short name T403
Test name
Test status
Simulation time 8410116173 ps
CPU time 7.17 seconds
Started Mar 24 02:40:43 PM PDT 24
Finished Mar 24 02:40:50 PM PDT 24
Peak memory 203552 kb
Host smart-75fa0b4b-ca59-4c40-9dc2-47d593a0f91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38928
99400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3892899400
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3290740198
Short name T618
Test name
Test status
Simulation time 8379711898 ps
CPU time 7.44 seconds
Started Mar 24 02:40:41 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 203540 kb
Host smart-da509986-3e59-4cf4-8d00-0230f43dd79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32907
40198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3290740198
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.4009182904
Short name T372
Test name
Test status
Simulation time 8358785660 ps
CPU time 9.58 seconds
Started Mar 24 02:40:43 PM PDT 24
Finished Mar 24 02:40:53 PM PDT 24
Peak memory 203584 kb
Host smart-72248ddc-1fa3-454c-bc87-7c63436162f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091
82904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.4009182904
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.780394478
Short name T279
Test name
Test status
Simulation time 8373312417 ps
CPU time 7.02 seconds
Started Mar 24 02:40:46 PM PDT 24
Finished Mar 24 02:40:54 PM PDT 24
Peak memory 203808 kb
Host smart-341f027d-137d-4281-8867-b2fdb16b2593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78039
4478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.780394478
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3193141300
Short name T596
Test name
Test status
Simulation time 114365482 ps
CPU time 1.39 seconds
Started Mar 24 02:40:46 PM PDT 24
Finished Mar 24 02:40:47 PM PDT 24
Peak memory 203652 kb
Host smart-99ba65a8-0d12-4272-94b2-dacf60dc1d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31931
41300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3193141300
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.395942968
Short name T537
Test name
Test status
Simulation time 8378501176 ps
CPU time 7.44 seconds
Started Mar 24 02:40:49 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 203488 kb
Host smart-98ad7eb9-94b2-43d5-aade-ea48f04a3521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39594
2968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.395942968
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.253915310
Short name T756
Test name
Test status
Simulation time 8408954554 ps
CPU time 7.99 seconds
Started Mar 24 02:40:48 PM PDT 24
Finished Mar 24 02:40:57 PM PDT 24
Peak memory 203560 kb
Host smart-61d46e46-4b6f-4cb9-a5b7-93dd36264e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391
5310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.253915310
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.271813548
Short name T805
Test name
Test status
Simulation time 8364359642 ps
CPU time 8.47 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 203540 kb
Host smart-ca211b0e-5fad-478b-a8ef-a0eaef84aee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27181
3548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.271813548
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3542767500
Short name T678
Test name
Test status
Simulation time 8382885876 ps
CPU time 7.96 seconds
Started Mar 24 02:40:46 PM PDT 24
Finished Mar 24 02:40:54 PM PDT 24
Peak memory 203512 kb
Host smart-de72ba29-cef2-413f-bb39-78cabe0671d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35427
67500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3542767500
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.784135214
Short name T366
Test name
Test status
Simulation time 8399576415 ps
CPU time 7.47 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:54 PM PDT 24
Peak memory 203540 kb
Host smart-336565c7-405f-4c57-ac53-eb61ca6521c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78413
5214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.784135214
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3866872014
Short name T781
Test name
Test status
Simulation time 23614593 ps
CPU time 0.62 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:40:53 PM PDT 24
Peak memory 203320 kb
Host smart-049ee148-3fd4-4ac8-a387-c1768de144f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38668
72014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3866872014
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3859485614
Short name T425
Test name
Test status
Simulation time 8365361441 ps
CPU time 7.32 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:55 PM PDT 24
Peak memory 203516 kb
Host smart-a34b523e-5458-4410-ae0f-3bd636e5a33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38594
85614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3859485614
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3900925505
Short name T730
Test name
Test status
Simulation time 8415432163 ps
CPU time 7.62 seconds
Started Mar 24 02:40:45 PM PDT 24
Finished Mar 24 02:40:53 PM PDT 24
Peak memory 203572 kb
Host smart-16f366b5-f255-4bbd-91e1-9fbd558d31c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39009
25505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3900925505
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1252959851
Short name T831
Test name
Test status
Simulation time 8363053585 ps
CPU time 7.18 seconds
Started Mar 24 02:40:48 PM PDT 24
Finished Mar 24 02:40:55 PM PDT 24
Peak memory 203532 kb
Host smart-a1ccf83a-390f-42da-aeaa-9468c89cb153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12529
59851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1252959851
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.4038832828
Short name T74
Test name
Test status
Simulation time 98436089 ps
CPU time 0.89 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:48 PM PDT 24
Peak memory 219420 kb
Host smart-967a6289-9a1d-4fe3-b43e-cd5a14be9648
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4038832828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.4038832828
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3757495471
Short name T737
Test name
Test status
Simulation time 8357795947 ps
CPU time 7.54 seconds
Started Mar 24 02:40:46 PM PDT 24
Finished Mar 24 02:40:53 PM PDT 24
Peak memory 203540 kb
Host smart-605cd6dd-629d-468e-a15e-73dc43ebc106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37574
95471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3757495471
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1617793851
Short name T477
Test name
Test status
Simulation time 8368223868 ps
CPU time 9.43 seconds
Started Mar 24 02:41:18 PM PDT 24
Finished Mar 24 02:41:28 PM PDT 24
Peak memory 203780 kb
Host smart-d246e2f5-a1b4-4d67-a74c-130bb98fbda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16177
93851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1617793851
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_enable.2277332888
Short name T832
Test name
Test status
Simulation time 8370726731 ps
CPU time 7.55 seconds
Started Mar 24 02:41:18 PM PDT 24
Finished Mar 24 02:41:26 PM PDT 24
Peak memory 203592 kb
Host smart-cc08180e-1865-423e-97df-d4458bfce017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22773
32888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.2277332888
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3858094364
Short name T852
Test name
Test status
Simulation time 202841631 ps
CPU time 2.26 seconds
Started Mar 24 02:41:18 PM PDT 24
Finished Mar 24 02:41:21 PM PDT 24
Peak memory 203588 kb
Host smart-b42be56f-d4b2-47c5-b0bf-81b08d992627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38580
94364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3858094364
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3818829930
Short name T187
Test name
Test status
Simulation time 8360510179 ps
CPU time 7.77 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:32 PM PDT 24
Peak memory 203444 kb
Host smart-bd62864a-dcf3-4a1f-a136-725c7e3e1936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38188
29930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3818829930
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2517476782
Short name T632
Test name
Test status
Simulation time 8392300488 ps
CPU time 10.08 seconds
Started Mar 24 02:41:19 PM PDT 24
Finished Mar 24 02:41:30 PM PDT 24
Peak memory 203552 kb
Host smart-377073cd-2ed1-48e1-921b-c64ad765d5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
76782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2517476782
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1925136563
Short name T826
Test name
Test status
Simulation time 8412018534 ps
CPU time 7.74 seconds
Started Mar 24 02:41:17 PM PDT 24
Finished Mar 24 02:41:25 PM PDT 24
Peak memory 203572 kb
Host smart-00631b7e-ff80-4010-b9ae-952d0d47524f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19251
36563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1925136563
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3178452590
Short name T417
Test name
Test status
Simulation time 8361053710 ps
CPU time 7.09 seconds
Started Mar 24 02:41:16 PM PDT 24
Finished Mar 24 02:41:23 PM PDT 24
Peak memory 203564 kb
Host smart-3552bcab-b434-4228-96bb-4f39c4cccc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31784
52590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3178452590
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2909314908
Short name T292
Test name
Test status
Simulation time 8380395501 ps
CPU time 7.58 seconds
Started Mar 24 02:41:16 PM PDT 24
Finished Mar 24 02:41:24 PM PDT 24
Peak memory 203516 kb
Host smart-72674c6d-3363-4f61-ab43-85ad2d0bb018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29093
14908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2909314908
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1075345992
Short name T871
Test name
Test status
Simulation time 8376298376 ps
CPU time 7.44 seconds
Started Mar 24 02:41:20 PM PDT 24
Finished Mar 24 02:41:28 PM PDT 24
Peak memory 203592 kb
Host smart-579b5923-78f9-4553-8222-39af72d1ccfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10753
45992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1075345992
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1691672501
Short name T430
Test name
Test status
Simulation time 8398153255 ps
CPU time 7.26 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:30 PM PDT 24
Peak memory 203532 kb
Host smart-60ef5f1a-1550-4540-85dc-63bdcc2a8282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16916
72501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1691672501
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1855566318
Short name T563
Test name
Test status
Simulation time 8397319824 ps
CPU time 7.26 seconds
Started Mar 24 02:41:25 PM PDT 24
Finished Mar 24 02:41:32 PM PDT 24
Peak memory 203556 kb
Host smart-8aff43b8-d344-4f11-b300-a22c59f87619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18555
66318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1855566318
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.571221337
Short name T519
Test name
Test status
Simulation time 8368421877 ps
CPU time 9.01 seconds
Started Mar 24 02:41:21 PM PDT 24
Finished Mar 24 02:41:30 PM PDT 24
Peak memory 203548 kb
Host smart-19566972-db1b-48ce-b22e-6534e2ffdcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57122
1337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.571221337
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.2907603914
Short name T644
Test name
Test status
Simulation time 8362211659 ps
CPU time 7.41 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:31 PM PDT 24
Peak memory 203596 kb
Host smart-275fe160-3d1c-49d6-90ea-85463e7176fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29076
03914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2907603914
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.3815910799
Short name T287
Test name
Test status
Simulation time 8371003466 ps
CPU time 7.39 seconds
Started Mar 24 02:41:26 PM PDT 24
Finished Mar 24 02:41:34 PM PDT 24
Peak memory 203552 kb
Host smart-10753fea-c9ca-44ab-9dfb-01c67fcc03fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38159
10799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.3815910799
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_enable.3435960184
Short name T869
Test name
Test status
Simulation time 8371970309 ps
CPU time 7.71 seconds
Started Mar 24 02:41:24 PM PDT 24
Finished Mar 24 02:41:32 PM PDT 24
Peak memory 203588 kb
Host smart-827d8e56-3d89-4db7-b6e2-7594d3011b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34359
60184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3435960184
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.721542011
Short name T555
Test name
Test status
Simulation time 177641973 ps
CPU time 2.08 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:26 PM PDT 24
Peak memory 203612 kb
Host smart-95d1cdf2-ebe7-448b-b322-8468c433b649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72154
2011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.721542011
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.880732457
Short name T452
Test name
Test status
Simulation time 8410269263 ps
CPU time 7.9 seconds
Started Mar 24 02:41:24 PM PDT 24
Finished Mar 24 02:41:32 PM PDT 24
Peak memory 203512 kb
Host smart-7d8619fb-e9a7-4c02-9342-57d5ddae997e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88073
2457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.880732457
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1660584701
Short name T785
Test name
Test status
Simulation time 8405929486 ps
CPU time 7.93 seconds
Started Mar 24 02:41:24 PM PDT 24
Finished Mar 24 02:41:32 PM PDT 24
Peak memory 203588 kb
Host smart-f622014c-3495-4bb0-bd45-a08df2d3656b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16605
84701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1660584701
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.283212831
Short name T613
Test name
Test status
Simulation time 8365154351 ps
CPU time 9.08 seconds
Started Mar 24 02:41:25 PM PDT 24
Finished Mar 24 02:41:34 PM PDT 24
Peak memory 203556 kb
Host smart-f8d21917-e374-4cca-84e9-c82011d6a264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28321
2831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.283212831
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3554595748
Short name T827
Test name
Test status
Simulation time 8381045373 ps
CPU time 9.79 seconds
Started Mar 24 02:41:22 PM PDT 24
Finished Mar 24 02:41:33 PM PDT 24
Peak memory 203568 kb
Host smart-e5ef28cd-785d-4376-9669-3edabc7b5e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35545
95748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3554595748
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.137544015
Short name T22
Test name
Test status
Simulation time 8375312155 ps
CPU time 7.12 seconds
Started Mar 24 02:41:22 PM PDT 24
Finished Mar 24 02:41:29 PM PDT 24
Peak memory 203544 kb
Host smart-d3b7b59a-0654-4b36-b3f2-15b0a1f1451d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13754
4015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.137544015
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.863156388
Short name T384
Test name
Test status
Simulation time 27599338 ps
CPU time 0.63 seconds
Started Mar 24 02:41:22 PM PDT 24
Finished Mar 24 02:41:23 PM PDT 24
Peak memory 203420 kb
Host smart-c4326df7-912f-4c28-9e6c-ab5e711c7d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86315
6388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.863156388
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3319408219
Short name T421
Test name
Test status
Simulation time 8385468610 ps
CPU time 8.57 seconds
Started Mar 24 02:41:26 PM PDT 24
Finished Mar 24 02:41:35 PM PDT 24
Peak memory 203532 kb
Host smart-47e3bfec-33fe-4460-87b7-109d300b7744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33194
08219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3319408219
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.3912401872
Short name T341
Test name
Test status
Simulation time 8463256023 ps
CPU time 7.67 seconds
Started Mar 24 02:41:24 PM PDT 24
Finished Mar 24 02:41:32 PM PDT 24
Peak memory 203616 kb
Host smart-5bee8b0f-d20c-4033-b172-7ff4ab46749a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39124
01872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3912401872
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2344443791
Short name T813
Test name
Test status
Simulation time 8393049440 ps
CPU time 7.3 seconds
Started Mar 24 02:41:25 PM PDT 24
Finished Mar 24 02:41:33 PM PDT 24
Peak memory 203576 kb
Host smart-e3742db4-1070-41aa-9fb8-b26419c96e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
43791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2344443791
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3741157623
Short name T574
Test name
Test status
Simulation time 8361367861 ps
CPU time 7.12 seconds
Started Mar 24 02:41:22 PM PDT 24
Finished Mar 24 02:41:30 PM PDT 24
Peak memory 203576 kb
Host smart-e5e5a55f-dd06-489e-9101-175fa4f2d66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37411
57623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3741157623
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.748161571
Short name T548
Test name
Test status
Simulation time 8473541242 ps
CPU time 8.85 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:33 PM PDT 24
Peak memory 203560 kb
Host smart-1985efd7-6b4c-4dc0-9801-6b8348e19b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74816
1571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.748161571
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2254423344
Short name T855
Test name
Test status
Simulation time 8370458517 ps
CPU time 9.22 seconds
Started Mar 24 02:41:32 PM PDT 24
Finished Mar 24 02:41:42 PM PDT 24
Peak memory 203560 kb
Host smart-c9fb9f81-c47a-461c-b8b1-fed7ed568729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22544
23344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2254423344
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_enable.687264184
Short name T295
Test name
Test status
Simulation time 8373546461 ps
CPU time 9.34 seconds
Started Mar 24 02:41:29 PM PDT 24
Finished Mar 24 02:41:39 PM PDT 24
Peak memory 203552 kb
Host smart-a989dd22-19a5-4211-90a6-f8565113a355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68726
4184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.687264184
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3395578500
Short name T812
Test name
Test status
Simulation time 35980342 ps
CPU time 0.94 seconds
Started Mar 24 02:41:29 PM PDT 24
Finished Mar 24 02:41:31 PM PDT 24
Peak memory 203600 kb
Host smart-2b18ecc1-5422-4ac4-a8a5-b382e4709730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
78500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3395578500
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.129112590
Short name T167
Test name
Test status
Simulation time 8361190297 ps
CPU time 8.4 seconds
Started Mar 24 02:41:30 PM PDT 24
Finished Mar 24 02:41:39 PM PDT 24
Peak memory 203472 kb
Host smart-bb3434f7-1812-4b08-a6f5-1cec0a1963ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12911
2590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.129112590
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.958425967
Short name T116
Test name
Test status
Simulation time 8392056873 ps
CPU time 8.65 seconds
Started Mar 24 02:41:30 PM PDT 24
Finished Mar 24 02:41:39 PM PDT 24
Peak memory 203568 kb
Host smart-33fea4b5-1d05-4ab6-86fd-5902771c8a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95842
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.958425967
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.110408969
Short name T474
Test name
Test status
Simulation time 8409020514 ps
CPU time 7.33 seconds
Started Mar 24 02:41:32 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 203872 kb
Host smart-5b4d34f8-0b52-42a0-8cfe-452d6f965613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11040
8969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.110408969
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3160950225
Short name T382
Test name
Test status
Simulation time 8363347791 ps
CPU time 9.65 seconds
Started Mar 24 02:41:27 PM PDT 24
Finished Mar 24 02:41:37 PM PDT 24
Peak memory 203600 kb
Host smart-d107d050-4f7d-4b18-adf9-466138e370ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31609
50225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3160950225
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3977396473
Short name T349
Test name
Test status
Simulation time 8383564736 ps
CPU time 7.67 seconds
Started Mar 24 02:41:32 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 203560 kb
Host smart-385585e9-f1f2-4ed4-a68e-92ca39e02bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39773
96473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3977396473
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2766475925
Short name T501
Test name
Test status
Simulation time 8396044648 ps
CPU time 8.66 seconds
Started Mar 24 02:41:33 PM PDT 24
Finished Mar 24 02:41:42 PM PDT 24
Peak memory 203876 kb
Host smart-88b52886-810c-4e1d-95d2-9113706945f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27664
75925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2766475925
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.996645404
Short name T554
Test name
Test status
Simulation time 22275524 ps
CPU time 0.64 seconds
Started Mar 24 02:41:27 PM PDT 24
Finished Mar 24 02:41:28 PM PDT 24
Peak memory 203468 kb
Host smart-2a46bae7-a069-436c-a366-4c02f0546ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99664
5404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.996645404
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.740696803
Short name T411
Test name
Test status
Simulation time 8387003644 ps
CPU time 9.09 seconds
Started Mar 24 02:41:27 PM PDT 24
Finished Mar 24 02:41:37 PM PDT 24
Peak memory 203556 kb
Host smart-e5c16fd4-1c16-4bca-a8f6-bef0fc0b12f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74069
6803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.740696803
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2033765440
Short name T830
Test name
Test status
Simulation time 8453537857 ps
CPU time 7.67 seconds
Started Mar 24 02:41:31 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 203528 kb
Host smart-189e93bd-b8e6-4279-9270-f29567a76c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20337
65440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2033765440
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1073113740
Short name T280
Test name
Test status
Simulation time 8413100063 ps
CPU time 8.41 seconds
Started Mar 24 02:41:32 PM PDT 24
Finished Mar 24 02:41:41 PM PDT 24
Peak memory 203872 kb
Host smart-fa9aa3d6-6970-46b3-99d5-44693fa91e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10731
13740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1073113740
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2423175618
Short name T377
Test name
Test status
Simulation time 8369759020 ps
CPU time 7.98 seconds
Started Mar 24 02:41:27 PM PDT 24
Finished Mar 24 02:41:36 PM PDT 24
Peak memory 203556 kb
Host smart-76d6a7d4-1bdd-4b1d-848e-49b528c461cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24231
75618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2423175618
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_enable.958932508
Short name T284
Test name
Test status
Simulation time 8371058896 ps
CPU time 8.37 seconds
Started Mar 24 02:41:29 PM PDT 24
Finished Mar 24 02:41:38 PM PDT 24
Peak memory 203552 kb
Host smart-01c09b64-9a59-49ea-b3ef-176eec5cf7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95893
2508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.958932508
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.207158122
Short name T570
Test name
Test status
Simulation time 242734516 ps
CPU time 1.99 seconds
Started Mar 24 02:41:31 PM PDT 24
Finished Mar 24 02:41:33 PM PDT 24
Peak memory 203648 kb
Host smart-c834720d-c2d3-4ec1-8a3d-99ffb137d546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
8122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.207158122
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1532256797
Short name T416
Test name
Test status
Simulation time 8450958717 ps
CPU time 8.72 seconds
Started Mar 24 02:41:28 PM PDT 24
Finished Mar 24 02:41:37 PM PDT 24
Peak memory 203532 kb
Host smart-11f2b217-ab7c-46c8-9550-a9d9d28f1096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
56797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1532256797
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3508424714
Short name T701
Test name
Test status
Simulation time 8412314347 ps
CPU time 7.43 seconds
Started Mar 24 02:41:31 PM PDT 24
Finished Mar 24 02:41:39 PM PDT 24
Peak memory 203604 kb
Host smart-83a9226e-cc1b-4df3-aa03-964f07147439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35084
24714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3508424714
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1372705725
Short name T837
Test name
Test status
Simulation time 8368244900 ps
CPU time 7.21 seconds
Started Mar 24 02:41:27 PM PDT 24
Finished Mar 24 02:41:35 PM PDT 24
Peak memory 203536 kb
Host smart-6ba5aa09-a18f-4e25-b0e6-1800bd99c0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13727
05725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1372705725
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.144666426
Short name T86
Test name
Test status
Simulation time 8401316005 ps
CPU time 8.4 seconds
Started Mar 24 02:41:31 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 203572 kb
Host smart-43f0c7fd-54e0-4e3d-9b1e-5918069d8c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14466
6426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.144666426
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.244272599
Short name T354
Test name
Test status
Simulation time 8399663113 ps
CPU time 7.19 seconds
Started Mar 24 02:41:32 PM PDT 24
Finished Mar 24 02:41:39 PM PDT 24
Peak memory 203868 kb
Host smart-b95be0ab-ffa0-490e-835a-b490b3cf9e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24427
2599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.244272599
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2548295004
Short name T332
Test name
Test status
Simulation time 8380437197 ps
CPU time 7.68 seconds
Started Mar 24 02:41:28 PM PDT 24
Finished Mar 24 02:41:37 PM PDT 24
Peak memory 203564 kb
Host smart-c3dd31eb-cc53-45e6-88b6-f4ffbf79fd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
95004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2548295004
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1688196154
Short name T526
Test name
Test status
Simulation time 27930986 ps
CPU time 0.67 seconds
Started Mar 24 02:41:36 PM PDT 24
Finished Mar 24 02:41:37 PM PDT 24
Peak memory 203388 kb
Host smart-d6e0058f-f37f-4cff-b9e1-6b526365a4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16881
96154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1688196154
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2623525050
Short name T843
Test name
Test status
Simulation time 8392257869 ps
CPU time 10.12 seconds
Started Mar 24 02:41:29 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 203812 kb
Host smart-79863d46-0559-4078-a46b-b7d85f20bf1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26235
25050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2623525050
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3242241966
Short name T671
Test name
Test status
Simulation time 8446643920 ps
CPU time 7.28 seconds
Started Mar 24 02:41:34 PM PDT 24
Finished Mar 24 02:41:42 PM PDT 24
Peak memory 203464 kb
Host smart-0a876083-ff75-475d-ba05-791fc793eea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32422
41966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3242241966
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.2182143920
Short name T604
Test name
Test status
Simulation time 8380271967 ps
CPU time 8.06 seconds
Started Mar 24 02:41:33 PM PDT 24
Finished Mar 24 02:41:41 PM PDT 24
Peak memory 203544 kb
Host smart-21bb746f-6921-4fe9-aed8-8e87a9d3b7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21821
43920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.2182143920
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2728570285
Short name T21
Test name
Test status
Simulation time 8356116589 ps
CPU time 8.64 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:44 PM PDT 24
Peak memory 203552 kb
Host smart-5a4f1c5d-9ee0-491b-8e63-786ef34b7123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27285
70285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2728570285
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1087569675
Short name T298
Test name
Test status
Simulation time 8366907519 ps
CPU time 9.35 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:44 PM PDT 24
Peak memory 203552 kb
Host smart-3ff8c1ea-7199-4e38-9869-44dbf5571098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10875
69675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1087569675
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_enable.2894681537
Short name T428
Test name
Test status
Simulation time 8369079710 ps
CPU time 8.37 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:43 PM PDT 24
Peak memory 203476 kb
Host smart-5be85dbd-aa39-4de9-8937-cbb9099de8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28946
81537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2894681537
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.412800201
Short name T731
Test name
Test status
Simulation time 68712126 ps
CPU time 1.85 seconds
Started Mar 24 02:41:36 PM PDT 24
Finished Mar 24 02:41:38 PM PDT 24
Peak memory 203624 kb
Host smart-f0353122-0cc0-4cc3-9373-a92b8cdec17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41280
0201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.412800201
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1775305783
Short name T565
Test name
Test status
Simulation time 8364427905 ps
CPU time 8.7 seconds
Started Mar 24 02:41:38 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203488 kb
Host smart-29ea7196-9946-4bde-962e-dd3f2a7d294c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17753
05783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1775305783
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.572862080
Short name T371
Test name
Test status
Simulation time 8392165309 ps
CPU time 7.16 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:42 PM PDT 24
Peak memory 203540 kb
Host smart-0c954029-6f35-4a1f-b609-ba6488ad580f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57286
2080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.572862080
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.143992095
Short name T703
Test name
Test status
Simulation time 8406250970 ps
CPU time 8.77 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:44 PM PDT 24
Peak memory 203604 kb
Host smart-3ba9e3c0-5073-4d08-b791-92f778b6d580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14399
2095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.143992095
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1871906744
Short name T851
Test name
Test status
Simulation time 8365186899 ps
CPU time 7.6 seconds
Started Mar 24 02:41:33 PM PDT 24
Finished Mar 24 02:41:41 PM PDT 24
Peak memory 203600 kb
Host smart-03112c8c-0f98-4f9f-9693-3a935a7f566a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18719
06744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1871906744
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.635662660
Short name T92
Test name
Test status
Simulation time 8421753563 ps
CPU time 7.16 seconds
Started Mar 24 02:41:33 PM PDT 24
Finished Mar 24 02:41:41 PM PDT 24
Peak memory 203556 kb
Host smart-5657a06e-0e61-423f-baa1-5c8e376317c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63566
2660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.635662660
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.877483614
Short name T793
Test name
Test status
Simulation time 8384151943 ps
CPU time 9.77 seconds
Started Mar 24 02:41:37 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203552 kb
Host smart-c8bf2a1a-fb0e-44ee-a0b0-1ed11a57b2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87748
3614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.877483614
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2271277079
Short name T699
Test name
Test status
Simulation time 8404810134 ps
CPU time 9.31 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:44 PM PDT 24
Peak memory 203584 kb
Host smart-6fac753a-b37b-4078-b392-c689a5db86df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22712
77079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2271277079
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1227910502
Short name T691
Test name
Test status
Simulation time 31329575 ps
CPU time 0.66 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:36 PM PDT 24
Peak memory 203392 kb
Host smart-3207440d-a61f-4622-af40-d755de0d0cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12279
10502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1227910502
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4070713609
Short name T47
Test name
Test status
Simulation time 8405737961 ps
CPU time 7.57 seconds
Started Mar 24 02:41:32 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 203512 kb
Host smart-50db3f8f-6bb3-4aa4-aaac-ed30cc0b3862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40707
13609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4070713609
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2570071557
Short name T520
Test name
Test status
Simulation time 8416540779 ps
CPU time 7.47 seconds
Started Mar 24 02:41:39 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203572 kb
Host smart-c16863ca-c4f7-453c-ac45-1192111d817d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25700
71557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2570071557
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2993549173
Short name T778
Test name
Test status
Simulation time 8379403154 ps
CPU time 7.56 seconds
Started Mar 24 02:41:34 PM PDT 24
Finished Mar 24 02:41:41 PM PDT 24
Peak memory 203564 kb
Host smart-8130ab15-dea4-4c1a-8f3f-669c0a31e697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29935
49173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2993549173
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3372401252
Short name T326
Test name
Test status
Simulation time 8357719542 ps
CPU time 7.46 seconds
Started Mar 24 02:41:38 PM PDT 24
Finished Mar 24 02:41:45 PM PDT 24
Peak memory 203588 kb
Host smart-9d1db087-1b53-42e6-868b-6a281bf2409e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33724
01252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3372401252
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4012383240
Short name T142
Test name
Test status
Simulation time 8477046569 ps
CPU time 9.83 seconds
Started Mar 24 02:41:34 PM PDT 24
Finished Mar 24 02:41:44 PM PDT 24
Peak memory 203592 kb
Host smart-7ed63761-ab70-4f8e-9548-814e52bcca4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40123
83240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4012383240
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1884798872
Short name T381
Test name
Test status
Simulation time 8366353324 ps
CPU time 8.07 seconds
Started Mar 24 02:41:33 PM PDT 24
Finished Mar 24 02:41:41 PM PDT 24
Peak memory 203484 kb
Host smart-c5de1e61-e7f1-488f-8b07-a3e7f3d489c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18847
98872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1884798872
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_enable.2677707072
Short name T766
Test name
Test status
Simulation time 8365436642 ps
CPU time 8.17 seconds
Started Mar 24 02:41:36 PM PDT 24
Finished Mar 24 02:41:45 PM PDT 24
Peak memory 203548 kb
Host smart-5d2d0cad-55a8-4796-bbc0-4c1a16dcc56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26777
07072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2677707072
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1541000322
Short name T226
Test name
Test status
Simulation time 43670592 ps
CPU time 1.28 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:36 PM PDT 24
Peak memory 203588 kb
Host smart-ce0ff4c0-4efb-48f0-8426-d3d2fc2872f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15410
00322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1541000322
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3589742137
Short name T186
Test name
Test status
Simulation time 8364865162 ps
CPU time 7.26 seconds
Started Mar 24 02:41:40 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203576 kb
Host smart-3a713de2-4387-4487-a98d-5bc0b26b31c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35897
42137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3589742137
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2687478996
Short name T748
Test name
Test status
Simulation time 8396305403 ps
CPU time 7.93 seconds
Started Mar 24 02:41:34 PM PDT 24
Finished Mar 24 02:41:42 PM PDT 24
Peak memory 203500 kb
Host smart-5e8fd7fc-ba70-4ac1-89d7-eacc6d2c26e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26874
78996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2687478996
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3235886750
Short name T347
Test name
Test status
Simulation time 8383266517 ps
CPU time 6.98 seconds
Started Mar 24 02:41:35 PM PDT 24
Finished Mar 24 02:41:43 PM PDT 24
Peak memory 203600 kb
Host smart-6e259051-7a6c-4a7d-8a84-d48ab50db752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32358
86750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3235886750
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.167657045
Short name T668
Test name
Test status
Simulation time 8400640617 ps
CPU time 7.51 seconds
Started Mar 24 02:41:40 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203500 kb
Host smart-d402f571-3c1d-4d58-a30d-8414853a9a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16765
7045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.167657045
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.1445596604
Short name T274
Test name
Test status
Simulation time 8376596685 ps
CPU time 9.13 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203520 kb
Host smart-7e61607b-fdda-4792-8efe-7088edb38272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14455
96604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.1445596604
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1764338716
Short name T43
Test name
Test status
Simulation time 28569146 ps
CPU time 0.64 seconds
Started Mar 24 02:41:45 PM PDT 24
Finished Mar 24 02:41:46 PM PDT 24
Peak memory 203668 kb
Host smart-ccb1fbd6-a013-4f5e-9d3d-d7f8a0bf74a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17643
38716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1764338716
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2083804816
Short name T503
Test name
Test status
Simulation time 8400498540 ps
CPU time 8.5 seconds
Started Mar 24 02:41:42 PM PDT 24
Finished Mar 24 02:41:51 PM PDT 24
Peak memory 203556 kb
Host smart-3ce2515e-83d0-4af2-ac86-8b58e7744641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20838
04816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2083804816
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2625512215
Short name T562
Test name
Test status
Simulation time 8389877684 ps
CPU time 8.18 seconds
Started Mar 24 02:41:41 PM PDT 24
Finished Mar 24 02:41:50 PM PDT 24
Peak memory 203484 kb
Host smart-6bc68329-11b3-412e-97b9-ecd44b29f3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26255
12215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2625512215
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.353019192
Short name T324
Test name
Test status
Simulation time 8409993700 ps
CPU time 7.38 seconds
Started Mar 24 02:41:42 PM PDT 24
Finished Mar 24 02:41:49 PM PDT 24
Peak memory 203556 kb
Host smart-65a6c1fd-e956-4fc6-bfa0-2b6ea70b9433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35301
9192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.353019192
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1742854548
Short name T864
Test name
Test status
Simulation time 8355348300 ps
CPU time 6.89 seconds
Started Mar 24 02:41:41 PM PDT 24
Finished Mar 24 02:41:49 PM PDT 24
Peak memory 203568 kb
Host smart-d86a5e62-61f3-4891-9a82-fd9e94722f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17428
54548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1742854548
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1641926290
Short name T152
Test name
Test status
Simulation time 8473512225 ps
CPU time 7.68 seconds
Started Mar 24 02:41:33 PM PDT 24
Finished Mar 24 02:41:41 PM PDT 24
Peak memory 203528 kb
Host smart-14f16e57-0f4c-4d6a-8169-8c886483c597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16419
26290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1641926290
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1722466748
Short name T867
Test name
Test status
Simulation time 8373268477 ps
CPU time 8.65 seconds
Started Mar 24 02:41:38 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203572 kb
Host smart-be173097-378e-4ecc-b4e3-33be8ae3f55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
66748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1722466748
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_enable.2817484117
Short name T278
Test name
Test status
Simulation time 8365059831 ps
CPU time 8.09 seconds
Started Mar 24 02:41:39 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203784 kb
Host smart-bee7a514-d1d4-438f-8746-2cff0c33eb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28174
84117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2817484117
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3336017753
Short name T661
Test name
Test status
Simulation time 201134111 ps
CPU time 2.11 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:46 PM PDT 24
Peak memory 203588 kb
Host smart-965184ef-7cd6-4044-9a98-5ce78c2b4af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
17753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3336017753
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1568863417
Short name T173
Test name
Test status
Simulation time 8357524055 ps
CPU time 8.77 seconds
Started Mar 24 02:41:39 PM PDT 24
Finished Mar 24 02:41:48 PM PDT 24
Peak memory 203512 kb
Host smart-981bbffe-a6f1-450a-854b-a7b995722383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
63417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1568863417
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.372333477
Short name T128
Test name
Test status
Simulation time 8415014404 ps
CPU time 8.13 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203536 kb
Host smart-bd6fdbb1-ca35-4444-9c17-3ee29b500484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37233
3477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.372333477
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.752670651
Short name T643
Test name
Test status
Simulation time 8411497739 ps
CPU time 8.06 seconds
Started Mar 24 02:41:40 PM PDT 24
Finished Mar 24 02:41:48 PM PDT 24
Peak memory 203488 kb
Host smart-30851fa2-302a-4ee0-9c13-459b1ba707b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75267
0651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.752670651
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1756862432
Short name T798
Test name
Test status
Simulation time 8362584407 ps
CPU time 7.34 seconds
Started Mar 24 02:41:41 PM PDT 24
Finished Mar 24 02:41:48 PM PDT 24
Peak memory 203572 kb
Host smart-374f9b33-be20-4f74-aa10-40b9ffa7b212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17568
62432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1756862432
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3282469031
Short name T809
Test name
Test status
Simulation time 8400768511 ps
CPU time 7.74 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203540 kb
Host smart-26fae3a4-248c-4b46-bfb5-e6e8f92b7bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824
69031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3282469031
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.346870634
Short name T9
Test name
Test status
Simulation time 8382365694 ps
CPU time 7.46 seconds
Started Mar 24 02:41:42 PM PDT 24
Finished Mar 24 02:41:50 PM PDT 24
Peak memory 203560 kb
Host smart-4a5f1287-af64-46f3-9a45-9a098c7ee44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34687
0634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.346870634
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2684675322
Short name T621
Test name
Test status
Simulation time 27713722 ps
CPU time 0.63 seconds
Started Mar 24 02:41:38 PM PDT 24
Finished Mar 24 02:41:39 PM PDT 24
Peak memory 203444 kb
Host smart-843f883f-dd20-41ba-a715-6f73bbe2a195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26846
75322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2684675322
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.947796519
Short name T37
Test name
Test status
Simulation time 8388163297 ps
CPU time 9.03 seconds
Started Mar 24 02:41:42 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203556 kb
Host smart-2ce7c17a-03c4-400c-b0ac-c943ede34fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94779
6519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.947796519
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.2306663719
Short name T121
Test name
Test status
Simulation time 8400501307 ps
CPU time 7.5 seconds
Started Mar 24 02:41:40 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203568 kb
Host smart-c843a535-4bf7-4ad1-a7b8-7dd970647fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23066
63719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.2306663719
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.1737677302
Short name T614
Test name
Test status
Simulation time 8368313198 ps
CPU time 6.88 seconds
Started Mar 24 02:41:39 PM PDT 24
Finished Mar 24 02:41:46 PM PDT 24
Peak memory 203604 kb
Host smart-9b9b9d68-a332-47b9-9090-fae8ec6b0c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17376
77302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.1737677302
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2259839320
Short name T580
Test name
Test status
Simulation time 8364076284 ps
CPU time 9.03 seconds
Started Mar 24 02:41:45 PM PDT 24
Finished Mar 24 02:41:54 PM PDT 24
Peak memory 203788 kb
Host smart-b68338d3-b655-4c7f-9142-88da357732be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22598
39320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2259839320
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1415216491
Short name T155
Test name
Test status
Simulation time 8481188041 ps
CPU time 8.54 seconds
Started Mar 24 02:41:41 PM PDT 24
Finished Mar 24 02:41:50 PM PDT 24
Peak memory 203592 kb
Host smart-f81ccbf9-881b-45a5-a69e-c59557ec323f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14152
16491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1415216491
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.242464441
Short name T589
Test name
Test status
Simulation time 8365554561 ps
CPU time 7.43 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:00 PM PDT 24
Peak memory 203540 kb
Host smart-015ab4d4-a15c-40d4-826f-db86581dd6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24246
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.242464441
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_enable.11816932
Short name T318
Test name
Test status
Simulation time 8370136601 ps
CPU time 7.01 seconds
Started Mar 24 02:41:39 PM PDT 24
Finished Mar 24 02:41:46 PM PDT 24
Peak memory 203516 kb
Host smart-c13c01d0-566b-4744-a315-7b127fcd83f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11816
932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.11816932
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.449760654
Short name T738
Test name
Test status
Simulation time 54336732 ps
CPU time 1.72 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:45 PM PDT 24
Peak memory 203600 kb
Host smart-752482f9-a682-44e6-a884-d2d0e1f5ea7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44976
0654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.449760654
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1743306547
Short name T163
Test name
Test status
Simulation time 8359790083 ps
CPU time 8.64 seconds
Started Mar 24 02:41:39 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203528 kb
Host smart-b99b83fd-997d-43cb-962e-6087c09d5c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17433
06547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1743306547
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.4215622468
Short name T420
Test name
Test status
Simulation time 8378638582 ps
CPU time 7.1 seconds
Started Mar 24 02:41:42 PM PDT 24
Finished Mar 24 02:41:49 PM PDT 24
Peak memory 203572 kb
Host smart-6cb66d40-f3c6-4192-8b8b-68745a688ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42156
22468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.4215622468
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1805293441
Short name T448
Test name
Test status
Simulation time 8408633409 ps
CPU time 7.56 seconds
Started Mar 24 02:41:41 PM PDT 24
Finished Mar 24 02:41:49 PM PDT 24
Peak memory 203560 kb
Host smart-5e1a61ac-7aff-4d66-a6b0-25a0b9efed1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18052
93441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1805293441
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3188829057
Short name T291
Test name
Test status
Simulation time 8362067236 ps
CPU time 7.76 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203572 kb
Host smart-981e4d2d-0fce-45d5-a3de-5b6b360923bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31888
29057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3188829057
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1867676999
Short name T99
Test name
Test status
Simulation time 8420506424 ps
CPU time 7.9 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203540 kb
Host smart-bf6fe896-d956-4584-ba29-322c19282600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18676
76999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1867676999
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3235056921
Short name T315
Test name
Test status
Simulation time 8392256223 ps
CPU time 7.6 seconds
Started Mar 24 02:41:40 PM PDT 24
Finished Mar 24 02:41:47 PM PDT 24
Peak memory 203560 kb
Host smart-2c2972c1-2c77-4a8e-9b5c-23530ed3c1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32350
56921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3235056921
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2055327205
Short name T513
Test name
Test status
Simulation time 8367895785 ps
CPU time 8.58 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:51 PM PDT 24
Peak memory 203520 kb
Host smart-bd92b92f-b2b5-40b0-970a-002ba843a0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20553
27205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2055327205
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.377295370
Short name T704
Test name
Test status
Simulation time 23306777 ps
CPU time 0.64 seconds
Started Mar 24 02:41:39 PM PDT 24
Finished Mar 24 02:41:40 PM PDT 24
Peak memory 203392 kb
Host smart-c30e843c-bb94-4a31-a7ac-50b16d744841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37729
5370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.377295370
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2257571751
Short name T406
Test name
Test status
Simulation time 8386716455 ps
CPU time 7.48 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:50 PM PDT 24
Peak memory 203500 kb
Host smart-99378568-7456-416a-ab4f-9705a5d9518c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22575
71751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2257571751
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1384051916
Short name T878
Test name
Test status
Simulation time 8454280388 ps
CPU time 8.03 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 203540 kb
Host smart-1ba90f58-47b5-4fef-90ac-d9e9ea571303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13840
51916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1384051916
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.287305852
Short name T457
Test name
Test status
Simulation time 8408752991 ps
CPU time 8.13 seconds
Started Mar 24 02:41:40 PM PDT 24
Finished Mar 24 02:41:48 PM PDT 24
Peak memory 203540 kb
Host smart-a24ddc49-1ebd-48e6-adc1-e33c1b769754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730
5852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.287305852
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3987874033
Short name T711
Test name
Test status
Simulation time 8354643145 ps
CPU time 7.5 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:50 PM PDT 24
Peak memory 203524 kb
Host smart-23d287b7-1372-4fba-9255-5ac9fd3d5c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39878
74033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3987874033
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1385428642
Short name T820
Test name
Test status
Simulation time 8470443517 ps
CPU time 7.84 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:51 PM PDT 24
Peak memory 203532 kb
Host smart-16f29cb4-4b9c-4b67-a74a-6c24129a1f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854
28642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1385428642
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1590887341
Short name T733
Test name
Test status
Simulation time 8372318011 ps
CPU time 8.54 seconds
Started Mar 24 02:41:45 PM PDT 24
Finished Mar 24 02:41:54 PM PDT 24
Peak memory 203528 kb
Host smart-92d2e782-1dfe-4351-a313-fcdceb83dade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
87341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1590887341
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_enable.393424721
Short name T219
Test name
Test status
Simulation time 8371314825 ps
CPU time 8.18 seconds
Started Mar 24 02:41:47 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203560 kb
Host smart-59cd5d2c-71e0-4799-adbf-e28e138ae86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39342
4721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.393424721
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3176890959
Short name T223
Test name
Test status
Simulation time 172758235 ps
CPU time 1.76 seconds
Started Mar 24 02:41:47 PM PDT 24
Finished Mar 24 02:41:49 PM PDT 24
Peak memory 203604 kb
Host smart-0c446fd6-54e3-44e1-adc1-999b7c76c577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31768
90959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3176890959
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3390040683
Short name T599
Test name
Test status
Simulation time 8383614333 ps
CPU time 7.45 seconds
Started Mar 24 02:41:44 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203560 kb
Host smart-dfa349fd-32ac-4de8-b64f-f7895386873a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33900
40683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3390040683
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3324035879
Short name T780
Test name
Test status
Simulation time 8406980785 ps
CPU time 7.14 seconds
Started Mar 24 02:41:45 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203548 kb
Host smart-9b7a6978-7349-40a0-b812-ba83277769c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33240
35879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3324035879
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.510646290
Short name T355
Test name
Test status
Simulation time 8367806053 ps
CPU time 7.45 seconds
Started Mar 24 02:41:44 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203552 kb
Host smart-7842e840-e262-4408-8443-467b92e70c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51064
6290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.510646290
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2575155688
Short name T83
Test name
Test status
Simulation time 8413906307 ps
CPU time 10.12 seconds
Started Mar 24 02:41:45 PM PDT 24
Finished Mar 24 02:41:55 PM PDT 24
Peak memory 203572 kb
Host smart-03f51427-bf2f-4dbf-931c-29cab03e5ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25751
55688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2575155688
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.35943297
Short name T858
Test name
Test status
Simulation time 8396854820 ps
CPU time 8.29 seconds
Started Mar 24 02:41:48 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203556 kb
Host smart-df8ca956-0f75-42ea-919b-52fa403a6702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.35943297
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1810042102
Short name T431
Test name
Test status
Simulation time 8373649404 ps
CPU time 7.33 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:51 PM PDT 24
Peak memory 203624 kb
Host smart-b4dc4e8f-129b-4f1b-a4bd-d96148c13cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18100
42102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1810042102
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1197505232
Short name T220
Test name
Test status
Simulation time 24451440 ps
CPU time 0.65 seconds
Started Mar 24 02:41:45 PM PDT 24
Finished Mar 24 02:41:46 PM PDT 24
Peak memory 203456 kb
Host smart-06014851-daac-4368-ad75-924eebbb2b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11975
05232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1197505232
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3647893904
Short name T546
Test name
Test status
Simulation time 8390194864 ps
CPU time 7.44 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:51 PM PDT 24
Peak memory 203556 kb
Host smart-85bcee45-6b89-4b3b-b86f-068a2c20cd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36478
93904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3647893904
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3749382583
Short name T481
Test name
Test status
Simulation time 8453291461 ps
CPU time 7.84 seconds
Started Mar 24 02:41:49 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203552 kb
Host smart-4549e637-1054-4817-b006-76410a03fff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37493
82583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3749382583
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.1087795338
Short name T583
Test name
Test status
Simulation time 8386453390 ps
CPU time 8.8 seconds
Started Mar 24 02:41:47 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203576 kb
Host smart-6d028954-a554-41ee-affd-bf3bb9b24032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10877
95338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.1087795338
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.760809042
Short name T361
Test name
Test status
Simulation time 8364769078 ps
CPU time 6.9 seconds
Started Mar 24 02:41:43 PM PDT 24
Finished Mar 24 02:41:51 PM PDT 24
Peak memory 203584 kb
Host smart-319b041e-c51f-4bc8-be47-6897057d97f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76080
9042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.760809042
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.149760311
Short name T697
Test name
Test status
Simulation time 8370103644 ps
CPU time 7.08 seconds
Started Mar 24 02:41:52 PM PDT 24
Finished Mar 24 02:41:59 PM PDT 24
Peak memory 203540 kb
Host smart-45c849ec-8959-4f9e-b6b3-61feb4ce7d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14976
0311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.149760311
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_enable.3311445539
Short name T493
Test name
Test status
Simulation time 8365886101 ps
CPU time 8.13 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 203572 kb
Host smart-0942a176-2a6a-490c-8630-569e183e8b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33114
45539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3311445539
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3592301376
Short name T51
Test name
Test status
Simulation time 60659039 ps
CPU time 1.77 seconds
Started Mar 24 02:41:47 PM PDT 24
Finished Mar 24 02:41:49 PM PDT 24
Peak memory 203616 kb
Host smart-e3bfa0f0-4fee-4c80-8f13-b425573e1a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923
01376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3592301376
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3162159517
Short name T811
Test name
Test status
Simulation time 8360497547 ps
CPU time 7.24 seconds
Started Mar 24 02:41:44 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203556 kb
Host smart-79131588-7af4-4911-88e1-2f80b4709363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31621
59517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3162159517
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.17412638
Short name T549
Test name
Test status
Simulation time 8411789998 ps
CPU time 7.75 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 203540 kb
Host smart-5056f19c-9daf-4bd4-abed-2629763d0ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17412
638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.17412638
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1574873844
Short name T335
Test name
Test status
Simulation time 8365900620 ps
CPU time 7.14 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203588 kb
Host smart-2bd6b364-17b1-497e-9697-6de7112f209c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15748
73844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1574873844
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1262559731
Short name T742
Test name
Test status
Simulation time 8368382881 ps
CPU time 9.15 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 203584 kb
Host smart-48a50435-42fe-492e-b6a2-e5a75cb28174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
59731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1262559731
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3105861295
Short name T273
Test name
Test status
Simulation time 8380315010 ps
CPU time 7.6 seconds
Started Mar 24 02:41:48 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203608 kb
Host smart-1b7746d2-b139-4620-b77e-89e66fc2e510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31058
61295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3105861295
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2120783659
Short name T419
Test name
Test status
Simulation time 28317685 ps
CPU time 0.62 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203420 kb
Host smart-4a59ce00-cd6b-41f4-b19d-ce11ce5b0ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21207
83659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2120783659
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.126754300
Short name T415
Test name
Test status
Simulation time 8364054329 ps
CPU time 7.16 seconds
Started Mar 24 02:41:52 PM PDT 24
Finished Mar 24 02:42:00 PM PDT 24
Peak memory 203544 kb
Host smart-4f60fdb5-a0bc-48f4-adc8-941077729f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12675
4300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.126754300
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.738554607
Short name T130
Test name
Test status
Simulation time 8405826278 ps
CPU time 8.3 seconds
Started Mar 24 02:41:48 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203524 kb
Host smart-722d1502-40aa-45db-acad-fe20fee300ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73855
4607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.738554607
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.2885084954
Short name T630
Test name
Test status
Simulation time 8378544574 ps
CPU time 7.69 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203572 kb
Host smart-28879827-8186-4382-93af-f31239c27118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28850
84954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.2885084954
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.824166818
Short name T511
Test name
Test status
Simulation time 8358905747 ps
CPU time 8.21 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203588 kb
Host smart-c088cbdc-0840-4822-9c98-d224d702c8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82416
6818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.824166818
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4157951681
Short name T17
Test name
Test status
Simulation time 8472070137 ps
CPU time 7.71 seconds
Started Mar 24 02:41:44 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203540 kb
Host smart-135f2c96-21fb-4294-86b1-7ea9fa444e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41579
51681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4157951681
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.998862155
Short name T413
Test name
Test status
Simulation time 8368647529 ps
CPU time 7.42 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:55 PM PDT 24
Peak memory 203556 kb
Host smart-618c3c41-52bb-438e-9091-26e4dadba7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99886
2155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.998862155
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_enable.1698970532
Short name T532
Test name
Test status
Simulation time 8368490188 ps
CPU time 9.09 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 203552 kb
Host smart-220ac276-1d79-4faf-91d6-4e24eec921cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16989
70532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1698970532
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2085855722
Short name T567
Test name
Test status
Simulation time 277541848 ps
CPU time 2.3 seconds
Started Mar 24 02:40:47 PM PDT 24
Finished Mar 24 02:40:50 PM PDT 24
Peak memory 203600 kb
Host smart-32091e8f-38ef-410a-8317-c3335b5040c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20858
55722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2085855722
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1152182954
Short name T346
Test name
Test status
Simulation time 8363290111 ps
CPU time 8.47 seconds
Started Mar 24 02:40:57 PM PDT 24
Finished Mar 24 02:41:06 PM PDT 24
Peak memory 203484 kb
Host smart-6ff99b12-ab8f-4f20-863d-6bfb107d4d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11521
82954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1152182954
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3605628975
Short name T467
Test name
Test status
Simulation time 8409752036 ps
CPU time 7.63 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:41:00 PM PDT 24
Peak memory 203568 kb
Host smart-d90cf180-403b-4a87-9591-b17e4f29eef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36056
28975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3605628975
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1948904438
Short name T344
Test name
Test status
Simulation time 8367182185 ps
CPU time 7.5 seconds
Started Mar 24 02:40:49 PM PDT 24
Finished Mar 24 02:40:57 PM PDT 24
Peak memory 203516 kb
Host smart-0263d2ed-a31b-48b7-b7cb-e7dbae4ec7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19489
04438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1948904438
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3527940695
Short name T97
Test name
Test status
Simulation time 8438876445 ps
CPU time 7.94 seconds
Started Mar 24 02:40:54 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203536 kb
Host smart-42553076-0c94-4232-89cf-6ec1e866f5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35279
40695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3527940695
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2589431133
Short name T502
Test name
Test status
Simulation time 8373610229 ps
CPU time 7.68 seconds
Started Mar 24 02:40:48 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 203572 kb
Host smart-26a68e36-9250-4390-84ed-dbdf5e8c01d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25894
31133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2589431133
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.383174588
Short name T603
Test name
Test status
Simulation time 8364658308 ps
CPU time 7.27 seconds
Started Mar 24 02:40:50 PM PDT 24
Finished Mar 24 02:40:58 PM PDT 24
Peak memory 203572 kb
Host smart-77dd9f88-ba02-4859-8aab-eb1484befbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38317
4588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.383174588
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3050066370
Short name T40
Test name
Test status
Simulation time 31292256 ps
CPU time 0.63 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 203388 kb
Host smart-601f0204-1072-41f6-be81-1cd0c955124a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500
66370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3050066370
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.4265865314
Short name T322
Test name
Test status
Simulation time 8377037300 ps
CPU time 8.2 seconds
Started Mar 24 02:40:45 PM PDT 24
Finished Mar 24 02:40:54 PM PDT 24
Peak memory 203572 kb
Host smart-1091424c-d107-4a94-a4b5-0453e295246e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42658
65314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4265865314
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3547787756
Short name T543
Test name
Test status
Simulation time 8451153658 ps
CPU time 9.1 seconds
Started Mar 24 02:40:49 PM PDT 24
Finished Mar 24 02:40:59 PM PDT 24
Peak memory 203572 kb
Host smart-ff756871-3e91-462d-8320-c7e66d691def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35477
87756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3547787756
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.4083157418
Short name T282
Test name
Test status
Simulation time 8398364949 ps
CPU time 7.7 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:41:00 PM PDT 24
Peak memory 203528 kb
Host smart-90d30af5-fe5c-433f-bab9-73ba653d8bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40831
57418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.4083157418
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2251905423
Short name T55
Test name
Test status
Simulation time 95329172 ps
CPU time 0.95 seconds
Started Mar 24 02:40:56 PM PDT 24
Finished Mar 24 02:40:58 PM PDT 24
Peak memory 219448 kb
Host smart-f1b12e59-9370-444f-9dcf-6a4f26b5c999
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2251905423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2251905423
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1122641033
Short name T553
Test name
Test status
Simulation time 8359476497 ps
CPU time 7.53 seconds
Started Mar 24 02:40:57 PM PDT 24
Finished Mar 24 02:41:05 PM PDT 24
Peak memory 203552 kb
Host smart-894bc648-d243-4cc7-a0e0-0336807e8d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11226
41033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1122641033
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.486322176
Short name T139
Test name
Test status
Simulation time 8474997752 ps
CPU time 8.03 seconds
Started Mar 24 02:40:46 PM PDT 24
Finished Mar 24 02:40:54 PM PDT 24
Peak memory 203572 kb
Host smart-5e509600-5d05-43c1-a434-20a261eae0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48632
2176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.486322176
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2938194819
Short name T808
Test name
Test status
Simulation time 8364786541 ps
CPU time 7.68 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:08 PM PDT 24
Peak memory 203556 kb
Host smart-3d982258-cc55-4e1e-8845-83844459e159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
94819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2938194819
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_enable.3992993910
Short name T771
Test name
Test status
Simulation time 8370533946 ps
CPU time 7.45 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203588 kb
Host smart-f8dbe7dc-a9b8-4899-b467-ed09404e1a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39929
93910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3992993910
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2255703216
Short name T438
Test name
Test status
Simulation time 144578634 ps
CPU time 1.65 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 203636 kb
Host smart-aec1e35c-f127-4e7b-9337-30feb5581920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22557
03216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2255703216
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3280465739
Short name T177
Test name
Test status
Simulation time 8355985745 ps
CPU time 7.67 seconds
Started Mar 24 02:41:50 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203476 kb
Host smart-c55acff0-8717-4031-8343-b1fe6c151a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
65739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3280465739
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3515172904
Short name T600
Test name
Test status
Simulation time 8450493463 ps
CPU time 8.18 seconds
Started Mar 24 02:41:48 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203556 kb
Host smart-73230081-af98-4955-b85b-baea6d7c1e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
72904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3515172904
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1102324655
Short name T787
Test name
Test status
Simulation time 8414788420 ps
CPU time 7.99 seconds
Started Mar 24 02:41:49 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203592 kb
Host smart-14f35fa2-6aff-42e0-9143-80dce81c0df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11023
24655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1102324655
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.361311879
Short name T628
Test name
Test status
Simulation time 8362265110 ps
CPU time 7.39 seconds
Started Mar 24 02:41:50 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203552 kb
Host smart-ed78130c-0e63-4027-9649-4287cd5d5af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36131
1879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.361311879
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.1605720060
Short name T35
Test name
Test status
Simulation time 8405796879 ps
CPU time 9.65 seconds
Started Mar 24 02:41:48 PM PDT 24
Finished Mar 24 02:41:58 PM PDT 24
Peak memory 203536 kb
Host smart-bc1c3ffd-8c06-40db-a008-1f4aa47efe64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16057
20060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.1605720060
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2299737252
Short name T310
Test name
Test status
Simulation time 8375426036 ps
CPU time 8.28 seconds
Started Mar 24 02:41:49 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203568 kb
Host smart-b2499846-5cb1-4f97-bdaa-75cd7f20232d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22997
37252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2299737252
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.645454464
Short name T620
Test name
Test status
Simulation time 8376198835 ps
CPU time 7.47 seconds
Started Mar 24 02:41:49 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203588 kb
Host smart-6cfab108-7ad4-4905-b673-239141eb225c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64545
4464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.645454464
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.894155786
Short name T533
Test name
Test status
Simulation time 8366407735 ps
CPU time 7.31 seconds
Started Mar 24 02:41:50 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203524 kb
Host smart-b002e08f-3715-436a-a45d-fc9b9f28017e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89415
5786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.894155786
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.554377474
Short name T446
Test name
Test status
Simulation time 8376499431 ps
CPU time 7.71 seconds
Started Mar 24 02:41:51 PM PDT 24
Finished Mar 24 02:41:59 PM PDT 24
Peak memory 203476 kb
Host smart-d4f3c93b-190f-4d17-bcdf-247f30755f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55437
7474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.554377474
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.405374803
Short name T306
Test name
Test status
Simulation time 8366936653 ps
CPU time 9.57 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:10 PM PDT 24
Peak memory 203588 kb
Host smart-b0e495b1-8c91-4911-aaf7-37db6f583da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40537
4803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.405374803
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1288995493
Short name T561
Test name
Test status
Simulation time 8359224900 ps
CPU time 7.8 seconds
Started Mar 24 02:41:48 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203568 kb
Host smart-42d5d27f-a946-455e-8480-1d12d6f90c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889
95493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1288995493
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1417259998
Short name T151
Test name
Test status
Simulation time 8473577910 ps
CPU time 8.76 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:08 PM PDT 24
Peak memory 203592 kb
Host smart-64719dc1-08fd-46da-aa0e-cf24072127a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14172
59998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1417259998
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1411463088
Short name T468
Test name
Test status
Simulation time 8365833214 ps
CPU time 7.46 seconds
Started Mar 24 02:41:49 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203544 kb
Host smart-2b6cb222-bf15-43f2-8ddc-0158a70ed5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14114
63088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1411463088
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_enable.2928073284
Short name T663
Test name
Test status
Simulation time 8367271985 ps
CPU time 9.45 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:42:04 PM PDT 24
Peak memory 203528 kb
Host smart-8fee2977-5bce-467d-947d-c49cd7fc05c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29280
73284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2928073284
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1434970992
Short name T836
Test name
Test status
Simulation time 72444078 ps
CPU time 2.11 seconds
Started Mar 24 02:41:50 PM PDT 24
Finished Mar 24 02:41:52 PM PDT 24
Peak memory 203624 kb
Host smart-2c1ef80c-76a4-40d5-a140-de6b74310a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14349
70992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1434970992
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2778484902
Short name T720
Test name
Test status
Simulation time 8363682338 ps
CPU time 7.67 seconds
Started Mar 24 02:41:55 PM PDT 24
Finished Mar 24 02:42:03 PM PDT 24
Peak memory 203568 kb
Host smart-ae33c61c-daab-47b5-b255-c2b6e6fd2b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27784
84902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2778484902
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2384210866
Short name T454
Test name
Test status
Simulation time 8464004998 ps
CPU time 7.44 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203496 kb
Host smart-e1b99d3a-ecc9-4e2c-849e-bbdeec57c880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23842
10866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2384210866
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2279662081
Short name T358
Test name
Test status
Simulation time 8408270997 ps
CPU time 8.04 seconds
Started Mar 24 02:41:49 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203528 kb
Host smart-3100c40d-ab22-41bf-8248-1fc6e2123fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22796
62081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2279662081
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2418463222
Short name T746
Test name
Test status
Simulation time 8363011445 ps
CPU time 7.6 seconds
Started Mar 24 02:41:48 PM PDT 24
Finished Mar 24 02:41:56 PM PDT 24
Peak memory 203544 kb
Host smart-130f4aa5-8f04-4d57-81fa-17957fdb5a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24184
63222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2418463222
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2014216049
Short name T84
Test name
Test status
Simulation time 8399553175 ps
CPU time 9.17 seconds
Started Mar 24 02:41:52 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203576 kb
Host smart-c6b1f336-b61c-4560-9d1e-aa7f681abcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20142
16049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2014216049
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3775265156
Short name T334
Test name
Test status
Simulation time 8386723037 ps
CPU time 6.95 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203540 kb
Host smart-c29f8c1b-8b23-4d74-9e71-6e2b65c7a1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37752
65156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3775265156
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1246327074
Short name T693
Test name
Test status
Simulation time 8373448001 ps
CPU time 8.33 seconds
Started Mar 24 02:41:50 PM PDT 24
Finished Mar 24 02:41:58 PM PDT 24
Peak memory 203608 kb
Host smart-264efa0c-26e8-4604-b6fa-7723d9a9453f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12463
27074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1246327074
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.3041854506
Short name T325
Test name
Test status
Simulation time 24631418 ps
CPU time 0.64 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:41:55 PM PDT 24
Peak memory 203432 kb
Host smart-c35d805e-8bc1-4d60-95cb-01cc38796d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30418
54506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.3041854506
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3759383729
Short name T552
Test name
Test status
Simulation time 8363801221 ps
CPU time 7.48 seconds
Started Mar 24 02:41:51 PM PDT 24
Finished Mar 24 02:41:59 PM PDT 24
Peak memory 203556 kb
Host smart-acccce94-66b5-473b-85f7-574b432dfad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37593
83729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3759383729
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3387735586
Short name T487
Test name
Test status
Simulation time 8380344873 ps
CPU time 7.2 seconds
Started Mar 24 02:41:50 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203576 kb
Host smart-ed62b410-e2a0-4c2b-97de-236c963fe6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33877
35586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3387735586
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1415446095
Short name T24
Test name
Test status
Simulation time 8408554900 ps
CPU time 7.04 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203556 kb
Host smart-97168d92-d1bc-4bbc-be06-6ae814f7f22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154
46095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1415446095
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.348519744
Short name T426
Test name
Test status
Simulation time 8358702207 ps
CPU time 7.84 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203592 kb
Host smart-c78c7372-0172-4af5-af3d-63681d6ac8b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34851
9744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.348519744
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.655997139
Short name T527
Test name
Test status
Simulation time 8471139494 ps
CPU time 7.27 seconds
Started Mar 24 02:41:50 PM PDT 24
Finished Mar 24 02:41:57 PM PDT 24
Peak memory 203604 kb
Host smart-ffd05cdd-3a25-49f5-bbe2-af30146e4656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65599
7139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.655997139
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1923991706
Short name T407
Test name
Test status
Simulation time 8370546529 ps
CPU time 8.33 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:08 PM PDT 24
Peak memory 203572 kb
Host smart-6b7acf47-c2b8-4475-a814-968b967aa8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19239
91706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1923991706
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_enable.2572047731
Short name T721
Test name
Test status
Simulation time 8367113817 ps
CPU time 8.7 seconds
Started Mar 24 02:41:56 PM PDT 24
Finished Mar 24 02:42:05 PM PDT 24
Peak memory 203552 kb
Host smart-e914f405-e030-42c4-beef-734f3abc1153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25720
47731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2572047731
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1767674525
Short name T174
Test name
Test status
Simulation time 8359137829 ps
CPU time 7.49 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203512 kb
Host smart-65065486-8d28-4ac7-ae04-45084490324a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17676
74525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1767674525
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2593920933
Short name T660
Test name
Test status
Simulation time 8413650947 ps
CPU time 8.06 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:42:03 PM PDT 24
Peak memory 203480 kb
Host smart-91ebfa71-56f9-4a27-9a5e-f34e2225f7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25939
20933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2593920933
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.693802386
Short name T25
Test name
Test status
Simulation time 8409230958 ps
CPU time 7.81 seconds
Started Mar 24 02:41:56 PM PDT 24
Finished Mar 24 02:42:04 PM PDT 24
Peak memory 203588 kb
Host smart-a5a8d5ce-a258-405f-874d-0cc522bd18aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69380
2386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.693802386
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3848443942
Short name T545
Test name
Test status
Simulation time 8366306873 ps
CPU time 7.59 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 203588 kb
Host smart-618bc88f-bace-4bc8-8ee9-c4d77db2770f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38484
43942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3848443942
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3715490214
Short name T692
Test name
Test status
Simulation time 8446195092 ps
CPU time 7.52 seconds
Started Mar 24 02:41:55 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 203512 kb
Host smart-d81dd672-75fb-42fb-be58-2fad2cb13432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37154
90214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3715490214
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2665040824
Short name T353
Test name
Test status
Simulation time 8391086666 ps
CPU time 7.02 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:00 PM PDT 24
Peak memory 203572 kb
Host smart-27b0e6e6-7bf0-473e-a138-2e389af8a961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26650
40824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2665040824
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.348414239
Short name T727
Test name
Test status
Simulation time 8368993799 ps
CPU time 7.85 seconds
Started Mar 24 02:41:55 PM PDT 24
Finished Mar 24 02:42:03 PM PDT 24
Peak memory 203492 kb
Host smart-71fc1477-9ac3-45ca-a193-8a9cfac92341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34841
4239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.348414239
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1856657079
Short name T443
Test name
Test status
Simulation time 21789881 ps
CPU time 0.66 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:41:54 PM PDT 24
Peak memory 203396 kb
Host smart-fc0c4f6c-dae1-4dac-a171-f5cce2fa2e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566
57079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1856657079
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1043844549
Short name T647
Test name
Test status
Simulation time 8398050026 ps
CPU time 7.57 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203576 kb
Host smart-1eeae0ac-eb7e-4d83-920a-7e2fa59f45f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10438
44549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1043844549
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2914021204
Short name T456
Test name
Test status
Simulation time 8433221707 ps
CPU time 7.38 seconds
Started Mar 24 02:41:56 PM PDT 24
Finished Mar 24 02:42:03 PM PDT 24
Peak memory 203564 kb
Host smart-810d073c-de90-44b2-9e24-2e5f4a80ef08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29140
21204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2914021204
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3746442137
Short name T573
Test name
Test status
Simulation time 8390766712 ps
CPU time 8.87 seconds
Started Mar 24 02:41:55 PM PDT 24
Finished Mar 24 02:42:04 PM PDT 24
Peak memory 203560 kb
Host smart-99206513-4f05-477c-871a-9c696ae5fdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37464
42137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3746442137
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2761383275
Short name T625
Test name
Test status
Simulation time 8358638243 ps
CPU time 8.46 seconds
Started Mar 24 02:41:56 PM PDT 24
Finished Mar 24 02:42:04 PM PDT 24
Peak memory 203568 kb
Host smart-3a5aaa17-e859-4ae4-9ea6-199b91d6aacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27613
83275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2761383275
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1272374
Short name T794
Test name
Test status
Simulation time 8366853691 ps
CPU time 8.28 seconds
Started Mar 24 02:41:53 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203552 kb
Host smart-50c27723-a4f8-42e9-b0f6-147f08a47355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12723
74 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1272374
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_enable.215877980
Short name T698
Test name
Test status
Simulation time 8369138778 ps
CPU time 7.26 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203552 kb
Host smart-dc98cdbd-9702-49dd-b8a5-3be499769a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21587
7980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.215877980
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2278646013
Short name T732
Test name
Test status
Simulation time 181052723 ps
CPU time 1.94 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 203608 kb
Host smart-41a21632-7ae1-4b1d-87e4-fd3440f03330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22786
46013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2278646013
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2386337484
Short name T849
Test name
Test status
Simulation time 8365308134 ps
CPU time 8.43 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:08 PM PDT 24
Peak memory 203520 kb
Host smart-0c507dc9-7c54-4e4a-98de-8b6349c4dacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23863
37484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2386337484
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.4187229774
Short name T665
Test name
Test status
Simulation time 8411279306 ps
CPU time 8.62 seconds
Started Mar 24 02:41:57 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203556 kb
Host smart-0fb82cd2-3ff1-40d5-9ad9-dd47805c7b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41872
29774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.4187229774
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1322424657
Short name T518
Test name
Test status
Simulation time 8405244845 ps
CPU time 7.24 seconds
Started Mar 24 02:41:54 PM PDT 24
Finished Mar 24 02:42:02 PM PDT 24
Peak memory 203484 kb
Host smart-3b4b1157-7a3c-4b48-b5be-b07317860051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13224
24657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1322424657
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.4251422206
Short name T626
Test name
Test status
Simulation time 8360322252 ps
CPU time 9.52 seconds
Started Mar 24 02:41:56 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203548 kb
Host smart-251d47ad-3887-454c-8c2e-5e8ccbc2ac7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42514
22206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.4251422206
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2228400408
Short name T398
Test name
Test status
Simulation time 8396078092 ps
CPU time 7.19 seconds
Started Mar 24 02:42:02 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 203560 kb
Host smart-a5b05716-3211-43be-84cb-840a8e68216b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22284
00408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2228400408
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.253801059
Short name T656
Test name
Test status
Simulation time 8382960757 ps
CPU time 7.87 seconds
Started Mar 24 02:42:01 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 203548 kb
Host smart-b99a3282-178d-4880-8301-242167da5dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
1059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.253801059
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1262246380
Short name T770
Test name
Test status
Simulation time 32483140 ps
CPU time 0.65 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:01 PM PDT 24
Peak memory 203436 kb
Host smart-cdd2e7d7-9ed8-4389-a085-3beabc8d3909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12622
46380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1262246380
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1112381533
Short name T453
Test name
Test status
Simulation time 8397972111 ps
CPU time 7.39 seconds
Started Mar 24 02:41:58 PM PDT 24
Finished Mar 24 02:42:05 PM PDT 24
Peak memory 203540 kb
Host smart-4ab35784-3df3-4df7-8c14-dce2ae43dcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11123
81533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1112381533
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3094488830
Short name T638
Test name
Test status
Simulation time 8440819508 ps
CPU time 7.58 seconds
Started Mar 24 02:41:58 PM PDT 24
Finished Mar 24 02:42:05 PM PDT 24
Peak memory 203552 kb
Host smart-24281df0-c144-4f7e-a9d4-b9c560f0cd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30944
88830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3094488830
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.2584188817
Short name T422
Test name
Test status
Simulation time 8403631504 ps
CPU time 7.27 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203540 kb
Host smart-af277d0a-5e94-4dca-8748-3d2be40a3340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25841
88817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.2584188817
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3538707268
Short name T301
Test name
Test status
Simulation time 8354216964 ps
CPU time 7.48 seconds
Started Mar 24 02:41:58 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203604 kb
Host smart-c4a006ed-711b-405c-9e59-15164f4a6b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35387
07268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3538707268
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.948971242
Short name T577
Test name
Test status
Simulation time 8371087943 ps
CPU time 8.12 seconds
Started Mar 24 02:42:02 PM PDT 24
Finished Mar 24 02:42:10 PM PDT 24
Peak memory 203572 kb
Host smart-82accf12-6914-45e2-8255-a43c1e0b2a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94897
1242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.948971242
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_enable.3412229431
Short name T679
Test name
Test status
Simulation time 8373327087 ps
CPU time 7.83 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203588 kb
Host smart-44ebe5fd-c5dd-412d-95c3-8ed3cc1944f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34122
29431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.3412229431
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.27950733
Short name T215
Test name
Test status
Simulation time 211250400 ps
CPU time 2.29 seconds
Started Mar 24 02:41:58 PM PDT 24
Finished Mar 24 02:42:00 PM PDT 24
Peak memory 203664 kb
Host smart-95a66b82-8286-472d-a138-e9356cc25396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27950
733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.27950733
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2515369154
Short name T564
Test name
Test status
Simulation time 8359681063 ps
CPU time 8.65 seconds
Started Mar 24 02:41:58 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203536 kb
Host smart-aa50a8c5-981d-4858-bdab-dcabe578f3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25153
69154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2515369154
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2158540546
Short name T360
Test name
Test status
Simulation time 8444857520 ps
CPU time 6.98 seconds
Started Mar 24 02:41:58 PM PDT 24
Finished Mar 24 02:42:06 PM PDT 24
Peak memory 203552 kb
Host smart-38563441-6d07-4386-9f82-adf7b9ce0c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21585
40546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2158540546
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.4188193471
Short name T504
Test name
Test status
Simulation time 8407650259 ps
CPU time 8.56 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 203556 kb
Host smart-2a10fa38-8185-4f65-b32b-0af47a5811f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41881
93471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.4188193471
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2119943948
Short name T514
Test name
Test status
Simulation time 8367422884 ps
CPU time 7.56 seconds
Started Mar 24 02:41:58 PM PDT 24
Finished Mar 24 02:42:05 PM PDT 24
Peak memory 203580 kb
Host smart-be27cd0c-2d12-4804-93f2-10e7cf4b7616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21199
43948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2119943948
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3187236481
Short name T576
Test name
Test status
Simulation time 8411508212 ps
CPU time 9.43 seconds
Started Mar 24 02:42:01 PM PDT 24
Finished Mar 24 02:42:11 PM PDT 24
Peak memory 203496 kb
Host smart-c2f11ae8-088f-44c4-9668-a51b9d1baea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31872
36481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3187236481
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.985119914
Short name T802
Test name
Test status
Simulation time 8374437152 ps
CPU time 7.54 seconds
Started Mar 24 02:42:01 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 203560 kb
Host smart-f048ab29-6204-4606-b5ff-bdb1e9ce1d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98511
9914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.985119914
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1219989815
Short name T752
Test name
Test status
Simulation time 27967022 ps
CPU time 0.66 seconds
Started Mar 24 02:42:00 PM PDT 24
Finished Mar 24 02:42:00 PM PDT 24
Peak memory 203444 kb
Host smart-f1083855-f764-4b73-bc48-6b46e40705ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12199
89815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1219989815
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1414880752
Short name T515
Test name
Test status
Simulation time 8404904314 ps
CPU time 7.95 seconds
Started Mar 24 02:41:59 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203468 kb
Host smart-9e159e06-a3de-408c-bd35-e979d6407b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14148
80752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1414880752
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.11042974
Short name T823
Test name
Test status
Simulation time 8464041180 ps
CPU time 7.86 seconds
Started Mar 24 02:42:02 PM PDT 24
Finished Mar 24 02:42:10 PM PDT 24
Peak memory 203564 kb
Host smart-2140adea-2302-4dae-ad86-0e088e8abb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042
974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.11042974
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.250952641
Short name T386
Test name
Test status
Simulation time 8379138383 ps
CPU time 7.55 seconds
Started Mar 24 02:41:57 PM PDT 24
Finished Mar 24 02:42:05 PM PDT 24
Peak memory 203576 kb
Host smart-e7af419e-0d0f-489f-9bd5-65cdb8fea3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25095
2641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.250952641
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2605019313
Short name T677
Test name
Test status
Simulation time 8357025923 ps
CPU time 8.55 seconds
Started Mar 24 02:41:58 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203536 kb
Host smart-3a15b5ca-5599-4f5c-9cd5-e8205a98bcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26050
19313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2605019313
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1786519634
Short name T491
Test name
Test status
Simulation time 8372392950 ps
CPU time 8.96 seconds
Started Mar 24 02:42:04 PM PDT 24
Finished Mar 24 02:42:13 PM PDT 24
Peak memory 203536 kb
Host smart-c572ada4-5c5d-47f6-bdcc-1b8b8856e1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17865
19634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1786519634
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_enable.1562293440
Short name T534
Test name
Test status
Simulation time 8371838038 ps
CPU time 8.22 seconds
Started Mar 24 02:42:05 PM PDT 24
Finished Mar 24 02:42:13 PM PDT 24
Peak memory 203780 kb
Host smart-0be4a468-954a-4573-bcb1-35459ec01156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15622
93440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1562293440
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.4247724363
Short name T594
Test name
Test status
Simulation time 65270606 ps
CPU time 1.87 seconds
Started Mar 24 02:42:03 PM PDT 24
Finished Mar 24 02:42:05 PM PDT 24
Peak memory 203664 kb
Host smart-11722cf9-5448-44c2-9091-e6ec0c543229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
24363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.4247724363
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2738866264
Short name T169
Test name
Test status
Simulation time 8357956738 ps
CPU time 7.53 seconds
Started Mar 24 02:42:05 PM PDT 24
Finished Mar 24 02:42:13 PM PDT 24
Peak memory 203532 kb
Host smart-9f148353-6e7a-4d67-a95f-1c42f98be787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27388
66264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2738866264
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1169396737
Short name T237
Test name
Test status
Simulation time 8395540680 ps
CPU time 9.05 seconds
Started Mar 24 02:42:05 PM PDT 24
Finished Mar 24 02:42:14 PM PDT 24
Peak memory 203572 kb
Host smart-f243930f-7e6f-43a8-a4ed-9e580ad2a10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693
96737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1169396737
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1977391163
Short name T350
Test name
Test status
Simulation time 8411760272 ps
CPU time 8.22 seconds
Started Mar 24 02:42:02 PM PDT 24
Finished Mar 24 02:42:10 PM PDT 24
Peak memory 203604 kb
Host smart-61ecdc8c-e969-4f19-b604-ff47e7c97e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19773
91163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1977391163
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2885284249
Short name T393
Test name
Test status
Simulation time 8369236148 ps
CPU time 9.3 seconds
Started Mar 24 02:42:05 PM PDT 24
Finished Mar 24 02:42:15 PM PDT 24
Peak memory 203576 kb
Host smart-3be115cb-fc5b-40c2-baea-a8ca6bf6fe65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28852
84249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2885284249
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2674465775
Short name T492
Test name
Test status
Simulation time 8392732263 ps
CPU time 7.32 seconds
Started Mar 24 02:42:02 PM PDT 24
Finished Mar 24 02:42:10 PM PDT 24
Peak memory 203500 kb
Host smart-eec51cf6-8af5-4e22-85f6-653ed57838e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
65775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2674465775
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2104287692
Short name T316
Test name
Test status
Simulation time 8375081331 ps
CPU time 7.91 seconds
Started Mar 24 02:42:01 PM PDT 24
Finished Mar 24 02:42:09 PM PDT 24
Peak memory 203592 kb
Host smart-3c5643f0-cada-4d3e-a0f8-f859f528993b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042
87692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2104287692
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.969426194
Short name T409
Test name
Test status
Simulation time 30943552 ps
CPU time 0.64 seconds
Started Mar 24 02:42:06 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203376 kb
Host smart-87d84c1a-8a7e-4341-8880-3360bbc32964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96942
6194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.969426194
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2641649051
Short name T801
Test name
Test status
Simulation time 8395020355 ps
CPU time 7.35 seconds
Started Mar 24 02:42:05 PM PDT 24
Finished Mar 24 02:42:13 PM PDT 24
Peak memory 203580 kb
Host smart-847ee39a-6aa8-426e-ae87-fcdb06ce29c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26416
49051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2641649051
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1180550556
Short name T686
Test name
Test status
Simulation time 8443650972 ps
CPU time 7.88 seconds
Started Mar 24 02:42:03 PM PDT 24
Finished Mar 24 02:42:11 PM PDT 24
Peak memory 203552 kb
Host smart-fd85ae88-2f25-40a1-8299-533ae37469d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
50556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1180550556
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.147445368
Short name T636
Test name
Test status
Simulation time 8382563197 ps
CPU time 8.08 seconds
Started Mar 24 02:42:03 PM PDT 24
Finished Mar 24 02:42:11 PM PDT 24
Peak memory 203564 kb
Host smart-d29ebe80-ca87-431a-9fdc-8cf162aedaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
5368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.147445368
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.140701810
Short name T634
Test name
Test status
Simulation time 8362206061 ps
CPU time 9.67 seconds
Started Mar 24 02:42:03 PM PDT 24
Finished Mar 24 02:42:13 PM PDT 24
Peak memory 203620 kb
Host smart-172b0ad2-7b8b-4d29-aa5a-e4d6916434a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14070
1810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.140701810
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2166453937
Short name T158
Test name
Test status
Simulation time 8475141549 ps
CPU time 7.88 seconds
Started Mar 24 02:42:03 PM PDT 24
Finished Mar 24 02:42:11 PM PDT 24
Peak memory 203548 kb
Host smart-7e4ca4ad-e217-4675-986e-e3a8b4cd2a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21664
53937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2166453937
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1033338596
Short name T609
Test name
Test status
Simulation time 8372065663 ps
CPU time 8.23 seconds
Started Mar 24 02:42:20 PM PDT 24
Finished Mar 24 02:42:28 PM PDT 24
Peak memory 203492 kb
Host smart-1dd96b8a-f7e9-4ccf-823b-05e6386424a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10333
38596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1033338596
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_enable.2300127120
Short name T646
Test name
Test status
Simulation time 8368695803 ps
CPU time 7.27 seconds
Started Mar 24 02:42:07 PM PDT 24
Finished Mar 24 02:42:14 PM PDT 24
Peak memory 203548 kb
Host smart-a4d33b2f-18ae-48b8-b9a5-936462f6320e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23001
27120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2300127120
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.692881726
Short name T459
Test name
Test status
Simulation time 201853166 ps
CPU time 2.13 seconds
Started Mar 24 02:42:08 PM PDT 24
Finished Mar 24 02:42:10 PM PDT 24
Peak memory 203612 kb
Host smart-f14600fb-8d99-4644-991a-9506ce8c95f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69288
1726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.692881726
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.749256878
Short name T179
Test name
Test status
Simulation time 8361877380 ps
CPU time 9.78 seconds
Started Mar 24 02:42:07 PM PDT 24
Finished Mar 24 02:42:17 PM PDT 24
Peak memory 203496 kb
Host smart-ee58bbb8-08ed-4ef1-8940-4f10078645f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74925
6878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.749256878
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.4254765290
Short name T117
Test name
Test status
Simulation time 8448541204 ps
CPU time 8.11 seconds
Started Mar 24 02:42:06 PM PDT 24
Finished Mar 24 02:42:14 PM PDT 24
Peak memory 203508 kb
Host smart-007c133a-224f-4651-8688-0b8b9d856550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42547
65290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.4254765290
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1007049897
Short name T615
Test name
Test status
Simulation time 8405296857 ps
CPU time 7.79 seconds
Started Mar 24 02:42:20 PM PDT 24
Finished Mar 24 02:42:28 PM PDT 24
Peak memory 203496 kb
Host smart-56dc7601-ffc5-4e92-8b5f-a65bedb56cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10070
49897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1007049897
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2100016552
Short name T717
Test name
Test status
Simulation time 8360928290 ps
CPU time 7.26 seconds
Started Mar 24 02:42:10 PM PDT 24
Finished Mar 24 02:42:17 PM PDT 24
Peak memory 203544 kb
Host smart-ff064db4-e277-4ead-957f-5ae58709558f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21000
16552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2100016552
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1057190984
Short name T400
Test name
Test status
Simulation time 8383613915 ps
CPU time 7.21 seconds
Started Mar 24 02:42:20 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203492 kb
Host smart-bddfb62f-9627-49b3-a303-6c20c95a8458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10571
90984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1057190984
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1139278446
Short name T352
Test name
Test status
Simulation time 8363305257 ps
CPU time 8.97 seconds
Started Mar 24 02:42:13 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203592 kb
Host smart-19baeefe-6752-4cb8-9816-b46bc247fb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11392
78446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1139278446
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2421051293
Short name T676
Test name
Test status
Simulation time 27185693 ps
CPU time 0.71 seconds
Started Mar 24 02:42:07 PM PDT 24
Finished Mar 24 02:42:07 PM PDT 24
Peak memory 203376 kb
Host smart-b4b73be3-a8ff-4c7f-8958-cbca4ef67ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24210
51293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2421051293
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.140516134
Short name T842
Test name
Test status
Simulation time 8384917134 ps
CPU time 7.94 seconds
Started Mar 24 02:42:10 PM PDT 24
Finished Mar 24 02:42:18 PM PDT 24
Peak memory 203560 kb
Host smart-79d524ba-c64c-424b-b9d8-d1da18ce3efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14051
6134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.140516134
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.789702598
Short name T33
Test name
Test status
Simulation time 8395366817 ps
CPU time 7.11 seconds
Started Mar 24 02:42:20 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203488 kb
Host smart-2c3a09dc-3785-4f4a-8bf7-5644e2e0a327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78970
2598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.789702598
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.3396371126
Short name T484
Test name
Test status
Simulation time 8403590565 ps
CPU time 8.49 seconds
Started Mar 24 02:42:11 PM PDT 24
Finished Mar 24 02:42:20 PM PDT 24
Peak memory 203528 kb
Host smart-6a23d5ed-4b09-481c-a496-d2a0073220a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
71126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.3396371126
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.171741446
Short name T662
Test name
Test status
Simulation time 8358037831 ps
CPU time 9.01 seconds
Started Mar 24 02:42:20 PM PDT 24
Finished Mar 24 02:42:29 PM PDT 24
Peak memory 203152 kb
Host smart-3bc5613a-d53e-403c-89dd-178da239f09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17174
1446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.171741446
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2599709156
Short name T157
Test name
Test status
Simulation time 8474666801 ps
CPU time 8.98 seconds
Started Mar 24 02:42:04 PM PDT 24
Finished Mar 24 02:42:13 PM PDT 24
Peak memory 203488 kb
Host smart-43931f71-e8b6-45de-b8c6-4d5d139a4c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25997
09156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2599709156
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.4083007547
Short name T774
Test name
Test status
Simulation time 8369998273 ps
CPU time 7.59 seconds
Started Mar 24 02:42:16 PM PDT 24
Finished Mar 24 02:42:24 PM PDT 24
Peak memory 203492 kb
Host smart-f2543933-f9ec-4757-af23-d5acc7e27ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40830
07547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.4083007547
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_enable.3689492753
Short name T741
Test name
Test status
Simulation time 8369556265 ps
CPU time 9.32 seconds
Started Mar 24 02:42:07 PM PDT 24
Finished Mar 24 02:42:16 PM PDT 24
Peak memory 203604 kb
Host smart-5b0e5ad6-df5f-41b3-84b5-85fda8b3442e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36894
92753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3689492753
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1399693347
Short name T465
Test name
Test status
Simulation time 121819239 ps
CPU time 1.49 seconds
Started Mar 24 02:42:20 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203288 kb
Host smart-041de480-09e8-4dd7-8301-b6894985a908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13996
93347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1399693347
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3993653286
Short name T817
Test name
Test status
Simulation time 8359703182 ps
CPU time 7.19 seconds
Started Mar 24 02:42:11 PM PDT 24
Finished Mar 24 02:42:23 PM PDT 24
Peak memory 203472 kb
Host smart-b7665d28-5660-4ca6-807f-b5049a45a6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936
53286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3993653286
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.376297348
Short name T225
Test name
Test status
Simulation time 8449494793 ps
CPU time 7.27 seconds
Started Mar 24 02:42:09 PM PDT 24
Finished Mar 24 02:42:16 PM PDT 24
Peak memory 203572 kb
Host smart-67f2cc92-7694-4e13-abec-4232c7e3ab61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37629
7348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.376297348
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.773108433
Short name T494
Test name
Test status
Simulation time 8409669054 ps
CPU time 7.1 seconds
Started Mar 24 02:42:06 PM PDT 24
Finished Mar 24 02:42:14 PM PDT 24
Peak memory 203580 kb
Host smart-ed8f51d4-99a8-46c0-9d7d-7958639868a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77310
8433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.773108433
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.4171168868
Short name T617
Test name
Test status
Simulation time 8366501587 ps
CPU time 9.2 seconds
Started Mar 24 02:42:17 PM PDT 24
Finished Mar 24 02:42:26 PM PDT 24
Peak memory 203580 kb
Host smart-8430c61f-66da-49e5-afcc-f3232c9d9431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711
68868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.4171168868
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2698567505
Short name T93
Test name
Test status
Simulation time 8395078724 ps
CPU time 7.52 seconds
Started Mar 24 02:42:15 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203552 kb
Host smart-312735df-1d35-4b1b-893d-fa5df1932942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26985
67505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2698567505
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.72339030
Short name T804
Test name
Test status
Simulation time 8379198027 ps
CPU time 7.65 seconds
Started Mar 24 02:42:15 PM PDT 24
Finished Mar 24 02:42:23 PM PDT 24
Peak memory 203496 kb
Host smart-c6948e38-d5b2-48c7-acbe-d468e18ce3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72339
030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.72339030
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2536726123
Short name T754
Test name
Test status
Simulation time 8388637461 ps
CPU time 7.22 seconds
Started Mar 24 02:42:13 PM PDT 24
Finished Mar 24 02:42:20 PM PDT 24
Peak memory 203624 kb
Host smart-116ba186-a25e-420f-9703-90cfbad1f2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25367
26123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2536726123
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2641375974
Short name T696
Test name
Test status
Simulation time 24386275 ps
CPU time 0.61 seconds
Started Mar 24 02:42:14 PM PDT 24
Finished Mar 24 02:42:15 PM PDT 24
Peak memory 203464 kb
Host smart-2bda9125-4d4a-438a-ba24-ef3a71aefb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
75974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2641375974
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.64766188
Short name T379
Test name
Test status
Simulation time 8359693449 ps
CPU time 9.21 seconds
Started Mar 24 02:42:12 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203556 kb
Host smart-877cec80-ec6b-40d5-b87e-e81944e96ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64766
188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.64766188
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.4060386305
Short name T776
Test name
Test status
Simulation time 8385996964 ps
CPU time 7.16 seconds
Started Mar 24 02:42:11 PM PDT 24
Finished Mar 24 02:42:19 PM PDT 24
Peak memory 203536 kb
Host smart-b1494b8d-2448-455d-9716-899c1d240298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603
86305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.4060386305
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.817591572
Short name T718
Test name
Test status
Simulation time 8388609857 ps
CPU time 7.7 seconds
Started Mar 24 02:42:14 PM PDT 24
Finished Mar 24 02:42:21 PM PDT 24
Peak memory 203548 kb
Host smart-28489506-fcf8-455a-977b-f37c996d80b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81759
1572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.817591572
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.558432576
Short name T342
Test name
Test status
Simulation time 8363313388 ps
CPU time 7.37 seconds
Started Mar 24 02:42:13 PM PDT 24
Finished Mar 24 02:42:21 PM PDT 24
Peak memory 203600 kb
Host smart-7114bd8a-111e-4b55-8778-ab00ac5bbb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55843
2576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.558432576
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.318864032
Short name T739
Test name
Test status
Simulation time 8476163226 ps
CPU time 8.5 seconds
Started Mar 24 02:42:07 PM PDT 24
Finished Mar 24 02:42:15 PM PDT 24
Peak memory 203568 kb
Host smart-243eaa7f-38e3-470c-9420-90726955c92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31886
4032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.318864032
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3888898543
Short name T760
Test name
Test status
Simulation time 8367365570 ps
CPU time 9.26 seconds
Started Mar 24 02:42:11 PM PDT 24
Finished Mar 24 02:42:21 PM PDT 24
Peak memory 203480 kb
Host smart-e078c1e0-c234-4833-93c5-71bfb5dacea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38888
98543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3888898543
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_enable.527010760
Short name T822
Test name
Test status
Simulation time 8370074368 ps
CPU time 7.57 seconds
Started Mar 24 02:42:14 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203588 kb
Host smart-dcaadf0b-5392-4bcf-8d56-2c3c9b22ba3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52701
0760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.527010760
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1830351910
Short name T705
Test name
Test status
Simulation time 55789620 ps
CPU time 1.56 seconds
Started Mar 24 02:42:15 PM PDT 24
Finished Mar 24 02:42:16 PM PDT 24
Peak memory 203592 kb
Host smart-61e17372-a210-4975-bcdb-5bd77a7e31c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18303
51910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1830351910
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1009544306
Short name T853
Test name
Test status
Simulation time 8362713700 ps
CPU time 8.44 seconds
Started Mar 24 02:42:17 PM PDT 24
Finished Mar 24 02:42:26 PM PDT 24
Peak memory 203496 kb
Host smart-4d53ce0d-7b43-42d7-9729-8766a8908149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10095
44306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1009544306
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.1585833145
Short name T684
Test name
Test status
Simulation time 8389613651 ps
CPU time 7.05 seconds
Started Mar 24 02:42:12 PM PDT 24
Finished Mar 24 02:42:19 PM PDT 24
Peak memory 203552 kb
Host smart-8292eea3-9224-443c-810a-fa7808024085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15858
33145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.1585833145
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1813400087
Short name T734
Test name
Test status
Simulation time 8409159688 ps
CPU time 9.35 seconds
Started Mar 24 02:42:14 PM PDT 24
Finished Mar 24 02:42:23 PM PDT 24
Peak memory 203788 kb
Host smart-a7e1083f-971b-4374-bbd2-b7593c39674f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18134
00087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1813400087
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3780412161
Short name T566
Test name
Test status
Simulation time 8360234556 ps
CPU time 7.48 seconds
Started Mar 24 02:42:13 PM PDT 24
Finished Mar 24 02:42:21 PM PDT 24
Peak memory 203560 kb
Host smart-90dcdd3e-fe65-49e6-af3c-3608bacc181a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37804
12161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3780412161
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.246427127
Short name T763
Test name
Test status
Simulation time 8425920334 ps
CPU time 9.98 seconds
Started Mar 24 02:42:24 PM PDT 24
Finished Mar 24 02:42:34 PM PDT 24
Peak memory 203552 kb
Host smart-ba45df44-8cdd-4786-b580-2fdba7374aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24642
7127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.246427127
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1564873734
Short name T374
Test name
Test status
Simulation time 8398205660 ps
CPU time 9.15 seconds
Started Mar 24 02:42:14 PM PDT 24
Finished Mar 24 02:42:23 PM PDT 24
Peak memory 203540 kb
Host smart-242aa3e7-c737-4b48-b2f9-f81a2a67fe64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15648
73734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1564873734
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1888323593
Short name T640
Test name
Test status
Simulation time 8370599658 ps
CPU time 7.76 seconds
Started Mar 24 02:42:14 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203544 kb
Host smart-26bca495-c4ed-42d6-9b30-430d556629a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18883
23593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1888323593
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2487866620
Short name T42
Test name
Test status
Simulation time 26135568 ps
CPU time 0.65 seconds
Started Mar 24 02:42:13 PM PDT 24
Finished Mar 24 02:42:14 PM PDT 24
Peak memory 203464 kb
Host smart-2dff1119-a9a1-47ac-a294-ae0a914b0d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24878
66620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2487866620
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2115032618
Short name T859
Test name
Test status
Simulation time 8393536926 ps
CPU time 7.4 seconds
Started Mar 24 02:42:14 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203536 kb
Host smart-e7d805fa-edd4-4322-ba9b-59f075b30cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21150
32618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2115032618
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1309694868
Short name T482
Test name
Test status
Simulation time 8395853481 ps
CPU time 7.27 seconds
Started Mar 24 02:42:14 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203484 kb
Host smart-b74b57be-f0a3-4fad-97ab-3c4d4e8cee2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13096
94868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1309694868
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.1344521221
Short name T675
Test name
Test status
Simulation time 8381869564 ps
CPU time 7.53 seconds
Started Mar 24 02:42:12 PM PDT 24
Finished Mar 24 02:42:20 PM PDT 24
Peak memory 203576 kb
Host smart-f65d5627-bd2d-4f0a-b1f3-fb40db112465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13445
21221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.1344521221
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3793472953
Short name T313
Test name
Test status
Simulation time 8358205984 ps
CPU time 8.08 seconds
Started Mar 24 02:42:12 PM PDT 24
Finished Mar 24 02:42:21 PM PDT 24
Peak memory 203780 kb
Host smart-6e0a157c-b514-4171-8033-5c412be19759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37934
72953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3793472953
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3963073301
Short name T846
Test name
Test status
Simulation time 8478059542 ps
CPU time 7.68 seconds
Started Mar 24 02:42:12 PM PDT 24
Finished Mar 24 02:42:20 PM PDT 24
Peak memory 203604 kb
Host smart-2cd968d6-1784-4f5d-9803-aea0e65b3649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39630
73301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3963073301
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2235529465
Short name T538
Test name
Test status
Simulation time 8373792275 ps
CPU time 7.35 seconds
Started Mar 24 02:42:23 PM PDT 24
Finished Mar 24 02:42:30 PM PDT 24
Peak memory 203464 kb
Host smart-25ec21c4-3e0c-4fa7-beda-bf43c122d0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22355
29465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2235529465
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_enable.2427666346
Short name T866
Test name
Test status
Simulation time 8369009372 ps
CPU time 7.9 seconds
Started Mar 24 02:42:19 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203548 kb
Host smart-dc4782da-3f8d-4325-bcc9-e36601696ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24276
66346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2427666346
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1252373708
Short name T166
Test name
Test status
Simulation time 8359625373 ps
CPU time 7.45 seconds
Started Mar 24 02:42:24 PM PDT 24
Finished Mar 24 02:42:32 PM PDT 24
Peak memory 203484 kb
Host smart-d624c3bf-008d-4b57-aaec-3b6536f0413f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12523
73708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1252373708
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1573430217
Short name T777
Test name
Test status
Simulation time 8412426610 ps
CPU time 7.49 seconds
Started Mar 24 02:42:16 PM PDT 24
Finished Mar 24 02:42:23 PM PDT 24
Peak memory 203556 kb
Host smart-31636994-7d4d-4b98-8166-08258affec1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15734
30217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1573430217
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2469417787
Short name T593
Test name
Test status
Simulation time 8410872899 ps
CPU time 7.97 seconds
Started Mar 24 02:42:21 PM PDT 24
Finished Mar 24 02:42:29 PM PDT 24
Peak memory 203576 kb
Host smart-8ba0468f-f3d7-4889-a607-f0b35e08cbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24694
17787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2469417787
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2328397013
Short name T612
Test name
Test status
Simulation time 8367935711 ps
CPU time 7.82 seconds
Started Mar 24 02:42:17 PM PDT 24
Finished Mar 24 02:42:25 PM PDT 24
Peak memory 203536 kb
Host smart-4d660cb0-7fa0-40f5-887b-d8aa3589bf6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23283
97013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2328397013
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1915710655
Short name T110
Test name
Test status
Simulation time 8411950837 ps
CPU time 9.25 seconds
Started Mar 24 02:42:21 PM PDT 24
Finished Mar 24 02:42:30 PM PDT 24
Peak memory 203572 kb
Host smart-a37ef45f-ecda-4411-9e77-83beb7f1ae59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19157
10655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1915710655
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1276980585
Short name T680
Test name
Test status
Simulation time 8399307555 ps
CPU time 7.77 seconds
Started Mar 24 02:42:17 PM PDT 24
Finished Mar 24 02:42:24 PM PDT 24
Peak memory 203552 kb
Host smart-c6845a3e-e4ae-449d-b070-58c883ea6629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12769
80585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1276980585
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1782729683
Short name T833
Test name
Test status
Simulation time 8368012066 ps
CPU time 10.08 seconds
Started Mar 24 02:42:16 PM PDT 24
Finished Mar 24 02:42:26 PM PDT 24
Peak memory 203604 kb
Host smart-1e9a7e8a-7577-4d60-9529-952a7f5f39e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17827
29683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1782729683
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1643599585
Short name T788
Test name
Test status
Simulation time 21613422 ps
CPU time 0.65 seconds
Started Mar 24 02:42:28 PM PDT 24
Finished Mar 24 02:42:28 PM PDT 24
Peak memory 203400 kb
Host smart-f26d79c3-ac4c-4850-b4d8-895738aa67ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16435
99585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1643599585
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.4266875640
Short name T365
Test name
Test status
Simulation time 8401611533 ps
CPU time 7.66 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:30 PM PDT 24
Peak memory 203580 kb
Host smart-d12a1648-38fc-47bd-9919-ea1c8115c62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668
75640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.4266875640
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2817436561
Short name T536
Test name
Test status
Simulation time 8383553441 ps
CPU time 7.68 seconds
Started Mar 24 02:42:24 PM PDT 24
Finished Mar 24 02:42:31 PM PDT 24
Peak memory 203556 kb
Host smart-d5b06b1d-d843-45e2-af9b-fbd1c542efe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28174
36561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2817436561
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.484401764
Short name T307
Test name
Test status
Simulation time 8367119523 ps
CPU time 8.74 seconds
Started Mar 24 02:42:19 PM PDT 24
Finished Mar 24 02:42:28 PM PDT 24
Peak memory 203568 kb
Host smart-09cb16a3-363b-4a40-a837-e768fcf3c74f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48440
1764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.484401764
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3168904367
Short name T586
Test name
Test status
Simulation time 8361267144 ps
CPU time 8.37 seconds
Started Mar 24 02:42:28 PM PDT 24
Finished Mar 24 02:42:36 PM PDT 24
Peak memory 203540 kb
Host smart-dcdff75f-b219-4ffc-b52f-4b7b2f7cbea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689
04367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3168904367
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1080098449
Short name T156
Test name
Test status
Simulation time 8470143672 ps
CPU time 7.98 seconds
Started Mar 24 02:42:28 PM PDT 24
Finished Mar 24 02:42:36 PM PDT 24
Peak memory 203584 kb
Host smart-bc51868b-8d8f-4ebd-ae55-47dafa083966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10800
98449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1080098449
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3047836175
Short name T236
Test name
Test status
Simulation time 8372507425 ps
CPU time 7.99 seconds
Started Mar 24 02:40:56 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 203512 kb
Host smart-2a1ee746-1e32-414d-abf7-b1b4dd697cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30478
36175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3047836175
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_enable.3665579733
Short name T427
Test name
Test status
Simulation time 8370712656 ps
CPU time 7.22 seconds
Started Mar 24 02:40:54 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203496 kb
Host smart-42dde304-2262-4512-8e4f-7f948c392883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36655
79733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3665579733
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.528598031
Short name T241
Test name
Test status
Simulation time 54868373 ps
CPU time 1.59 seconds
Started Mar 24 02:40:51 PM PDT 24
Finished Mar 24 02:40:52 PM PDT 24
Peak memory 203608 kb
Host smart-12a8a614-e73d-45bd-b692-daf08905f25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52859
8031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.528598031
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3235727051
Short name T180
Test name
Test status
Simulation time 8360290600 ps
CPU time 8.73 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:41:01 PM PDT 24
Peak memory 203528 kb
Host smart-a39c4869-2672-44e3-a325-3fe240f75c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32357
27051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3235727051
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2928362494
Short name T120
Test name
Test status
Simulation time 8397286669 ps
CPU time 7.04 seconds
Started Mar 24 02:40:57 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 203520 kb
Host smart-2417d0d9-27b8-4bc9-84f6-d395d2457961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29283
62494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2928362494
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.424916668
Short name T523
Test name
Test status
Simulation time 8402542827 ps
CPU time 7.23 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203544 kb
Host smart-c3201ee3-0c1c-4b64-86bd-f389822f26cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42491
6668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.424916668
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1021832588
Short name T77
Test name
Test status
Simulation time 8364434409 ps
CPU time 6.95 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203544 kb
Host smart-c0c8fe5a-ade6-4c0a-8d28-566709d8a54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10218
32588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1021832588
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1839836887
Short name T106
Test name
Test status
Simulation time 8427990210 ps
CPU time 7.33 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203540 kb
Host smart-17d8c913-e0aa-4cba-877f-5adcfc51b2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18398
36887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1839836887
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.4134212579
Short name T868
Test name
Test status
Simulation time 8382542904 ps
CPU time 7.39 seconds
Started Mar 24 02:40:57 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 203520 kb
Host smart-5def8652-8031-4af0-855a-316b798aca1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342
12579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.4134212579
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.71118038
Short name T328
Test name
Test status
Simulation time 8372211992 ps
CPU time 7.99 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:41:00 PM PDT 24
Peak memory 203528 kb
Host smart-610ec8cf-3340-4249-9491-a4ad704bcc18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71118
038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.71118038
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.238463132
Short name T631
Test name
Test status
Simulation time 25630445 ps
CPU time 0.65 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:40:53 PM PDT 24
Peak memory 203420 kb
Host smart-1686ba5d-9244-4402-b98d-9f82f7df7eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23846
3132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.238463132
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.386277167
Short name T605
Test name
Test status
Simulation time 8372785908 ps
CPU time 8.19 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 203548 kb
Host smart-5c8ebf60-ca82-4b6e-a2e8-bf46fb029f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38627
7167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.386277167
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.243151741
Short name T136
Test name
Test status
Simulation time 8426459842 ps
CPU time 7.52 seconds
Started Mar 24 02:40:54 PM PDT 24
Finished Mar 24 02:41:01 PM PDT 24
Peak memory 203804 kb
Host smart-65ea2749-1641-44fa-bcfe-8d44134cb036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24315
1741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.243151741
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.1749145761
Short name T522
Test name
Test status
Simulation time 8365178135 ps
CPU time 7.45 seconds
Started Mar 24 02:40:54 PM PDT 24
Finished Mar 24 02:41:02 PM PDT 24
Peak memory 203564 kb
Host smart-f22fbaba-8b14-48a4-af44-8f96e16a68e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17491
45761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.1749145761
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3271621601
Short name T56
Test name
Test status
Simulation time 168969122 ps
CPU time 1.03 seconds
Started Mar 24 02:40:54 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 220492 kb
Host smart-a37f711b-c765-429f-965a-04e1898c111d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3271621601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3271621601
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.115813993
Short name T238
Test name
Test status
Simulation time 8355913031 ps
CPU time 8.84 seconds
Started Mar 24 02:40:52 PM PDT 24
Finished Mar 24 02:41:01 PM PDT 24
Peak memory 203564 kb
Host smart-8207a874-f952-4fab-900a-b0916ec0bd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11581
3993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.115813993
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2901950936
Short name T146
Test name
Test status
Simulation time 8477647211 ps
CPU time 7.88 seconds
Started Mar 24 02:40:54 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203516 kb
Host smart-2aaf044e-c3a1-4c22-8861-693dace098d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29019
50936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2901950936
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.43307006
Short name T338
Test name
Test status
Simulation time 8370519756 ps
CPU time 7.65 seconds
Started Mar 24 02:42:24 PM PDT 24
Finished Mar 24 02:42:32 PM PDT 24
Peak memory 203528 kb
Host smart-d2074124-f180-4a53-9568-cba018b25703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43307
006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.43307006
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2214263256
Short name T444
Test name
Test status
Simulation time 69384095 ps
CPU time 1.92 seconds
Started Mar 24 02:42:25 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203588 kb
Host smart-c419c8a7-fd43-462b-9aad-6aaaa74bfb60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22142
63256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2214263256
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2020469069
Short name T716
Test name
Test status
Simulation time 8357999383 ps
CPU time 8.33 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:30 PM PDT 24
Peak memory 203500 kb
Host smart-2f908ceb-6faf-46a4-a29d-1a735f65206e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20204
69069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2020469069
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2925582998
Short name T138
Test name
Test status
Simulation time 8403265351 ps
CPU time 8.79 seconds
Started Mar 24 02:42:16 PM PDT 24
Finished Mar 24 02:42:24 PM PDT 24
Peak memory 203556 kb
Host smart-2458feb4-1d15-4ed7-862e-20c757fb73d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29255
82998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2925582998
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.386858894
Short name T623
Test name
Test status
Simulation time 8408059340 ps
CPU time 7.94 seconds
Started Mar 24 02:42:24 PM PDT 24
Finished Mar 24 02:42:32 PM PDT 24
Peak memory 203604 kb
Host smart-e6ec0493-caab-4dbc-8dd3-ae36a70a8520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38685
8894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.386858894
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3373076265
Short name T816
Test name
Test status
Simulation time 8361974707 ps
CPU time 8.3 seconds
Started Mar 24 02:42:17 PM PDT 24
Finished Mar 24 02:42:26 PM PDT 24
Peak memory 203580 kb
Host smart-8a7e682d-e37c-4c01-8842-6baa5d9b3c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33730
76265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3373076265
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2490966071
Short name T95
Test name
Test status
Simulation time 8402663175 ps
CPU time 7.59 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:30 PM PDT 24
Peak memory 203556 kb
Host smart-a9bc0a80-7a17-45ee-ba51-4e44b5a7a495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24909
66071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2490966071
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.80350870
Short name T495
Test name
Test status
Simulation time 8389675430 ps
CPU time 8.44 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:30 PM PDT 24
Peak memory 203500 kb
Host smart-a40d5702-bef7-4e52-b128-7f752d783ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80350
870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.80350870
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3356582728
Short name T569
Test name
Test status
Simulation time 8383427690 ps
CPU time 7.53 seconds
Started Mar 24 02:42:16 PM PDT 24
Finished Mar 24 02:42:24 PM PDT 24
Peak memory 203560 kb
Host smart-93d07ebe-ac87-4039-92f3-e3e975152ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
82728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3356582728
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.4104904251
Short name T642
Test name
Test status
Simulation time 30340313 ps
CPU time 0.65 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:31 PM PDT 24
Peak memory 203420 kb
Host smart-1fd95fef-3471-4931-984f-2e46aa95c6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41049
04251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.4104904251
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3869506828
Short name T627
Test name
Test status
Simulation time 8369956324 ps
CPU time 7.72 seconds
Started Mar 24 02:42:18 PM PDT 24
Finished Mar 24 02:42:25 PM PDT 24
Peak memory 203560 kb
Host smart-304fddb9-9683-409d-b92c-c209ccc7c2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38695
06828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3869506828
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.770106361
Short name T510
Test name
Test status
Simulation time 8410900267 ps
CPU time 7.63 seconds
Started Mar 24 02:42:15 PM PDT 24
Finished Mar 24 02:42:22 PM PDT 24
Peak memory 203568 kb
Host smart-d97e5a5b-1195-44f4-b393-457a57fd3f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77010
6361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.770106361
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3291921957
Short name T483
Test name
Test status
Simulation time 8402400466 ps
CPU time 9.28 seconds
Started Mar 24 02:42:23 PM PDT 24
Finished Mar 24 02:42:32 PM PDT 24
Peak memory 203676 kb
Host smart-04e87cf6-5b28-48fc-a81b-70fc90c2eeb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32919
21957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3291921957
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3807532153
Short name T369
Test name
Test status
Simulation time 8356220697 ps
CPU time 7.88 seconds
Started Mar 24 02:42:23 PM PDT 24
Finished Mar 24 02:42:31 PM PDT 24
Peak memory 203600 kb
Host smart-1bd8c16f-1e86-4fec-960e-de72bb4b57ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38075
32153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3807532153
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.712093761
Short name T639
Test name
Test status
Simulation time 8472366973 ps
CPU time 8.16 seconds
Started Mar 24 02:42:18 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203556 kb
Host smart-b462c7e0-62a2-400f-b0bc-5d38a1039ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71209
3761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.712093761
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1487766152
Short name T772
Test name
Test status
Simulation time 8370087550 ps
CPU time 8.76 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:31 PM PDT 24
Peak memory 203560 kb
Host smart-6fe860f5-f71b-4d50-80f6-47d7f181473b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14877
66152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1487766152
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_enable.3835514737
Short name T13
Test name
Test status
Simulation time 8370980352 ps
CPU time 9.25 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:31 PM PDT 24
Peak memory 203548 kb
Host smart-48ca8f9d-891d-4455-b0bb-6fcbe82fe771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38355
14737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3835514737
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.208916439
Short name T50
Test name
Test status
Simulation time 70413657 ps
CPU time 1.99 seconds
Started Mar 24 02:42:23 PM PDT 24
Finished Mar 24 02:42:25 PM PDT 24
Peak memory 203560 kb
Host smart-8a765500-4e7e-455b-8859-799e2b2013c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20891
6439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.208916439
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1440269814
Short name T473
Test name
Test status
Simulation time 8362937997 ps
CPU time 8.38 seconds
Started Mar 24 02:42:32 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203544 kb
Host smart-25fa5b0c-d78d-4ba9-8017-7584e41a9138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14402
69814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1440269814
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4063494451
Short name T751
Test name
Test status
Simulation time 8461955850 ps
CPU time 7.75 seconds
Started Mar 24 02:42:21 PM PDT 24
Finished Mar 24 02:42:29 PM PDT 24
Peak memory 203536 kb
Host smart-9b858468-db2c-4d44-b6c2-4738b818329b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40634
94451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4063494451
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2530087711
Short name T499
Test name
Test status
Simulation time 8406367562 ps
CPU time 7.9 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:40 PM PDT 24
Peak memory 203484 kb
Host smart-5f7b9a03-0681-461f-91b2-14d1e038b1e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25300
87711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2530087711
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4258899229
Short name T651
Test name
Test status
Simulation time 8369717512 ps
CPU time 9.45 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203588 kb
Host smart-e805275d-6f1c-4d40-96bc-a97f2dc7024f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42588
99229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4258899229
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1628598671
Short name T224
Test name
Test status
Simulation time 8423089417 ps
CPU time 7.31 seconds
Started Mar 24 02:42:23 PM PDT 24
Finished Mar 24 02:42:30 PM PDT 24
Peak memory 203644 kb
Host smart-4638b92e-7fcd-4f2f-a744-a716097c9f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16285
98671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1628598671
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2220797359
Short name T470
Test name
Test status
Simulation time 8385191114 ps
CPU time 7.39 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:29 PM PDT 24
Peak memory 203512 kb
Host smart-ca0ca275-b379-4b45-bce4-d20b20c7baf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22207
97359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2220797359
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3398385069
Short name T666
Test name
Test status
Simulation time 8367012444 ps
CPU time 7.03 seconds
Started Mar 24 02:42:32 PM PDT 24
Finished Mar 24 02:42:40 PM PDT 24
Peak memory 203560 kb
Host smart-4e87fb0d-e011-4110-9925-975b833143d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33983
85069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3398385069
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.155475104
Short name T879
Test name
Test status
Simulation time 27579603 ps
CPU time 0.64 seconds
Started Mar 24 02:42:29 PM PDT 24
Finished Mar 24 02:42:30 PM PDT 24
Peak memory 203388 kb
Host smart-70e41f34-ebc4-483c-9555-3055cc45fba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15547
5104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.155475104
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4173192773
Short name T757
Test name
Test status
Simulation time 8405363713 ps
CPU time 7.39 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 203472 kb
Host smart-179f7c00-81eb-41cd-b9eb-7ff7dfede311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41731
92773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4173192773
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3714375806
Short name T114
Test name
Test status
Simulation time 8373574172 ps
CPU time 8.2 seconds
Started Mar 24 02:42:26 PM PDT 24
Finished Mar 24 02:42:34 PM PDT 24
Peak memory 203572 kb
Host smart-682b7ab6-bbeb-4650-a584-3b43072c3489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37143
75806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3714375806
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.4170652918
Short name T232
Test name
Test status
Simulation time 8378522968 ps
CPU time 8.95 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:31 PM PDT 24
Peak memory 203576 kb
Host smart-03a4c2bb-2129-4667-9c03-4ad9d34863b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41706
52918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.4170652918
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2141293146
Short name T755
Test name
Test status
Simulation time 8355961737 ps
CPU time 7.8 seconds
Started Mar 24 02:42:19 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203544 kb
Host smart-3603ce79-1d3a-47a5-8042-ecd9f519b9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21412
93146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2141293146
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.583261232
Short name T286
Test name
Test status
Simulation time 8370701905 ps
CPU time 7.39 seconds
Started Mar 24 02:42:27 PM PDT 24
Finished Mar 24 02:42:35 PM PDT 24
Peak memory 203560 kb
Host smart-44b9726f-b58b-4bf1-af46-40dcf868bb96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58326
1232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.583261232
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_enable.2061320540
Short name T314
Test name
Test status
Simulation time 8371583831 ps
CPU time 7.73 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:38 PM PDT 24
Peak memory 203592 kb
Host smart-8495dc8b-575d-4a0d-b527-5c27148b90a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20613
20540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2061320540
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1833616154
Short name T488
Test name
Test status
Simulation time 55974003 ps
CPU time 1.62 seconds
Started Mar 24 02:42:25 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203540 kb
Host smart-2856a3fb-2ce0-47cf-b7e8-559cc9cf589c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
16154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1833616154
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1453118541
Short name T183
Test name
Test status
Simulation time 8356158913 ps
CPU time 7.22 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203516 kb
Host smart-edafca5d-840b-4b8a-86fc-21eadc285122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14531
18541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1453118541
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3399315826
Short name T405
Test name
Test status
Simulation time 8445295307 ps
CPU time 7.45 seconds
Started Mar 24 02:42:19 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203552 kb
Host smart-e967203a-2544-4301-8282-64b3f3b3cf42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33993
15826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3399315826
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.325677493
Short name T311
Test name
Test status
Simulation time 8406374907 ps
CPU time 7.56 seconds
Started Mar 24 02:42:28 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 203548 kb
Host smart-28fcce36-8e56-44ea-9fbf-ceb817b3c71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
7493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.325677493
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2844095846
Short name T854
Test name
Test status
Simulation time 8361587356 ps
CPU time 7.31 seconds
Started Mar 24 02:42:20 PM PDT 24
Finished Mar 24 02:42:27 PM PDT 24
Peak memory 203560 kb
Host smart-174238e3-1148-437f-973f-821a20f2ae0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28440
95846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2844095846
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.866577678
Short name T735
Test name
Test status
Simulation time 8412399474 ps
CPU time 7.65 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203524 kb
Host smart-af9a9158-35b8-445d-9a20-6743dfaf7416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86657
7678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.866577678
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.506223928
Short name T8
Test name
Test status
Simulation time 8372751987 ps
CPU time 7.79 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203548 kb
Host smart-55666c76-7b50-43f3-96fe-c5b73053f188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50622
3928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.506223928
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3061773626
Short name T834
Test name
Test status
Simulation time 8395188857 ps
CPU time 7.17 seconds
Started Mar 24 02:42:34 PM PDT 24
Finished Mar 24 02:42:42 PM PDT 24
Peak memory 203532 kb
Host smart-7967f7e2-907f-42d8-84df-be3cfdc0435c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30617
73626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3061773626
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2416603849
Short name T814
Test name
Test status
Simulation time 27788161 ps
CPU time 0.63 seconds
Started Mar 24 02:42:26 PM PDT 24
Finished Mar 24 02:42:28 PM PDT 24
Peak memory 203416 kb
Host smart-6d711f90-a4c3-4ee9-8239-1f3bfb902e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24166
03849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2416603849
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3595844918
Short name T450
Test name
Test status
Simulation time 8384357009 ps
CPU time 8.11 seconds
Started Mar 24 02:42:28 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 203484 kb
Host smart-74197b05-6a1a-4f95-9e51-e41b0d2a4e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35958
44918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3595844918
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2156230288
Short name T125
Test name
Test status
Simulation time 8441560232 ps
CPU time 7.73 seconds
Started Mar 24 02:42:20 PM PDT 24
Finished Mar 24 02:42:28 PM PDT 24
Peak memory 203552 kb
Host smart-76510957-ee16-4a24-8ade-afe358d5fbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21562
30288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2156230288
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.3971095508
Short name T670
Test name
Test status
Simulation time 8376600337 ps
CPU time 7.54 seconds
Started Mar 24 02:42:22 PM PDT 24
Finished Mar 24 02:42:29 PM PDT 24
Peak memory 203556 kb
Host smart-d639dbfa-b0d3-4001-9316-edaaabcceed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39710
95508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.3971095508
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3862110018
Short name T658
Test name
Test status
Simulation time 8360389571 ps
CPU time 8.23 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203540 kb
Host smart-46b7c90d-055f-4c0b-86cb-80ae2080c977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38621
10018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3862110018
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3464635776
Short name T559
Test name
Test status
Simulation time 8476544586 ps
CPU time 7.33 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 203536 kb
Host smart-3aee42e5-8044-47b4-aa71-f8afafbfa411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34646
35776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3464635776
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.629679380
Short name T769
Test name
Test status
Simulation time 8372820569 ps
CPU time 8.27 seconds
Started Mar 24 02:42:27 PM PDT 24
Finished Mar 24 02:42:35 PM PDT 24
Peak memory 203540 kb
Host smart-6cb4e5bc-03e4-4e9a-a598-a4adf1426c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62967
9380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.629679380
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_enable.2439263352
Short name T848
Test name
Test status
Simulation time 8366873848 ps
CPU time 7.7 seconds
Started Mar 24 02:42:25 PM PDT 24
Finished Mar 24 02:42:33 PM PDT 24
Peak memory 203568 kb
Host smart-6f096979-de8a-4918-8ea0-807aa893ef5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24392
63352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2439263352
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1065136845
Short name T330
Test name
Test status
Simulation time 67332915 ps
CPU time 2.03 seconds
Started Mar 24 02:42:27 PM PDT 24
Finished Mar 24 02:42:29 PM PDT 24
Peak memory 203688 kb
Host smart-61e7e723-b675-4155-8eaf-8c6d342a4baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10651
36845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1065136845
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2280256528
Short name T387
Test name
Test status
Simulation time 8361614887 ps
CPU time 9.55 seconds
Started Mar 24 02:42:24 PM PDT 24
Finished Mar 24 02:42:34 PM PDT 24
Peak memory 203528 kb
Host smart-aa05207b-9542-40f3-a540-54257c8c4481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22802
56528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2280256528
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3981864242
Short name T129
Test name
Test status
Simulation time 8463270399 ps
CPU time 7.95 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:40 PM PDT 24
Peak memory 203540 kb
Host smart-08a73556-2519-4564-ab22-b9c77e8b780b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
64242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3981864242
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1320530867
Short name T463
Test name
Test status
Simulation time 8404660490 ps
CPU time 8.05 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:38 PM PDT 24
Peak memory 203564 kb
Host smart-7d422f6d-799c-439e-ba49-cd224138bf88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13205
30867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1320530867
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1358583936
Short name T690
Test name
Test status
Simulation time 8366117997 ps
CPU time 7.2 seconds
Started Mar 24 02:42:28 PM PDT 24
Finished Mar 24 02:42:35 PM PDT 24
Peak memory 203532 kb
Host smart-fbf16053-ceee-45d8-b9e6-20fb3580e19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13585
83936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1358583936
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3737659741
Short name T87
Test name
Test status
Simulation time 8423321866 ps
CPU time 7.86 seconds
Started Mar 24 02:42:26 PM PDT 24
Finished Mar 24 02:42:34 PM PDT 24
Peak memory 203480 kb
Host smart-9440e187-63fc-421a-957f-1c6e4b033ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37376
59741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3737659741
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2344226796
Short name T653
Test name
Test status
Simulation time 8385261214 ps
CPU time 9.83 seconds
Started Mar 24 02:42:27 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 203484 kb
Host smart-a88efde4-43da-4ec4-ac19-62f3049b6454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23442
26796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2344226796
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2910434014
Short name T464
Test name
Test status
Simulation time 8377410848 ps
CPU time 8.76 seconds
Started Mar 24 02:42:32 PM PDT 24
Finished Mar 24 02:42:42 PM PDT 24
Peak memory 203592 kb
Host smart-ef685ff2-39e1-47dc-84f2-77af0c811378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29104
34014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2910434014
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3461787014
Short name T323
Test name
Test status
Simulation time 24271335 ps
CPU time 0.64 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:35 PM PDT 24
Peak memory 203420 kb
Host smart-6a0bbb7f-03d2-4466-93a9-8bc5c1743f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34617
87014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3461787014
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.2748183259
Short name T637
Test name
Test status
Simulation time 8381180366 ps
CPU time 8 seconds
Started Mar 24 02:42:32 PM PDT 24
Finished Mar 24 02:42:40 PM PDT 24
Peak memory 203560 kb
Host smart-02f9296d-b08c-4927-9422-64f42548152b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27481
83259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.2748183259
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2568269471
Short name T132
Test name
Test status
Simulation time 8378051886 ps
CPU time 7.8 seconds
Started Mar 24 02:42:27 PM PDT 24
Finished Mar 24 02:42:35 PM PDT 24
Peak memory 203540 kb
Host smart-73c2d2ec-4a14-44c2-a882-ffd80f97f40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25682
69471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2568269471
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.2657797937
Short name T272
Test name
Test status
Simulation time 8380976757 ps
CPU time 7.31 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203584 kb
Host smart-16d3ea2f-5edf-4923-9fec-54d21d6e235a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26577
97937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.2657797937
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2308538169
Short name T722
Test name
Test status
Simulation time 8354952564 ps
CPU time 8.1 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:42 PM PDT 24
Peak memory 203552 kb
Host smart-32476032-76f1-4dc5-b9d2-328d4e143578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23085
38169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2308538169
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.246629140
Short name T383
Test name
Test status
Simulation time 8372024582 ps
CPU time 8.01 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:38 PM PDT 24
Peak memory 203568 kb
Host smart-1cb15d9d-c9a7-4aae-b41f-ad91ded8e4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24662
9140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.246629140
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_enable.2970332598
Short name T795
Test name
Test status
Simulation time 8371629422 ps
CPU time 8.16 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203780 kb
Host smart-c3962732-294d-4316-9754-271104f46e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703
32598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2970332598
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.4028144350
Short name T740
Test name
Test status
Simulation time 8445134034 ps
CPU time 8.8 seconds
Started Mar 24 02:42:27 PM PDT 24
Finished Mar 24 02:42:36 PM PDT 24
Peak memory 203536 kb
Host smart-f9813a62-f91b-4030-8462-326b4334786a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40281
44350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.4028144350
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1871154632
Short name T715
Test name
Test status
Simulation time 8403729302 ps
CPU time 7.66 seconds
Started Mar 24 02:42:36 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203568 kb
Host smart-4121414e-5705-4aa3-b059-99e8bd6fefba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18711
54632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1871154632
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4261607166
Short name T709
Test name
Test status
Simulation time 8368388520 ps
CPU time 7.2 seconds
Started Mar 24 02:42:34 PM PDT 24
Finished Mar 24 02:42:43 PM PDT 24
Peak memory 203588 kb
Host smart-a8485022-5b82-42f1-9814-21222f47c298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42616
07166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4261607166
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1736597218
Short name T88
Test name
Test status
Simulation time 8393699669 ps
CPU time 8.53 seconds
Started Mar 24 02:42:28 PM PDT 24
Finished Mar 24 02:42:38 PM PDT 24
Peak memory 203532 kb
Host smart-cbdda1f7-8797-4ed3-b253-1ea01d036eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17365
97218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1736597218
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2823618832
Short name T509
Test name
Test status
Simulation time 8371896796 ps
CPU time 10.09 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:42 PM PDT 24
Peak memory 203784 kb
Host smart-405e9cee-4c6a-4c78-a6ed-714fe1406c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28236
18832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2823618832
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3377004749
Short name T390
Test name
Test status
Simulation time 8370145685 ps
CPU time 7.92 seconds
Started Mar 24 02:42:26 PM PDT 24
Finished Mar 24 02:42:34 PM PDT 24
Peak memory 203560 kb
Host smart-d637bc8f-28d8-48a6-9c8c-0e01be133402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33770
04749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3377004749
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1199494005
Short name T39
Test name
Test status
Simulation time 30463858 ps
CPU time 0.65 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:32 PM PDT 24
Peak memory 203444 kb
Host smart-2c42d281-72a2-4749-9d1f-c0881d37a0a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11994
94005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1199494005
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3055248579
Short name T689
Test name
Test status
Simulation time 8386924530 ps
CPU time 7.48 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:38 PM PDT 24
Peak memory 203520 kb
Host smart-c5897596-98b8-4dd9-827a-fd07455f09cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30552
48579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3055248579
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3519859803
Short name T516
Test name
Test status
Simulation time 8440614371 ps
CPU time 8.15 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203516 kb
Host smart-be1a6106-c309-462e-9187-376c7d64f6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35198
59803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3519859803
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2813208516
Short name T521
Test name
Test status
Simulation time 8410612733 ps
CPU time 9.83 seconds
Started Mar 24 02:42:29 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203540 kb
Host smart-f35cb812-0f5e-4256-a248-527ce32c5c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28132
08516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2813208516
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2326094058
Short name T650
Test name
Test status
Simulation time 8359687307 ps
CPU time 7.26 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:38 PM PDT 24
Peak memory 203580 kb
Host smart-208ed68c-ee85-4182-aec9-3e25f25f4c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23260
94058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2326094058
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.984196856
Short name T160
Test name
Test status
Simulation time 8474932102 ps
CPU time 7.3 seconds
Started Mar 24 02:42:26 PM PDT 24
Finished Mar 24 02:42:33 PM PDT 24
Peak memory 203788 kb
Host smart-070b8433-6528-4c9b-8a7b-ef0082be2991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98419
6856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.984196856
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3350114365
Short name T819
Test name
Test status
Simulation time 8367186077 ps
CPU time 9.86 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203572 kb
Host smart-b11152f3-76fe-4bbe-83d5-fa6b61c7ae7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33501
14365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3350114365
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_enable.624436470
Short name T736
Test name
Test status
Simulation time 8367726745 ps
CPU time 7.87 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203536 kb
Host smart-150b8392-23b6-4e01-8d98-94ed04ce25bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62443
6470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.624436470
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1252760236
Short name T863
Test name
Test status
Simulation time 264035976 ps
CPU time 2.12 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:33 PM PDT 24
Peak memory 203640 kb
Host smart-f1cee7a3-d736-4410-a65d-7c33c1e52dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12527
60236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1252760236
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2043974679
Short name T189
Test name
Test status
Simulation time 8358910676 ps
CPU time 9.4 seconds
Started Mar 24 02:42:34 PM PDT 24
Finished Mar 24 02:42:45 PM PDT 24
Peak memory 203492 kb
Host smart-a62673c1-bfbd-439f-a16d-8e5a119d4f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20439
74679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2043974679
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1037950698
Short name T392
Test name
Test status
Simulation time 8402181614 ps
CPU time 7.93 seconds
Started Mar 24 02:42:29 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 203556 kb
Host smart-0c29277c-6759-44d1-9539-d0702eb48d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10379
50698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1037950698
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.46565429
Short name T217
Test name
Test status
Simulation time 8412904447 ps
CPU time 9.21 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:40 PM PDT 24
Peak memory 203532 kb
Host smart-23d377b6-6241-4832-ba5b-7edd88025ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46565
429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.46565429
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.35679838
Short name T581
Test name
Test status
Simulation time 8362782435 ps
CPU time 8.02 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203572 kb
Host smart-6fd92403-dd14-4ff5-805c-e7b86ad52ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35679
838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.35679838
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.831789111
Short name T108
Test name
Test status
Simulation time 8405370070 ps
CPU time 6.94 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:43 PM PDT 24
Peak memory 203484 kb
Host smart-007edcb0-6ba4-4332-9b8f-4fe457fb5a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83178
9111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.831789111
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3651681851
Short name T681
Test name
Test status
Simulation time 8397104116 ps
CPU time 8.23 seconds
Started Mar 24 02:42:36 PM PDT 24
Finished Mar 24 02:42:46 PM PDT 24
Peak memory 203484 kb
Host smart-56a98c89-e197-49be-96c9-525ac30fb5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36516
81851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3651681851
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.391471516
Short name T674
Test name
Test status
Simulation time 8378737198 ps
CPU time 7.49 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203608 kb
Host smart-796f230c-5c82-4822-a8ff-4221c71f6e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39147
1516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.391471516
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2305441608
Short name T672
Test name
Test status
Simulation time 30208411 ps
CPU time 0.64 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:32 PM PDT 24
Peak memory 203380 kb
Host smart-ce794e64-0150-444a-acd4-a39135776608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23054
41608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2305441608
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2606331980
Short name T724
Test name
Test status
Simulation time 8379041129 ps
CPU time 7.4 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203532 kb
Host smart-70ea46e7-dbb1-4b56-a621-6f3daf6b86b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26063
31980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2606331980
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.646228727
Short name T486
Test name
Test status
Simulation time 8379370496 ps
CPU time 9.39 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203480 kb
Host smart-c261ff4b-d024-447e-9908-3b4eb30fe439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64622
8727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.646228727
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.1322196320
Short name T841
Test name
Test status
Simulation time 8378801867 ps
CPU time 8.61 seconds
Started Mar 24 02:42:27 PM PDT 24
Finished Mar 24 02:42:36 PM PDT 24
Peak memory 203576 kb
Host smart-cbd82fff-6890-4eb0-906f-33d282587515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13221
96320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.1322196320
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2640704144
Short name T348
Test name
Test status
Simulation time 8359417076 ps
CPU time 7.27 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203580 kb
Host smart-2c55eb86-e40e-4f34-a167-00805c727c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26407
04144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2640704144
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2712063442
Short name T119
Test name
Test status
Simulation time 8480715189 ps
CPU time 7.68 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:40 PM PDT 24
Peak memory 203548 kb
Host smart-f83aa7e1-7fa8-49f9-bf4b-15a386389a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27120
63442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2712063442
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.1143929234
Short name T682
Test name
Test status
Simulation time 8371455038 ps
CPU time 7.71 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:40 PM PDT 24
Peak memory 203536 kb
Host smart-7495348f-f836-4705-b0ea-9edde73ea1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11439
29234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1143929234
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_enable.2990803018
Short name T786
Test name
Test status
Simulation time 8374163111 ps
CPU time 7.99 seconds
Started Mar 24 02:42:30 PM PDT 24
Finished Mar 24 02:42:38 PM PDT 24
Peak memory 203560 kb
Host smart-8115995d-1725-4fab-a959-6668251a39d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29908
03018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2990803018
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.4073112517
Short name T683
Test name
Test status
Simulation time 51557755 ps
CPU time 1.39 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:35 PM PDT 24
Peak memory 203608 kb
Host smart-6364ee02-8327-48f4-a211-7112caebbbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40731
12517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.4073112517
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1111672410
Short name T875
Test name
Test status
Simulation time 8360192268 ps
CPU time 8.13 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:54 PM PDT 24
Peak memory 203572 kb
Host smart-a61758ee-5060-4ad4-b1fd-6d2529a21d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11116
72410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1111672410
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.264529501
Short name T575
Test name
Test status
Simulation time 8434178701 ps
CPU time 7.5 seconds
Started Mar 24 02:42:29 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 203508 kb
Host smart-19d4f6cf-80c6-4c43-a776-cad462493627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26452
9501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.264529501
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1784744230
Short name T629
Test name
Test status
Simulation time 8410605376 ps
CPU time 7.34 seconds
Started Mar 24 02:42:38 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203540 kb
Host smart-8d558c89-0168-491f-a028-bb42640bd5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17847
44230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1784744230
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.445244898
Short name T616
Test name
Test status
Simulation time 8366874322 ps
CPU time 7.1 seconds
Started Mar 24 02:42:34 PM PDT 24
Finished Mar 24 02:42:42 PM PDT 24
Peak memory 203556 kb
Host smart-954cb5da-8ae1-4328-a0d1-fe765225a61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44524
4898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.445244898
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1915668030
Short name T103
Test name
Test status
Simulation time 8411406998 ps
CPU time 7.63 seconds
Started Mar 24 02:42:31 PM PDT 24
Finished Mar 24 02:42:40 PM PDT 24
Peak memory 203532 kb
Host smart-3826c69d-911a-4fc1-929b-41386665d3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156
68030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1915668030
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.861502662
Short name T768
Test name
Test status
Simulation time 8383709086 ps
CPU time 7.55 seconds
Started Mar 24 02:42:33 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203496 kb
Host smart-0e11a845-f2b5-47aa-9c7b-ba39065cf801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86150
2662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.861502662
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2444686264
Short name T23
Test name
Test status
Simulation time 8371378721 ps
CPU time 9.31 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203532 kb
Host smart-62aeff26-6f3a-4189-927a-718312b1beec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24446
86264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2444686264
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3789156360
Short name T303
Test name
Test status
Simulation time 27684241 ps
CPU time 0.64 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203664 kb
Host smart-31fc2310-8c0c-44c0-b5f6-186086da7029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37891
56360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3789156360
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2036082743
Short name T46
Test name
Test status
Simulation time 8405869704 ps
CPU time 7.44 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:45 PM PDT 24
Peak memory 203484 kb
Host smart-e4f8b53c-df7a-40de-8e4f-3a14615eb97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20360
82743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2036082743
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.3682107169
Short name T437
Test name
Test status
Simulation time 8385410263 ps
CPU time 7.75 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203592 kb
Host smart-365bf34a-f1b2-47f4-820e-08eb91ed0bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36821
07169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.3682107169
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1102063617
Short name T508
Test name
Test status
Simulation time 8361736017 ps
CPU time 7.52 seconds
Started Mar 24 02:42:36 PM PDT 24
Finished Mar 24 02:42:46 PM PDT 24
Peak memory 203544 kb
Host smart-c7620f43-ed24-4bee-82a3-2f05d8fa69d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11020
63617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1102063617
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1968455183
Short name T775
Test name
Test status
Simulation time 8469449067 ps
CPU time 8.65 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:46 PM PDT 24
Peak memory 203516 kb
Host smart-2d25e45c-d230-4abb-9e6b-f949952fa4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19684
55183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1968455183
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.4052781927
Short name T857
Test name
Test status
Simulation time 8368582921 ps
CPU time 9.27 seconds
Started Mar 24 02:42:38 PM PDT 24
Finished Mar 24 02:42:48 PM PDT 24
Peak memory 203512 kb
Host smart-fbae1b58-ff1a-4ffa-b502-84e7fa087cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40527
81927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.4052781927
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_enable.495878499
Short name T402
Test name
Test status
Simulation time 8367931714 ps
CPU time 8.84 seconds
Started Mar 24 02:42:40 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 203592 kb
Host smart-92f67a25-ba0f-40b5-a536-d98d0a8c7b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49587
8499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.495878499
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2846956881
Short name T687
Test name
Test status
Simulation time 90422112 ps
CPU time 1.3 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:39 PM PDT 24
Peak memory 203604 kb
Host smart-efb2b35f-077a-46ed-9a4d-a7d863b15732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28469
56881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2846956881
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2705822576
Short name T168
Test name
Test status
Simulation time 8356943405 ps
CPU time 8.53 seconds
Started Mar 24 02:42:40 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203532 kb
Host smart-cc1158bf-6c39-4244-8678-359f8c89b19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27058
22576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2705822576
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1202233370
Short name T652
Test name
Test status
Simulation time 8454377926 ps
CPU time 7.59 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203568 kb
Host smart-de7c7652-cf22-4ea0-b5b2-fc697d044543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12022
33370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1202233370
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1370639703
Short name T619
Test name
Test status
Simulation time 8407302007 ps
CPU time 7.74 seconds
Started Mar 24 02:42:39 PM PDT 24
Finished Mar 24 02:42:48 PM PDT 24
Peak memory 203592 kb
Host smart-1aced573-0ffc-405a-9c0d-e2adafc296f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13706
39703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1370639703
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3070032908
Short name T461
Test name
Test status
Simulation time 8361690754 ps
CPU time 7.28 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203788 kb
Host smart-ee69cb6e-e261-439a-834f-f32adc11ffdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30700
32908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3070032908
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3413024116
Short name T91
Test name
Test status
Simulation time 8415235666 ps
CPU time 8.91 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:51 PM PDT 24
Peak memory 203540 kb
Host smart-043559d1-72ca-4054-950a-9e75aba73bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34130
24116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3413024116
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.452162390
Short name T26
Test name
Test status
Simulation time 8396023703 ps
CPU time 9.31 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203552 kb
Host smart-37acda35-c8d5-4d77-ab77-5273f0cbf427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45216
2390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.452162390
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2814016433
Short name T343
Test name
Test status
Simulation time 8387434441 ps
CPU time 8.77 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203564 kb
Host smart-33db6709-c475-4567-a2f0-43732a6871ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
16433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2814016433
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.4285035574
Short name T582
Test name
Test status
Simulation time 30257864 ps
CPU time 0.66 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:43 PM PDT 24
Peak memory 203464 kb
Host smart-f3b41219-4d3e-4413-8122-e29c191653ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42850
35574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.4285035574
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.1722823503
Short name T396
Test name
Test status
Simulation time 8378281323 ps
CPU time 7.94 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 203568 kb
Host smart-cf3477c5-ffcb-4526-a9d6-fde552e33696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17228
23503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.1722823503
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1768653083
Short name T137
Test name
Test status
Simulation time 8409406902 ps
CPU time 8.65 seconds
Started Mar 24 02:42:43 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203524 kb
Host smart-d5fb80f5-8a6e-4167-9910-a84fa1e80130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17686
53083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1768653083
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.3594684413
Short name T391
Test name
Test status
Simulation time 8393235724 ps
CPU time 7.7 seconds
Started Mar 24 02:42:46 PM PDT 24
Finished Mar 24 02:42:53 PM PDT 24
Peak memory 203604 kb
Host smart-dd5637e5-39eb-4683-b598-4c4b13c5b941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35946
84413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.3594684413
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.488240419
Short name T441
Test name
Test status
Simulation time 8364246268 ps
CPU time 7.16 seconds
Started Mar 24 02:42:36 PM PDT 24
Finished Mar 24 02:42:45 PM PDT 24
Peak memory 203548 kb
Host smart-92ca4aca-fd01-45a6-aed1-8257987ce1d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48824
0419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.488240419
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.666339946
Short name T147
Test name
Test status
Simulation time 8470205535 ps
CPU time 7.65 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:45 PM PDT 24
Peak memory 203584 kb
Host smart-35edd2c7-0a31-492c-b6ce-5d469b5e25da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66633
9946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.666339946
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.4112328607
Short name T874
Test name
Test status
Simulation time 8366776917 ps
CPU time 7.37 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:44 PM PDT 24
Peak memory 203540 kb
Host smart-1334ef6a-9c03-469b-8a02-f5c819979303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41123
28607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.4112328607
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_enable.3117842403
Short name T408
Test name
Test status
Simulation time 8365299603 ps
CPU time 7.26 seconds
Started Mar 24 02:43:02 PM PDT 24
Finished Mar 24 02:43:10 PM PDT 24
Peak memory 203488 kb
Host smart-b986aebf-492b-4f15-a3c2-21cd014798af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31178
42403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3117842403
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3721682841
Short name T876
Test name
Test status
Simulation time 137595759 ps
CPU time 1.71 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:44 PM PDT 24
Peak memory 203616 kb
Host smart-cadc464a-4e20-4af0-83d3-106f1487fcbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37216
82841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3721682841
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3706366200
Short name T172
Test name
Test status
Simulation time 8357191981 ps
CPU time 7.6 seconds
Started Mar 24 02:42:38 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203500 kb
Host smart-c3dfc0cb-b893-48a8-a17a-e6cf33e93a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37063
66200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3706366200
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.646011958
Short name T622
Test name
Test status
Simulation time 8403743085 ps
CPU time 8.31 seconds
Started Mar 24 02:42:36 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203564 kb
Host smart-e46f484a-f825-4a67-9155-2a24e9a22856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64601
1958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.646011958
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3316148779
Short name T442
Test name
Test status
Simulation time 8406139272 ps
CPU time 8.06 seconds
Started Mar 24 02:42:40 PM PDT 24
Finished Mar 24 02:42:48 PM PDT 24
Peak memory 203588 kb
Host smart-576cf48f-921f-4f98-a366-03573d706ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33161
48779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3316148779
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1687494401
Short name T423
Test name
Test status
Simulation time 8366164067 ps
CPU time 8.54 seconds
Started Mar 24 02:42:38 PM PDT 24
Finished Mar 24 02:42:48 PM PDT 24
Peak memory 203600 kb
Host smart-463d06a3-02e6-480f-838a-8fa33f8581ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16874
94401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1687494401
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.111644577
Short name T111
Test name
Test status
Simulation time 8408407688 ps
CPU time 8.6 seconds
Started Mar 24 02:42:35 PM PDT 24
Finished Mar 24 02:42:45 PM PDT 24
Peak memory 203528 kb
Host smart-efe5ef09-c9d8-4f1f-8a2c-dde92ef42d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11164
4577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.111644577
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.633651254
Short name T304
Test name
Test status
Simulation time 8398087855 ps
CPU time 8.46 seconds
Started Mar 24 02:42:37 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203572 kb
Host smart-98ef0223-29af-4bc2-af94-b3562bee0c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63365
1254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.633651254
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3205756927
Short name T540
Test name
Test status
Simulation time 8378849807 ps
CPU time 7.76 seconds
Started Mar 24 02:42:38 PM PDT 24
Finished Mar 24 02:42:48 PM PDT 24
Peak memory 203564 kb
Host smart-7c37c8fb-72ea-4b01-9e67-c57d9401bba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32057
56927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3205756927
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.766417157
Short name T385
Test name
Test status
Simulation time 28003311 ps
CPU time 0.69 seconds
Started Mar 24 02:42:39 PM PDT 24
Finished Mar 24 02:42:41 PM PDT 24
Peak memory 203664 kb
Host smart-0999dcfe-dd60-40cf-b25f-49e22cd90a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76641
7157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.766417157
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2193558232
Short name T595
Test name
Test status
Simulation time 8406228326 ps
CPU time 8.2 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203872 kb
Host smart-341c8019-74f9-4e90-9244-8bac49240ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21935
58232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2193558232
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.1872573600
Short name T118
Test name
Test status
Simulation time 8396469044 ps
CPU time 6.91 seconds
Started Mar 24 02:42:43 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 203540 kb
Host smart-76aaafe9-7b31-47fc-90e8-3e068b954680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18725
73600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.1872573600
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.339765219
Short name T556
Test name
Test status
Simulation time 8384122363 ps
CPU time 7.14 seconds
Started Mar 24 02:42:39 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203572 kb
Host smart-3e664287-7ae7-4654-a5c8-2a3e207bce1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33976
5219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.339765219
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3565392862
Short name T506
Test name
Test status
Simulation time 8357206962 ps
CPU time 7.31 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:48 PM PDT 24
Peak memory 203548 kb
Host smart-6b63f8e8-eb88-4165-8f00-2b26730e1852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35653
92862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3565392862
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3450185770
Short name T294
Test name
Test status
Simulation time 8369115543 ps
CPU time 6.94 seconds
Started Mar 24 02:42:40 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203512 kb
Host smart-609eed30-5201-43aa-a8e8-5adda9c0c843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34501
85770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3450185770
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_enable.4125646898
Short name T3
Test name
Test status
Simulation time 8368079121 ps
CPU time 8.41 seconds
Started Mar 24 02:42:38 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203536 kb
Host smart-b0142897-b463-45ee-bc75-16775cdd568b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41256
46898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.4125646898
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.250900441
Short name T397
Test name
Test status
Simulation time 45918337 ps
CPU time 1.41 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:46 PM PDT 24
Peak memory 203644 kb
Host smart-8646caf1-419a-4f36-a545-8335c1ca48f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25090
0441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.250900441
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1053645003
Short name T188
Test name
Test status
Simulation time 8360234672 ps
CPU time 8.96 seconds
Started Mar 24 02:42:43 PM PDT 24
Finished Mar 24 02:42:53 PM PDT 24
Peak memory 203556 kb
Host smart-913ae888-8305-4286-a12e-a40ecd1743c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10536
45003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1053645003
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.767558185
Short name T773
Test name
Test status
Simulation time 8398603657 ps
CPU time 7.32 seconds
Started Mar 24 02:42:43 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 203872 kb
Host smart-bcdd05d7-54f1-4f6d-a756-c47b3c0609c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76755
8185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.767558185
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1558481291
Short name T865
Test name
Test status
Simulation time 8413518900 ps
CPU time 9.09 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:54 PM PDT 24
Peak memory 203604 kb
Host smart-ff38ad40-f2ba-42e8-a64e-250f3ea48523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15584
81291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1558481291
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1039959386
Short name T860
Test name
Test status
Simulation time 8364543888 ps
CPU time 7.64 seconds
Started Mar 24 02:42:42 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 203568 kb
Host smart-6d2a6b79-ef8b-48df-8c37-e5f22cb504d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10399
59386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1039959386
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1160502458
Short name T803
Test name
Test status
Simulation time 8437149272 ps
CPU time 7.51 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:51 PM PDT 24
Peak memory 203536 kb
Host smart-6f3b9db4-fbf8-4580-bf56-bf98301d0ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11605
02458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1160502458
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2162109017
Short name T535
Test name
Test status
Simulation time 8401997356 ps
CPU time 7.5 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:53 PM PDT 24
Peak memory 203544 kb
Host smart-bd0d7090-e727-406c-9f62-30adea770e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21621
09017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2162109017
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1147938306
Short name T729
Test name
Test status
Simulation time 8378494616 ps
CPU time 7.74 seconds
Started Mar 24 02:42:42 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 203596 kb
Host smart-628b3392-8f07-47da-98d4-a6b1596d5e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11479
38306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1147938306
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3577665847
Short name T305
Test name
Test status
Simulation time 21656496 ps
CPU time 0.64 seconds
Started Mar 24 02:42:46 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203404 kb
Host smart-bde76cb1-95cb-4acf-b856-f2ed954073a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35776
65847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3577665847
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1369659541
Short name T373
Test name
Test status
Simulation time 8382168015 ps
CPU time 8.99 seconds
Started Mar 24 02:42:40 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203560 kb
Host smart-4c261a33-2e2d-4378-854c-414bf8dff221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13696
59541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1369659541
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.846315346
Short name T475
Test name
Test status
Simulation time 8384793538 ps
CPU time 7.39 seconds
Started Mar 24 02:42:39 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203572 kb
Host smart-d37d8127-d681-43f9-87ea-0125b0bd7af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84631
5346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.846315346
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.2478690434
Short name T529
Test name
Test status
Simulation time 8368895126 ps
CPU time 8.34 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:53 PM PDT 24
Peak memory 203544 kb
Host smart-e5e77dff-ae59-4962-94e9-5361a778ca9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24786
90434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.2478690434
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1629695987
Short name T460
Test name
Test status
Simulation time 8363477927 ps
CPU time 7.19 seconds
Started Mar 24 02:42:42 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203564 kb
Host smart-521359c7-6034-4598-bd01-fe41e8c43d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16296
95987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1629695987
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2883174120
Short name T153
Test name
Test status
Simulation time 8475991827 ps
CPU time 7.37 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203576 kb
Host smart-35e376ed-4ee1-4641-a7f5-a3e340252997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28831
74120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2883174120
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2342650065
Short name T844
Test name
Test status
Simulation time 8373902197 ps
CPU time 9.01 seconds
Started Mar 24 02:40:57 PM PDT 24
Finished Mar 24 02:41:06 PM PDT 24
Peak memory 203540 kb
Host smart-93507a0b-0fbd-4024-870a-ff64368a3893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23426
50065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2342650065
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_enable.2173512803
Short name T633
Test name
Test status
Simulation time 8369069199 ps
CPU time 9.84 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:41:05 PM PDT 24
Peak memory 203584 kb
Host smart-15a315cd-70fd-4911-a88c-b3b54880eef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21735
12803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2173512803
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3092731965
Short name T317
Test name
Test status
Simulation time 167590339 ps
CPU time 1.99 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:40:57 PM PDT 24
Peak memory 203672 kb
Host smart-f2028252-93b1-40eb-b71c-7e34c26747e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927
31965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3092731965
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1156870944
Short name T182
Test name
Test status
Simulation time 8358544460 ps
CPU time 7.17 seconds
Started Mar 24 02:40:56 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 203508 kb
Host smart-a857a525-20d6-4f16-a1b3-d66ad1356bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11568
70944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1156870944
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2214575356
Short name T861
Test name
Test status
Simulation time 8438451777 ps
CPU time 7.06 seconds
Started Mar 24 02:40:56 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203496 kb
Host smart-44163c56-1788-4518-8d56-67c329800dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22145
75356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2214575356
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.4121674426
Short name T602
Test name
Test status
Simulation time 8414653222 ps
CPU time 9.79 seconds
Started Mar 24 02:40:59 PM PDT 24
Finished Mar 24 02:41:09 PM PDT 24
Peak memory 203592 kb
Host smart-6f943e47-8355-48be-9347-d5901a0e98d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41216
74426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.4121674426
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.780962923
Short name T320
Test name
Test status
Simulation time 8359965949 ps
CPU time 7.59 seconds
Started Mar 24 02:40:58 PM PDT 24
Finished Mar 24 02:41:06 PM PDT 24
Peak memory 203552 kb
Host smart-a58036fd-335f-49f0-9e7c-13d9e8fd7b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78096
2923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.780962923
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2732415215
Short name T96
Test name
Test status
Simulation time 8441254667 ps
CPU time 7.23 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203536 kb
Host smart-7550dcee-2d7b-489e-be18-55e06e13686b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27324
15215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2732415215
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.102766949
Short name T277
Test name
Test status
Simulation time 8371639217 ps
CPU time 7.79 seconds
Started Mar 24 02:40:58 PM PDT 24
Finished Mar 24 02:41:06 PM PDT 24
Peak memory 203576 kb
Host smart-731852ba-0972-40e5-9b69-db3ba4e42aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10276
6949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.102766949
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1782092353
Short name T765
Test name
Test status
Simulation time 28746681 ps
CPU time 0.65 seconds
Started Mar 24 02:40:55 PM PDT 24
Finished Mar 24 02:40:56 PM PDT 24
Peak memory 203400 kb
Host smart-b9190ece-f17c-4b7e-84c3-37661308fa6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17820
92353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1782092353
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2861038335
Short name T750
Test name
Test status
Simulation time 8400790374 ps
CPU time 7.92 seconds
Started Mar 24 02:40:59 PM PDT 24
Finished Mar 24 02:41:07 PM PDT 24
Peak memory 203484 kb
Host smart-0997adff-a1f9-48e2-8a98-ea326e3ec7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28610
38335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2861038335
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.120557734
Short name T134
Test name
Test status
Simulation time 8445357486 ps
CPU time 7.45 seconds
Started Mar 24 02:40:56 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 203524 kb
Host smart-993ae090-1f5b-41d7-b1ec-e9cc3e055518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12055
7734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.120557734
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.675700959
Short name T439
Test name
Test status
Simulation time 8385738264 ps
CPU time 7.07 seconds
Started Mar 24 02:40:57 PM PDT 24
Finished Mar 24 02:41:05 PM PDT 24
Peak memory 203544 kb
Host smart-1c6c03d3-14d4-47f5-b8b5-342fb7fefb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67570
0959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.675700959
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2105327094
Short name T75
Test name
Test status
Simulation time 87858886 ps
CPU time 0.97 seconds
Started Mar 24 02:41:02 PM PDT 24
Finished Mar 24 02:41:03 PM PDT 24
Peak memory 219476 kb
Host smart-1f2b9c3a-8aad-46c2-adbe-963c07173c19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2105327094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2105327094
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.261363253
Short name T368
Test name
Test status
Simulation time 8361080478 ps
CPU time 7.17 seconds
Started Mar 24 02:40:59 PM PDT 24
Finished Mar 24 02:41:07 PM PDT 24
Peak memory 203584 kb
Host smart-3ee776d5-9551-46cd-9dfc-beff1d276ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26136
3253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.261363253
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.712763470
Short name T159
Test name
Test status
Simulation time 8477483022 ps
CPU time 10 seconds
Started Mar 24 02:40:59 PM PDT 24
Finished Mar 24 02:41:10 PM PDT 24
Peak memory 203572 kb
Host smart-864bef33-2df5-4a3c-b748-05db3a12eb9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71276
3470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.712763470
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.504557065
Short name T48
Test name
Test status
Simulation time 8369521625 ps
CPU time 7.42 seconds
Started Mar 24 02:42:40 PM PDT 24
Finished Mar 24 02:42:48 PM PDT 24
Peak memory 203532 kb
Host smart-1933655f-aa58-4ecc-b7bf-f651ed4e6460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50455
7065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.504557065
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_enable.19822977
Short name T839
Test name
Test status
Simulation time 8368251560 ps
CPU time 7.76 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203484 kb
Host smart-f380c258-b5ad-4eab-92cc-8457426fe435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.19822977
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1633291718
Short name T285
Test name
Test status
Simulation time 43826999 ps
CPU time 1.28 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:45 PM PDT 24
Peak memory 203564 kb
Host smart-0f68d0f7-31ae-4eb2-8613-258cb58c440a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16332
91718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1633291718
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2155628371
Short name T170
Test name
Test status
Simulation time 8359350466 ps
CPU time 8.24 seconds
Started Mar 24 02:43:22 PM PDT 24
Finished Mar 24 02:43:31 PM PDT 24
Peak memory 203536 kb
Host smart-b20fe961-a93e-4a02-abd9-dc7af69a78e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21556
28371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2155628371
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1284855618
Short name T598
Test name
Test status
Simulation time 8454765885 ps
CPU time 7.6 seconds
Started Mar 24 02:42:39 PM PDT 24
Finished Mar 24 02:42:48 PM PDT 24
Peak memory 203576 kb
Host smart-367d94c4-bc87-4d18-94a4-986437ba8573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12848
55618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1284855618
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1135206666
Short name T370
Test name
Test status
Simulation time 8417182859 ps
CPU time 7.45 seconds
Started Mar 24 02:42:39 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203540 kb
Host smart-33ddae38-8657-4d99-be7d-ba27797365bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11352
06666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1135206666
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2528156079
Short name T434
Test name
Test status
Simulation time 8369787339 ps
CPU time 7.39 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203872 kb
Host smart-4a9df7af-cbaf-4b1d-9806-3e417c374bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25281
56079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2528156079
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3030461210
Short name T85
Test name
Test status
Simulation time 8415470986 ps
CPU time 8.33 seconds
Started Mar 24 02:42:40 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203536 kb
Host smart-ef9c4f2e-bd53-4385-9213-bb2c759014dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30304
61210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3030461210
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1052417791
Short name T694
Test name
Test status
Simulation time 8387015225 ps
CPU time 7.18 seconds
Started Mar 24 02:42:42 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203560 kb
Host smart-9eddd143-dd9e-4637-b4ab-f6558d26455a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10524
17791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1052417791
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1095388569
Short name T293
Test name
Test status
Simulation time 8366199132 ps
CPU time 7.01 seconds
Started Mar 24 02:42:40 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203548 kb
Host smart-85ab22e5-ceea-42cf-9e2d-83a595f5f9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10953
88569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1095388569
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.406269740
Short name T227
Test name
Test status
Simulation time 25988003 ps
CPU time 0.62 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:45 PM PDT 24
Peak memory 203452 kb
Host smart-c781c4be-c402-4e6b-b648-e7016e043be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40626
9740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.406269740
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.178273241
Short name T469
Test name
Test status
Simulation time 8373259850 ps
CPU time 9.67 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:55 PM PDT 24
Peak memory 203548 kb
Host smart-0c50bdf5-f50b-4142-a422-01d2a2d7f95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17827
3241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.178273241
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2064725923
Short name T14
Test name
Test status
Simulation time 8375635163 ps
CPU time 9.48 seconds
Started Mar 24 02:42:42 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203868 kb
Host smart-08768449-2625-4189-8728-c2b791cbae5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20647
25923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2064725923
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.1631991253
Short name T436
Test name
Test status
Simulation time 8393630747 ps
CPU time 7.56 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203556 kb
Host smart-f75be52b-cd4a-4be1-be2d-ba33c5ecd8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16319
91253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.1631991253
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3268506125
Short name T800
Test name
Test status
Simulation time 8356261758 ps
CPU time 6.89 seconds
Started Mar 24 02:43:12 PM PDT 24
Finished Mar 24 02:43:21 PM PDT 24
Peak memory 203568 kb
Host smart-b2a8337a-e1ef-4bb1-96d2-22d7ff0850cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32685
06125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3268506125
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2953249002
Short name T123
Test name
Test status
Simulation time 8478336703 ps
CPU time 7.66 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203872 kb
Host smart-6e7f3ad9-9f95-4276-9e94-ec82c7256d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29532
49002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2953249002
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3625547505
Short name T557
Test name
Test status
Simulation time 8370138459 ps
CPU time 8.3 seconds
Started Mar 24 02:42:47 PM PDT 24
Finished Mar 24 02:42:55 PM PDT 24
Peak memory 203524 kb
Host smart-b3f77bf2-3121-4f0e-8db8-f04ceff4a998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36255
47505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3625547505
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_enable.3229481336
Short name T667
Test name
Test status
Simulation time 8370219589 ps
CPU time 7.66 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203568 kb
Host smart-040b2da5-5e46-4bf1-97cf-128e57a3c9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32294
81336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3229481336
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.2704752242
Short name T530
Test name
Test status
Simulation time 67913638 ps
CPU time 1.89 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:46 PM PDT 24
Peak memory 203668 kb
Host smart-7282c96f-be85-4979-b457-879c4603be78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27047
52242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.2704752242
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2775057213
Short name T185
Test name
Test status
Simulation time 8362661451 ps
CPU time 7.41 seconds
Started Mar 24 02:42:51 PM PDT 24
Finished Mar 24 02:42:58 PM PDT 24
Peak memory 203548 kb
Host smart-9263f35f-4acc-4ee4-9a04-31f83289c967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27750
57213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2775057213
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1407568182
Short name T648
Test name
Test status
Simulation time 8391478517 ps
CPU time 8.53 seconds
Started Mar 24 02:42:52 PM PDT 24
Finished Mar 24 02:43:06 PM PDT 24
Peak memory 203556 kb
Host smart-fd9954ec-58da-4476-89b4-c4adb23083cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14075
68182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1407568182
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1373003101
Short name T744
Test name
Test status
Simulation time 8411531720 ps
CPU time 8.38 seconds
Started Mar 24 02:42:51 PM PDT 24
Finished Mar 24 02:42:59 PM PDT 24
Peak memory 203556 kb
Host smart-f97d2a1b-f84f-4b67-81e7-1313b1972b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13730
03101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1373003101
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.643160701
Short name T528
Test name
Test status
Simulation time 8363166510 ps
CPU time 7.99 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:53 PM PDT 24
Peak memory 203560 kb
Host smart-ea743f38-127c-4f21-a366-2070ce40741f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64316
0701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.643160701
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.196515291
Short name T445
Test name
Test status
Simulation time 8381407277 ps
CPU time 7.44 seconds
Started Mar 24 02:42:41 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203540 kb
Host smart-c2f1e180-5590-4a7a-afa1-0d672a3ec858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19651
5291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.196515291
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3431781228
Short name T657
Test name
Test status
Simulation time 8378038123 ps
CPU time 8.18 seconds
Started Mar 24 02:42:51 PM PDT 24
Finished Mar 24 02:42:59 PM PDT 24
Peak memory 203552 kb
Host smart-4b67d342-2721-45b0-becf-2f44782439c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34317
81228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3431781228
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2905135977
Short name T412
Test name
Test status
Simulation time 8405696583 ps
CPU time 8.76 seconds
Started Mar 24 02:42:55 PM PDT 24
Finished Mar 24 02:43:04 PM PDT 24
Peak memory 203576 kb
Host smart-34cd385d-b6c5-4b1a-95d9-9f35e368baa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29051
35977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2905135977
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.453952590
Short name T635
Test name
Test status
Simulation time 23970463 ps
CPU time 0.66 seconds
Started Mar 24 02:42:57 PM PDT 24
Finished Mar 24 02:42:58 PM PDT 24
Peak memory 203420 kb
Host smart-c468c850-1827-4a55-a117-83bc5d1ae67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45395
2590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.453952590
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2547205634
Short name T796
Test name
Test status
Simulation time 8390913105 ps
CPU time 7.29 seconds
Started Mar 24 02:42:46 PM PDT 24
Finished Mar 24 02:42:53 PM PDT 24
Peak memory 203560 kb
Host smart-88b7e327-6908-45ce-a921-8ce74d1ce932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25472
05634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2547205634
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.439985768
Short name T29
Test name
Test status
Simulation time 8436515466 ps
CPU time 7.35 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203560 kb
Host smart-cb306f7e-a787-45c9-af70-4abcd552fea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43998
5768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.439985768
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2726957211
Short name T380
Test name
Test status
Simulation time 8382373827 ps
CPU time 7.58 seconds
Started Mar 24 02:42:43 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 203572 kb
Host smart-cfa08689-93cd-4f42-b491-6cc338f5f7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27269
57211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2726957211
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.642170874
Short name T531
Test name
Test status
Simulation time 8364254740 ps
CPU time 8.5 seconds
Started Mar 24 02:42:43 PM PDT 24
Finished Mar 24 02:42:51 PM PDT 24
Peak memory 203568 kb
Host smart-ae9b7657-a8bd-44d3-b1f0-0b548ff9b175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64217
0874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.642170874
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.4124733399
Short name T131
Test name
Test status
Simulation time 8476777822 ps
CPU time 7.61 seconds
Started Mar 24 02:42:56 PM PDT 24
Finished Mar 24 02:43:04 PM PDT 24
Peak memory 203596 kb
Host smart-7daca343-4ffe-44a9-9498-92eea29849af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41247
33399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.4124733399
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2916441352
Short name T10
Test name
Test status
Simulation time 8372722582 ps
CPU time 8.28 seconds
Started Mar 24 02:42:45 PM PDT 24
Finished Mar 24 02:42:53 PM PDT 24
Peak memory 203532 kb
Host smart-df1f751c-10ea-4b9d-92f8-63ae6b999b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29164
41352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2916441352
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_enable.4047893279
Short name T719
Test name
Test status
Simulation time 8365587599 ps
CPU time 6.99 seconds
Started Mar 24 02:42:51 PM PDT 24
Finished Mar 24 02:42:58 PM PDT 24
Peak memory 203548 kb
Host smart-1bff792b-70b5-4f09-85fe-44f931e7ad1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40478
93279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.4047893279
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2920894151
Short name T558
Test name
Test status
Simulation time 51010258 ps
CPU time 1.26 seconds
Started Mar 24 02:42:46 PM PDT 24
Finished Mar 24 02:42:47 PM PDT 24
Peak memory 203604 kb
Host smart-4cb62de6-e089-43f5-8e5a-cbadee0d30c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29208
94151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2920894151
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3163954353
Short name T5
Test name
Test status
Simulation time 8363033907 ps
CPU time 7.27 seconds
Started Mar 24 02:42:46 PM PDT 24
Finished Mar 24 02:42:54 PM PDT 24
Peak memory 203488 kb
Host smart-aa06156e-8860-40b3-a54d-6dc6fffe1c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31639
54353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3163954353
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2052832276
Short name T547
Test name
Test status
Simulation time 8380121168 ps
CPU time 8.82 seconds
Started Mar 24 02:42:46 PM PDT 24
Finished Mar 24 02:42:55 PM PDT 24
Peak memory 203552 kb
Host smart-2871a48e-dd24-45a7-a220-c17091093593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20528
32276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2052832276
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.797770028
Short name T229
Test name
Test status
Simulation time 8408380151 ps
CPU time 8.46 seconds
Started Mar 24 02:43:04 PM PDT 24
Finished Mar 24 02:43:13 PM PDT 24
Peak memory 203572 kb
Host smart-072fec71-5ac0-4997-9c11-a1b6f450f6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79777
0028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.797770028
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1304647379
Short name T395
Test name
Test status
Simulation time 8361069421 ps
CPU time 8.09 seconds
Started Mar 24 02:42:43 PM PDT 24
Finished Mar 24 02:42:51 PM PDT 24
Peak memory 203568 kb
Host smart-6a8392e9-f935-41d5-a487-cc458f4f0581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13046
47379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1304647379
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.868673959
Short name T584
Test name
Test status
Simulation time 8443502631 ps
CPU time 7.78 seconds
Started Mar 24 02:43:04 PM PDT 24
Finished Mar 24 02:43:13 PM PDT 24
Peak memory 203540 kb
Host smart-b25950fb-62d4-419c-a529-4d534b0ca915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86867
3959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.868673959
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1149414495
Short name T490
Test name
Test status
Simulation time 8387556877 ps
CPU time 7.46 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:52 PM PDT 24
Peak memory 203484 kb
Host smart-b3d77624-81f2-43f9-b68e-473117b8fd62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11494
14495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1149414495
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.574907822
Short name T829
Test name
Test status
Simulation time 8372898682 ps
CPU time 8.83 seconds
Started Mar 24 02:42:44 PM PDT 24
Finished Mar 24 02:42:53 PM PDT 24
Peak memory 203552 kb
Host smart-cfd9b995-b89f-48f2-b46b-61671cbbe574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57490
7822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.574907822
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3206403802
Short name T641
Test name
Test status
Simulation time 31368691 ps
CPU time 0.65 seconds
Started Mar 24 02:42:48 PM PDT 24
Finished Mar 24 02:42:49 PM PDT 24
Peak memory 203440 kb
Host smart-10d18f01-bb8e-4f21-b9a7-6bf4a60bde15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064
03802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3206403802
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.130127459
Short name T877
Test name
Test status
Simulation time 8374648913 ps
CPU time 7.49 seconds
Started Mar 24 02:43:10 PM PDT 24
Finished Mar 24 02:43:20 PM PDT 24
Peak memory 203544 kb
Host smart-f48370f1-af2e-4953-b11e-8664c12b530f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13012
7459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.130127459
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2741405449
Short name T124
Test name
Test status
Simulation time 8389594078 ps
CPU time 7.14 seconds
Started Mar 24 02:42:57 PM PDT 24
Finished Mar 24 02:43:04 PM PDT 24
Peak memory 203560 kb
Host smart-403f3de2-1d3e-41d8-9cf3-a0351593b60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27414
05449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2741405449
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.1922476440
Short name T706
Test name
Test status
Simulation time 8404941069 ps
CPU time 8.07 seconds
Started Mar 24 02:43:08 PM PDT 24
Finished Mar 24 02:43:17 PM PDT 24
Peak memory 203572 kb
Host smart-1ec8eb54-6726-44b4-8aa1-333a4e949737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19224
76440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.1922476440
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2610228114
Short name T389
Test name
Test status
Simulation time 8359293831 ps
CPU time 7.55 seconds
Started Mar 24 02:42:53 PM PDT 24
Finished Mar 24 02:43:01 PM PDT 24
Peak memory 203572 kb
Host smart-f52ed3d9-c427-461a-9a4e-bc577ba749fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
28114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2610228114
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.231887607
Short name T148
Test name
Test status
Simulation time 8476527722 ps
CPU time 8.04 seconds
Started Mar 24 02:43:10 PM PDT 24
Finished Mar 24 02:43:20 PM PDT 24
Peak memory 203572 kb
Host smart-fe2f6904-1d45-4657-b222-06bf01237042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23188
7607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.231887607
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3580646775
Short name T447
Test name
Test status
Simulation time 8371604087 ps
CPU time 7.38 seconds
Started Mar 24 02:42:48 PM PDT 24
Finished Mar 24 02:42:55 PM PDT 24
Peak memory 203548 kb
Host smart-2075fc34-09f7-4ad9-a112-aebc12a4a2f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
46775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3580646775
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_enable.649258852
Short name T296
Test name
Test status
Simulation time 8368137481 ps
CPU time 8.19 seconds
Started Mar 24 02:42:49 PM PDT 24
Finished Mar 24 02:42:57 PM PDT 24
Peak memory 203560 kb
Host smart-07d1962f-64fc-42c1-90dd-04cb15c9abd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64925
8852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.649258852
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.216638517
Short name T333
Test name
Test status
Simulation time 74344893 ps
CPU time 1.94 seconds
Started Mar 24 02:43:08 PM PDT 24
Finished Mar 24 02:43:11 PM PDT 24
Peak memory 203648 kb
Host smart-4c76cf9f-29a8-4a60-9ba7-6fb6aff49ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21663
8517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.216638517
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2836109781
Short name T178
Test name
Test status
Simulation time 8355469733 ps
CPU time 6.91 seconds
Started Mar 24 02:42:49 PM PDT 24
Finished Mar 24 02:42:56 PM PDT 24
Peak memory 203568 kb
Host smart-359d4092-75d0-42a7-a055-3c117a41705e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28361
09781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2836109781
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.936728496
Short name T592
Test name
Test status
Simulation time 8438237927 ps
CPU time 7.36 seconds
Started Mar 24 02:42:52 PM PDT 24
Finished Mar 24 02:43:00 PM PDT 24
Peak memory 203548 kb
Host smart-6bd5627e-eee5-473f-ae70-c1170e969a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93672
8496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.936728496
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.691860340
Short name T435
Test name
Test status
Simulation time 8413079798 ps
CPU time 7.71 seconds
Started Mar 24 02:42:49 PM PDT 24
Finished Mar 24 02:42:57 PM PDT 24
Peak memory 203540 kb
Host smart-0d3fdf44-3994-4788-8730-e50de4f432b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69186
0340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.691860340
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1864125322
Short name T290
Test name
Test status
Simulation time 8360159647 ps
CPU time 6.98 seconds
Started Mar 24 02:42:49 PM PDT 24
Finished Mar 24 02:42:56 PM PDT 24
Peak memory 203576 kb
Host smart-b2672828-69d5-44e4-b019-b012ca89c203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18641
25322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1864125322
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3722352763
Short name T429
Test name
Test status
Simulation time 8412017285 ps
CPU time 7.38 seconds
Started Mar 24 02:43:11 PM PDT 24
Finished Mar 24 02:43:22 PM PDT 24
Peak memory 203556 kb
Host smart-438bc77f-9412-4518-930b-36690db52cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37223
52763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3722352763
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3257156854
Short name T466
Test name
Test status
Simulation time 8384918629 ps
CPU time 7.38 seconds
Started Mar 24 02:42:53 PM PDT 24
Finished Mar 24 02:43:01 PM PDT 24
Peak memory 203556 kb
Host smart-a53d489b-a9b7-4dc0-bbd2-61dd83af97f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32571
56854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3257156854
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2493222178
Short name T818
Test name
Test status
Simulation time 8365073364 ps
CPU time 8.64 seconds
Started Mar 24 02:42:53 PM PDT 24
Finished Mar 24 02:43:02 PM PDT 24
Peak memory 203552 kb
Host smart-e66f9765-9f7c-4a18-9cfc-c463b5543bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24932
22178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2493222178
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3013934976
Short name T753
Test name
Test status
Simulation time 23555036 ps
CPU time 0.63 seconds
Started Mar 24 02:43:06 PM PDT 24
Finished Mar 24 02:43:09 PM PDT 24
Peak memory 203420 kb
Host smart-96158cf4-130d-4f93-9456-b9c48f7d8513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30139
34976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3013934976
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.127757411
Short name T308
Test name
Test status
Simulation time 8370257668 ps
CPU time 7.85 seconds
Started Mar 24 02:42:48 PM PDT 24
Finished Mar 24 02:42:56 PM PDT 24
Peak memory 203528 kb
Host smart-9ecc0652-f8a6-41cd-b02c-4bc63896023b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12775
7411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.127757411
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2427357158
Short name T525
Test name
Test status
Simulation time 8453167136 ps
CPU time 7.85 seconds
Started Mar 24 02:42:50 PM PDT 24
Finished Mar 24 02:42:58 PM PDT 24
Peak memory 203552 kb
Host smart-1a8f245d-300d-4664-9065-4e1ad8cae995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24273
57158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2427357158
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.402487442
Short name T610
Test name
Test status
Simulation time 8401414849 ps
CPU time 7.2 seconds
Started Mar 24 02:42:51 PM PDT 24
Finished Mar 24 02:42:59 PM PDT 24
Peak memory 203588 kb
Host smart-57fe8aca-fcf5-4fef-a5c6-ff1f4b32635c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40248
7442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.402487442
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.4045237609
Short name T840
Test name
Test status
Simulation time 8361619014 ps
CPU time 7.88 seconds
Started Mar 24 02:42:48 PM PDT 24
Finished Mar 24 02:42:56 PM PDT 24
Peak memory 203552 kb
Host smart-2f6b5878-e213-4ca5-9033-9e76ae3e440d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40452
37609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.4045237609
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2405456751
Short name T141
Test name
Test status
Simulation time 8479598391 ps
CPU time 9.53 seconds
Started Mar 24 02:43:05 PM PDT 24
Finished Mar 24 02:43:15 PM PDT 24
Peak memory 203592 kb
Host smart-e979cd67-e3c0-4cbe-a567-45e4b7e80618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24054
56751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2405456751
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1511529781
Short name T363
Test name
Test status
Simulation time 8369907572 ps
CPU time 7.48 seconds
Started Mar 24 02:42:52 PM PDT 24
Finished Mar 24 02:43:00 PM PDT 24
Peak memory 203548 kb
Host smart-d5acc798-e4a8-4801-9796-2f226fb5306b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15115
29781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1511529781
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_enable.1148484394
Short name T38
Test name
Test status
Simulation time 8372098188 ps
CPU time 8.31 seconds
Started Mar 24 02:42:47 PM PDT 24
Finished Mar 24 02:42:56 PM PDT 24
Peak memory 203604 kb
Host smart-c7c2055b-b1d9-45aa-a8c8-51b5aa80e7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11484
84394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1148484394
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1819264684
Short name T821
Test name
Test status
Simulation time 70135964 ps
CPU time 2.04 seconds
Started Mar 24 02:43:12 PM PDT 24
Finished Mar 24 02:43:16 PM PDT 24
Peak memory 203664 kb
Host smart-afcb8abb-7116-4ea0-a545-2379f70138d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
64684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1819264684
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2170529492
Short name T872
Test name
Test status
Simulation time 8356531086 ps
CPU time 7.13 seconds
Started Mar 24 02:42:53 PM PDT 24
Finished Mar 24 02:43:01 PM PDT 24
Peak memory 203516 kb
Host smart-9754d4ac-6b5b-4f0a-9809-5d304f2af539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21705
29492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2170529492
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.1314435121
Short name T239
Test name
Test status
Simulation time 8434341624 ps
CPU time 7.86 seconds
Started Mar 24 02:43:08 PM PDT 24
Finished Mar 24 02:43:17 PM PDT 24
Peak memory 203556 kb
Host smart-6767594a-f21a-41cd-ad36-4d8437b2a849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13144
35121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1314435121
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2905548133
Short name T783
Test name
Test status
Simulation time 8403539170 ps
CPU time 7.7 seconds
Started Mar 24 02:43:10 PM PDT 24
Finished Mar 24 02:43:22 PM PDT 24
Peak memory 203788 kb
Host smart-7312c98b-0ee9-4684-aebd-cd19871ea886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
48133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2905548133
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1812529555
Short name T824
Test name
Test status
Simulation time 8366396446 ps
CPU time 7.07 seconds
Started Mar 24 02:43:14 PM PDT 24
Finished Mar 24 02:43:23 PM PDT 24
Peak memory 203548 kb
Host smart-1d2fd260-a7ac-401b-a07b-61d25ab25108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18125
29555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1812529555
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1537886307
Short name T34
Test name
Test status
Simulation time 8396537500 ps
CPU time 9.31 seconds
Started Mar 24 02:42:53 PM PDT 24
Finished Mar 24 02:43:03 PM PDT 24
Peak memory 203552 kb
Host smart-6b49dab8-3e45-4f1c-80f2-ff8c3a7ed924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15378
86307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1537886307
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.4267284600
Short name T321
Test name
Test status
Simulation time 8378702685 ps
CPU time 7.39 seconds
Started Mar 24 02:42:54 PM PDT 24
Finished Mar 24 02:43:02 PM PDT 24
Peak memory 203564 kb
Host smart-85b3a863-a1b1-4455-98ce-bd49de287389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42672
84600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4267284600
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3516147568
Short name T414
Test name
Test status
Simulation time 8362733206 ps
CPU time 7.78 seconds
Started Mar 24 02:43:08 PM PDT 24
Finished Mar 24 02:43:17 PM PDT 24
Peak memory 203576 kb
Host smart-8890a45e-f5aa-4acc-a2b5-666b8e601e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35161
47568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3516147568
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.4268391970
Short name T572
Test name
Test status
Simulation time 30764017 ps
CPU time 0.65 seconds
Started Mar 24 02:42:57 PM PDT 24
Finished Mar 24 02:42:58 PM PDT 24
Peak memory 203496 kb
Host smart-65ac43c7-8907-44e6-9cfc-da46e42093cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42683
91970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.4268391970
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1438684572
Short name T275
Test name
Test status
Simulation time 8377097052 ps
CPU time 7.9 seconds
Started Mar 24 02:42:53 PM PDT 24
Finished Mar 24 02:43:02 PM PDT 24
Peak memory 203580 kb
Host smart-a78a3e63-6cc8-4654-be4d-cdc9f9cc75f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14386
84572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1438684572
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.749341596
Short name T799
Test name
Test status
Simulation time 8450021613 ps
CPU time 7.83 seconds
Started Mar 24 02:43:10 PM PDT 24
Finished Mar 24 02:43:20 PM PDT 24
Peak memory 203568 kb
Host smart-01fbeec3-2386-48e4-9e7c-106624c63e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74934
1596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.749341596
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.907181575
Short name T815
Test name
Test status
Simulation time 8368460805 ps
CPU time 7.6 seconds
Started Mar 24 02:43:01 PM PDT 24
Finished Mar 24 02:43:09 PM PDT 24
Peak memory 203544 kb
Host smart-a80c1046-a06b-4d84-b4f8-8f4d7a0ab6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90718
1575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.907181575
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.555969437
Short name T478
Test name
Test status
Simulation time 8354947550 ps
CPU time 7.2 seconds
Started Mar 24 02:42:56 PM PDT 24
Finished Mar 24 02:43:03 PM PDT 24
Peak memory 203488 kb
Host smart-d2b68b11-7749-4993-a883-f24f25ea2be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55596
9437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.555969437
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1313214139
Short name T144
Test name
Test status
Simulation time 8470478026 ps
CPU time 9.56 seconds
Started Mar 24 02:42:51 PM PDT 24
Finished Mar 24 02:43:00 PM PDT 24
Peak memory 203556 kb
Host smart-e4b574d5-34cf-40aa-88e1-85e32f9ae78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13132
14139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1313214139
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.891496651
Short name T351
Test name
Test status
Simulation time 8372151377 ps
CPU time 8.77 seconds
Started Mar 24 02:42:57 PM PDT 24
Finished Mar 24 02:43:06 PM PDT 24
Peak memory 203552 kb
Host smart-ae0fb87e-9f21-4aff-97f6-2502bfb4c858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89149
6651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.891496651
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_enable.477266064
Short name T587
Test name
Test status
Simulation time 8366631516 ps
CPU time 7.94 seconds
Started Mar 24 02:43:11 PM PDT 24
Finished Mar 24 02:43:22 PM PDT 24
Peak memory 203548 kb
Host smart-df648f95-ca58-4a97-bdd2-b1ef4a629505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47726
6064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.477266064
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3432736852
Short name T479
Test name
Test status
Simulation time 175111859 ps
CPU time 2.04 seconds
Started Mar 24 02:42:52 PM PDT 24
Finished Mar 24 02:42:54 PM PDT 24
Peak memory 203632 kb
Host smart-29ad601b-3df8-439d-9b9b-f5d8ef20434b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34327
36852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3432736852
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3696498869
Short name T11
Test name
Test status
Simulation time 8362436170 ps
CPU time 10.09 seconds
Started Mar 24 02:43:19 PM PDT 24
Finished Mar 24 02:43:29 PM PDT 24
Peak memory 203572 kb
Host smart-acbecb07-1107-49fc-b484-2b7c122f4482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36964
98869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3696498869
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2621219791
Short name T571
Test name
Test status
Simulation time 8442435014 ps
CPU time 7.44 seconds
Started Mar 24 02:43:10 PM PDT 24
Finished Mar 24 02:43:20 PM PDT 24
Peak memory 203540 kb
Host smart-93791e88-eb81-4ca5-8a0c-61914c02f253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26212
19791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2621219791
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1257776139
Short name T340
Test name
Test status
Simulation time 8407578838 ps
CPU time 7.57 seconds
Started Mar 24 02:43:23 PM PDT 24
Finished Mar 24 02:43:31 PM PDT 24
Peak memory 203584 kb
Host smart-c587f724-f7f0-4750-9c81-2ad2208102da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
76139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1257776139
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3070857632
Short name T579
Test name
Test status
Simulation time 8364858991 ps
CPU time 7.52 seconds
Started Mar 24 02:43:05 PM PDT 24
Finished Mar 24 02:43:13 PM PDT 24
Peak memory 203580 kb
Host smart-4b5909eb-7078-4743-8ec9-5246132e40b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30708
57632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3070857632
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1935196986
Short name T655
Test name
Test status
Simulation time 8395207906 ps
CPU time 7.79 seconds
Started Mar 24 02:43:00 PM PDT 24
Finished Mar 24 02:43:08 PM PDT 24
Peak memory 202804 kb
Host smart-0d191d53-3973-4e20-81fe-cfb1d7710eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
96986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1935196986
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1754242386
Short name T539
Test name
Test status
Simulation time 8405314321 ps
CPU time 7.2 seconds
Started Mar 24 02:43:13 PM PDT 24
Finished Mar 24 02:43:23 PM PDT 24
Peak memory 203568 kb
Host smart-7844e1af-fd6d-4038-85dd-3ad673dafc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17542
42386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1754242386
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3327279400
Short name T418
Test name
Test status
Simulation time 8397768272 ps
CPU time 7.86 seconds
Started Mar 24 02:43:00 PM PDT 24
Finished Mar 24 02:43:08 PM PDT 24
Peak memory 203536 kb
Host smart-44f4f25d-3c8a-4211-8f95-38be31805f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33272
79400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3327279400
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.34156927
Short name T654
Test name
Test status
Simulation time 26297109 ps
CPU time 0.66 seconds
Started Mar 24 02:43:16 PM PDT 24
Finished Mar 24 02:43:19 PM PDT 24
Peak memory 203440 kb
Host smart-4c9d6791-ca32-47c3-9abf-732129466ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34156
927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.34156927
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.4040528232
Short name T45
Test name
Test status
Simulation time 8397077363 ps
CPU time 7.34 seconds
Started Mar 24 02:43:00 PM PDT 24
Finished Mar 24 02:43:08 PM PDT 24
Peak memory 203560 kb
Host smart-cb0f650f-784b-4ab2-8152-e6d49f25ad86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40405
28232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.4040528232
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.686598231
Short name T289
Test name
Test status
Simulation time 8412927000 ps
CPU time 7.58 seconds
Started Mar 24 02:43:24 PM PDT 24
Finished Mar 24 02:43:32 PM PDT 24
Peak memory 203572 kb
Host smart-ae2a0c91-b26d-4dc5-be4f-2faac33e07ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68659
8231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.686598231
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.3599521179
Short name T299
Test name
Test status
Simulation time 8383317190 ps
CPU time 7.9 seconds
Started Mar 24 02:43:02 PM PDT 24
Finished Mar 24 02:43:11 PM PDT 24
Peak memory 203556 kb
Host smart-90ed0925-2980-480c-b123-e01dbe87fdd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35995
21179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.3599521179
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1871297717
Short name T611
Test name
Test status
Simulation time 8363380125 ps
CPU time 8.62 seconds
Started Mar 24 02:43:15 PM PDT 24
Finished Mar 24 02:43:27 PM PDT 24
Peak memory 203572 kb
Host smart-a0c3c2df-0acb-46c0-8b58-b65aed83449e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18712
97717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1871297717
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2484499588
Short name T708
Test name
Test status
Simulation time 8476236035 ps
CPU time 9.47 seconds
Started Mar 24 02:42:52 PM PDT 24
Finished Mar 24 02:43:02 PM PDT 24
Peak memory 203496 kb
Host smart-d2e19aaf-2754-43bb-8735-b10cdc6af436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24844
99588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2484499588
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.525508395
Short name T288
Test name
Test status
Simulation time 8369823243 ps
CPU time 7.39 seconds
Started Mar 24 02:43:02 PM PDT 24
Finished Mar 24 02:43:10 PM PDT 24
Peak memory 203544 kb
Host smart-31b3aada-e852-48a2-ae11-02844b1f1424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52550
8395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.525508395
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_enable.2816092664
Short name T850
Test name
Test status
Simulation time 8369720442 ps
CPU time 7.38 seconds
Started Mar 24 02:43:01 PM PDT 24
Finished Mar 24 02:43:08 PM PDT 24
Peak memory 203536 kb
Host smart-097a4c11-eb05-498f-80f5-fefa459da358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28160
92664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2816092664
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3810045948
Short name T359
Test name
Test status
Simulation time 49900016 ps
CPU time 1.47 seconds
Started Mar 24 02:43:20 PM PDT 24
Finished Mar 24 02:43:21 PM PDT 24
Peak memory 203604 kb
Host smart-dcd7eb17-8b97-4021-b6f2-90b5b090650f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38100
45948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3810045948
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1984025067
Short name T162
Test name
Test status
Simulation time 8358779490 ps
CPU time 7.4 seconds
Started Mar 24 02:43:00 PM PDT 24
Finished Mar 24 02:43:08 PM PDT 24
Peak memory 202792 kb
Host smart-5923cbe2-74f4-4541-8d9f-d90a2f030c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19840
25067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1984025067
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1551686153
Short name T550
Test name
Test status
Simulation time 8438588487 ps
CPU time 7 seconds
Started Mar 24 02:43:13 PM PDT 24
Finished Mar 24 02:43:23 PM PDT 24
Peak memory 203496 kb
Host smart-f081f994-4acc-4225-b402-a1e96a492b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15516
86153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1551686153
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2536372720
Short name T297
Test name
Test status
Simulation time 8410431776 ps
CPU time 7.03 seconds
Started Mar 24 02:43:03 PM PDT 24
Finished Mar 24 02:43:11 PM PDT 24
Peak memory 203788 kb
Host smart-e6ec1c03-a0ba-4237-8f2f-ce165e4b88a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25363
72720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2536372720
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.969105920
Short name T319
Test name
Test status
Simulation time 8363249155 ps
CPU time 7.33 seconds
Started Mar 24 02:42:59 PM PDT 24
Finished Mar 24 02:43:06 PM PDT 24
Peak memory 203524 kb
Host smart-435ac068-5648-465b-a125-1719ab9efca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96910
5920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.969105920
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1481517176
Short name T870
Test name
Test status
Simulation time 8443531671 ps
CPU time 10.28 seconds
Started Mar 24 02:43:01 PM PDT 24
Finished Mar 24 02:43:12 PM PDT 24
Peak memory 203544 kb
Host smart-751953a6-3022-425f-abdb-ba2d8dff1ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14815
17176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1481517176
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3637191179
Short name T356
Test name
Test status
Simulation time 8372485019 ps
CPU time 7.28 seconds
Started Mar 24 02:43:04 PM PDT 24
Finished Mar 24 02:43:12 PM PDT 24
Peak memory 203544 kb
Host smart-eef335af-bc2f-47e0-9ba0-d19f6992c31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36371
91179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3637191179
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1883417282
Short name T472
Test name
Test status
Simulation time 8400405260 ps
CPU time 7.75 seconds
Started Mar 24 02:43:02 PM PDT 24
Finished Mar 24 02:43:11 PM PDT 24
Peak memory 203572 kb
Host smart-874ca734-dcfe-455b-a773-04a355e1c8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18834
17282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1883417282
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.233475200
Short name T41
Test name
Test status
Simulation time 27054954 ps
CPU time 0.63 seconds
Started Mar 24 02:43:01 PM PDT 24
Finished Mar 24 02:43:02 PM PDT 24
Peak memory 203416 kb
Host smart-19af3e89-e067-4b97-9d28-badb1dd9113f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23347
5200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.233475200
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1848535943
Short name T845
Test name
Test status
Simulation time 8388384236 ps
CPU time 7.11 seconds
Started Mar 24 02:42:59 PM PDT 24
Finished Mar 24 02:43:07 PM PDT 24
Peak memory 203496 kb
Host smart-a4f69e72-09ff-4704-a46d-c4afd72410fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18485
35943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1848535943
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3126391827
Short name T135
Test name
Test status
Simulation time 8416711036 ps
CPU time 7.27 seconds
Started Mar 24 02:43:02 PM PDT 24
Finished Mar 24 02:43:10 PM PDT 24
Peak memory 203460 kb
Host smart-f006f2c8-46bb-48c1-97b1-e85dd2b660df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31263
91827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3126391827
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.260038006
Short name T792
Test name
Test status
Simulation time 8382535640 ps
CPU time 8.86 seconds
Started Mar 24 02:42:59 PM PDT 24
Finished Mar 24 02:43:08 PM PDT 24
Peak memory 203620 kb
Host smart-5d753b72-7d98-491f-ba07-201fade01f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26003
8006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.260038006
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2228226892
Short name T505
Test name
Test status
Simulation time 8357479122 ps
CPU time 8.33 seconds
Started Mar 24 02:43:01 PM PDT 24
Finished Mar 24 02:43:09 PM PDT 24
Peak memory 203540 kb
Host smart-8493fcd7-e15f-4afb-825c-24a416299450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282
26892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2228226892
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.806638805
Short name T143
Test name
Test status
Simulation time 8475319567 ps
CPU time 8.99 seconds
Started Mar 24 02:43:06 PM PDT 24
Finished Mar 24 02:43:15 PM PDT 24
Peak memory 203600 kb
Host smart-9b850074-a92c-41ea-906f-991401fac992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80663
8805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.806638805
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.220689894
Short name T607
Test name
Test status
Simulation time 8368092621 ps
CPU time 7.27 seconds
Started Mar 24 02:43:15 PM PDT 24
Finished Mar 24 02:43:25 PM PDT 24
Peak memory 203568 kb
Host smart-ad4929a7-0f68-4c0b-82e3-3ab0bb612382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22068
9894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.220689894
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_enable.2363168225
Short name T551
Test name
Test status
Simulation time 8373860034 ps
CPU time 7.4 seconds
Started Mar 24 02:43:02 PM PDT 24
Finished Mar 24 02:43:10 PM PDT 24
Peak memory 203532 kb
Host smart-b1659448-c3fd-4aa7-8659-99d002c9f65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23631
68225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2363168225
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.482992908
Short name T743
Test name
Test status
Simulation time 186853311 ps
CPU time 2.05 seconds
Started Mar 24 02:43:20 PM PDT 24
Finished Mar 24 02:43:22 PM PDT 24
Peak memory 203592 kb
Host smart-38c9e377-2d18-4d53-ac07-190406250f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48299
2908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.482992908
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.2873894866
Short name T175
Test name
Test status
Simulation time 8363823950 ps
CPU time 7.44 seconds
Started Mar 24 02:43:01 PM PDT 24
Finished Mar 24 02:43:09 PM PDT 24
Peak memory 203556 kb
Host smart-28006b59-4c5f-4bad-8ebe-1e9ad43ccc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28738
94866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.2873894866
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1638382211
Short name T133
Test name
Test status
Simulation time 8392923947 ps
CPU time 7.63 seconds
Started Mar 24 02:43:02 PM PDT 24
Finished Mar 24 02:43:11 PM PDT 24
Peak memory 203528 kb
Host smart-c475fbd2-a781-4c4a-9447-f549630bc612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
82211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1638382211
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.851098942
Short name T378
Test name
Test status
Simulation time 8405292341 ps
CPU time 7.2 seconds
Started Mar 24 02:43:14 PM PDT 24
Finished Mar 24 02:43:23 PM PDT 24
Peak memory 203588 kb
Host smart-997c1a59-9210-4c55-aa07-b1ab0370c409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85109
8942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.851098942
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4242501950
Short name T838
Test name
Test status
Simulation time 8367463887 ps
CPU time 7.37 seconds
Started Mar 24 02:43:06 PM PDT 24
Finished Mar 24 02:43:15 PM PDT 24
Peak memory 203540 kb
Host smart-762bba25-31a2-4435-9a1b-6a0d03551323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42425
01950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4242501950
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.122888171
Short name T98
Test name
Test status
Simulation time 8382288848 ps
CPU time 7.91 seconds
Started Mar 24 02:43:03 PM PDT 24
Finished Mar 24 02:43:13 PM PDT 24
Peak memory 203556 kb
Host smart-c0560a60-dca8-4744-8fae-5f2b8019a03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12288
8171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.122888171
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1305233223
Short name T590
Test name
Test status
Simulation time 8371199189 ps
CPU time 7.73 seconds
Started Mar 24 02:43:22 PM PDT 24
Finished Mar 24 02:43:30 PM PDT 24
Peak memory 203568 kb
Host smart-55c06b2a-a7aa-4f99-a252-4f8afbe26160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13052
33223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1305233223
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1359799574
Short name T410
Test name
Test status
Simulation time 8365043987 ps
CPU time 7.99 seconds
Started Mar 24 02:43:23 PM PDT 24
Finished Mar 24 02:43:31 PM PDT 24
Peak memory 203588 kb
Host smart-4fb8a383-fd4e-4b8e-bb6d-2f1725a2b5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13597
99574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1359799574
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1696811199
Short name T367
Test name
Test status
Simulation time 25606278 ps
CPU time 0.65 seconds
Started Mar 24 02:43:18 PM PDT 24
Finished Mar 24 02:43:19 PM PDT 24
Peak memory 203360 kb
Host smart-bc768a62-264e-43df-9375-9d29e333d548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16968
11199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1696811199
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3501540871
Short name T231
Test name
Test status
Simulation time 8368137818 ps
CPU time 7.84 seconds
Started Mar 24 02:43:03 PM PDT 24
Finished Mar 24 02:43:11 PM PDT 24
Peak memory 203560 kb
Host smart-391f338a-73a9-4b40-9755-92e876423057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35015
40871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3501540871
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2501579704
Short name T789
Test name
Test status
Simulation time 8446298494 ps
CPU time 7.12 seconds
Started Mar 24 02:43:01 PM PDT 24
Finished Mar 24 02:43:08 PM PDT 24
Peak memory 203540 kb
Host smart-103c3e32-534a-4e4f-833e-75f55a6d7547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25015
79704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2501579704
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3571897195
Short name T597
Test name
Test status
Simulation time 8399817785 ps
CPU time 9.3 seconds
Started Mar 24 02:43:08 PM PDT 24
Finished Mar 24 02:43:18 PM PDT 24
Peak memory 203556 kb
Host smart-a61b2fbe-3ba2-4148-a830-0fca58642dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35718
97195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3571897195
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.979611313
Short name T362
Test name
Test status
Simulation time 8356689709 ps
CPU time 8.5 seconds
Started Mar 24 02:43:19 PM PDT 24
Finished Mar 24 02:43:28 PM PDT 24
Peak memory 203588 kb
Host smart-ec4d8ea2-2d68-4958-a740-ef43974ba70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97961
1313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.979611313
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3870792161
Short name T764
Test name
Test status
Simulation time 8476297078 ps
CPU time 9.84 seconds
Started Mar 24 02:43:09 PM PDT 24
Finished Mar 24 02:43:19 PM PDT 24
Peak memory 203572 kb
Host smart-621bb34e-e8e6-40dc-8136-9bd1116d2792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38707
92161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3870792161
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3437362806
Short name T517
Test name
Test status
Simulation time 8367202155 ps
CPU time 8.8 seconds
Started Mar 24 02:43:17 PM PDT 24
Finished Mar 24 02:43:27 PM PDT 24
Peak memory 203780 kb
Host smart-f24f3dd8-d683-4c69-b3f5-d59e3228f132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
62806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3437362806
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_enable.1282541573
Short name T873
Test name
Test status
Simulation time 8368116234 ps
CPU time 8.78 seconds
Started Mar 24 02:43:07 PM PDT 24
Finished Mar 24 02:43:16 PM PDT 24
Peak memory 203532 kb
Host smart-692dac6c-99b8-4eae-9a5b-6e47fa6e2b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12825
41573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1282541573
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2567373106
Short name T222
Test name
Test status
Simulation time 133203386 ps
CPU time 1.65 seconds
Started Mar 24 02:43:06 PM PDT 24
Finished Mar 24 02:43:09 PM PDT 24
Peak memory 203652 kb
Host smart-7869a3cf-a172-4fda-bc29-518d90f11580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25673
73106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2567373106
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3423174784
Short name T190
Test name
Test status
Simulation time 8360208662 ps
CPU time 7.76 seconds
Started Mar 24 02:43:05 PM PDT 24
Finished Mar 24 02:43:15 PM PDT 24
Peak memory 203496 kb
Host smart-a06c821d-8cad-4768-972a-03028561b8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34231
74784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3423174784
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.770015385
Short name T578
Test name
Test status
Simulation time 8431078875 ps
CPU time 7.74 seconds
Started Mar 24 02:43:23 PM PDT 24
Finished Mar 24 02:43:31 PM PDT 24
Peak memory 203512 kb
Host smart-13a14de6-f753-4b2e-8b10-eca9b0d3adc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77001
5385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.770015385
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3305625829
Short name T432
Test name
Test status
Simulation time 8405021363 ps
CPU time 7.31 seconds
Started Mar 24 02:43:01 PM PDT 24
Finished Mar 24 02:43:08 PM PDT 24
Peak memory 203496 kb
Host smart-6f59fc1b-5f50-4820-98a6-e90def47752d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33056
25829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3305625829
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2001220198
Short name T747
Test name
Test status
Simulation time 8361492607 ps
CPU time 8.59 seconds
Started Mar 24 02:43:15 PM PDT 24
Finished Mar 24 02:43:27 PM PDT 24
Peak memory 203528 kb
Host smart-e1b26073-63d5-4b95-8c5b-94ae81a9654b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20012
20198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2001220198
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.113295479
Short name T107
Test name
Test status
Simulation time 8428818514 ps
CPU time 7.56 seconds
Started Mar 24 02:43:04 PM PDT 24
Finished Mar 24 02:43:13 PM PDT 24
Peak memory 203572 kb
Host smart-84c7919a-8fcb-48f9-b2bd-2180e5a6efe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11329
5479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.113295479
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.122474662
Short name T485
Test name
Test status
Simulation time 8375396063 ps
CPU time 7.79 seconds
Started Mar 24 02:43:05 PM PDT 24
Finished Mar 24 02:43:14 PM PDT 24
Peak memory 203536 kb
Host smart-3c1bb899-b940-4cee-920e-f64f6830ff74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12247
4662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.122474662
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2627430713
Short name T790
Test name
Test status
Simulation time 8402364276 ps
CPU time 7.9 seconds
Started Mar 24 02:43:04 PM PDT 24
Finished Mar 24 02:43:14 PM PDT 24
Peak memory 203580 kb
Host smart-33bfe0aa-955a-43aa-b95b-2805576a0ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26274
30713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2627430713
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2571357931
Short name T30
Test name
Test status
Simulation time 26781289 ps
CPU time 0.66 seconds
Started Mar 24 02:43:04 PM PDT 24
Finished Mar 24 02:43:06 PM PDT 24
Peak memory 203456 kb
Host smart-68311f20-599b-4129-8751-0a063ef30f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25713
57931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2571357931
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2011346699
Short name T357
Test name
Test status
Simulation time 8406352940 ps
CPU time 7.43 seconds
Started Mar 24 02:43:16 PM PDT 24
Finished Mar 24 02:43:25 PM PDT 24
Peak memory 203556 kb
Host smart-1d95d4c5-2d8c-4c63-82c5-accd599899ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20113
46699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2011346699
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2204400173
Short name T649
Test name
Test status
Simulation time 8387429168 ps
CPU time 7.32 seconds
Started Mar 24 02:43:18 PM PDT 24
Finished Mar 24 02:43:26 PM PDT 24
Peak memory 203496 kb
Host smart-c6a51e77-a535-4631-8cd1-8debc8415b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22044
00173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2204400173
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3457047889
Short name T480
Test name
Test status
Simulation time 8398279667 ps
CPU time 7.26 seconds
Started Mar 24 02:43:23 PM PDT 24
Finished Mar 24 02:43:30 PM PDT 24
Peak memory 203496 kb
Host smart-051dc50f-8692-4295-bc84-614c53855447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
47889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3457047889
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3075493544
Short name T19
Test name
Test status
Simulation time 8364367682 ps
CPU time 8.58 seconds
Started Mar 24 02:43:03 PM PDT 24
Finished Mar 24 02:43:13 PM PDT 24
Peak memory 203552 kb
Host smart-e0b915a5-eca1-4860-93a9-657476179d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30754
93544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3075493544
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3604332982
Short name T127
Test name
Test status
Simulation time 8476170335 ps
CPU time 7.33 seconds
Started Mar 24 02:43:05 PM PDT 24
Finished Mar 24 02:43:13 PM PDT 24
Peak memory 203556 kb
Host smart-7be98540-bc8d-4972-aae9-6c8881bef8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36043
32982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3604332982
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.670010287
Short name T364
Test name
Test status
Simulation time 8375291415 ps
CPU time 8.06 seconds
Started Mar 24 02:43:18 PM PDT 24
Finished Mar 24 02:43:27 PM PDT 24
Peak memory 203552 kb
Host smart-df5399a5-bd9a-44dd-a2b4-c0120f8d5361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67001
0287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.670010287
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.4194002805
Short name T810
Test name
Test status
Simulation time 8367854283 ps
CPU time 8.27 seconds
Started Mar 24 02:43:02 PM PDT 24
Finished Mar 24 02:43:12 PM PDT 24
Peak memory 203572 kb
Host smart-63b12250-9c8b-4428-ae08-7deb74ac989b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41940
02805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.4194002805
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.22108330
Short name T685
Test name
Test status
Simulation time 216729256 ps
CPU time 1.97 seconds
Started Mar 24 02:43:22 PM PDT 24
Finished Mar 24 02:43:25 PM PDT 24
Peak memory 203608 kb
Host smart-c69a6580-d6d3-4122-abd2-e0fef921c23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22108
330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.22108330
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1419074606
Short name T476
Test name
Test status
Simulation time 8363169628 ps
CPU time 7.79 seconds
Started Mar 24 02:43:25 PM PDT 24
Finished Mar 24 02:43:33 PM PDT 24
Peak memory 203516 kb
Host smart-297cf6e2-2638-4cd9-9e8b-3dbe9eed45b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14190
74606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1419074606
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3628678273
Short name T710
Test name
Test status
Simulation time 8369812667 ps
CPU time 6.92 seconds
Started Mar 24 02:43:18 PM PDT 24
Finished Mar 24 02:43:26 PM PDT 24
Peak memory 203508 kb
Host smart-6cc1ed7b-658d-44fe-aa0c-cd27bee2a71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36286
78273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3628678273
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.4221898271
Short name T233
Test name
Test status
Simulation time 8408660538 ps
CPU time 8.12 seconds
Started Mar 24 02:43:20 PM PDT 24
Finished Mar 24 02:43:28 PM PDT 24
Peak memory 203588 kb
Host smart-d4a6affe-f5fe-42d6-b6cb-be2a8431560e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218
98271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.4221898271
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1902104010
Short name T762
Test name
Test status
Simulation time 8362692360 ps
CPU time 9.25 seconds
Started Mar 24 02:43:22 PM PDT 24
Finished Mar 24 02:43:32 PM PDT 24
Peak memory 203600 kb
Host smart-72fe9b8e-339a-45b9-b12d-149a4fb4f491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021
04010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1902104010
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1671145807
Short name T94
Test name
Test status
Simulation time 8428777985 ps
CPU time 7.95 seconds
Started Mar 24 02:43:06 PM PDT 24
Finished Mar 24 02:43:16 PM PDT 24
Peak memory 203536 kb
Host smart-d9dea241-869e-4949-8c2a-51167e7d6893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16711
45807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1671145807
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1054876440
Short name T339
Test name
Test status
Simulation time 8395315719 ps
CPU time 8.15 seconds
Started Mar 24 02:43:10 PM PDT 24
Finished Mar 24 02:43:20 PM PDT 24
Peak memory 203552 kb
Host smart-087d9bff-edc5-44bc-91bc-7999dd350bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548
76440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1054876440
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3354884197
Short name T749
Test name
Test status
Simulation time 8364257869 ps
CPU time 7.45 seconds
Started Mar 24 02:43:23 PM PDT 24
Finished Mar 24 02:43:31 PM PDT 24
Peak memory 203500 kb
Host smart-c1003055-559c-4abd-9bca-238daf300552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33548
84197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3354884197
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.235780204
Short name T331
Test name
Test status
Simulation time 29681063 ps
CPU time 0.71 seconds
Started Mar 24 02:43:21 PM PDT 24
Finished Mar 24 02:43:22 PM PDT 24
Peak memory 203360 kb
Host smart-e8e82a38-24fa-4f73-ab02-168482267932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23578
0204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.235780204
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.4238113806
Short name T302
Test name
Test status
Simulation time 8392318040 ps
CPU time 7.96 seconds
Started Mar 24 02:43:08 PM PDT 24
Finished Mar 24 02:43:17 PM PDT 24
Peak memory 203540 kb
Host smart-e5aa1feb-0be8-42ef-b6ea-013cd9b3943d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42381
13806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.4238113806
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.972448625
Short name T664
Test name
Test status
Simulation time 8383930675 ps
CPU time 9.35 seconds
Started Mar 24 02:43:08 PM PDT 24
Finished Mar 24 02:43:19 PM PDT 24
Peak memory 203800 kb
Host smart-55f121c2-958f-430f-a05d-1d1904725b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97244
8625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.972448625
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3439397014
Short name T726
Test name
Test status
Simulation time 8408102395 ps
CPU time 7.79 seconds
Started Mar 24 02:43:23 PM PDT 24
Finished Mar 24 02:43:31 PM PDT 24
Peak memory 203580 kb
Host smart-b8ac809a-f073-41ea-bb4f-9e245a7ce50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34393
97014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3439397014
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1897251401
Short name T700
Test name
Test status
Simulation time 8361179101 ps
CPU time 7.87 seconds
Started Mar 24 02:43:17 PM PDT 24
Finished Mar 24 02:43:26 PM PDT 24
Peak memory 203568 kb
Host smart-2f5b7062-b4e3-4a64-a842-d3dff783025c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18972
51401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1897251401
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1793973386
Short name T149
Test name
Test status
Simulation time 8477353105 ps
CPU time 8.32 seconds
Started Mar 24 02:43:24 PM PDT 24
Finished Mar 24 02:43:33 PM PDT 24
Peak memory 203588 kb
Host smart-b2898119-592e-44da-abf1-8be58aabfe66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17939
73386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1793973386
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1730584506
Short name T281
Test name
Test status
Simulation time 8370985609 ps
CPU time 7.76 seconds
Started Mar 24 02:41:03 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 203548 kb
Host smart-2e44cfc5-13a2-48ad-9d00-b253d25a20bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17305
84506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1730584506
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_enable.2269374125
Short name T327
Test name
Test status
Simulation time 8364276601 ps
CPU time 7.51 seconds
Started Mar 24 02:41:03 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 203592 kb
Host smart-cc6daf87-c9aa-472f-b95b-a9176ba57265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22693
74125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2269374125
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2197291908
Short name T723
Test name
Test status
Simulation time 145863118 ps
CPU time 1.4 seconds
Started Mar 24 02:41:04 PM PDT 24
Finished Mar 24 02:41:06 PM PDT 24
Peak memory 203640 kb
Host smart-79cecb31-3dc5-49d2-abc4-a05564bff954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972
91908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2197291908
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.4227345531
Short name T181
Test name
Test status
Simulation time 8359439069 ps
CPU time 7.88 seconds
Started Mar 24 02:41:04 PM PDT 24
Finished Mar 24 02:41:12 PM PDT 24
Peak memory 203532 kb
Host smart-a63845ef-0814-4785-a413-8851c5efd464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42273
45531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.4227345531
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3557706079
Short name T695
Test name
Test status
Simulation time 8383942184 ps
CPU time 7.32 seconds
Started Mar 24 02:41:01 PM PDT 24
Finished Mar 24 02:41:09 PM PDT 24
Peak memory 203532 kb
Host smart-3044bd6b-a6f3-490f-93de-d0fff8a0d8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35577
06079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3557706079
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1021951299
Short name T761
Test name
Test status
Simulation time 8412867064 ps
CPU time 7.36 seconds
Started Mar 24 02:41:04 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 203528 kb
Host smart-02297105-6331-4149-adf5-bffa50a234ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10219
51299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1021951299
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3243295723
Short name T216
Test name
Test status
Simulation time 8364602894 ps
CPU time 7.73 seconds
Started Mar 24 02:41:04 PM PDT 24
Finished Mar 24 02:41:12 PM PDT 24
Peak memory 203588 kb
Host smart-ec86d6b2-8bbd-4bc0-9202-d6ca2b8d5871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32432
95723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3243295723
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3771299231
Short name T451
Test name
Test status
Simulation time 8397663422 ps
CPU time 7.95 seconds
Started Mar 24 02:41:05 PM PDT 24
Finished Mar 24 02:41:13 PM PDT 24
Peak memory 203568 kb
Host smart-016461d7-4ea2-480f-8682-725690d30177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37712
99231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3771299231
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.510460200
Short name T404
Test name
Test status
Simulation time 8405304749 ps
CPU time 8.08 seconds
Started Mar 24 02:41:03 PM PDT 24
Finished Mar 24 02:41:12 PM PDT 24
Peak memory 203556 kb
Host smart-f2aa4d6e-5d54-4203-aedd-7442b919d40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51046
0200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.510460200
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2846350628
Short name T512
Test name
Test status
Simulation time 8387195691 ps
CPU time 8.38 seconds
Started Mar 24 02:41:02 PM PDT 24
Finished Mar 24 02:41:10 PM PDT 24
Peak memory 203520 kb
Host smart-045e7e62-db51-47b5-9490-ffea92851128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28463
50628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2846350628
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1216057558
Short name T498
Test name
Test status
Simulation time 27250338 ps
CPU time 0.66 seconds
Started Mar 24 02:41:01 PM PDT 24
Finished Mar 24 02:41:02 PM PDT 24
Peak memory 203372 kb
Host smart-ce20ec66-61b7-4cd2-bbdb-225fca5a9fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12160
57558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1216057558
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2482406660
Short name T797
Test name
Test status
Simulation time 8374365918 ps
CPU time 8.91 seconds
Started Mar 24 02:41:02 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 203552 kb
Host smart-e0c2e569-e4cb-48f4-99f8-cc84a46ba1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24824
06660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2482406660
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.214045889
Short name T449
Test name
Test status
Simulation time 8421420287 ps
CPU time 8.86 seconds
Started Mar 24 02:41:03 PM PDT 24
Finished Mar 24 02:41:12 PM PDT 24
Peak memory 203484 kb
Host smart-617dcb31-eda3-45e7-aea0-a11a974dfb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21404
5889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.214045889
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.1994145787
Short name T329
Test name
Test status
Simulation time 8396235863 ps
CPU time 9.14 seconds
Started Mar 24 02:41:02 PM PDT 24
Finished Mar 24 02:41:12 PM PDT 24
Peak memory 203548 kb
Host smart-08f7ea84-383c-4326-ae36-82d704f961b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19941
45787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.1994145787
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3580692218
Short name T462
Test name
Test status
Simulation time 8360998261 ps
CPU time 7.37 seconds
Started Mar 24 02:41:04 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 203576 kb
Host smart-f7c12b9e-e4e1-4d94-b2c1-6f6be9ee3ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
92218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3580692218
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2470268225
Short name T806
Test name
Test status
Simulation time 8468102264 ps
CPU time 7.99 seconds
Started Mar 24 02:41:00 PM PDT 24
Finished Mar 24 02:41:08 PM PDT 24
Peak memory 203604 kb
Host smart-bb118111-fe54-4102-8619-6a32583a1f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24702
68225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2470268225
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1333062121
Short name T862
Test name
Test status
Simulation time 8365773242 ps
CPU time 7.25 seconds
Started Mar 24 02:41:02 PM PDT 24
Finished Mar 24 02:41:09 PM PDT 24
Peak memory 203552 kb
Host smart-cf52251c-3ee1-4aff-a86c-0dbd549c8389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13330
62121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1333062121
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_enable.225326015
Short name T345
Test name
Test status
Simulation time 8374578661 ps
CPU time 8.12 seconds
Started Mar 24 02:41:01 PM PDT 24
Finished Mar 24 02:41:10 PM PDT 24
Peak memory 203556 kb
Host smart-4641ef56-2c9d-410c-9efe-de3e8ae5352a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532
6015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.225326015
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.2751044213
Short name T507
Test name
Test status
Simulation time 165434065 ps
CPU time 1.88 seconds
Started Mar 24 02:41:02 PM PDT 24
Finished Mar 24 02:41:04 PM PDT 24
Peak memory 203624 kb
Host smart-df33680b-abaa-4ad6-a73f-a23d5e15a5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27510
44213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2751044213
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3428798881
Short name T184
Test name
Test status
Simulation time 8360692839 ps
CPU time 9.75 seconds
Started Mar 24 02:41:08 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203484 kb
Host smart-2c8f5e5f-7240-4458-93dc-62f182e8e6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34287
98881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3428798881
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.253968350
Short name T608
Test name
Test status
Simulation time 8446860844 ps
CPU time 9.75 seconds
Started Mar 24 02:41:01 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 203520 kb
Host smart-d986a364-2bae-4dae-9225-c3b35d0b7d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25396
8350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.253968350
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3645257023
Short name T228
Test name
Test status
Simulation time 8409122723 ps
CPU time 9.32 seconds
Started Mar 24 02:41:07 PM PDT 24
Finished Mar 24 02:41:17 PM PDT 24
Peak memory 203560 kb
Host smart-291407ff-16d7-4e19-a4d3-14996d4f979c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36452
57023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3645257023
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3576836472
Short name T401
Test name
Test status
Simulation time 8365167152 ps
CPU time 8.09 seconds
Started Mar 24 02:41:07 PM PDT 24
Finished Mar 24 02:41:15 PM PDT 24
Peak memory 203560 kb
Host smart-7b8fabb6-693b-4642-9d52-b2f93c3a1302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35768
36472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3576836472
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1499616177
Short name T109
Test name
Test status
Simulation time 8428501486 ps
CPU time 8.01 seconds
Started Mar 24 02:41:09 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203496 kb
Host smart-8f2b3f95-e590-4065-8b0b-9d8c549c4e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14996
16177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1499616177
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.546900522
Short name T375
Test name
Test status
Simulation time 8366747611 ps
CPU time 10.19 seconds
Started Mar 24 02:41:07 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203556 kb
Host smart-eb23466f-1ee5-49ab-9527-8b1495fbc487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54690
0522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.546900522
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4143680140
Short name T541
Test name
Test status
Simulation time 8401492711 ps
CPU time 7.96 seconds
Started Mar 24 02:41:09 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203532 kb
Host smart-83a0b72f-7048-42b4-9ca3-c30f3663c3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41436
80140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4143680140
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2712968808
Short name T312
Test name
Test status
Simulation time 22900175 ps
CPU time 0.67 seconds
Started Mar 24 02:41:13 PM PDT 24
Finished Mar 24 02:41:14 PM PDT 24
Peak memory 203416 kb
Host smart-2c7c7e36-89b8-4171-b63d-e6c77e629c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27129
68808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2712968808
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2634041418
Short name T601
Test name
Test status
Simulation time 8389665430 ps
CPU time 7.26 seconds
Started Mar 24 02:41:07 PM PDT 24
Finished Mar 24 02:41:14 PM PDT 24
Peak memory 203556 kb
Host smart-5a5a7699-5737-474b-9460-4c84607b4ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26340
41418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2634041418
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.4164041227
Short name T542
Test name
Test status
Simulation time 8448399100 ps
CPU time 7.16 seconds
Started Mar 24 02:41:05 PM PDT 24
Finished Mar 24 02:41:12 PM PDT 24
Peak memory 203540 kb
Host smart-ef085de2-a67b-4d54-90d4-1b1bbf11eae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41640
41227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.4164041227
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.1342434866
Short name T714
Test name
Test status
Simulation time 8383333363 ps
CPU time 7.46 seconds
Started Mar 24 02:41:07 PM PDT 24
Finished Mar 24 02:41:15 PM PDT 24
Peak memory 203568 kb
Host smart-fce68d04-b359-45c9-969d-e5876e9de19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13424
34866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.1342434866
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.689661952
Short name T20
Test name
Test status
Simulation time 8356083534 ps
CPU time 7.58 seconds
Started Mar 24 02:41:09 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203572 kb
Host smart-8ea275ef-205b-4219-be9e-bc445381f96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68966
1952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.689661952
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.649471013
Short name T745
Test name
Test status
Simulation time 8474506252 ps
CPU time 7.47 seconds
Started Mar 24 02:41:03 PM PDT 24
Finished Mar 24 02:41:10 PM PDT 24
Peak memory 203552 kb
Host smart-1101273d-5941-46a2-8292-f69599c27b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64947
1013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.649471013
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.23695105
Short name T659
Test name
Test status
Simulation time 8371998896 ps
CPU time 6.89 seconds
Started Mar 24 02:41:10 PM PDT 24
Finished Mar 24 02:41:17 PM PDT 24
Peak memory 203556 kb
Host smart-f10c8caf-cec9-45c0-aeb4-90ce9e512e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23695
105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.23695105
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_enable.3862908605
Short name T568
Test name
Test status
Simulation time 8371905222 ps
CPU time 7.18 seconds
Started Mar 24 02:41:08 PM PDT 24
Finished Mar 24 02:41:15 PM PDT 24
Peak memory 203576 kb
Host smart-2f2426b5-d2a9-47d9-ac2f-4eef401eff47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38629
08605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3862908605
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.4116582950
Short name T606
Test name
Test status
Simulation time 34662983 ps
CPU time 1.09 seconds
Started Mar 24 02:41:06 PM PDT 24
Finished Mar 24 02:41:07 PM PDT 24
Peak memory 203588 kb
Host smart-1d024395-9d18-4b71-b1e1-81cdbc6b3373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41165
82950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.4116582950
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3246869219
Short name T779
Test name
Test status
Simulation time 8439663139 ps
CPU time 7.51 seconds
Started Mar 24 02:41:09 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203556 kb
Host smart-1fbabd6b-2b38-461a-af14-ddc88405bcf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32468
69219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3246869219
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.968684356
Short name T712
Test name
Test status
Simulation time 8407258719 ps
CPU time 7.79 seconds
Started Mar 24 02:41:10 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203560 kb
Host smart-d6e00d68-16e2-4b63-a7dc-162245b14767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96868
4356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.968684356
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2602172116
Short name T433
Test name
Test status
Simulation time 8364930876 ps
CPU time 7.33 seconds
Started Mar 24 02:41:09 PM PDT 24
Finished Mar 24 02:41:17 PM PDT 24
Peak memory 203572 kb
Host smart-7cb100dd-b6b2-4f44-9738-6f2c15deae85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26021
72116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2602172116
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.233684582
Short name T112
Test name
Test status
Simulation time 8410430251 ps
CPU time 9.73 seconds
Started Mar 24 02:41:15 PM PDT 24
Finished Mar 24 02:41:25 PM PDT 24
Peak memory 203552 kb
Host smart-49ab6fe3-68e6-4a09-82a4-eecc65edc1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23368
4582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.233684582
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2140943150
Short name T27
Test name
Test status
Simulation time 8378908960 ps
CPU time 7.88 seconds
Started Mar 24 02:41:06 PM PDT 24
Finished Mar 24 02:41:14 PM PDT 24
Peak memory 203480 kb
Host smart-466038ce-55ef-4a68-b103-35e4f48a8da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21409
43150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2140943150
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.359204201
Short name T847
Test name
Test status
Simulation time 8403921315 ps
CPU time 7.46 seconds
Started Mar 24 02:41:07 PM PDT 24
Finished Mar 24 02:41:14 PM PDT 24
Peak memory 203560 kb
Host smart-79c4a7d8-b500-4a7a-9b1d-88d9c7e35d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35920
4201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.359204201
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2922964038
Short name T394
Test name
Test status
Simulation time 23526896 ps
CPU time 0.63 seconds
Started Mar 24 02:41:06 PM PDT 24
Finished Mar 24 02:41:06 PM PDT 24
Peak memory 203368 kb
Host smart-3970e7e2-6d92-4491-abdc-b2af8d6ea12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29229
64038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2922964038
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.4108288606
Short name T309
Test name
Test status
Simulation time 8380959359 ps
CPU time 8.54 seconds
Started Mar 24 02:41:12 PM PDT 24
Finished Mar 24 02:41:21 PM PDT 24
Peak memory 203552 kb
Host smart-eabf5cc9-3334-472e-be41-3266f3912427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41082
88606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.4108288606
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.337003092
Short name T645
Test name
Test status
Simulation time 8401651712 ps
CPU time 7.59 seconds
Started Mar 24 02:41:05 PM PDT 24
Finished Mar 24 02:41:13 PM PDT 24
Peak memory 203548 kb
Host smart-5b114e0c-1c7c-4367-83e8-7e427b4279ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33700
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.337003092
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.3908101182
Short name T283
Test name
Test status
Simulation time 8369844665 ps
CPU time 9.23 seconds
Started Mar 24 02:41:06 PM PDT 24
Finished Mar 24 02:41:16 PM PDT 24
Peak memory 203784 kb
Host smart-6a4a53a7-0b63-40cb-b352-b1f9063e80f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
01182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.3908101182
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3267851431
Short name T500
Test name
Test status
Simulation time 8358233383 ps
CPU time 7.6 seconds
Started Mar 24 02:41:06 PM PDT 24
Finished Mar 24 02:41:14 PM PDT 24
Peak memory 203600 kb
Host smart-85b5f5bc-12d7-469e-95a7-690090169a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32678
51431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3267851431
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2118049861
Short name T497
Test name
Test status
Simulation time 8475532751 ps
CPU time 7.6 seconds
Started Mar 24 02:41:08 PM PDT 24
Finished Mar 24 02:41:16 PM PDT 24
Peak memory 203516 kb
Host smart-01fdb852-8363-48d2-a7c0-f46624fbc9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21180
49861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2118049861
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.4234573044
Short name T376
Test name
Test status
Simulation time 8366353310 ps
CPU time 7.08 seconds
Started Mar 24 02:41:15 PM PDT 24
Finished Mar 24 02:41:22 PM PDT 24
Peak memory 203572 kb
Host smart-067427c9-e8d7-47b7-8ed5-43b68f99f50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345
73044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.4234573044
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_enable.1243289555
Short name T300
Test name
Test status
Simulation time 8373110386 ps
CPU time 7.94 seconds
Started Mar 24 02:41:15 PM PDT 24
Finished Mar 24 02:41:24 PM PDT 24
Peak memory 203572 kb
Host smart-14c0d26e-1eec-45d0-a5b6-b30926e6930a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12432
89555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1243289555
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.4203426053
Short name T49
Test name
Test status
Simulation time 43792148 ps
CPU time 1.29 seconds
Started Mar 24 02:41:11 PM PDT 24
Finished Mar 24 02:41:13 PM PDT 24
Peak memory 203656 kb
Host smart-020cf087-6fbc-4253-81d3-5ace3bb19018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
26053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.4203426053
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1015075037
Short name T171
Test name
Test status
Simulation time 8357654900 ps
CPU time 9.51 seconds
Started Mar 24 02:41:12 PM PDT 24
Finished Mar 24 02:41:21 PM PDT 24
Peak memory 203532 kb
Host smart-afff8c80-f181-499e-aeb7-cc31066c1916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10150
75037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1015075037
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1980211365
Short name T585
Test name
Test status
Simulation time 8433238974 ps
CPU time 7.43 seconds
Started Mar 24 02:41:16 PM PDT 24
Finished Mar 24 02:41:24 PM PDT 24
Peak memory 203568 kb
Host smart-b1075204-9e03-404f-a3c5-89c926509f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19802
11365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1980211365
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3600648605
Short name T455
Test name
Test status
Simulation time 8410484020 ps
CPU time 7.35 seconds
Started Mar 24 02:41:11 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203588 kb
Host smart-7464b84b-0d6f-492f-9671-4edbb407e46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36006
48605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3600648605
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.196260772
Short name T458
Test name
Test status
Simulation time 8364877078 ps
CPU time 9.43 seconds
Started Mar 24 02:41:15 PM PDT 24
Finished Mar 24 02:41:25 PM PDT 24
Peak memory 203576 kb
Host smart-ea118c6c-72c1-49e3-bb24-bb38ed83f88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19626
0772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.196260772
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2719384306
Short name T102
Test name
Test status
Simulation time 8426822543 ps
CPU time 7.45 seconds
Started Mar 24 02:41:11 PM PDT 24
Finished Mar 24 02:41:19 PM PDT 24
Peak memory 203508 kb
Host smart-8efd5507-6f41-47c5-86d0-38ead87b5ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27193
84306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2719384306
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.861044625
Short name T399
Test name
Test status
Simulation time 8381275158 ps
CPU time 7.82 seconds
Started Mar 24 02:41:11 PM PDT 24
Finished Mar 24 02:41:19 PM PDT 24
Peak memory 203560 kb
Host smart-7f6db7d9-4a08-4579-a747-d3fcf92e6c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86104
4625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.861044625
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.962606457
Short name T276
Test name
Test status
Simulation time 8399392907 ps
CPU time 8.67 seconds
Started Mar 24 02:41:14 PM PDT 24
Finished Mar 24 02:41:23 PM PDT 24
Peak memory 203568 kb
Host smart-76d7c110-0dee-43d3-9822-3a8e0fd41185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96260
6457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.962606457
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3614972862
Short name T31
Test name
Test status
Simulation time 27408308 ps
CPU time 0.64 seconds
Started Mar 24 02:41:11 PM PDT 24
Finished Mar 24 02:41:12 PM PDT 24
Peak memory 203436 kb
Host smart-b0c8e03a-4b0b-4751-8a33-d72dcaad6bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
72862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3614972862
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2848046531
Short name T591
Test name
Test status
Simulation time 8363960891 ps
CPU time 9.21 seconds
Started Mar 24 02:41:14 PM PDT 24
Finished Mar 24 02:41:23 PM PDT 24
Peak memory 203568 kb
Host smart-243b4d59-a673-49bc-8f3c-fa8b70c4ad7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28480
46531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2848046531
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.498499603
Short name T560
Test name
Test status
Simulation time 8430487670 ps
CPU time 7.75 seconds
Started Mar 24 02:41:11 PM PDT 24
Finished Mar 24 02:41:19 PM PDT 24
Peak memory 203552 kb
Host smart-441df170-d75a-4bd0-a570-e2363966551a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49849
9603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.498499603
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3307810621
Short name T471
Test name
Test status
Simulation time 8395857096 ps
CPU time 7.53 seconds
Started Mar 24 02:41:13 PM PDT 24
Finished Mar 24 02:41:21 PM PDT 24
Peak memory 203496 kb
Host smart-5d525e3d-d478-4977-9dbc-c48df903e07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33078
10621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3307810621
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2198325711
Short name T835
Test name
Test status
Simulation time 8362850542 ps
CPU time 7.42 seconds
Started Mar 24 02:41:14 PM PDT 24
Finished Mar 24 02:41:21 PM PDT 24
Peak memory 203552 kb
Host smart-a2094a08-a65a-4a9f-beb7-974776763575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21983
25711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2198325711
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3379785778
Short name T150
Test name
Test status
Simulation time 8474435716 ps
CPU time 9.7 seconds
Started Mar 24 02:41:10 PM PDT 24
Finished Mar 24 02:41:20 PM PDT 24
Peak memory 203576 kb
Host smart-ae901d9a-853e-44cf-9b07-95a359e16d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33797
85778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3379785778
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1939585688
Short name T424
Test name
Test status
Simulation time 8367964011 ps
CPU time 9.23 seconds
Started Mar 24 02:41:11 PM PDT 24
Finished Mar 24 02:41:20 PM PDT 24
Peak memory 203548 kb
Host smart-098ef738-3c41-4465-9218-8afcfeff8958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19395
85688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1939585688
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_enable.79199887
Short name T828
Test name
Test status
Simulation time 8367099978 ps
CPU time 7.57 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:31 PM PDT 24
Peak memory 203588 kb
Host smart-a76b8712-e330-40aa-bb9e-631d832d72c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79199
887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.79199887
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1081069254
Short name T218
Test name
Test status
Simulation time 50752409 ps
CPU time 1.38 seconds
Started Mar 24 02:41:17 PM PDT 24
Finished Mar 24 02:41:18 PM PDT 24
Peak memory 203644 kb
Host smart-71e75203-80c7-4f2c-b135-5adaa50a2d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810
69254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1081069254
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.532584025
Short name T165
Test name
Test status
Simulation time 8356038648 ps
CPU time 7.4 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:31 PM PDT 24
Peak memory 203516 kb
Host smart-4556e62b-4485-4e06-8a73-4557d366084a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53258
4025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.532584025
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3123974269
Short name T524
Test name
Test status
Simulation time 8395360544 ps
CPU time 7.92 seconds
Started Mar 24 02:41:16 PM PDT 24
Finished Mar 24 02:41:24 PM PDT 24
Peak memory 203548 kb
Host smart-29bc568c-1679-4bcc-abc6-fe5860b8cce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31239
74269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3123974269
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3012376261
Short name T440
Test name
Test status
Simulation time 8409425476 ps
CPU time 7.63 seconds
Started Mar 24 02:41:15 PM PDT 24
Finished Mar 24 02:41:22 PM PDT 24
Peak memory 203488 kb
Host smart-18cd25f0-659e-43e1-b24c-6fd806b23904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30123
76261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3012376261
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3070138964
Short name T337
Test name
Test status
Simulation time 8363827888 ps
CPU time 7.58 seconds
Started Mar 24 02:41:23 PM PDT 24
Finished Mar 24 02:41:31 PM PDT 24
Peak memory 203584 kb
Host smart-1d0ada48-4bcc-42f3-8ed5-1b22d5cd1a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30701
38964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3070138964
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1678597130
Short name T336
Test name
Test status
Simulation time 8370390461 ps
CPU time 7.79 seconds
Started Mar 24 02:41:17 PM PDT 24
Finished Mar 24 02:41:25 PM PDT 24
Peak memory 203536 kb
Host smart-84c7fc09-9020-4258-bcc8-8423e4f52dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16785
97130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1678597130
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1308546445
Short name T759
Test name
Test status
Simulation time 8383909263 ps
CPU time 7.55 seconds
Started Mar 24 02:41:18 PM PDT 24
Finished Mar 24 02:41:26 PM PDT 24
Peak memory 203580 kb
Host smart-59bfdd7d-2a7e-415e-92ac-004185617fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13085
46445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1308546445
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1213271739
Short name T388
Test name
Test status
Simulation time 29795102 ps
CPU time 0.65 seconds
Started Mar 24 02:41:22 PM PDT 24
Finished Mar 24 02:41:23 PM PDT 24
Peak memory 203380 kb
Host smart-f131347f-26ea-4abe-a927-6b6ea583aa19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12132
71739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1213271739
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.122887517
Short name T588
Test name
Test status
Simulation time 8390039596 ps
CPU time 7.28 seconds
Started Mar 24 02:41:19 PM PDT 24
Finished Mar 24 02:41:27 PM PDT 24
Peak memory 203552 kb
Host smart-0d8b24b9-080c-49f2-9415-7c42cec347f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12288
7517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.122887517
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.4245330139
Short name T673
Test name
Test status
Simulation time 8453109747 ps
CPU time 7.33 seconds
Started Mar 24 02:41:17 PM PDT 24
Finished Mar 24 02:41:25 PM PDT 24
Peak memory 203500 kb
Host smart-c362498d-3599-4b0a-a79e-9baf32156a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42453
30139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.4245330139
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.3542867648
Short name T7
Test name
Test status
Simulation time 8393868842 ps
CPU time 7.66 seconds
Started Mar 24 02:41:17 PM PDT 24
Finished Mar 24 02:41:25 PM PDT 24
Peak memory 203540 kb
Host smart-0dea24dc-3221-4bfe-8e00-8d3c0b42fed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35428
67648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.3542867648
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.838746627
Short name T702
Test name
Test status
Simulation time 8358619024 ps
CPU time 8.19 seconds
Started Mar 24 02:41:18 PM PDT 24
Finished Mar 24 02:41:26 PM PDT 24
Peak memory 203556 kb
Host smart-48090b29-a149-4bb6-b588-9353ce34ced2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83874
6627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.838746627
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.110504920
Short name T15
Test name
Test status
Simulation time 8471950377 ps
CPU time 8.55 seconds
Started Mar 24 02:41:16 PM PDT 24
Finished Mar 24 02:41:25 PM PDT 24
Peak memory 203572 kb
Host smart-06a89c4a-ef6d-46cc-884a-dcc4b4c622c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11050
4920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.110504920
Directory /workspace/9.usbdev_smoke/latest
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