Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2814	1		T1	3		T2	4		T3	2
all_values[1]	2814	1		T1	3		T2	4		T3	2
all_values[2]	2814	1		T1	3		T2	4		T3	2
all_values[3]	2814	1		T1	3		T2	4		T3	2
all_values[4]	2814	1		T1	3		T2	4		T3	2
all_values[5]	2814	1		T1	3		T2	4		T3	2
all_values[6]	2814	1		T1	3		T2	4		T3	2
all_values[7]	2814	1		T1	3		T2	4		T3	2
all_values[8]	2814	1		T1	3		T2	4		T3	2
all_values[9]	2814	1		T1	3		T2	4		T3	2
all_values[10]	2814	1		T1	3		T2	4		T3	2
all_values[11]	2814	1		T1	3		T2	4		T3	2
all_values[12]	2814	1		T1	3		T2	4		T3	2
all_values[13]	2814	1		T1	3		T2	4		T3	2
all_values[14]	2814	1		T1	3		T2	4		T3	2
all_values[15]	2814	1		T1	3		T2	4		T3	2
all_values[16]	2814	1		T1	3		T2	4		T3	2
all_values[17]	2814	1		T1	3		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	48062	1		T1	51		T2	72		T3	36
auto[1]	2590	1		T1	3		T7	4		T12	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	47868	1		T1	54		T2	72		T3	36
auto[1]	2784	1		T66	76		T63	74		T64	131

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2003	1		T1	3		T2	4		T3	2
all_values[0]	auto[0]	auto[1]	83	1		T66	1		T63	4		T65	1
all_values[0]	auto[1]	auto[0]	666	1		T7	4		T12	3		T27	4
all_values[0]	auto[1]	auto[1]	62	1		T66	4		T63	1		T64	3
all_values[1]	auto[0]	auto[0]	2348	1		T2	4		T3	2		T7	4
all_values[1]	auto[0]	auto[1]	83	1		T66	2		T63	3		T64	2
all_values[1]	auto[1]	auto[0]	315	1		T1	3		T22	3		T23	3
all_values[1]	auto[1]	auto[1]	68	1		T66	3		T64	5		T65	4
all_values[2]	auto[0]	auto[0]	2648	1		T1	3		T2	4		T3	2
all_values[2]	auto[0]	auto[1]	83	1		T66	4		T63	4		T65	3
all_values[2]	auto[1]	auto[0]	17	1		T64	1		T65	1		T239	2
all_values[2]	auto[1]	auto[1]	66	1		T66	1		T64	7		T65	1
all_values[3]	auto[0]	auto[0]	2652	1		T1	3		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	54	1		T66	4		T64	1		T65	1
all_values[3]	auto[1]	auto[0]	13	1		T64	1		T240	1		T241	1
all_values[3]	auto[1]	auto[1]	95	1		T63	4		T64	6		T65	3
all_values[4]	auto[0]	auto[0]	2638	1		T1	3		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	75	1		T66	3		T63	3		T64	2
all_values[4]	auto[1]	auto[0]	4	1		T242	1		T243	1		T244	1
all_values[4]	auto[1]	auto[1]	97	1		T66	1		T63	2		T64	5
all_values[5]	auto[0]	auto[0]	2642	1		T1	3		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	86	1		T66	4		T63	3		T64	4
all_values[5]	auto[1]	auto[0]	14	1		T245	1		T241	2		T246	1
all_values[5]	auto[1]	auto[1]	72	1		T66	1		T63	1		T64	4
all_values[6]	auto[0]	auto[0]	2650	1		T1	3		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	86	1		T66	1		T63	1		T64	5
all_values[6]	auto[1]	auto[0]	7	1		T242	2		T247	1		T248	1
all_values[6]	auto[1]	auto[1]	71	1		T66	3		T63	4		T64	2
all_values[7]	auto[0]	auto[0]	2648	1		T1	3		T2	4		T3	2
all_values[7]	auto[0]	auto[1]	77	1		T66	4		T63	1		T64	2
all_values[7]	auto[1]	auto[0]	7	1		T245	1		T242	1		T249	1
all_values[7]	auto[1]	auto[1]	82	1		T66	1		T63	3		T64	6
all_values[8]	auto[0]	auto[0]	2660	1		T1	3		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	82	1		T66	3		T63	4		T64	4
all_values[8]	auto[1]	auto[0]	14	1		T63	1		T250	1		T246	2
all_values[8]	auto[1]	auto[1]	58	1		T66	1		T64	4		T65	5
all_values[9]	auto[0]	auto[0]	2643	1		T1	3		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	67	1		T66	1		T63	4		T64	6
all_values[9]	auto[1]	auto[0]	7	1		T240	1		T248	3		T251	1
all_values[9]	auto[1]	auto[1]	97	1		T66	4		T63	1		T64	2
all_values[10]	auto[0]	auto[0]	2644	1		T1	3		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	66	1		T66	3		T64	1		T65	1
all_values[10]	auto[1]	auto[0]	10	1		T66	2		T247	1		T248	1
all_values[10]	auto[1]	auto[1]	94	1		T63	3		T64	7		T65	3
all_values[11]	auto[0]	auto[0]	2645	1		T1	3		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	73	1		T63	2		T64	2		T65	5
all_values[11]	auto[1]	auto[0]	12	1		T239	2		T246	4		T252	1
all_values[11]	auto[1]	auto[1]	84	1		T66	5		T63	3		T64	6
all_values[12]	auto[0]	auto[0]	2646	1		T1	3		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	82	1		T63	3		T64	7		T65	4
all_values[12]	auto[1]	auto[0]	7	1		T240	1		T239	1		T252	1
all_values[12]	auto[1]	auto[1]	79	1		T66	4		T63	1		T64	1
all_values[13]	auto[0]	auto[0]	2644	1		T1	3		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	92	1		T66	3		T64	1		T65	4
all_values[13]	auto[1]	auto[0]	12	1		T66	2		T64	1		T241	1
all_values[13]	auto[1]	auto[1]	66	1		T64	4		T65	1		T245	1
all_values[14]	auto[0]	auto[0]	2640	1		T1	3		T2	4		T3	2
all_values[14]	auto[0]	auto[1]	70	1		T66	4		T63	4		T64	7
all_values[14]	auto[1]	auto[0]	16	1		T65	1		T242	2		T246	1
all_values[14]	auto[1]	auto[1]	88	1		T66	1		T63	1		T64	1
all_values[15]	auto[0]	auto[0]	2645	1		T1	3		T2	4		T3	2
all_values[15]	auto[0]	auto[1]	73	1		T63	1		T64	3		T65	3
all_values[15]	auto[1]	auto[0]	12	1		T66	1		T245	3		T253	1
all_values[15]	auto[1]	auto[1]	84	1		T63	4		T64	5		T240	5
all_values[16]	auto[0]	auto[0]	2641	1		T1	3		T2	4		T3	2
all_values[16]	auto[0]	auto[1]	66	1		T66	1		T64	6		T65	3
all_values[16]	auto[1]	auto[0]	20	1		T240	1		T245	1		T241	1
all_values[16]	auto[1]	auto[1]	87	1		T66	4		T63	4		T64	2
all_values[17]	auto[0]	auto[0]	2656	1		T1	3		T2	4		T3	2
all_values[17]	auto[0]	auto[1]	71	1		T66	3		T63	3		T64	2
all_values[17]	auto[1]	auto[0]	22	1		T240	1		T241	2		T250	5
all_values[17]	auto[1]	auto[1]	65	1		T66	2		T63	2		T64	6